一种芯粒的晶圆级集成封装结构与方法
By fabricating double-sided redistribution layers and through-silicon vias on a silicon interposer and bonding it to a substrate using a support carrier, the warpage and high cost issues in existing technologies are solved, achieving high-yield, large-size packaged wafer-level integration.
CN117116899BActive Publication Date: 2026-07-17ZHEJIANG UNIV +1
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG UNIV
- Filing Date
- 2023-07-13
- Publication Date
- 2026-07-17
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Figure CN117116899B_ABST
Abstract
本发明公开了一种芯粒的晶圆级集成封装结构与方法。本发明的芯粒的晶圆级集成封装结构包括芯粒、硅转接板、基板与散热载体。本发明通过硅转接板上的重布线层进行芯粒间的信号连接，并通过硅转接板上的硅通孔进行垂直方向上的供电与信号扇出。本发明采用将芯粒与硅转接板进行键合，将芯粒与硅转接板的塑封体与散热载体进行机械黏合，形成复合体，复合体再进一步与基板通过金属凸块进行键合的封装方式实现了整晶圆大小的多芯粒封装。本发明兼容和适用于各种模拟芯粒、射频芯粒与数字芯粒的晶圆级大规模集成封装，具有抗翘曲、封装良率高等特点。
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