High-order harmonic controlled low-noise four-core voltage-controlled oscillator

Abstract

A low-noise four-core voltage-controlled oscillator controlled by higher harmonics comprises four oscillation cores which are connected in a ring shape, the Dn + end of each oscillation core is connected with the Dn-end of the adjacent oscillation core through two inductors LD, the Gp + end of each oscillation core is connected with the Gp-end of the adjacent oscillation core through two inductors LP, and the Gn + end of each oscillation core is connected with the Gp-end of the adjacent oscillation core through two inductors LP. And the + end is connected with the Gn-end of the opposite oscillation core through four inductors LG. Output signals are shaped through the third harmonic resonant cavity and the fifth harmonic resonant cavity, the noise circulation technology is combined, noise sources and conversion from the noise sources to phase noise are reduced at the same time, noise performance optimization is achieved, and meanwhile low-noise clock signals with the frequency of GHz or above can be output.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of wireless communication, and particularly relates to a high-harmonic controlled low-noise four-core voltage-controlled oscillator. BACKGROUND

[0002] In the existing multi-core coupled oscillator, mainly used is an inductance quality factor enhancement technology, through same-direction coupling between multiple inductances, the quality factor is equivalently improved, noise performance is optimized, or a multi-path synchronization scheme is combined with a harmonic control technology, frequency mismatch between oscillation cores is reduced, and phase noise is optimized through harmonic control. However, the existing four-core voltage-controlled oscillator technology has high power consumption and poor noise performance. SUMMARY

[0003] The application provides a high-harmonic controlled low-noise four-core voltage-controlled oscillator, which shapes an output signal through third and fifth harmonic resonant cavities, combines noise circulation technology, simultaneously reduces a noise source and conversion of the noise source to phase noise, and realizes noise performance optimization while being capable of outputting a low-noise clock signal with a frequency of more than GHz.

[0004] The application is implemented through the following technical scheme:

[0005] The application relates to a high-harmonic controlled low-noise four-core voltage-controlled oscillator, which comprises four ring-connected oscillation cores, wherein: n,+ the D D end of each oscillation core is connected with the D n,- end of an adjacent oscillation core through two inductances L p,+ the G P end of each oscillation core is connected with the G p,- end of an adjacent oscillation core through two inductances L n,+ the G G end of each oscillation core is connected with the G n,- end of an opposite oscillation core through four inductances L .

[0006] The oscillation core comprises an NMOS transistor pair M1 and M2, a PMOS transistor pair M3 and M4, a variable capacitance array and a switch capacitance array, wherein: D the drain end of the first NMOS transistor M1 is connected with the C sw,+ end of the switch capacitance array in the capacitance array C var,+ the end of the variable capacitance array, and constitutes the D n,+ end of the oscillation core, the gate end of the first NMOS transistor M1 is connected with the C G end of the switch capacitance array in the capacitance array C sw,+ the end of the variable capacitance array, and constitutes the G var,+The ends are connected to form the oscillation core G n,+ The drain terminal of the second NMOS transistor M2 and the capacitor array C D C in the switched capacitor array sw,- terminal, C of the variable capacitor array var,- The D ends are connected to form the oscillation core n,- The gate terminal of the second NMOS transistor M2 and the capacitor array C G C in the switched capacitor array sw,- terminal, C of the variable capacitor array var,- The ends are connected to form the oscillation core G n,- The gate terminal of the third PMOS transistor M3 and the switch capacitor array C P C sw,+ The ends are connected to form the oscillation core G p,+ The gate terminal of the third PMOS transistor M3 is connected to the switch capacitor array C P C sw,- The ends are connected to form the oscillation core G p,- end.

[0007] Technical Effects

[0008] The present invention realizes the third and fifth harmonic resonant cavities simultaneously, shapes the output signal of the voltage-controlled oscillator, thereby improving the slew rate of the inversion edge of the output signal of the voltage-controlled oscillator, reducing the conversion of the noise source to phase noise in the voltage-controlled oscillator, and improving the phase noise performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a structural diagram of the present invention;

[0010] Figure 2 This is a schematic diagram of the oscillation core circuit;

[0011] Figure 3 Schematic diagram of transient waveform simulation results at various nodes of the voltage-controlled oscillator in the embodiment;

[0012] Figure 4 Schematic diagram of the simulation results of the differential mode impedance of the resonant cavity of the quad-core voltage-controlled oscillator in the embodiment;

[0013] Figure 5 The frequency tuning range curve of the quad-core voltage controlled oscillator in the embodiment;

[0014] Figure 6 Schematic diagram of phase noise results of the output signal of the quad-core voltage-controlled oscillator within the full frequency tuning range at frequency offsets of 100 kHz, 1 MHz, and 10 MHz in the embodiment;

[0015] Figure 7 This is the plan view of the segmented toroidal three-wire transformer. DETAILED DESCRIPTION

[0016] As Figure 1 shown, the present embodiment relates to a high-harmonic control low-noise four-core voltage-controlled oscillator, comprising four ring-connected oscillation cores, wherein: n,+ the D D end of each oscillation core is connected to the D n,- end of the adjacent oscillation core through two inductors L p,+ , the G P end of each oscillation core is connected to the G p,- end of the adjacent oscillation core through two inductors L n,+ , and the G G end of each oscillation core is connected to the G n,- end of the opposite oscillation core through four inductors L

[0017] The segmented ring-shaped three-wire transformer specifically refers to four three-wire transformers arranged in a central symmetry, wherein:

[0018] The first transformer comprises: an inductor L n,+ connecting the D n,- end and the D D,12 end arranged between the first oscillation core 1 and the second oscillation core 2, an inductor L p,+ connecting the G p,- end and the G P,12 end arranged between the first oscillation core 1 and the third oscillation core 3, an inductor L n,+ connecting the G n,- end and the G G,13-1 end arranged between the second oscillation core 2 and the fourth oscillation core 4, and an inductor L n,+ connecting the G n,- end and the G G,42-2 end arranged between the first oscillation core 1 and the third oscillation core 3.

[0019] The second transformer comprises: an inductor L n,+ connecting the D n,- end and the D D,23 end arranged between the second oscillation core 2 and the third oscillation core 3, an inductor L p,+ connecting the G p,- end and the G P,23 end arranged between the second oscillation core 2 and the fourth oscillation core 4, and an inductor L n,+ connecting the G n,- end and the G G,24-1 end arranged between the first oscillation core 1 and the third oscillation core 3. n,+ n,- G,13-2

[0020] ​​​The third transformer includes: a transformer disposed between the third oscillating core 3 and the fourth oscillating core 4 and connected to D n,+ End and D n,- The inductance L D,34 , connect G p,+ End and G p,- The inductance L at the end P,34 , is set between the first oscillation core 1 and the third oscillation core 3 and connected to G n,- End and G n,+ The inductance L G,31-1 , is set between the second oscillation core 2 and the fourth oscillation core 4 and connected to G n,- End and G n,+ The inductance L G,24-2 .

[0021] The fourth transformer includes: a first oscillating core 1 and a fourth oscillating core 4 disposed between the first oscillating core 1 and connected to the D n,+ End and D n,- The inductance L at the end D,41 , connect G p,+ End and G p,- The inductance L at the end P,41 , is set between the first oscillation core 1 and the third oscillation core 3 and connected to G n,- End and G n,+ The inductance L at the end G,31-2 , is set between the second oscillation core 2 and the fourth oscillation core 4 and connected to G n,- End and G n,+ The inductance L G,42-1 .

[0022] In the inductor connecting two adjacent oscillation cores, L D,12 , L D,23 , L D,34 , L D,41 The tap is V dd End, L P,12 , L P,23 , L P,34 , L p,41 The tap is V b,p End, connect the inductor L between non-adjacent oscillation cores G,13 , L G,24 , L G,31 , L G,42 The tap is V b,n end.

[0023] The inductor L D,12 , L D,23 , L D,34 , L D,41 With L P,12 , L P,23 , LP,34 , L P,41 They are all coupled in the same direction, so that the NMOS tube and PMOS tube on the same side are in the on or off state at the same time, reducing the noise current injected into the resonant cavity. The transient waveform is as follows Figure 4 shown.

[0024] like Figure 2 As shown, the oscillation core includes: NMOS transistor pair M1, M2, PMOS transistor pair M3, M4, variable capacitor array and switch capacitor array, wherein: the drain end of the first NMOS transistor M1 is connected to the capacitor array C D C in the switched capacitor array sw,+ terminal, C of the variable capacitor array var,+ The D ends are connected to form the oscillation core n,+ The gate terminal of the first NMOS transistor M1 and the capacitor array C G C in the switched capacitor array sw,+ terminal, C of the variable capacitor array var,+ The ends are connected to form the oscillation core G n,+ The drain terminal of the second NMOS transistor M2 and the capacitor array C D C in the switched capacitor array sw,- terminal, C of the variable capacitor array var,- The D ends are connected to form the oscillation core n,- The gate terminal of the second NMOS transistor M2 and the capacitor array C G C in the switched capacitor array sw,- terminal, C of the variable capacitor array var,- The ends are connected to form the oscillation core G n,- The gate terminal of the third PMOS transistor M3 and the switch capacitor array C P C sw,+ The ends are connected to form the oscillation core G p,+ The gate terminal of the third PMOS transistor M3 is connected to the switch capacitor array C P C sw,- The ends are connected to form the oscillation core G p,- end.

[0025] The PMOS transistor degrades the NMOS transistor in the circuit working device.

[0026] like Figure 2 As shown, the variable capacitor array includes: a pair of AC coupling capacitors C L , a pair of variable capacitors C V and a pair of bias resistors R L , where: the variable capacitor C in the variable capacitor array V,1 and C V,2One end is connected to each other and used as the off-chip frequency tuning voltage V ctrl The input node, variable capacitor C V,1 The other end of the AC coupling capacitor C L,1 , AC coupling bias resistor R L,1 One end of the variable capacitor C V,2 The other end of the AC coupling capacitor C L,2 , AC coupling bias resistor R L,2 One end of the AC coupling bias resistor R L,1 、R L,2 The other ends are connected to each other and serve as the bias voltage V bias Input node, AC coupling capacitor C L,1 、C L,2 The other end serves as the signal input node C of the variable capacitor array var,+ 、C var- Connected to the oscillating core.

[0027] The bias voltage Vbias is used to adjust the linearity of the continuous frequency tuning of the voltage controlled oscillator.

[0028] The switch capacitor array includes: a main switch tube M sw , a pair of auxiliary switch tubes M sw,b and a pair of switched capacitors C sw , where: main switch tube M sw The source terminal and capacitor C sw,1 One end of the auxiliary switch tube M sw,b1 The drain end of the switch tube M sw The drain terminal and capacitor C sw,2 One end of the auxiliary switch tube M sw,b2 The drain end of the switch tube M sw The gate terminal is used as the switch capacitor control signal d_sw_b <n>the input node of the auxiliary switch transistor M sw,b1 , M sw,b2 the gate terminal of the auxiliary switch transistor M bias the input node of the auxiliary switch transistor M sw,b1 , M sw,b2 the source terminals of the auxiliary switch transistors M <n>The input node, capacitor C sw,1 and C sw,2 The other end of the switch capacitor is used as the signal input node C sw,+ 、C sw,- Connected to the oscillating core.

[0029] The process coupling coefficient of the quad-core voltage controlled oscillator ,in: is the coupling coefficient under reference conditions, usually taken as 0.75, is the equivalent line width of the transformer inductance, is the inductance L D.12 , L D.23 , L D.34 , L D.41 Line width and inductor L G,13-1 , L G,13-2 , L G,31-1 , L G,31-2 , L G,24-1 , L G,24-2 , L G,42-1 , L G,42-2 Line width The geometric mean , is the coil width under reference conditions, which is 5 μm, and s is the edge spacing of the inductor coil. is the equivalent flux attenuation length of the metal, and the inductance L in the transformer is taken D.12 , L D.23 , L D.34 , L D.41 Line width and inductor L G,13-1 , L G,13-2 , L G,31-1 , L G,31-2 , L G,24-1 , L G,24-2 , L G,42-1 , L G,42-2 Arithmetic mean of flux decay length , where the flux decay length is , , is the asymmetry factor of the transformer inductance, given by Calculated.

[0030] The line width, spacing and other parameters of the inductance in the transformer are designed and calculated through the model formula. The inductance L at the D end is D.12 , L D.23 , L D.34 , L D.41 Line width Take 12μm, G-end inductor L G,13-1 , L G,13-2 , L G,31-1 , L G,31-2 , L G,24-1 , L G,24-2 , L G,42-1 , L G,42-2 Line width Taking 10μm and the distance s between the two inductors as 2μm, the coupling coefficient k=0.702~0.743 can be obtained.

[0031] According to the harmonic control technology, the resonant frequency relationship between the primary and secondary inductance resonant cavities satisfies , connect the inductor L at the D end D.12 , L D.23 , L D.34 , L D.41 and G-terminal inductor L G,13-1 , L G,13-2 , L G,31-1 , L G,31-2 , L G,24-1 , L G,24-2 , L G,42-1 , L G,42-2 The inductance value is set to 1:3, and the D-terminal capacitor C D and G terminal capacitor C G Set to 1:1, set the resonant frequency of the G-end resonant cavity in the voltage-controlled oscillator to the fundamental frequency, and the resonant frequency of the D-end resonant cavity to the third harmonic frequency, to achieve the shaping of the output clock signal, improve the slew rate of the voltage flip device, reduce the impact of noise modulation on noise performance, and provide additional passive voltage gain from the drain to the gate of the NMOS pair. D.12 , L D.23 , L D.34 , L D.41 Connect adjacent resonant cavities, inductor L G,13-1 , L G,13-2 , L G,31-1 , L G,31-2 , L G,24-1 , L G,24-2 , L G,42-1 , L G,42-2 Connecting non-adjacent resonant cavities suppresses noise performance loss due to frequency mismatch between oscillating cores.

[0032] like Figure 7 As shown, it is the plan view of the segmented ring three-wire transformer for high-order harmonic control multi-core voltage-controlled oscillator. The inductor L D , L G It is implemented using the top metal M8 and uses the second top metal M7 for layer connection at the intersection. P Use AP layer metal for wiring. L in toroidal transformer D , L G , L P The inductors are connected through metal resistors with a value of about 5Ω to avoid latching and oscillation mode ambiguity.

[0033] In the non-targeted even-mode oscillation mode, adjacent oscillation cores output in-phase signals, which must be transmitted through metal resistors. In this mode, the oscillation gain is significantly reduced, suppressing even-mode oscillation. In the odd-mode oscillation mode, adjacent oscillation cores output anti-phase signals, and the metal resistors are virtually short-circuited, without affecting the oscillator.

[0034] like Figure 5 As shown, this is the frequency tuning range curve of the quad-core voltage-controlled oscillator in the embodiment. By synchronously controlling the switch capacitor array and the variable capacitor array of each oscillation core in the quad-core voltage-controlled oscillator, the frequency of the oscillator output signal is tuned to achieve a frequency output of 14.2GHz~16GHz.

[0035] like Figure 6 Figure 2 shows the phase noise results of the output signal of the quad-core voltage-controlled oscillator in the full frequency tuning range at 100kHz, 1MHz, and 10MHz frequency offsets. Using the noise suppression techniques proposed in the examples, the oscillator output signal achieves a minimum phase noise of -95.42dBc / Hz at a 100kHz frequency offset, -121.8dBc / Hz at a 1MHz frequency offset, and -144.8dBc / Hz at a 10MHz frequency offset.

[0036] Compared to existing technologies, this invention uses a dual-path synchronization scheme to suppress noise performance losses caused by oscillating core frequency mismatch, while also providing additional passive voltage gain from the drain to the gate. This improves the matching between successive resonant cavities, designs appropriate coupling coefficients between coils in a three-wire transformer, and achieves improvements in third- and fifth-order resonant gain. The output signal is shaped to generate a square wave signal, reducing signal inversion time and the conversion of circuit noise to phase noise. A noise recycling technique allows the NMOS and PMOS transistors on the same side to be simultaneously on or off, reducing power consumption of the voltage-controlled oscillator and noise current injected into the resonant cavity.

[0037] The above-mentioned specific implementation can be partially adjusted in different ways by those skilled in the art without departing from the principles and purpose of the present invention. The scope of protection of the present invention shall be based on the claims and shall not be limited by the above-mentioned specific implementation. All implementation schemes within its scope shall be subject to the constraints of the present invention.< / n> < / n>

Claims

1. A low-noise quad-core voltage-controlled oscillator with high-order harmonic control, characterized in that: include: Four ring-connected oscillation cores, where: D of each oscillation core n,+ The two inductors L D D of the adjacent oscillation core n,- The G of each oscillating core is connected to p,+ The two inductors L P G of the adjacent oscillating core p,- The G of each oscillating core is connected to n,+ The four inductors L G With the relative oscillation core G n,- Ends connected; The segmented annular three-wire transformer is specifically four three-wire transformers arranged symmetrically with respect to the center.

2. The high-harmonic controlled low-noise quad-core voltage-controlled oscillator according to claim 1, characterized in that: In the segmented toroidal three-wire transformer, the first transformer includes: a first oscillating core 1 and a second oscillating core 2 and connected to D n,+ End and D n,- The inductance L D,12 , connect G p,+ End and G p,- The inductance L P,12 , is set between the first oscillation core 1 and the third oscillation core 3 and connected to G n,+ End and G n,- The inductance L G,13-1 , is set between the second oscillation core 2 and the fourth oscillation core 4 and connected to G n,+ End and G n,- The inductance L G,42-2 ; The second transformer includes: a transformer disposed between the second oscillating core 2 and the third oscillating core 3 and connected to D n,+ End and D n,- The inductance L D,23 , connect G p,+ End and G p,- The inductance L P,23 , is set between the second oscillation core 2 and the fourth oscillation core 4 and connected to G n,+ End and G n,- The inductance L G,24-1 , is set between the first oscillation core 1 and the third oscillation core 3 and connected to G n,+ End and G n,- The inductance L G,13-2 ; The third transformer includes: a transformer provided between the third oscillating core 3 and the fourth oscillating core 4 and connected to D n,+ End and D n,- The inductance L D,34 , connect G p,+ End and G p,- The inductance L P,34 , is set between the first oscillation core 1 and the third oscillation core 3 and connected to G n,- End and G n,+ The inductance L G,31-1 , is set between the second oscillation core 2 and the fourth oscillation core 4 and connected to G n,- End and G n,+ The inductance L G,24-2 ; The fourth transformer includes: a first oscillating core 1 and a fourth oscillating core 4 disposed between the first oscillating core 1 and connected to the D n,+ End and D n,- The inductance L D,41 , connect G p,+ End and G p,- The inductance L P,41 , is set between the first oscillation core 1 and the third oscillation core 3 and connected to G n,- End and G n,+ The inductance L G,31-2 , is set between the second oscillation core 2 and the fourth oscillation core 4 and connected to G n,- End and G n,+ The inductance L G,42-1 .

3. The high-harmonic controlled low-noise quad-core voltage-controlled oscillator according to claim 2, wherein The inductor connecting two adjacent oscillating cores, L D,12 、L D,23 、L D,34 、L D,41 The tap is V dd End, L P,12 、L P,23 、L P,34 、L p,41 The tap is V b,p End, connect the inductor L between non-adjacent oscillation cores G,13 、L G,24 、L G,31 、L G,42 The tap is V b,n end.

4. The high-harmonic controlled low-noise quad-core voltage-controlled oscillator according to claim 2, wherein: The inductor L D,12 、L D,23 、L D,34 、L D,41 With L P,12 、L P,23 、L P,34 、L P,41 They are all coupled in the same direction, so that the NMOS tube and PMOS tube on the same side are in the on or off state at the same time, reducing the noise current injected into the resonant cavity.

5. The high-harmonic controlled low-noise quad-core voltage-controlled oscillator according to claim 1, characterized in that: The oscillation core includes: NMOS transistor pair M1, M2, PMOS transistor pair M3, M4, variable capacitor array and switch capacitor array, wherein: the drain end of the first NMOS transistor M1 is connected to the capacitor array C D C in the switched capacitor array sw,+ terminal, C of the variable capacitor array var,+ The D ends are connected to form the oscillation core n,+ The gate terminal of the first NMOS transistor M1 and the capacitor array C G C in the switched capacitor array sw,+ terminal, C of the variable capacitor array var,+ The ends are connected to form the oscillation core G n,+ The drain terminal of the second NMOS transistor M2 and the capacitor array C D C in the switched capacitor array sw,- terminal, C of the variable capacitor array var,- The D ends are connected to form the oscillation core n,- The gate terminal of the second NMOS transistor M2 and the capacitor array C G C in the switched capacitor array sw,- terminal, C of the variable capacitor array var,- The ends are connected to form the oscillation core G n,- The gate terminal of the third PMOS transistor M3 and the switch capacitor array C P C sw,+ The ends are connected to form the oscillation core G p,+ The gate terminal of the third PMOS transistor M3 is connected to the switch capacitor array C P C sw,- The ends are connected to form the oscillation core G p,- end.

6. The high-harmonic controlled low-noise quad-core voltage-controlled oscillator according to claim 5, characterized in that: The variable capacitor array includes: a pair of AC coupling capacitors C L , a pair of variable capacitors C V and a pair of bias resistors R L , where: the variable capacitor C in the variable capacitor array V,1 and C V,2 One end is connected to each other and used as the off-chip frequency tuning voltage V ctrl The input node, variable capacitor C V,1 The other end of the AC coupling capacitor C L,1 , AC coupling bias resistor R L,1 One end of the variable capacitor C V,2 The other end of the AC coupling capacitor C L,2 , AC coupling bias resistor R L,2 One end of the AC coupling bias resistor R L,1 、R L,2 The other ends are connected to each other and serve as the bias voltage V bias Input node, AC coupling capacitor C L,1 、C L,2 The other end serves as the signal input node C of the variable capacitor array var,+ 、C var- Connected to the oscillating core.

7. The high-harmonic controlled low-noise quad-core voltage-controlled oscillator according to claim 5, characterized in that: The switch capacitor array includes: a main switch tube M sw , a pair of auxiliary switch tubes M sw,b and a pair of switched capacitors C sw , where: main switch tube M sw The source terminal and capacitor C sw,1 One end of the auxiliary switch tube M sw,b1 The drain end of the switch tube M sw The drain terminal and capacitor C sw,2 One end of the auxiliary switch tube M sw,b2 The drain end of the switch tube M sw The gate terminal is used as the switch capacitor control signal d_sw_b <n>The input node of the auxiliary switch tube M sw,b1 、M sw,b2 The gate terminal is connected to the chip and used as the off-chip bias voltage V bias The input node of the auxiliary switch tube M sw,b1 、M sw,b2 The source terminals of the switch capacitors are connected to each other and serve as the switch capacitor control signal d_sw <n>The input node, capacitor C sw,1 and C sw,2 The other end of the switch capacitor is used as the signal input node C sw,+ 、C sw,- Connected to the oscillating core.< / n> < / n> 8. The high-harmonic controlled low-noise quad-core voltage-controlled oscillator according to any one of claims 1 to 7, characterized in that: The process coupling coefficient of the quad-core voltage controlled oscillator ,in: is the coupling coefficient under reference conditions, is the equivalent line width of the transformer inductance, is the inductance L D.12 、L D.23 、L D.34 、L D.41 Line width and inductor L G,13-1 、L G,13-2 、L G,31-1 、L G,31-2 、L G,24-1 、L G,24-2 、L G,42-1 、L G,42-2 Line width The geometric mean , is the coil width under reference conditions, s is the edge spacing of the inductor coil, is the equivalent flux attenuation length of the metal, and the inductance L in the transformer is taken D.12 、L D.23 、L D.34 、L D.41 Line width and inductor L G,13-1 、L G,13-2 、L G,31-1 、L G,31-2 、L G,24-1 、L G,24-2 、L G,42-1 、L G,42-2 Arithmetic mean of flux decay length , is the asymmetry factor of the transformer inductance.

9. The high-harmonic controlled low-noise quad-core voltage-controlled oscillator according to any one of claims 1 to 7, characterized in that: The resonant frequency relationship between the primary and secondary inductance resonant cavities satisfies , D-terminal inductor L D.12 、L D.23 、L D.34 、L D.41 and G-terminal inductor L G,13-1 、L G,13-2 、L G,31-1 、L G,31-2 、L G,24-1 、L G,24-2 、L G,42-1 、L G,42-2 The inductance value is set to 1:3, and the D-terminal capacitor C D and G terminal capacitor C G Set it to 1:1, set the resonant frequency of the G-end resonant cavity in the voltage-controlled oscillator to the fundamental frequency, and the resonant frequency of the D-end resonant cavity to the third harmonic frequency.

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