Full-perovskite latch-free complementary photosensitive field effect transistor and preparation method thereof

Abstract

The invention discloses a full-perovskite latch-free complementary photosensitive field effect transistor and a preparation method thereof. The full-perovskite latch-free complementary photosensitive field effect transistor comprises a substrate; the buffer layer is positioned above the substrate; the N-type perovskite functional layer and the P-type perovskite functional layer are located above the two ends of the buffer layer respectively; the source electrode and the drain electrode are respectively positioned above the two ends of the N-type perovskite functional layer and the P-type perovskite functional layer; the dielectric layer is positioned above the N-type perovskite functional layer and the P-type perovskite functional layer and is positioned between the source electrode and the drain electrode; the gate electrode is positioned above the dielectric layer; and the isolation layer is positioned above the buffer layer. According to the invention, the complementary photosensitive field effect transistor is constructed through the P-type or N-type characteristic presented by perovskite, and the latch-up effect of the complementary photosensitive field effect transistor is eliminated and the layout design is simplified by adopting the cooperation technology of the buffer layer, the perovskite functional layer and the isolation layer of the full perovskite strategy.

Description

Technical Field

[0001] The present invention belongs to the technical field of optoelectronic semiconductors, and in particular relates to an all-perovskite latch-free complementary photosensitive field-effect transistor and a preparation method thereof. Background Art

[0002] Optoelectronic integrated circuits integrate optical devices and electronic components onto a single chip, enabling efficient conversion and processing of optical and electrical signals. Photodetectors, a key component of optoelectronic integrated circuits, perform the conversion from optical to electrical signals and are widely used in diverse scientific and industrial fields, including biological / chemical sensing, video / biological / medical imaging, optical communications, and fire / environmental monitoring. They play a vital role in the modern information society. Among various photodetectors, photosensitive field-effect transistors (PFETs), due to their inherent amplification capability and high internal photocurrent gain, hold enormous potential for development.

[0003] Traditional integrated circuit devices are fabricated on silicon substrates through doping. For photosensitive field-effect transistors (PFETs), achieving photosensitivity in the functional layer is difficult. Silicon substrates have poor light transmittance, and incident light has difficulty penetrating the electrodes to reach the functional layer. More seriously, the silicon-based doping method introduces parasitic transistor-level circuit structures into complementary metal-oxide-semiconductor (CMOS) circuits, which can cause latch-up and render the device inoperable. Therefore, a new and simple PFET technology is needed that eliminates latch-up without increasing process complexity.

[0004] How to construct and prepare a new type of simple complementary photosensitive field-effect transistor with optoelectronic dual-control characteristics that eliminates the latch effect has become an urgent problem that needs to be solved. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a full perovskite latch-free complementary photosensitive field-effect transistor and a method for preparing the same. The technical problem to be solved by the present invention is achieved through the following technical solutions: An all-perovskite latch-free complementary photosensitive field-effect transistor, comprising: Substrate 1; a buffer layer 2, located above the substrate 1; The N-type perovskite functional layer 3 and the P-type perovskite functional layer 4 are respectively located above the two ends of the buffer layer 2; The source electrode 51 and the drain electrode 52 are respectively located above the N-type perovskite functional layer 3 and the P-type perovskite functional layer 4; a dielectric layer 6 , located above the N-type perovskite functional layer 3 and the P-type perovskite functional layer 4 , and between the source electrode 51 and the drain electrode 52 ; a gate electrode 8 located above the dielectric layer 6; The isolation layer 7 is located above the buffer layer 2 and between the source electrode 51 and the gate electrode 8 and between the drain electrode 52 and the gate electrode 8 .

[0006] In a specific embodiment, the substrate 1 is any one of glass, polyimide, polyethylene terephthalate, and polyethylene naphthalate.

[0007] In a specific embodiment, the buffer layer 2, the dielectric layer 6 and the isolation layer 7 are any one of N-chloromethyl-1,4-diazacyclo[2.2.2]octanium-ammonium-hexafluorophosphate two-dimensional all-organic perovskite and N-bromomethyl-1,4-diazacyclo[2.2.2]octanium-ammonium-hexafluorophosphate two-dimensional all-organic perovskite.

[0008] In a specific embodiment, the N-type perovskite functional layer 3 is a nanowire perovskite, a two-dimensional perovskite, a quasi-two-dimensional perovskite or a three-dimensional perovskite having N-type transfer characteristics.

[0009] In a specific embodiment, the N-type perovskite functional layer 3 is Cs2SnI6, (RNH3)2MA n-1 Pb n X 3n+1 Any one of the following, wherein RNH3 is PEA or BA, X is Cl, Br or I, and the value of n is 1-5.

[0010] In a specific embodiment, the P-type perovskite functional layer 4 is a nanowire perovskite, a two-dimensional perovskite, a quasi-two-dimensional perovskite or a three-dimensional perovskite having a P-type transfer characteristic.

[0011] In a specific embodiment, the P-type perovskite functional layer 4 is (Cs x FA 1-x )PEA2Sn8I 25 、(RNH3)2FA n-1 Sn n X 3n+1 , FASnX3, wherein RNH3 is PEA or BA, X is Cl, Br or I, and n is a positive integer.

[0012] In a specific embodiment, the source electrode 51, the drain electrode 52 and the gate electrode 8 are any one of indium tin oxide, fluorine-doped tin oxide, ultra-thin metal Au, ultra-thin metal Ag, ultra-thin metal Cu, ultra-thin metal Al, silver nanowires, graphene, poly (3,4-ethylenedioxythiophene) -poly (styrene sulfonate), and carbon-based nanomaterials.

[0013] In one specific embodiment, the thickness of the substrate 1 is 50-500 μm; the thickness of the buffer layer 2 is 50-300 nm; the thickness of the N-type perovskite functional layer 3 and the P-type perovskite functional layer 4 is 100-1000 nm; the thickness of the dielectric layer 6 is 50-300 nm; the thickness of the isolation layer 7 is 45-1350 nm; and the thickness of the source electrode 51, the drain electrode 52 and the gate electrode 8 is 5-50 nm.

[0014] The application also provides a preparation method of the full-perovskite latch-free complementary photosensitive field effect transistor. A device substrate is obtained, and the substrate is pretreated. A buffer layer is grown on the surface of the pretreated substrate. A first isolation layer and a perovskite functional layer are grown on the surface of the buffer layer; the first isolation layer and the perovskite functional layer are highly flush, and the perovskite functional layer comprises an N-type perovskite functional layer and a P-type perovskite functional layer. A source electrode, a drain electrode and a dielectric layer are respectively grown on the surface of the perovskite functional layer, and a second isolation layer is grown on the surface of the first isolation layer, the source electrode and the drain electrode. A gate electrode and a third isolation layer are grown on the surface of the dielectric layer and the second isolation layer. The first isolation layer, the second isolation layer and the third isolation layer form a total isolation layer.

[0015] The application has the following advantages: 1. The application provides a full-perovskite latch-free complementary photosensitive field effect transistor with a buffer layer, which has the effects of mechanical support of the buffer layer and the substrate, reduction of stress of the substrate and the perovskite functional layer caused by thermal expansion, elimination of the influence of substrate traps or defects on carrier behavior, etc., greatly improving the reliability of device operation. 2. The application provides a CMOS-like complementary field effect transistor technology, which integrates P-type and N-type perovskite functional layers to realize the complementation of the photosensitive field effect transistor by containing the perovskite functional layer between the buffer layer and the source electrode or the drain electrode, and uses the isolation layer to realize electrical protection and inhibit signal coupling effect between transistors. 3. The application provides a complementary field effect transistor technology without latch-up effect, which is constructed by P-type or N-type characteristics of perovskite itself, discards the traditional ion doping technology causing the transistor parasitic effect, adopts a full perovskite strategy of buffer layer, functional layer, isolation layer and dielectric layer, that is, each layer (buffer layer, functional layer, isolation layer and dielectric layer) is composed of perovskite material, and a technical system formed by the synergistic effect of the multi-layer structure, so that the complementary photosensitive field effect transistor eliminates the latch-up effect and simplifies the layout design. 4. The full perovskite latch-up-free complementary photosensitive field effect transistor has the characteristics of photoelectric double control, low cost, high reliability, high sensitivity, high photoelectric conversion efficiency, fast response, high mobility and easy integration, and has great application potential in the field of photoelectric semiconductors, such as photoelectric integrated circuits.

[0016] The application will be further described in detail below with reference to the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0017] Figure 1 is a full perovskite latch-up-free complementary photosensitive field effect transistor process schematic diagram provided by the application; Figure 2 is a flow chart of a preparation method of a full perovskite latch-up-free complementary photosensitive field effect transistor provided by the application; Figure 3a to Figure 3e is a process schematic diagram of a preparation method of a full perovskite latch-up-free complementary photosensitive field effect transistor provided by the application. DETAILED DESCRIPTION

[0018] The application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0019] Embodiment one Please refer to Figure 1 , Figure 1 is a structure schematic diagram of a full perovskite latch-up-free complementary photosensitive field effect transistor provided by the application, which comprises: a substrate 1; a buffer layer 2 located above the substrate 1; an N-type perovskite functional layer 3 and a P-type perovskite functional layer 4, which are respectively located above both ends of the buffer layer 2; a source electrode 51 and a drain electrode 52, which are respectively located above both ends of the N-type perovskite functional layer 3 and the P-type perovskite functional layer 4; a dielectric layer 6 located above the N-type perovskite functional layer 3 and the P-type perovskite functional layer 4, and between the source electrode 51 and the drain electrode 52; a gate electrode 8 above the dielectric layer 6; a spacer layer 7 above the buffer layer 2, and between the source electrode 51 and the gate electrode 8, and between the drain electrode 52 and the gate electrode 8.

[0020] The device substrate of the embodiment is generally a substrate with certain transparency, which can be, but is not limited to, glass, polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN).

[0021] Preferably, the substrate 1 is any one of glass, PI, PET, and PEN.

[0022] The buffer layer 2, the dielectric layer 6, and the spacer layer 7 of the embodiment can be, but are not limited to, N-chloromethyl-1,4-diazabicyclo[2.2.2]octenium-ammonium-hexafluorophosphate two-dimensional full-organic perovskite (CMD-N-P2) or N-bromomethyl-1,4-diazabicyclo[2.2.2]octenium-ammonium-hexafluorophosphate two-dimensional full-organic perovskite (BMD-N-P2), which are full-organic perovskites with large band gaps. Further, the CMD-N-P2 and BMD-N-P2 need to be saturated in acetone and single crystals are precipitated by slow diffusion of 1,2-dichloroethane.

[0023] Preferably, the buffer layer 2, the dielectric layer 6, and the spacer layer 7 are any one of CMD-N-P2 and BMD-N-P2, which are full-organic perovskites with large band gaps.

[0024] The N-type perovskite functional layer 3 of the embodiment is a nanowire perovskite, a two-dimensional perovskite, a quasi-two-dimensional perovskite, or a three-dimensional perovskite with N-type transfer characteristics.

[0025] The N-type perovskite functional layer 3 of the embodiment can be, but is not limited to, any one of Cs2SnI6, (RNH3)2MA n- 1Pb n X 3n+1 , RNH3 is PEA or BA, X is Cl, Br, or I, and n is 1-5.

[0026] Preferably, the N-type perovskite functional layer 3 is any one of Cs2SnI6, (RNH3)2MA n-1 Pb n X 3n+1 , RNH3 is PEA or BA, X is Cl, Br, or I, and n is 1-5.

[0027] The P-type perovskite functional layer 4 of this embodiment is a nanowire perovskite, a two-dimensional perovskite, a quasi-two-dimensional perovskite or a three-dimensional perovskite having a P-type transfer characteristic.

[0028] The P-type perovskite functional layer 4 of this embodiment can be made of but not limited to (Cs x FA 1-x )PEA2Sn8I 25 、(RNH3)2FA n-1 Sn n X 3n+1 , FASnX3, wherein RNH3 is PEA or BA, X is Cl, Br or I, and n is a positive integer; the P-type perovskite functional layer 4 can be prepared from a precursor solution dissolved in methanol, N,N-dimethylformamide (DMF), dimethyl sulfoxide (DMSO) or a mixed solvent of DMF and DMSO.

[0029] Preferably, the P-type perovskite functional layer 4 is (Cs x FA 1-x )PEA2Sn8I 25 、(RNH3)2FA n-1 Sn n X 3n+1 , FASnX3, wherein RNH3 is PEA or BA, X is Cl, Br or I, and n is a positive integer.

[0030] The source electrode 51, the drain electrode 52 and the gate electrode 8 of this embodiment have a certain degree of light transmittance, and can be made of, but not limited to, any one of indium tin oxide (ITO), fluorine-doped tin oxide (FTO), ultra-thin metal, silver nanowire, graphene (GR), poly (3,4-ethylenedioxythiophene) - poly (styrene sulfonate) (PEDOT:PSS), and carbon-based nanomaterials.

[0031] Preferably, the source electrode 51 , the drain electrode 52 and the gate electrode 8 are any one of ITO, FTO, ultra-thin metal Au, ultra-thin metal Ag, ultra-thin metal Cu, ultra-thin metal Al, silver nanowire, GR, PEDOT:PSS, and carbon-based nanomaterials.

[0032] In this embodiment, the thickness of the substrate 1 is 50-500 μm; the thickness of the buffer layer 2 is 50-300 nm; the thickness of the N-type perovskite functional layer 3 and the P-type perovskite functional layer 4 is 100-1000 nm; the thickness of the dielectric layer 6 is 50-300 nm; the thickness of the isolation layer 7 is 45-1350 nm; the thickness of the source electrode 51, the drain electrode 52 and the gate electrode 8 is 5-50 nm.

[0033] The buffer layer of this embodiment adopts an all-organic perovskite, which has the characteristics of large band gap and flexibility. Among them, the large band gap can suppress carrier recombination, and the flexibility can adapt to flexible substrates, which enables the substrate to overcome the brittleness limitation of traditional inorganic perovskites. At the same time, it has a high degree of lattice matching with the perovskite in the N / P-type functional layer, which can reduce interface defects and improve carrier transmission efficiency; the large band gap of the all-organic perovskite can shield defects such as hydroxyl groups and metal ions in the glass substrate; the use of all-organic perovskite as a buffer layer forms an integrated system of all-perovskites with the functional layer, dielectric layer and isolation layer, avoiding the problem of charge accumulation at the interface. It is also one of the key structures for collaboratively eliminating the latch-up effect, providing double protection.

[0034] Preferably, in an embodiment provided by the present invention, the substrate 1 is selected as glass, the buffer layer 2 is selected as CMD-N-P2, the isolation layer 7 is selected as CMD-N-P2, the N-type perovskite functional layer 3 is selected as Cs2SnI6, the P-type perovskite functional layer 4 is selected as (PEA)2SnI4, the source electrode 51 and the drain electrode 52 are selected as ultra-thin Ag, the dielectric layer 6 is selected as BMD-N-P2 and the gate electrode 8 is selected as ultra-thin Ag, wherein the glass substrate carries the entire complementary photosensitive field effect transistor device.

[0035] Preferably, in an embodiment provided by the present invention, the thickness of the substrate 1 is 300 μm; the thickness of the buffer layer 2 is about 160 nm; the thickness of the N-type perovskite functional layer 3 and the P-type perovskite functional layer 4 is 500 nm; the thickness of the dielectric layer 6 is 100 nm; the thickness of the isolation layer 7 is 80~620 nm; the thickness of the source electrode 51, the drain electrode 52, and the gate electrode 8 is 20 nm.

[0036] Example 2 See Figure 2 , Figure 2 This is a flow chart of a method for preparing a full perovskite latch-free complementary photosensitive field-effect transistor provided by an embodiment of the present invention, comprising: S1. Obtain a device substrate 1 and perform pre-treatment on the substrate 1, such as Figure 3a Shown; including: S11. The obtained device substrate 1 was ultrasonically cleaned with N-methylpyrrolidone (NMP), isopropyl alcohol (IPA), and acetone for at least 15 minutes respectively; Preferably, the substrate 1 is glass with a thickness of 300 nm and a cleaning time of 20 minutes; S12. After step S11, the substrate 1 was ultrasonically cleaned with deionized water for at least 20 minutes and dried with nitrogen gas; Preferably, the cleaning time is 30 minutes; S2. The buffer layer 2 is grown on the surface of the substrate after pre-treatment, as Figure 3b Shown; including: S21. Prepare a saturated buffer solution dissolved in acetone; Preferably, N-chloromethyl-1,4-diazabicyclo[2.2.2]octane hexafluorophosphate (CMD-PF6) and ammonium hexafluorophosphate (NH4PF6) are dissolved in acetone at a ratio of 1:2 until saturated to prepare a saturated solution of the buffer layer dissolved in acetone; S22. The saturated solution in the buffer layer is saturated with 1,2-dichloroethane so that the buffer layer slowly precipitates a single crystal; In a specific embodiment of the present invention, 1,2-dichloroethane is injected into the saturated solution of the buffer layer as an anti-solvent, and the difference in solubility between the anti-solvent and acetone is utilized to induce the slow precipitation of the solute, so that the single crystal grows freely in the solution; the growth time of the single crystal is 12 to 48 hours, and the growth temperature is room temperature; Preferably, the buffer layer saturated solution is slowly diffused through 1,2-dichloroethane to precipitate CMD-N-P2 single crystals; S23. Dry-transferring the single crystal to form the buffer layer 2 on the substrate surface; Among them, dry transfer is to transfer the single crystal to the substrate after the single crystal is generated. First, the single crystal is freely grown in the solution, and then the grown single crystal is transferred by dry transfer. Preferably, a 160 nm thick CMD-N-P2 single crystal sheet is dry-transferred onto the device substrate to form the buffer layer 2; The controlled growth of the single crystal thin film of this embodiment is achieved by first dissolving the material in acetone to form a saturated solution, using 1,2-dichloroethane as an anti-solvent to induce its growth, and then transferring it to the substrate by dry transfer, avoiding contamination by solvent residues. The single crystal can also improve the uniformity of the film and reduce grain boundary defects, thereby simplifying the process and improving compatibility.

[0037] S3. Growing a first isolation layer 71 and a perovskite functional layer on the surface of the buffer layer 2, such as Figure 3c As shown; wherein, the first isolation layer 71 and the perovskite functional layer are highly flush, and the perovskite functional layer includes an N-type perovskite functional layer 51 and a P-type perovskite functional layer 52; including: S31. Preparing a first mask having a first spacer layer interlaced with each other; S32. The first mask is tightly bonded to the buffer layer 2, and the functional layer perovskite is filled at the first isolation layer 71 by diffusion growth or dry transfer; Preferably, the first mask is tightly bonded to the buffer layer 2, and CMD-N-P2 all-organic perovskite is filled at the first isolation layer 71 by diffusion growth. Specifically, CMD-PF6 and NH4PF6 are dissolved in acetone at a ratio of 1:2 until saturation, and 1,2-dichloroethane is used as an anti-solvent to precipitate a single crystal of CMD-N-P2. S33. Preparing a perovskite precursor solution for dissolving N-type perovskite 3 and P-type perovskite 4; Preferably, a precursor solution of Cs2SnI6 of N-type perovskite 3 and (PEA)2SnI4 of P-type perovskite 4 is prepared; S34. Remove the first mask and fill the area except the first isolation layer 71 with a perovskite precursor solution; Preferably, the first mask is removed, and the area 71 except the first isolation layer is filled with Cs2SnI6 and (PEA)2SnI4 perovskite precursor solutions at a rotation speed of 4000 rpm for 30 s. S35. Annealing and laterally removing the top first isolation layer 71 and the portion of the perovskite functional layer exceeding the specified thickness, so that the first functional layer and the perovskite functional layer surface are highly flush, providing a flat interface for subsequent electrode deposition; Preferably, annealing is performed in a vacuum at 100° C. for 1 hour and the first isolation layer 71 and the perovskite functional layer with a thickness exceeding 200 nm are laterally removed; S4. A source electrode 51, a drain electrode 52 and a dielectric layer 6 are grown on the surface of the perovskite functional layer, and a second isolation layer 72 is grown on the surface of the first isolation layer 71, the source electrode 51 and the drain electrode 52, respectively. Figure 3d Shown; including: S41. Preparing a second mask in which the source electrode 51 or the drain electrode 52 is distributed, and a third mask in which the dielectric layer 6 and the second isolation layer 72 are alternately distributed; S42. The second mask is tightly combined with the perovskite functional layer to prepare an electrode at the source electrode 51 or the drain electrode 52; Preferably, the second mask is tightly combined with the Cs2SnI6 and (PEA)2SnI4 perovskite functional layers, and an ultra-thin Ag electrode is grown at the source electrode 51 or the drain electrode 52 by vacuum thermal evaporation. The thickness of the ultra-thin Ag electrode is 20 nm. S43 removes the second mask, tightly combines the third mask with the perovskite functional layer, and fills the dielectric layer 6 and the second isolation layer 72 with the fully organic perovskite by diffusion growth or dry transfer; Preferably, the second mask is removed, and the third mask is tightly combined with the Cs2SnI6 and (PEA)2SnI4 perovskite functional layers, and the BMD-N-P2 and CMD-N-P2 all-organic perovskites are filled in the dielectric layer 6 and the second isolation layer 72 respectively by dry transfer; S44 removes the third mask, the second mask and the dielectric layer 6, the source electrode 51 or the drain electrode 52 are tightly combined, and the second isolation layer 72 is filled on the upper surface of the source electrode 51 or the drain electrode 52; Preferably, the third mask is removed, the second mask is tightly combined with the dielectric layer 6, the source electrode 51 and the drain electrode 52, and the second isolation layer 72 is filled on the upper surface of the source electrode 51 and the drain electrode 52 by dry transfer; S45 . Remove the second mask and laterally remove the top dielectric layer 6 and the top second isolation layer 72 above the source electrode 51 or the drain electrode 52 .

[0038] Preferably, the second mask is removed, and the portion of the dielectric layer 6 and the second isolation layer 72 that is more than 100 nm thick on the top of the source electrode 51 and the drain electrode 52 is laterally removed; S5. The gate electrode 8 and the third isolation layer 73 are grown on the surface of the dielectric layer 6 and the second isolation layer 72, as Figure 3e As shown; Preferably, a 20 nm thick ultra-thin Ag gate electrode 8 is grown on the upper surface of the dielectric layer 6 and the second isolation layer 72 by vacuum thermal evaporation, and a 20 nm thick CMD-N-P2 isolation layer is transferred by dry method; In one embodiment of the present invention, the gate electrode 8 and the third isolation layer are grown on the surface of the dielectric layer 6 and the second isolation layer 72, including: S51. Preparing a fourth mask having 8 interlaced gate electrodes; S52. The fourth mask is tightly combined with the second isolation layer 72 and the dielectric layer 6 to prepare an electrode at the gate electrode 8; Preferably, the fourth mask is tightly bonded to the second isolation layer 72 and the dielectric layer 6, and a 20 nm thick ultra-thin Ag layer is deposited on the gate electrode 8 by vacuum thermal evaporation. The third isolation layer 73 is filled on the surface of the ultra-thin Ag gate electrode 8 by dry transfer; wherein the second isolation layer 72 and the third isolation layer are CMD-N-P2, and the dielectric layer 6 is BMD-N-P2; S53. Remove the fourth mask and perform vacuum annealing to enhance contact.

[0039] Preferably, the fourth mask is removed, and the portion of the third isolation layer with a thickness exceeding 20 nm on the top of the gate electrode 8 is laterally removed, and annealing is performed at 100° C. in a vacuum for 1 hour to enhance contact.

[0040] In one embodiment of the present application, the first isolation layer 71, the second isolation layer 72, and the third isolation layer 73 form an isolation layer 7.

[0041] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Also, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in an appropriate manner. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in the present specification.

[0042] Although the present application is described herein in conjunction with various embodiments, those skilled in the art will appreciate that other variations of the disclosed embodiments are possible in light of the description and drawings, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite articles "a" or "an" do not exclude a plurality. A single processor or other unit can fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0043] The above is a further detailed description of the present application in conjunction with specific preferred embodiments, and the specific implementation of the present application cannot be limited to these descriptions. For those skilled in the art to which the present application belongs, a number of simple deductions or substitutions can be made without departing from the concept of the present application, and all of them should be considered as falling within the scope of protection of the present application.

Claims

1. An all-perovskite latch-free complementary photosensitive field-effect transistor, characterized in that: include: substrate (1); a buffer layer (2) located above the substrate (1); An N-type perovskite functional layer (3) and a P-type perovskite functional layer (4), respectively located above both ends of the buffer layer (2); A source electrode (51) and a drain electrode (52) are respectively located above the ends of the N-type perovskite functional layer (3) and the P-type perovskite functional layer (4); a dielectric layer (6) located above the N-type perovskite functional layer (3) and the P-type perovskite functional layer (4), and between the source electrode (51) and the drain electrode (52); a gate electrode (8) located above the dielectric layer (6); An isolation layer (7) is located above the buffer layer (2) and between the source electrode (51) and the gate electrode (8), and between the drain electrode (52) and the gate electrode (8).

2. The all-perovskite latch-free complementary photosensitive field-effect transistor according to claim 1, characterized in that: The substrate (1) is any one of glass, polyimide, polyethylene terephthalate, and polyethylene naphthalate.

3. The all-perovskite latch-free complementary photosensitive field-effect transistor according to claim 1, characterized in that: The buffer layer (2), the dielectric layer (6) and the isolation layer (7) are any one of N-chloromethyl-1,4-diazacyclo[2.2.2]octyl ammonium-ammonium-hexafluorophosphate two-dimensional all-organic perovskite and N-bromomethyl-1,4-diazacyclo[2.2.2]octyl ammonium-ammonium-hexafluorophosphate two-dimensional all-organic perovskite.

4. The all-perovskite latch-free complementary photosensitive field-effect transistor according to claim 1, characterized in that: The N-type perovskite functional layer (3) is a nanowire perovskite, a two-dimensional perovskite, a quasi-two-dimensional perovskite or a three-dimensional perovskite having N-type transfer characteristics.

5. The all-perovskite latch-free complementary photosensitive field-effect transistor according to claim 1, characterized in that: The N-type perovskite functional layer (3) is Cs2SnI6, (RNH3)2MA n-1 Pb n X 3n+1 Any one of the following, wherein RNH3 is PEA or BA, X is Cl, Br or I, and the value of n is 1-5.

6. The all-perovskite latch-free complementary photosensitive field-effect transistor according to claim 1, characterized in that: The P-type perovskite functional layer (4) is a nanowire perovskite, a two-dimensional perovskite, a quasi-two-dimensional perovskite or a three-dimensional perovskite having a P-type transfer characteristic.

7. The all-perovskite latch-free complementary photosensitive field-effect transistor according to claim 1, characterized in that: The P-type perovskite functional layer (4) is (Cs x FA 1-x )PEA2Sn8I 25 、(RNH3)2FA n-1 Sn n X 3n+1 , FASnX3, wherein RNH3 is PEA or BA, X is Cl, Br or I, and n is a positive integer.

8. The all-perovskite latch-free complementary photosensitive field-effect transistor according to claim 1, characterized in that: The source electrode (51), the drain electrode (52) and the gate electrode (8) are any one of indium tin oxide, fluorine-doped tin oxide, ultrathin metal Au, ultrathin metal Ag, ultrathin metal Cu, ultrathin metal Al, silver nanowires, graphene, poly (3,4-ethylenedioxythiophene) -poly (styrene sulfonate), and carbon-based nanomaterials.

9. The all-perovskite latch-free complementary photosensitive field-effect transistor according to claim 1, characterized in that: The thickness of the substrate (1) is 50-500 μm; the thickness of the buffer layer (2) is 50-300 nm; the thickness of the N-type perovskite functional layer (3) and the P-type perovskite functional layer (4) is 100-1000 nm; the thickness of the dielectric layer (6) is 50-300 nm; the thickness of the isolation layer (7) is 45-1350 nm; and the thickness of the source electrode (51), the drain electrode (52) and the gate electrode (8) is 5-50 nm.

10. A method for preparing an all-perovskite latch-free complementary photosensitive field-effect transistor, characterized in that: include: Obtaining a device substrate (1), and performing pre-processing on the substrate (1); growing a buffer layer (2) on the surface of the pre-treated substrate (1); A first isolation layer (71) and a perovskite functional layer are grown on the surface of the buffer layer (2); wherein the first isolation layer (71) and the perovskite functional layer are flush with each other, and the perovskite functional layer comprises an N-type perovskite functional layer (3) and a P-type perovskite functional layer (4); Growing a source electrode (51), a drain electrode (52) and a dielectric layer (6) on the surface of the perovskite functional layer, and growing a second isolation layer (72) on the surfaces of the first isolation layer (71), the source electrode (51) and the drain electrode (52); Growing a gate electrode (8) and a third isolation layer (73) on the surfaces of the dielectric layer (6) and the second isolation layer (72); The first isolation layer (71), the second isolation layer (72) and the third isolation layer (73) form an isolation layer (7).

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