A performance optimized passive DHTRB test circuit, method and product

Abstract

The application discloses a performance-optimized passive DHTRB test circuit, method and product, which comprises a power supply, a first auxiliary measuring tube S1, a second auxiliary measuring tube S2, a device under test DUT, a positive overshoot circuit and a negative overshoot circuit. The positive electrode of the power supply is connected to the input end of the positive overshoot circuit, the output end of the positive overshoot circuit is connected to the drain electrode of the first auxiliary measuring tube S1, the source electrode of the first auxiliary measuring tube S1 is connected to the drain electrode of the second auxiliary measuring tube S2 and the device under test DUT respectively, the source electrode of the second auxiliary measuring tube S2 is connected to the input end of the negative overshoot circuit, the output end of the negative overshoot circuit is connected to the source electrode of the device under test DUT and the negative electrode of the power supply. When the first auxiliary measuring tube S1 is turned on and the second auxiliary measuring tube S2 is turned off, the positive overshoot circuit outputs a forward overshoot voltage; when the first auxiliary measuring tube S1 is turned off and the second auxiliary measuring tube S2 is turned on, the negative overshoot circuit outputs a reverse overshoot voltage. The application can improve the dV / dt performance of passive DHTRB test.

Description

TECHNICAL FIELD

[0001] The present application relates to a passive DHTRB test circuit, method and product for performance optimization in the field of semiconductor testing. BACKGROUND

[0002] At present, dynamic high temperature reverse bias aging system test (DHTRB test) is indispensable for MOSFET semiconductor device products. This includes passive mode DHTRB test, that is, the DUT does not actively participate in the circuit operation, but passively withstands the test of external high voltage stress. The purpose of the test is to simulate the device under voltage stress and detect its reliability, voltage breakdown resistance and long-term degradation stability, so as to efficiently screen static defects of the device.

[0003] The traditional passive DHTRB test circuit is shown in Figure 1 , which is composed of a first auxiliary measuring tube S1, a second auxiliary measuring tube S2, a bus capacitor , a power supply , line stray inductance and stray resistance, and a DUT. The voltage across the second auxiliary measuring tube S2 is . The voltage signal source is generated by the power supply and the switch tube, which reflects the switching action of the first auxiliary measuring tube S1 and the second auxiliary measuring tube S2. The output frequency of the first auxiliary measuring tube S1 and the second auxiliary measuring tube S2 is synchronized with the switching time sequence through the switching of the first auxiliary measuring tube S1 and the second auxiliary measuring tube S2. The voltage signal source is generated by the power supply and the switch tube, which reflects the switching action of the first auxiliary measuring tube S1 and the second auxiliary measuring tube S2. The output frequency of the first auxiliary measuring tube S1 and the second auxiliary measuring tube S2 is synchronized with the switching time sequence through the switching of the first auxiliary measuring tube S1 and the second auxiliary measuring tube S2. The RL filtered and DUT responsive hysteresis waveforms. In passive DHTRB test, The actual slope of the waveform represents the dV / dt voltage stress intensity of the DUT. The circuit controls the change rate of to indirectly constrain the change of .

[0004] In passive DHTRB test, in order to make the test have enough screening force, the requirement of dV / dt of DUT is higher and higher. The architecture of the above-mentioned traditional test circuit has no more way to improve dV / dt except adjusting the driving parameters of the auxiliary measuring tube and selecting auxiliary measuring tube with higher switching speed. It is limited in higher dV / dt demand occasions, and it is difficult to realize the screening of DUT with high dV / dt requirement. SUMMARY

[0005] The application aims to overcome the deficiencies of the prior art and provide a passive DHTRB test circuit, method and product with optimized performance, which can improve the dV / dt performance of passive DHTRB test.

[0006] In a first aspect, the application provides a passive DHTRB test circuit with optimized performance, which adopts the following technical scheme:

[0007] The test circuit comprises a power supply , a first auxiliary test tube S1, a second auxiliary test tube S2 and a device under test DUT, and further comprises a positive overshoot circuit and a negative overshoot circuit.

[0008] The first auxiliary test tube S1, the second auxiliary test tube S2 and the device under test DUT are MOS tubes.

[0009] The positive electrode of the power supply is connected with the input end of the positive overshoot circuit, the output end of the positive overshoot circuit is connected with the drain electrode of the first auxiliary test tube S1, the source electrode of the first auxiliary test tube S1 is connected with the drain electrode of the second auxiliary test tube S2 and the device under test DUT respectively, the source electrode of the second auxiliary test tube S2 is connected with the input end of the negative overshoot circuit, the output end of the negative overshoot circuit is connected with the source electrode of the device under test DUT, and the negative electrode of the power supply is connected.

[0010] When the first auxiliary test tube S1 is turned on and the second auxiliary test tube S2 is turned off, the positive overshoot circuit outputs a forward overshoot voltage to the outside.

[0011] When the first auxiliary test tube S1 is turned off and the second auxiliary test tube S2 is turned on, the negative overshoot circuit outputs a reverse overshoot voltage to the outside.

[0012] By adopting the above technical scheme, the positive overshoot circuit is connected between the positive electrode of the power supply and the drain electrode of the first auxiliary test tube S1, and the negative overshoot circuit is connected between the positive electrode of the power supply and the source electrode of the second auxiliary test tube S2, so that a rising peak based on the forward overshoot voltage output by the positive overshoot circuit to the outside is generated at the rising edge of the voltage across the second auxiliary test tube S2, a falling peak based on the reverse overshoot voltage output by the negative overshoot circuit to the outside is generated at the falling edge of the voltage , the dV / dt during switching of the switch tube is improved, so that the controllable voltage stress intensity on the device under test DUT is improved, and the screening force on the device under test DUT is improved.

[0013] Preferably, the positive overshoot circuit comprises a positive overshoot power supply , a positive charge control tube S3 and a positive overshoot capacitor .

[0014] The positive charge control tube S3 is a MOS tube.​

[0015] The input terminals of the positive overshoot circuit are connected to the positive overshoot power supply. overshoot capacitors at the negative and positive terminals One end, positive overcharge power supply The positive terminal is connected to the drain of the positive charging control transistor S3, and the source of the positive charging control transistor S3 is connected to the positive overshoot capacitor. The other end is connected to the output terminal of the positive overshoot circuit.

[0016] Preferably, the negative overshoot circuit includes a negative overshoot power supply. Negative charging control transistor S4 and negative overshoot capacitor ;

[0017] The negative electrode charging control transistor S4 is a MOSFET;

[0018] The input terminals of the negative overshoot circuit are connected to the drain of the negative charging control transistor S4 and the negative overshoot capacitor, respectively. At one end, the source of the negative charging control transistor S4 is connected to the negative overcharge power supply. The negative terminal, negative terminal overcharge power supply overshoot capacitors at the positive and negative terminals The other end is connected to the output terminal of the negative overshoot circuit.

[0019] The above technical solution utilizes a positive overshoot capacitor supplied with power. and negative overshoot capacitor Energy storage and charging are achieved by discharging a large instantaneous current during switching of the transistor. This is accomplished through a combination of capacitors and power supply polarity. The output terminal generates a high-dV / dt high-voltage pulse, realizing the control of forward and reverse overshoot voltages. The waveform is adjusted to meet the high dV / dt testing requirements of the DUT.

[0020] As a preferred option, the positive overshoot capacitor The capacitance is smaller than the bus capacitance. Negative overshoot capacitor Less than the bus capacitance .

[0021] By using the above technical solution, a positive overshoot capacitor with a relatively small capacitance value is selected. and negative overshoot capacitor The rate of decrease of the positive overshoot voltage depends on the positive overshoot capacitance. The magnitude of the reverse overshoot voltage and the recovery speed depend on the negative overshoot capacitor. The size, the small capacitance value makes In the waveform, a high dV / dt can be achieved without a particularly large overshoot voltage.

[0022] In a second aspect, the application provides a performance-optimized passive DHTRB test method, which adopts the technical solution comprising the following steps:

[0023] The first auxiliary tube S1 is turned on.

[0024] When the first auxiliary tube S1 is turned on, the negative electrode charging control tube S4 is turned on to charge the negative electrode overshoot capacitor to a preset voltage, and then the negative electrode charging control tube S4 is turned off.

[0025] The first auxiliary tube S1 is turned off, and the second auxiliary tube S2 is turned on. At this time, the negative electrode overshoot capacitor outputs a reverse overshoot voltage .

[0026] When the second auxiliary tube S2 is turned on, the positive electrode charging control tube S3 is turned on to charge the positive electrode overshoot capacitor to a preset voltage, and then the positive electrode charging control tube S3 is turned off.

[0027] The second auxiliary tube S2 is turned off, and the first auxiliary tube S1 is turned on. At this time, the positive electrode overshoot capacitor outputs a forward overshoot voltage .

[0028] The above steps are repeated to output a voltage signal with an overshoot voltage waveform to the device under test DUT.

[0029] Through the above technical solution, the periodic on-off switching action of the first auxiliary tube S1 and the second auxiliary tube S2 is realized to output a square wave voltage signal; through the periodic on-off control of the positive electrode charging control tube S3 and the negative electrode charging control tube S4 in the timing, the charging of the positive electrode overshoot capacitor and the negative electrode overshoot capacitor is realized, and when the first auxiliary tube S1 and the second auxiliary tube S2 are switched, the discharge is performed, and the overshoot discharge is superimposed on the square wave voltage , thereby realizing the high dV / dt of the DHTRB test.

[0030] As a preferred, the on duration of the first auxiliary tube S1 is , the on duration of the second auxiliary tube S2 is , and there is an interval dead time .

[0031] As a preferred, after the first auxiliary tube S1 is turned on, the waiting time The negative electrode charging control tube S4 is turned on again, and the on duration of the negative electrode charging control tube S4 is , ; the second auxiliary measuring tube S2 is turned on, and the waiting time is The positive electrode charging control tube S3 is turned on again, and the on duration of the positive electrode charging control tube S3 is , .

[0032] Through the above technical solution, by setting the dead time to avoid direct short circuit, the switching tube and the capacitor are protected, and the Ring amplitude of the uncontrollable waveform edge is reduced, the signal quality is improved, and the reliability of the test data is ensured; by determining the on time and the on duration of the first auxiliary measuring tube S1, the second auxiliary measuring tube S2, the positive electrode charging control tube S3 and the negative electrode charging control tube S4, the test voltage signal of the determined frequency is realized, and the implementation of the DHTRB test is ensured.

[0033] As preferred, the voltage value of the positive overshoot power supply , the voltage value of the negative overshoot power supply , the preset voltage of the positive overshoot capacitor and the preset voltage of the negative overshoot capacitor are adjustable.

[0034] Through the above technical solution, the amplitude of the forward overshoot voltage and the reverse process voltage can be controlled, and the falling speed of the forward overshoot voltage and the recovery speed of the reverse overshoot voltage can be controlled, so that the automatic stepless continuous adjustment of the waveform is realized, and the dV / dt voltage stress intensity of the specific test requirement of the device to be tested can be obtained.

[0035] As preferred, before the first time the first auxiliary measuring tube S1 is turned on, the positive overshoot capacitor is pre-charged, so that when the first auxiliary measuring tube S1 is turned on for the first time, the positive overshoot capacitor can output the forward overshoot voltage .

[0036] Through the above technical solution, when the first auxiliary measuring tube S1 is turned on for the first time, the rising edge of the voltage signal can generate the forward overshoot voltage waveform, ensuring the integrity of the test waveform signal and improving the reliability of the test.

[0037] In a third aspect, the present application provides a computer program product, which comprises a computer program or instructions, so that the computer program or instructions can realize the steps in the above performance optimization passive DHTRB test method.

[0038] In summary, the present application includes at least one of the following beneficial technical effects:

[0039] 1. The present application can actively superimpose controllable overshoot voltage waveforms on the voltage waveforms of when passive DHTRB testing is performed, and can cause overshoot voltage spikes on the rising and falling edges of when the switching tube is switched, which can significantly improve the dV / dt performance of the test, provide higher dV / dt test voltage stress for the device under test, and improve the screening ability for the device.

[0040] 2. The present application can realize stepless adjustment of the test dV / dt performance, can adjust and obtain the corresponding dV / dt according to the test requirements, and improves the accuracy and convenience of the test. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 is a schematic diagram of a traditional passive DHTRB test circuit;

[0042] Figure 2 is a schematic diagram of a performance-optimized passive DHTRB test circuit in an embodiment of the present application;

[0043] Figure 3 is a flowchart of a performance-optimized passive DHTRB test method in an embodiment of the present application;

[0044] Figure 4 is a circuit control logic and voltage waveform timing diagram of a performance-optimized passive DHTRB test method in an embodiment of the present application;

[0045] Figure 5 is a waveform and a waveform of a traditional passive DHTRB test circuit, and waveform and a waveform of a performance-optimized passive DHTRB test circuit in an embodiment of the present application;

[0046] Figure 6 is a schematic diagram of an exemplary electronic device architecture in an embodiment of the present application. DETAILED DESCRIPTION

[0047] This specific embodiment is only an explanation of the present application, and is not a limitation of the present application. Those skilled in the art can make modifications to the present embodiment without creative contribution after reading the present specification, but as long as the modifications are within the scope of the present application, they are protected by the patent law.

[0048] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. It should be noted that in the optional embodiments of this application, the object information and other related data involved require the permission or consent of the object when the embodiments of this application are applied to specific products or technologies, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. That is to say, if the embodiments of this application involve data related to the object, it needs to be obtained with the authorization and consent of the object, the authorization and consent of the relevant departments, and in compliance with the relevant laws, regulations, and standards of the country and region. If personal information is involved in the embodiments, the acquisition of all personal information requires the consent of the individual. If sensitive information is involved, the separate consent of the information subject is required, and the embodiments also need to be implemented with the authorization and consent of the object.

[0049] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0050] Example 1:

[0051] Please see Figure 2 An embodiment of this application provides a performance-optimized passive DHTRB test circuit, including a power supply. Bus capacitor The test tubes include a first test tube S1, a second test tube S2, the device under test (DUT), a positive overshoot circuit, a negative overshoot circuit, and stray inductance and stray resistance. Those skilled in the art will understand that... Figure 2 The structure shown is merely a circuit connection diagram of some components related to the solution of this application, and does not constitute a limitation on the circuit designed in this application. Specific electronic components may include more or fewer components than those shown in the figure, or combine the functions of certain components, or have different component arrangements.

[0052] The device under test (DUT) is a MOSFET. The first and second auxiliary test transistors (S1 and S2) are also MOSFETs, serving as high-speed switches in the circuit. Bus capacitor. Connected to the power supply At both ends, power supply The positive terminal is connected to the input terminal of the positive overshoot circuit. The output terminal of the positive overshoot circuit is connected to the drain of the first test tube S1. The source of the first test tube S1 is connected to the drain of the second test tube S2 and the device under test (DUT). The source of the second test tube S2 is connected to the input terminal of the negative overshoot circuit. The output terminal of the negative overshoot circuit is connected to the source of the DUT and connected to a power supply. The negative electrode.

[0053] When the first test tube S1 is turned on and the second test tube S2 is turned off When the first test tube S1 is off and the second test tube S2 is on, It is located at a low level. Specifically, the voltage across the second test tube S2 is... The two ends of the device under test (DUT) are , yes The hysteresis waveform after RL filtering and DUT response. When the first auxiliary test tube S1 is on and the second auxiliary test tube S2 is off, the positive overshoot circuit outputs a positive overshoot voltage; when the first auxiliary test tube S1 is off and the second auxiliary test tube S2 is on, the negative overshoot circuit outputs a reverse overshoot voltage. Bus capacitor. Used to suppress uncontrollable switching oscillations, absorb high-frequency oscillation energy, and reduce... and The edge spikes protect the DUT from uncontrollable voltage surges.

[0054] More specifically, the positive overshoot circuit includes the positive overshoot power supply. Positive charging control transistor S3 and positive overshoot capacitor The positive charging control transistor S3 is a MOSFET. The input terminals of the positive overshoot circuit are connected to the positive overshoot power supply. overshoot capacitors at the negative and positive terminals One end, positive overcharge power supply The positive terminal is connected to the drain of the positive charging control transistor S3, and the source of the positive charging control transistor S3 is connected to the positive overshoot capacitor. The other end is connected to the output terminal of the positive overshoot circuit.

[0055] The negative overshoot circuit includes a negative overshoot power supply. Negative charging control transistor S4 and negative overshoot capacitor The negative charging control transistor S4 is a MOSFET. The input terminals of the negative overshoot circuit are connected to the drain of the negative charging control transistor S4 and the negative overshoot capacitor, respectively. At one end, the source of the negative charging control transistor S4 is connected to the negative overcharge power supply. The negative terminal, negative terminal overcharge power supply overshoot capacitors at the positive and negative terminals The other end is connected to the output terminal of the negative overshoot circuit.

[0056] Since passive DHTRB testing requires generating a steep reverse bias voltage on the DUT, i.e., a high dV / dt is needed, and When the first test tube S1 and the second test tube S2 switch at high speed, they can release or absorb large current pulses to the DUT, supporting the switching action of the switching transistor. An overshoot voltage is applied to the changing rising and falling edges of the waveform, thereby ensuring that the voltage change rate across the DUT meets the test requirements, thus applying a dV / dt voltage stress to the DUT that meets the test requirements. The positive charging control transistor S3 and the negative charging control transistor S4 are used to control the positive overshoot capacitor. and negative overshoot capacitor The charging process is controlled to adjust the voltage waveform signal.

[0057] It should also be noted that the rate of decrease of the positive overshoot voltage depends on the positive overshoot capacitor. The magnitude of the reverse overshoot voltage and the recovery speed depend on the negative overshoot capacitor. The size of the positive overshoot capacitor is therefore usually determined by the size of the positive overshoot capacitor. and negative overshoot capacitor By selecting a capacitor with a relatively small capacitance value, rapid discharge can be achieved, and a high dV / dt can be obtained without a large overshoot voltage.

[0058] In this application, the material of the MOSFET is selected from monocrystalline silicon, polycrystalline silicon, or amorphous silicon, and may also be one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), gallium arsenide (GaAs), gallium nitride (GaN), and gallium oxide (Ga2O3). For example, in this embodiment, the material of the MOSFET is silicon carbide.

[0059] Example 2:

[0060] Please see Figure 3 and Figure 4 The passive DHTRB testing method for performance optimization according to the embodiments of this application will be described.

[0061] Step 1: Turn on the first test tube S1.

[0062] Step 2: When the first test tube S1 is turned on, the negative terminal charging control tube S4 is turned on to charge the negative terminal overshoot capacitor. Charge the device until it reaches the preset voltage, then disconnect the negative terminal charging control transistor S4.

[0063] Step 3: Turn off the first auxiliary test tube S1 and turn on the second auxiliary test tube S2. At this time, the negative overshoot capacitor... Output reverse overshoot voltage .

[0064] Step 4: When the second test tube S2 is turned on, the positive terminal charging control tube S3 is turned on to charge the positive terminal overshoot capacitor. Charge the device until it reaches the preset voltage, then disconnect the positive charging control transistor S3.

[0065] Step 5: Turn off the second auxiliary test tube S2 and turn on the first auxiliary test tube S1, i.e., return to step 2. At this time, the positive overshoot capacitor... Output positive overshoot voltage .

[0066] Repeat the above steps to output a voltage signal with an overshoot voltage waveform to the device under test (DUT).

[0067] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0068] More specifically, in the above passive DHTRB test method, the conduction time of the first test tube S1 is... The conduction time of the second test tube S2 is , and There is a dead time interval between them. Dead time It can prevent shoot-through short circuits, protect the switching transistors and capacitors, and suppress... Oscillations are avoided, thereby improving the stability and reliability of test data. In embodiments of this application, to simplify testing and calculation, [the following is implemented]: .

[0069] When the first auxiliary test tube S1 is turned on, the time when the second auxiliary test tube S2 is turned off can be used to turn on the negative terminal charging control tube S4 to form a charging circuit and charge the negative terminal overshoot capacitor. Charge without affecting This affects the test. Similarly, by turning on the second auxiliary test tube S2, the time when the first auxiliary test tube S1 is off can be used to turn on the positive charging control tube S3 to form a charging circuit, which then charges the positive overshoot capacitor. Charging will not cause The test has an impact. It should be noted that after turning on the first test tube S1, a waiting period is required. As an isolation time interval, the negative charging control transistor S4 is turned on again to ensure that the charging circuit is properly connected. The test section is not affected, and the conduction time of the negative electrode charging control transistor S4 is , This ensures that the time for forming the charging circuit falls within the conduction time range of the first auxiliary test tube S1. Similarly, the waiting time after turning on the second auxiliary test tube S2 is... Then turn on the positive charging control transistor S3. The on-time of the positive charging control transistor S3 is: , Similarly, in the embodiments of this application, making .

[0070] Users can overcharge the positive terminal power supply Voltage value, negative overshoot power supply The voltage value can be adjusted, and the positive overshoot capacitor can also be adjusted. The preset voltage and the negative overshoot capacitor Preset voltage and charging time The above adjustments can regulate the peak value and descent rate of the overshoot voltage waveform, thereby achieving stepless and continuous adjustment of dV / dt. This facilitates precise setting of the voltage stress of the DUT during the test period according to the test objectives and requirements.

[0071] In another embodiment, before the first test tube S1 is turned on for the first time, the positive overshoot capacitor is... Pre-charge ( Before the moment (, when the first test tube S1 is turned on for the first time, the positive overshoot capacitor) Capable of outputting positive overshoot voltage .

[0072] The following is combined Figure 4 Control timing diagram, for An example will be given using the rising edge.

[0073] At time t2, the second test tube S2 is turned on. At time t3, the positive charging control tube S3 is turned on, and the positive overcharge power supply... Positive overshoot capacitor Charging, will Charge to the preset voltage. Then turn off the positive charging control transistor S3.

[0074] At time t4, the first test tube S1 is turned on. The initial voltage across the terminals is Then it drops to the platform voltage. This forms a waveform with a rising edge. The principle of falling edge is similar to that of rising edge, and will not be elaborated here. The circled parts in the waveform diagram represent the waveform of the overshoot voltage, specifically the rising and falling edges.

[0075] Please see Figure 5 In the figure, the blue dashed line represents the waveform generated by the traditional DHTRB test circuit, while the red solid line represents the waveform generated using the technical solution of this application. It can be seen that there is a significant difference in dV / dt between the two, as shown by the red line. The slope of the former is significantly higher than that of the latter, indicating that a larger dV / dt voltage stress intensity can be applied to the DUT during the test period.

[0076] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM or random access memory (RAM), magnetic disks, or optical disks.

[0077] Example 3:

[0078] Another embodiment of this application provides a computer program product comprising a computer program or instructions that enables the computer program or instructions to implement the steps in the above-described performance-optimized passive DHTRB testing method.

[0079] Please refer to the exemplary electronic device used by the computer program or instructions. Figure 6 The electronic device includes a processor, memory, and external data interface connected via a system bus. The memory of the electronic device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system, the computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database of the electronic device stores control strategies for each switching transistor and charging control transistor, as well as test data of the device under test (DUT). The processor of the electronic device provides control capabilities and executes control programs for each switching transistor and charging control transistor. The external data interface of the electronic device is connected to each switching transistor and to the detection sensors of the DUT.

[0080] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," "third," and similar terms used in this application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. The terms "an" or "a" and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "comprising" or "including" and similar terms mean that the elements or objects preceding "comprising" or "including" encompass the elements or objects listed following "comprising" or "including" and their equivalents, and do not exclude other elements or objects. "Above," "below," "left," "right," etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0081] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A performance-optimized passive DHTRB test circuit, including a power supply V DC Bus capacitor C bus The first test tube S1, the second test tube S2, and the device under test (DUT) are characterized in that... It also includes positive overshoot circuit and negative overshoot circuit; The first test tube S1, the second test tube S2, and the device under test (DUT) are all MOS transistors; The bus capacitor C bus Connected to the power supply V DC At both ends, power supply V DC The positive terminal is connected to the input terminal of the positive overshoot circuit. The output terminal of the positive overshoot circuit is connected to the drain of the first test tube S1. The source of the first test tube S1 is connected to the drain of the second test tube S2 and the device under test (DUT). The source of the second test tube S2 is connected to the input terminal of the negative overshoot circuit. The output terminal of the negative overshoot circuit is connected to the source of the DUT and connected to the power supply V. DC The negative electrode; When the first test tube S1 is turned on and the second test tube S2 is turned off, the positive overshoot circuit outputs a positive overshoot voltage. When the first test tube S1 is turned off and the second test tube S2 is turned on, the negative overshoot circuit outputs a reverse overshoot voltage.

2. The performance-optimized passive DHTRB test circuit according to claim 1, characterized in that, The positive overshoot circuit includes a positive overshoot power supply V. DC+ Positive charging control transistor S3 and positive overshoot capacitor C bus+ ; The positive charging control transistor S3 is a MOSFET; The input terminals of the positive overshoot circuit are respectively connected to the positive overshoot power supply V. DC+ overshoot capacitors C at the negative and positive terminals bus+ One end, positive overcharge power supply V DC+ The positive terminal is connected to the drain of the positive charging control transistor S3, and the source of the positive charging control transistor S3 is connected to the positive overshoot capacitor C. bus+ The other end is connected to the output terminal of the positive overshoot circuit.

3. The performance-optimized passive DHTRB test circuit according to claim 2, characterized in that, The negative overshoot circuit includes a negative overshoot power supply V. DC- Negative charging control transistor S4 and negative overshoot capacitor C bus- ; The negative electrode charging control transistor S4 is a MOSFET; The input terminals of the negative overshoot circuit are connected to the drain of the negative charging control transistor S4 and the negative overshoot capacitor C, respectively. bus- At one end, the source of the negative charging control transistor S4 is connected to the negative overcharge power supply V. DC- The negative terminal, negative terminal overcharge power supply V DC- overshoot capacitor C at the positive and negative terminals bus- The other end is connected to the output terminal of the negative overshoot circuit.

4. A performance-optimized passive DHTRB test circuit according to claim 2 or claim 3, characterized in that, Positive overshoot capacitor C bus+ The capacitance is less than the bus capacitance C. bus Negative overshoot capacitor C bus- Less than the bus capacitance C bus .

5. A performance-optimized passive DHTRB testing method, applied to the performance-optimized passive DHTRB testing circuit of claim 3, characterized in that it includes the following steps: Turn on the first test tube S1; When the first test tube S1 is turned on, the negative terminal charging control tube S4 is turned on, which controls the negative terminal overshoot capacitor C. bus- Charge the device until it reaches the preset voltage, then disconnect the negative terminal charging control transistor S4. Turn off the first auxiliary test tube S1 and turn on the second auxiliary test tube S2; at this time, the negative overshoot capacitor C bus- Output reverse overshoot voltage V cbus- ; When the second test tube S2 is turned on, the positive charging control tube S3 is turned on, which affects the positive overshoot capacitor C. bus+ Charge the device until it reaches the preset voltage, then disconnect the positive charging control transistor S3. The second auxiliary test tube S2 is turned off, and the first auxiliary test tube S1 is turned on; at this time, the positive overshoot capacitor C bus+ Output positive overshoot voltage V cbus+ ; Repeat the above steps to output a voltage signal with an overshoot voltage waveform to the device under test (DUT).

6. The performance-optimized passive DHTRB testing method according to claim 5, characterized in that, The conduction time of the first test tube S1 is t. a1 The conduction time of the second test tube S2 is t. a2 , t a1 and t a2 There is a dead time t between them. c .

7. A performance-optimized passive DHTRB testing method according to claim 6, characterized in that, Waiting time t after the first test tube S1 is turned on d Then the negative electrode charging control transistor S4 is turned on again, and the on-time of the negative electrode charging control transistor S4 is t. b1 , t d +t b1 <t a1 Waiting time t after the second test tube S2 is turned on d The positive charging control transistor S3 is then turned on again, and the on-time of the positive charging control transistor S3 is t. b2 , t d +t b2 <t a2 .

8. A performance-optimized passive DHTRB testing method according to claim 5, characterized in that, Positive overshoot power supply V DC+ Voltage value, negative overshoot power supply V DC- Voltage value, positive overshoot capacitor C bus+ The preset voltage and the negative overshoot capacitor C bus- The preset voltage is adjustable.

9. A performance-optimized passive DHTRB testing method according to claim 5, characterized in that, Before the first test tube S1 is turned on for the first time, the positive overshoot capacitor C is... bus+ Pre-charging is performed so that when the first auxiliary test tube S1 is turned on for the first time, the positive overshoot capacitor C... bus+ Capable of outputting positive overshoot voltage V cbus+ .

10. A computer program product, characterized in that, The computer program product includes a computer program or instructions that enable the computer program or instructions to perform the steps in the performance-optimized passive DHTRB testing method according to any one of claims 5 to 9.

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