Intelligent arc discharge detection control system and method based on SPI (Serial Peripheral Interface) multi-chip cascade

Abstract

The invention discloses an intelligent arcing detection control system based on serial peripheral interface (SPI) multi-chip cascading, which is characterized in that a plurality of chips are cascaded through an SPI interface, and only one chip as a master control is required to be communicated with an upper computer with flash storage firmware, so that N-1 flash hardware (N is the total number of cascaded chips) can be saved, and the cost is saved. Moreover, through an arc discharge host chip and an SPI interface, other N-1 arc discharge slave chips are controlled, arc discharge data of the arc discharge slave chips are collected, summarized and unified to communicate with an upper computer, an arc discharge detection algorithm is used in the arc discharge chips, and once an arc discharge result exists, the arc discharge result is quickly reported to a master controller through the SPI interface to carry out turn-off operation, so that the arc discharge is realized. Compared with a uart bus, the speed is greatly improved (the uart speed is usually 9600-115200 Baud rate, and the speed of an SPI (Serial Peripheral Interface) bus can reach 40000000-12000000).

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of arc detection, and particularly relates to an intelligent arc detection control system and method based on SPI multi-chip cascading. BACKGROUND

[0002] In the use process of photovoltaic products, a set of arc detection device is designed for whether the product appears arc fault. Usually, a main control photovoltaic inverter needs to externally hang an arc detection chip to separately process the report of arc fault. The detection ADC channel of one arc detection chip is usually limited, such as only 6 channels, but the actual inverter may need more channels for detection, which requires multiple arc detection chips for cascading processing.

[0003] The common method on the market is to cascade multiple detection chips through a uart bus, but this cannot effectively reduce the hardware cost and realize efficient arc detection communication. Through the cascading chips of the uart bus, independent flash storage firmware is used between multiple chips, and each chip and the host computer are communicated with the host computer through a low-speed uart, which causes waste of flash hardware and high hardware cost, and low communication efficiency. SUMMARY

[0004] The purpose of the application is to provide an intelligent arc detection control system and method based on SPI multi-chip cascading, which cascades multiple chips through an SPI interface, and only needs to store firmware and communicate with the host computer through a flash storage firmware of one chip as a master chip, thereby saving N-1 (N is the total number of cascaded chips) flash hardware and saving cost.

[0005] To solve the above problems, the technical scheme of the application is as follows: An intelligent arc detection control system based on SPI multi-chip cascading, comprising: an inverter host computer for overall control decision; an arc master chip connected with the inverter host computer through a first communication interface; at least one arc slave chip cascaded with the arc master chip through an SPI bus; wherein the arc master chip is provided with an external FLASH memory for storing firmware of an arc detection algorithm; the arc master chip is preferentially started after power-on, and distributes the firmware to each arc slave chip through the SPI bus, so that the arc slave chip runs an arc detection program in the respective RAM; the arc slave chip returns the detected arc state data to the arc master chip through the SPI bus, and the arc master chip reports to the inverter host computer after summarizing to execute the shutdown decision.

[0006] According to an embodiment of the present application, the first communication interface is at least one of CAN, RS485, UART, Ethernet, and PLC power carrier.

[0007] According to an embodiment of the present application, the SPI bus is in a daisy chain topology, and the arc host chip and the arc slave chip are cascaded in sequence through MOSI, MISO, SCK, and NSS signal lines.

[0008] According to an embodiment of the present application, the arc host chip performs firmware loading and state data collection on the arc slave chip in sequence through a chip selection signal CS polling mode.

[0009] According to an embodiment of the present application, the RAM of the arc slave chip is an on-chip SRAM, and the firmware is written by the arc host chip through a DMA mode before running.

[0010] According to an embodiment of the present application, the external FLASH memory adopts a dual-mirror backup mechanism, and when a firmware check error is detected, the backup mirror is automatically switched to for reloading.

[0011] According to an embodiment of the present application, the arc host chip and the arc slave chip are the same model of MCU, and the MCU internally integrates a hardware CRC check module for data integrity check during firmware distribution and state feedback.

[0012] An arc detection method, comprising the following steps: S1, loading an arc detection firmware from an external FLASH memory after power-on of an arc host chip; S2, distributing the firmware by the arc host chip to each arc slave chip through an SPI bus, so that the arc slave chip runs in a respective RAM; S3, detecting an arc state in real time by each arc slave chip, and feeding back state data to the arc host chip through the SPI bus; S4, summarizing the state data of each arc slave chip by the arc host chip, and reporting to an inverter host computer through a first communication interface; and S5, executing a shutdown or alarm decision according to the summarized data by the inverter host computer.

[0013] According to an embodiment of the present application, in step S2, the arc host chip selects each arc slave chip in sequence through a chip selection signal CS, and performs firmware distribution and state feedback in parallel in a pipeline mode.

[0014] According to an embodiment of the present application, in step S3, the state data includes an arc fault flag, an arc intensity value, a timestamp, and a chip ID, and is transmitted through the SPI bus in a compression encoding format.

[0015] The present application has the following advantages and positive effects compared with the prior art by adopting the above technical solutions: 1) The intelligent arc detection control system based on SPI multi-chip cascade in an embodiment of the present application is cascaded with multiple chips through the SPI interface. Only one chip as the master control chip with flash storage firmware and communication with the upper computer is needed, which can save N-1 (N is the total number of cascaded chips) flash hardware and save costs.

[0016] 2) The system collects arc data of other chips for summary through a master control arc chip, controls other N-1 slave chips through the SPI interface, and communicates with the upper computer. The AI algorithm for arc detection runs in the arc chip. Once there is an arc result, the master control is quickly reported through the SPI for shutdown operation, which greatly improves the speed compared with the UART bus (the UART rate is usually 9600-115200 baud, and the SPI bus rate can reach 40000000-12000000). BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 The block diagram of the intelligent arc detection control system based on SPI multi-chip cascade in an embodiment of the present application is shown in the figure. Figure 2 The connection diagram of the arc host chip and the arc slave chip in an embodiment of the present application is shown in the figure. Figure 3 The flowchart of the arc detection method in an embodiment of the present application is shown in the figure. Figure 4 The data interaction diagram of the arc detection method in an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0018] The intelligent arc detection control system and method based on SPI multi-chip cascade according to the present application will be further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description and claims.

[0019] At present, the scheme of externally hanging arc chip for photovoltaic inverter system is not mature. The general UART interface communication scheme is usually considered. Due to the rate limitation of UART, it is not possible to effectively load and start the firmware through this interface quickly, so each externally hanging cascaded chip must have its own flash storage firmware, which leads to waste of flash hardware and high hardware cost, and low communication efficiency.

[0020] In view of the above problems, the present embodiment provides an intelligent arc detection control system based on SPI multi-chip cascade, which can reduce costs and improve communication efficiency.

[0021] Please refer to Figure 1The intelligent arc-drawing detection control system based on the SPI multi-chip cascade comprises: an inverter upper computer for overall control decision; an arc-drawing master chip connected with the inverter upper computer through a first communication interface; and at least one arc-drawing slave chip cascaded with the arc-drawing master chip through an SPI bus, wherein the arc-drawing master chip is provided with an external FLASH memory for storing firmware of an arc-drawing detection algorithm; the arc-drawing master chip is started preferentially after power-on, and distributes the firmware to each arc-drawing slave chip through the SPI bus, so that the arc-drawing slave chip runs an arc-drawing detection program in a respective RAM; and the arc-drawing slave chip returns arc-drawing state data detected by the arc-drawing slave chip to the arc-drawing master chip through the SPI bus, and the arc-drawing master chip reports the arc-drawing state data to the inverter upper computer after summarizing the arc-drawing state data to execute a shutdown decision.

[0022] Specifically, the first communication interface between the arc-drawing master chip and the inverter upper computer is at least one of CAN, RS485, UART, Ethernet and PLC power carrier.

[0023] The arc-drawing master chip and the arc-drawing slave chip are cascaded through the SPI bus, which can be a daisy chain topology, and the arc-drawing master chip and the arc-drawing slave chip are cascaded in sequence through MOSI, MISO, SCK and NSS signal lines, please refer to Figure 2 .

[0024] Further, the arc-drawing master chip performs firmware loading and state data collection on the arc-drawing slave chip in sequence through a chip selection signal CS polling mode.

[0025] The RAM of the arc-drawing slave chip is an on-chip SRAM, and the firmware is written by the arc-drawing master chip through a DMA mode before running. The arc-drawing slave chip no longer needs an external Flash memory, which reduces BOM cost and PCB area, saves Flash address / data lines, simplifies wiring and reduces EMI risk; compared with an external Flash, the on-chip SRAM has no solder joint aging and signal integrity problems, and is suitable for harsh environments such as high vibration and high temperature; the DMA can integrate CRC verification to ensure error-free firmware writing and avoid false positives or false negatives of arc-drawing faults caused by code errors of the slave chip.

[0026] The arc-drawing detection algorithm in the firmware can be a signal domain algorithm or an artificial intelligence algorithm. The signal domain algorithm includes a zero-crossing statistical method, a high-frequency energy integration method, and a harmonic ratio method. In the actual application, multiple algorithms can be combined, such as a double-condition criterion algorithm based on the high-frequency energy integration and the harmonic ratio.

[0027] The artificial intelligence algorithm includes a CNN-1D convolution network, an LSTM sequence model, or a Random Forest decision tree integrated model. For example, a 1D-CNN model is used to perform two-level classification on the current waveform, and the model weight is stored in the external FLASH of the host chip and is distributed to the on-chip SRAM of the slave chip through DMA during running.

[0028] The arc-drawing host chip and the arc-drawing slave chip can be the same type of MCU, and the MCU is internally integrated with a hardware CRC verification module for data integrity verification during firmware distribution and state feedback.

[0029] Further, the external FLASH memory of the arc-drawing host chip adopts a dual-mirror backup mechanism, and automatically switches to a backup image for reloading when a firmware verification error is detected. The FLASH may have bit flips or bad blocks after long-term high temperature, radiation, or write wear. If the main image fails the verification, the system can still start normally by switching to the backup image. If the main image is accidentally powered off during the upgrade process, the backup image remains intact and automatically rolls back during the next power-on, avoiding the risk of “burning to death”.

[0030] The intelligent arc-drawing detection and control system based on the SPI multi-chip cascade can cascade multiple chips through the SPI interface. Only one chip needs to be used as the master chip to store the firmware and communicate with the upper computer, which can save N-1 (N is the total number of cascaded chips) flash hardware and save costs. Moreover, one arc-drawing host chip controls the other N-1 arc-drawing slave chips through the SPI interface, collects arc-drawing data of the arc-drawing slave chips, and communicates with the upper computer. The arc-drawing detection algorithm runs in the arc-drawing chip. Once the arc-drawing result is obtained, it is quickly reported to the master control for shutdown operation through the SPI, which greatly improves the speed of the UART bus (the UART rate is usually 9600-115200 baud, while the SPI bus rate can reach 40000000-12000000).

[0031] The arc detection method for the SPI multi-chip cascade-based intelligent arc detection control system, please refer to Figure 3 The arc detection method comprises the following steps: S1, after the arc host chip is powered on, loading the arc detection firmware from the external FLASH memory; S2, the arc host chip distributes the firmware to each arc slave chip through the SPI bus, so that the arc slave chip runs in the respective RAM; S3, each arc slave chip detects the arc state in real time and returns the state data to the arc host chip through the SPI bus; S4, the arc host chip aggregates the state data of each arc slave chip and reports to the inverter host computer through the first communication interface; S5, the inverter host computer executes the shutdown or alarm decision according to the aggregated data.

[0032] In step S2, it also includes: the arc host chip selects each arc slave chip in turn through the chip selection signal CS, and performs firmware distribution and state return in a pipeline manner in parallel.

[0033] In step S3, after the arc slave chip is normally started, the internal 6-channel ADC samples the inverter 6-channel PV source current data and sends it to the arc intelligent algorithm module. The state data includes the arc fault flag, the arc intensity value, the timestamp and the chip ID, and is transmitted in a compression encoding format through the SPI bus.

[0034] Specifically, please refer to Figure 4 The arc detection method comprises: Step 1: after the master (arc host chip) is powered on, the firmware in the flash externally hung by itself is loaded through the SPI interface to the arc slave chips slave1 and slave2, respectively. The loading process is transmitted through the chip upgrade protocol and the SPI port to ensure that the entire firmware content is transmitted to slave1 and slave2, so that they run in their respective ram spaces. Each arc chip has its own independent 3M RAM space, and the firmware content includes the communication protocol and the arc algorithm. (During the master operation of the flash, the chip selection signal CS3 must be pulled low to be effective. In this way, multiple cascaded chips use only one flash, and through the software protocol design scheme, the hardware cost is saved.) Step 2: if any of slave1 / slave2 devices occurs an arc event, the GPIO port connected with the master triggers an external interrupt to the master (if the master is transmitting the PCM large data generated by the arc or operating the flash, the master will immediately stop the existing transmission) and pulls down the chip selection signals CS1 / CS2 of slave1 / slave2, and immediately transmits the arc event to the master through the SPI bus; Step 3: After the master transmits the arc completion event, the slave1 / slave2 arc data PCM transmission is started (the arc data of the PCM exists in the flash space of the host, and is used for subsequent data iteration algorithm model; the arc event is used for the upper computer to quickly cut off the PV source after receiving the arc event, and the priority of the arc event is the highest), and the transmission is performed through the SPI bus. During the transmission, if there is an arc event, the arc data transmission can be interrupted at high priority; Step 4: The master writes the arc data to the flash. During the master operation of the flash, the chip select CS3 of the SPI is pulled low, and writing is performed in units of 4 kb (the writing can be interrupted by the arc event, the transmission can be continued, and new arc data generated during the incomplete transmission will be discarded).

[0035] In summary, the intelligent arc detection control system and method based on the SPI multi-chip cascade in the embodiment can reduce the cost while improving the communication efficiency.

[0036] The embodiments of the application are described in detail above with reference to the drawings, but the application is not limited to the above-described embodiments. Even if various changes are made to the application, if the changes belong to the scope of the claims of the application and equivalent technologies thereof, they still fall within the protection scope of the application.

Claims

1. An intelligent arc detection and control system based on SPI multi-chip cascade, characterized in that: include: Inverter host computer, used for overall control and decision-making; The arc host chip is connected to the inverter host computer via a first communication interface; At least one arc-pulling slave chip, cascaded with the arc-pulling master chip via an SPI bus; in, The arc host chip is provided with an external FLASH memory for storing the firmware of the arc detection algorithm; The arc master chip starts first after power-on, and distributes the firmware to each arc slave chip through the SPI bus, so that the arc slave chips run the arc detection program in their respective RAMs; Each arcing slave chip transmits the detected arcing status data back to the arcing master chip via the SPI bus, and the arcing master chip summarizes and reports the data to the inverter host computer to execute the shutdown decision.

2. The intelligent arc detection and control system based on SPI multi-chip cascade according to claim 1, characterized in that: The first communication interface is at least one of the following: CAN, RS485, UART, Ethernet, and PLC power carrier.

3. The intelligent arc detection and control system based on SPI multi-chip cascade according to claim 1 or 2, characterized in that: The SPI bus is a daisy chain topology structure, and the arc host chip and the arc slave chip are cascaded in sequence through MOSI, MISO, SCK, and NSS signal lines.

4. The intelligent arc detection and control system based on SPI multi-chip cascade as claimed in claim 3, characterized in that: The arcing master chip sequentially loads firmware and collects status data of the arcing slave chips through a chip select signal CS polling method.

5. The intelligent arc detection and control system based on SPI multi-chip cascade according to claim 1, characterized in that: The RAM of the arcing slave chip is an on-chip SRAM, and the firmware is written by the arcing master chip through DMA before running.

6. The intelligent arc detection and control system based on SPI multi-chip cascade according to claim 1, characterized in that: The external FLASH memory adopts a dual-image backup mechanism, and when a firmware verification error is detected, it automatically switches to the backup image for reloading.

7. The intelligent arc detection and control system based on SPI multi-chip cascade according to claim 1, characterized in that: The arc host chip and the arc slave chip are MCUs of the same model, and a hardware CRC check module is integrated inside the MCU for performing data integrity verification during firmware distribution and status feedback.

8. An arc detection method for the system according to any one of claims 1 to 7, characterized in that: The following steps are involved: S1. After the arc host chip is powered on, the arc detection firmware is loaded from the external FLASH memory; S2. The arc host chip distributes the firmware to each arc slave chip through the SPI bus, so that the arc slave chips run in their respective RAMs; S3. Each arc slave chip detects the arc status in real time and transmits the status data back to the arc host chip through the SPI bus; S4. The arc host chip summarizes the status data of each arc slave chip and reports it to the inverter host computer through the first communication interface; S5. The inverter host computer executes a shutdown or alarm decision based on the summarized data.

9. The arc detection method according to claim 8, wherein: In step S2, it also includes: the arcing master chip selects each arcing slave chip in turn through the chip selection signal CS, and uses a pipeline method to distribute firmware and return status in parallel.

10. The arc detection method according to claim 8 or 9, characterized in that: In step S3, the status data includes an arc fault flag, an arc intensity value, a timestamp, and a chip ID, and is transmitted via the SPI bus in a compressed encoding format.

Images