Clock control system and method

Abstract

This invention relates to the field of signal processing technology and discloses a clock control system and method. In this invention, the first clock module and the second clock module have the same structure. The input terminal of a phase detector is connected to both the first and second clock modules, and the output terminal is connected to a controller. The phase detector compares and determines the phase difference between the clock signals output by the first and second clock modules and feeds it back to the controller. The controller is connected to both the first and second clock modules and outputs an adjustment signal to either the first or second clock module based on the phase difference. A combiner is connected to both the first and second clock modules and combines the clock signals output by the first and second clock modules before outputting the result. Self-calibration is achieved through the main clock link and the compensation clock link, reducing the phase difference between the clock signals of the main clock link and the compensation clock link, eliminating interference from the external environment, thereby reducing phase noise and improving stability.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and more specifically to a clock control system and method. Background Technology

[0002] The accuracy and stability of the clock module directly affect the overall performance of the spectrum analyzer and the accuracy of the measurement results. In the clock module, the phase noise generated by the crystal oscillator directly affects the spectrum analyzer's ability to detect weak signals, reducing its resolution, signal-to-noise ratio, and other performance characteristics. Furthermore, as the crystal oscillator ages over time, its phase noise further worsens the performance impact. In addition, the reference signal of the clock module is also affected by environmental factors such as temperature and vibration, leading to frequency drift and other problems. The combined effect of these factors results in high phase noise interference and low stability in current clock modules. Summary of the Invention

[0003] In view of this, the present invention provides a clock control system and method to solve the problems of high phase noise interference and low stability of clock modules.

[0004] In a first aspect, the present invention provides a clock control system, the system comprising:

[0005] First clock module, second clock module, phase detector, controller and combiner;

[0006] The first clock module and the second clock module have the same structure;

[0007] The input terminal of the phase detector is connected to both the first clock module and the second clock module, and the output terminal is connected to the controller. The phase detector compares and determines the phase difference between the clock signals output by the first clock module and the second clock module, and feeds it back to the controller.

[0008] The controller is connected to both the first clock module and the second clock module, and the controller outputs an adjustment signal to the first clock module or the second clock module based on the phase difference;

[0009] The combiner is connected to both the first clock module and the second clock module. The combiner combines the clock signals output by the first clock module and the second clock module and outputs them.

[0010] In one alternative implementation, the first clock module includes a first digital-to-analog converter, a first crystal oscillator, and a first coupler;

[0011] The first digital-to-analog converter is connected to both the controller and the first crystal oscillator, converting the signal output by the controller into an analog signal and outputting it to the first crystal oscillator.

[0012] The first crystal oscillator is connected to the first coupler, and the first coupler couples the first clock signal output by the first crystal oscillator to the phase detector.

[0013] In one alternative implementation, the first clock module further includes a first phase-locked loop and a first power divider;

[0014] The first power divider is connected to the first phase-locked loop, the first crystal oscillator, and the first coupler respectively. The first power divider splits the first clock signal output by the first crystal oscillator into two paths and feeds them back to the first phase-locked loop and the first coupler respectively.

[0015] The first phase-locked loop is connected to the first crystal oscillator. The first phase-locked loop receives an externally input reference signal and synchronizes the first clock signal with the reference signal.

[0016] In one alternative implementation, the first clock module further includes a first switch;

[0017] The first switch is connected to the first phase-locked loop, the first digital-to-analog converter, and the first crystal oscillator, respectively.

[0018] In one alternative implementation, the system further includes a third power divider;

[0019] The third power divider is connected to the second phase-locked loop of the first phase-locked loop and the second phase-locked loop of the second clock module. The third power divider splits the externally input reference signal into two paths and feeds them back to the first phase-locked loop and the second phase-locked loop, respectively.

[0020] In one alternative implementation, the system further includes an analog-to-digital converter;

[0021] The analog-to-digital converter is connected to both the phase detector and the controller. The analog-to-digital converter converts the phase difference output by the phase detector into a digital signal and outputs it to the controller.

[0022] In a second aspect, the present invention provides a clock control method, applied in a clock control system of the first aspect or any corresponding embodiment thereof, the method comprising:

[0023] The first clock module generates and outputs a first clock signal based on the initial configuration signal, and the second clock module generates and outputs a second clock signal based on the initial configuration signal.

[0024] The phase detector determines the phase difference between the first clock module and the second clock module based on the first clock signal and the second clock signal, and feeds it back to the controller;

[0025] The controller determines the adjustment signal based on the phase difference and outputs the adjustment signal to the first clock module or the second clock module.

[0026] The first clock module or the second clock module adjusts the corresponding clock signal based on the adjustment signal.

[0027] In one optional implementation, a first clock module generates and outputs a first clock signal based on an initial configuration signal, and a second clock module generates and outputs a second clock signal based on the initial configuration signal, including:

[0028] If the initial configuration signal is the signal output by the controller, then in the first clock module, the first switch controls the connection between the first digital-to-analog converter and the first crystal oscillator, so that the first digital-to-analog converter controls the first crystal oscillator to generate and output the first clock signal based on the initial configuration signal;

[0029] In the second clock module, the second switch controls the connection between the second digital-to-analog converter and the second crystal oscillator, so that the second digital-to-analog converter controls the second crystal oscillator to generate and output the second clock signal based on the initial configuration signal.

[0030] In one optional implementation, a first clock module generates and outputs a first clock signal based on an initial configuration signal, and a second clock module generates and outputs a second clock signal based on the initial configuration signal, including:

[0031] If the initial configuration signal is an externally input signal, then in the first clock module, the first switch controls the first phase-locked loop to connect with the first crystal oscillator, so that the first phase-locked loop controls the first crystal oscillator to generate and output the first clock signal based on the initial configuration signal;

[0032] In the second clock module, the second switch controls the connection between the second digital-to-analog converter and the second crystal oscillator, so that the second digital-to-analog converter controls the second crystal oscillator to generate and output a second clock signal based on the reference signal output by the controller. The reference signal is generated by the controller based on the initial configuration signal input by an external source.

[0033] In one alternative implementation, the controller determines the adjustment signal based on the phase difference, including:

[0034] The controller searches for the correspondence between the phase difference and the adjustment signal based on the phase difference to determine the adjustment signal corresponding to the phase difference. The correspondence between the phase difference and the adjustment signal is calculated based on gradient descent.

[0035] The clock control system provided in this embodiment of the invention sets up two clock modules with identical structures, using one clock module as the main clock link and the other as the compensation clock link. This allows for internal self-calibration of the clock system through the main clock link and the compensation clock link, thereby eliminating interference from the external environment and improving stability. A phase detector determines the phase difference between the clock signals output by the two clock modules, and a controller determines the adjustment signal corresponding to this phase difference. Based on the adjustment signal, the clock module serving as the compensation clock link is controlled to adjust its output clock signal, thereby reducing the phase difference between the clock signals of the main clock link and the compensation clock link, and thus reducing phase noise. Attached Figure Description

[0036] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the architecture of a clock control system provided in an embodiment of the present invention;

[0038] Figure 2 This is a schematic diagram of the structure of a clock control system provided in an embodiment of the present invention;

[0039] Figure 3 This is a flowchart illustrating a clock control method provided in an embodiment of the present invention;

[0040] Explanation of reference numerals in the attached figures:

[0041] 1. First clock module; 2. Second clock module; 3. Phase detector; 4. Controller; 5. Combiner. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] The accuracy and stability of the clock module directly affect the overall performance of the spectrum analyzer and the accuracy of the measurement results. In the clock module, the phase noise generated by the crystal oscillator directly affects the spectrum analyzer's ability to detect weak signals, reducing its resolution, signal-to-noise ratio, and other performance characteristics. Furthermore, as the crystal oscillator ages over time, its phase noise further worsens the performance impact. In addition, the reference signal of the clock module is also affected by environmental factors such as temperature and vibration, leading to frequency drift and other problems. The combined effect of these factors results in high phase noise interference and low stability in current clock modules.

[0044] Based on this, the present invention provides a clock control system, comprising: a first clock module, a second clock module, a phase detector, a controller, and a combiner; wherein the first clock module and the second clock module have the same structure; the input terminal of the phase detector is connected to both the first clock module and the second clock module, and the output terminal is connected to the controller; the phase detector compares and determines the phase difference between the clock signals output by the first clock module and the second clock module, and feeds it back to the controller; the controller is connected to both the first clock module and the second clock module, and outputs an adjustment signal to the first clock module or the second clock module based on the phase difference; the combiner is connected to both the first clock module and the second clock module, and combines the clock signals output by the first clock module and the second clock module and outputs them. This invention uses two clock modules with identical structures, one as the main clock link and the other as a compensation clock link. This allows for self-calibration within the clock system, eliminating external interference and improving stability. A phase detector determines the phase difference between the clock signals output by the two modules, and a controller determines the corresponding adjustment signal. Based on this adjustment signal, the clock module acting as the compensation clock link is controlled to adjust its output clock signal, thereby reducing the phase difference between the clock signals of the main and compensation clock links and thus lowering phase noise.

[0045] It should be noted that the terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0046] According to an embodiment of the present invention, a clock control system embodiment is provided. For example... Figure 1 As shown, the system includes: a first clock module 1, a second clock module 2, a phase detector 3, a controller 4, and a combiner 5. The first clock module 1 and the second clock module 2 have the same structure. In the first clock module 1 and the second clock module 2, one clock module serves as the main clock link, and the other clock module serves as the compensation clock link. By comparing and adjusting the clock signals of the main clock link and the compensation clock link, the clock signal self-calibration within the clock control system is achieved.

[0047] In this embodiment of the invention, the input terminal of the phase detector 3 is connected to both the first clock module 1 and the second clock module 2, and the output terminal is connected to the controller 4. The phase detector 3 compares and determines the phase difference between the clock signals output by the first clock module 1 and the second clock module 2, and feeds it back to the controller 4.

[0048] In this embodiment of the invention, the controller 4 is connected to both the first clock module 1 and the second clock module 2. The controller 4 outputs an adjustment signal to the first clock module 1 or the second clock module 2 based on the phase difference. The combiner 5 is connected to both the first clock module 1 and the second clock module 2. The combiner 5 combines the clock signals output by the first clock module 1 and the second clock module 2 and outputs them.

[0049] In one alternative implementation, Figure 2 This is a schematic diagram of a clock control system provided in an embodiment of the present invention, as shown below. Figure 2 As shown, the first clock module 1 includes a first digital-to-analog converter, a first crystal oscillator, and a first coupler.

[0050] The first digital-to-analog converter (DAC) converts digital signals into analog signals. It is connected to both the controller 4 and the first crystal oscillator. The controller 4 outputs a digital signal, which the DAC converts back to an analog signal and outputs to the first crystal oscillator. It should be noted that if the first clock module 1 is used as the master clock link, the controller 4 outputs a signal to the DAC of the first clock module 1 only when the reference clock is an internal reference source. In this case, the reference clock is generated by the controller 4 and output to both the first clock module 1 and the second clock module 2. If the first clock module 1 is used as a compensation clock link, the controller 4 outputs an adjustment signal to the DAC of the first clock module 1 regardless of whether the reference clock is an internal or external reference source.

[0051] In one alternative implementation, such as Figure 2 As shown, the first crystal oscillator is connected to the first coupler, and the first coupler couples the first clock signal output by the first crystal oscillator to the phase detector 3.

[0052] In one alternative implementation, such as Figure 2 As shown, the first clock module 1 further includes a first phase-locked loop (PLL) and a first power divider. The first power divider is connected to the first PLL, the first crystal oscillator, and the first coupler, respectively. The first power divider splits the first clock signal output from the first crystal oscillator into two paths and feeds them back to the first PLL and the first coupler, respectively. The first PLL is connected to the first crystal oscillator, receives an externally input reference signal, and synchronizes the first clock signal with the reference signal. When an external reference source is used as the reference clock, a first phase-locked loop (PLL) and a first power divider are used to ensure that the clock signal generated by the crystal oscillator in the clock module is consistent with the reference clock. The first power divider splits the first clock signal output by the first crystal oscillator into two paths. One path is fed back to the first coupler, which couples the first clock signal to the phase detector 3, ensuring that the phase detector 3 can determine the phase difference between the clock signals output by the first clock module 1 and the second clock module 2. The other path is fed back to the first PLL, which compares the externally input reference signal with the first clock signal. If the two are inconsistent, the first PLL controls the first crystal oscillator to adjust the generated first clock signal so that the first clock signal is consistent with the externally input reference clock.

[0053] In one alternative implementation, such as Figure 2 As shown, the first clock module 1 further includes a first switch, which is used to select and switch the signal controlling the first crystal oscillator under different conditions of internal reference source and external reference source, and under different conditions of the first clock module 1 as the main clock link and the compensation clock link; the selection and switching of the signal by the first switch can be referred to the following method embodiment. The first switch is connected to the first phase-locked loop, the first digital-to-analog converter and the first crystal oscillator respectively.

[0054] In one alternative implementation, such as Figure 2 As shown, the second clock module 2 has the same structure as the first clock module 1, that is, the second clock module 2 includes a second digital-to-analog converter, a second crystal oscillator, a second coupler, a second phase-locked loop, a second power divider and a second switch. The connection relationship and function of each component in the second clock module 2 can be referred to the above description of the first clock module 1, and will not be repeated here.

[0055] In an optional implementation, the system further includes a third power divider; the third power divider is connected to the second phase-locked loop of the first phase-locked loop and the second phase-locked loop of the second clock module 2, respectively. The third power divider splits the externally input reference signal into two paths and feeds them back to the first phase-locked loop and the second phase-locked loop, respectively. Then, the signal controlling the crystal oscillator in the first clock module 1 and the second switch in the second clock module 2 are selected by the first switch in the first clock module 1 and the second switch in the second clock module 2, so that the externally input reference signal can be input into both clock modules, so that both clock modules can be used as master clock links, thereby improving the flexibility of the clock control system.

[0056] In one alternative implementation, such as Figure 2 As shown, the system also includes an analog-to-digital converter (ADC). The ADC is connected to both the phase detector 3 and the controller 4. Since the output of the phase detector 3 is an analog signal, and the controller 4 needs to receive digital signals, the ADC is connected between the phase detector 3 and the controller 4. The ADC converts the phase difference output by the phase detector 3 into a digital signal and outputs it to the controller 4.

[0057] The clock control system provided in this embodiment of the invention sets up two clock modules with identical structures, using one clock module as the main clock link and the other as the compensation clock link. This allows for internal self-calibration of the clock system through the main clock link and the compensation clock link, thereby eliminating interference from the external environment and improving stability. A phase detector determines the phase difference between the clock signals output by the two clock modules, and a controller determines the adjustment signal corresponding to this phase difference. Based on the adjustment signal, the clock module serving as the compensation clock link is controlled to adjust its output clock signal, thereby reducing the phase difference between the clock signals of the main clock link and the compensation clock link, and thus reducing phase noise.

[0058] According to an embodiment of the present invention, a clock control method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0059] This embodiment provides a clock control method that can be used in the aforementioned clock control system. Figure 3 This is a flowchart illustrating a clock control method provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the process includes the following steps:

[0060] In step S301, the first clock module 1 generates and outputs a first clock signal based on the initial configuration signal, and the second clock module 2 generates and outputs a second clock signal based on the initial configuration signal.

[0061] In this embodiment of the invention, the initial configuration signal is the reference signal, also known as the reference clock. The initial configuration signal can be externally input, i.e., an external reference source, or it can be internally generated, i.e., an internal reference source. Specifically, for the clock module serving as the master clock link, its initial configuration signal changes differently depending on the reference source. For the clock module serving as the compensation clock link, its initial configuration signal is internally generated, i.e., generated by the controller 4.

[0062] In one optional implementation, taking the first clock module 1 as the master clock link and the second clock module 2 as the compensation clock link as an example, step S301 will be described in detail:

[0063] If the initial configuration signal is the signal output by controller 4, i.e., the internal reference source, then in the first clock module 1, the first switch controls the connection between the first digital-to-analog converter and the first crystal oscillator to output the initial configuration signal from controller 4 to the first crystal oscillator. This allows the first digital-to-analog converter to control the first crystal oscillator to generate and output a first clock signal based on the initial configuration signal. In the second clock module 2, the second switch controls the connection between the second digital-to-analog converter and the second crystal oscillator to output the initial configuration signal from controller 4 to the first crystal oscillator. This allows the second digital-to-analog converter to control the second crystal oscillator to generate and output a second clock signal based on the initial configuration signal.

[0064] If the initial configuration signal is an externally input signal, i.e., an external reference source, then in the first clock module 1, the first switch controls the first phase-locked loop to connect with the first crystal oscillator, so as to output the externally input initial configuration signal to the first crystal oscillator, thereby enabling the first phase-locked loop to control the first crystal oscillator to generate and output the first clock signal based on the initial configuration signal; in the second clock module 2, the second switch controls the second digital-to-analog converter to connect with the second crystal oscillator, so as to output the initial configuration signal output by the controller 4 to the first crystal oscillator, thereby enabling the second digital-to-analog converter to control the second crystal oscillator to generate and output the second clock signal based on the reference signal output by the controller 4, wherein the reference signal output by the controller 4 is generated by the controller 4 based on the externally input initial configuration signal.

[0065] In the case of an internal reference source, the initial configuration signal generated by controller 4 is based on user-defined configuration information. The user pre-configures the signal performance parameters of the clock signal, such as frequency, phase, and amplitude, and controller 4 generates the initial configuration signal based on this configuration. In the case of an external reference source, the reference signal generated by controller 4 based on the externally input initial configuration signal can be generated by parsing the externally input initial configuration signal, or, as shown in the case of an internal reference source, based on user-defined configuration information. Similarly, the initial configuration signal of the externally input signal is also generated based on user-defined configuration information.

[0066] It should be noted that the above examples are merely illustrative of embodiments of the present invention and are not intended to limit the main clock link and the compensation clock link. In practical applications, the second clock module 2 can also be used as the main clock link and the first clock module 1 can be used as the compensation clock link.

[0067] In step S302, the phase detector 3 determines the phase difference between the first clock module 1 and the second clock module 2 based on the first clock signal and the second clock signal, and feeds it back to the controller 4.

[0068] In this embodiment of the invention, the phase detector 3 compares the first clock signal and the second clock signal to determine the phase difference between the first clock signal and the second clock signal. After obtaining the phase difference, it outputs the phase difference of the analog quantity into a digital quantity through an analog-to-digital converter and feeds it back to the controller 4 so that the controller 4 can determine the adjustment signal based on the phase difference.

[0069] In step S303, the controller 4 determines the adjustment signal based on the phase difference and outputs the adjustment signal to the first clock module 1 or the second clock module 2.

[0070] In this embodiment of the invention, the controller 4 searches for the correspondence between the phase difference and the adjustment signal based on the phase difference, determines the adjustment signal corresponding to the phase difference, and outputs the adjustment signal to the first clock module 1 or the second clock module 2. Specifically, it outputs the signal to the clock module that serves as the compensation clock link. The correspondence between the phase difference and the adjustment signal is calculated based on gradient descent.

[0071] In one optional implementation, when calculating the correspondence between the phase difference and the adjustment signal based on gradient descent, a function for the change of phase noise power is set. This function can be measured by an external phase noise meter or obtained through digital signal processing, such as FFT analysis of phase jitter. The phase difference parameter and learning rate are initialized. During iteration, the gradient of the function is calculated using the current phase difference parameter. Based on the set learning rate, the function moves one step along the negative gradient direction to update the phase difference. This process is repeated multiple times until the gradient approaches zero, yielding the phase adjustment amount corresponding to the current phase difference. Thus, the correspondence between the phase adjustment amount and the phase difference is calculated. Simultaneously, since the controller 4 outputs a digital signal, a correspondence is established between the phase adjustment amount and the signal voltage value output by the controller 4. This establishes the correspondence between the phase difference and the signal voltage value, which is the correspondence between the phase difference and the adjustment signal.

[0072] In step S304, the first clock module 1 or the second clock module 2 adjusts the corresponding clock signal based on the adjustment signal.

[0073] In this embodiment of the invention, the clock module, serving as the compensation clock link, adjusts the corresponding clock signal based on the adjustment signal. This process is repeated iteratively until the phase difference between the first and second clock signals meets the phase difference requirement, or the number of iterations reaches a threshold. At this point, the first and second clock signals are combined and output via combiner 5.

[0074] In one optional implementation, the signals output by controller 4, namely the initial configuration signal and the adjustment signal, can both be output to the first clock module 1 and the second clock module 2. These signals are then selected by the first and second switches in the first and second clock modules 1 and 2 before being output to the corresponding crystal oscillators. Specifically, if the first clock module 1 serves as the master clock link and the second clock module 2 serves as the compensation clock link, then with an internal reference source, the first switch connects the first digital-to-analog converter (DAC) to the first crystal oscillator, and the second switch connects the second DAC to the second crystal oscillator. With an external reference source, the first switch connects the first phase-locked loop (PLL) to the first crystal oscillator, and the second switch connects the second DAC to the second crystal oscillator. If the first clock module 1 serves as the compensation clock link and the second clock module 2 serves as the master clock link, then with an internal reference source, the first switch connects the first DAC to the first crystal oscillator, and the second switch connects the second DAC to the second crystal oscillator. With an external reference source, the first switch connects the first DAC to the first crystal oscillator, and the second switch connects the second PLL to the second crystal oscillator.

[0075] The clock control method provided in this invention sets up two clock modules with identical structures, using one clock module as the main clock link and the other as the compensation clock link. This allows for self-calibration within the clock system through the main and compensation clock links, thereby eliminating interference from the external environment and improving stability. A phase detector determines the phase difference between the clock signals output by the two clock modules, and a controller determines the adjustment signal corresponding to this phase difference. Based on this adjustment signal, the clock module acting as the compensation clock link is controlled to adjust its output clock signal, thereby reducing the phase difference between the clock signals of the main and compensation clock links and thus lowering phase noise.

[0076] Although embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the present invention.

Claims

1. A clock control system, characterized in that, The system includes: The system consists of a first clock module (1), a second clock module (2), a phase detector (3), a controller (4), and a combiner (5). The first clock module (1) and the second clock module (2) have the same structure; The input terminal of the phase detector (3) is connected to both the first clock module (1) and the second clock module (2), and the output terminal is connected to the controller (4). The phase detector (3) compares and determines the phase difference between the clock signals output by the first clock module (1) and the second clock module (2), and feeds it back to the controller (4). The controller (4) is connected to both the first clock module (1) and the second clock module (2), and the controller (4) outputs an adjustment signal to the first clock module (1) or the second clock module (2) based on the phase difference. The combiner (5) is connected to both the first clock module (1) and the second clock module (2). The combiner (5) combines the clock signals output by the first clock module (1) and the second clock module (2) and outputs them. The first clock module (1) includes a first digital-to-analog converter, a first crystal oscillator, a first coupler, a first phase-locked loop, and a first power divider; The first digital-to-analog converter is connected to the controller (4) and the first crystal oscillator respectively, and converts the signal output by the controller (4) into an analog signal and outputs it to the first crystal oscillator; The first crystal oscillator is connected to the first coupler, and the first coupler couples the first clock signal output by the first crystal oscillator to the phase detector (3). The first power divider is connected to the first phase-locked loop, the first crystal oscillator and the first coupler respectively. The first power divider splits the first clock signal output by the first crystal oscillator into two paths and feeds them back to the first phase-locked loop and the first coupler respectively. The first phase-locked loop is connected to the first crystal oscillator. The first phase-locked loop receives an externally input reference signal and synchronizes the first clock signal with the reference signal.

2. The system according to claim 1, characterized in that, The first clock module (1) also includes a first switch; The first switch is connected to the first phase-locked loop, the first digital-to-analog converter, and the first crystal oscillator, respectively.

3. The system according to claim 2, characterized in that, The system also includes a third power divider; The third power divider is connected to the second phase-locked loop of the first phase-locked loop and the second phase-locked loop of the second clock module (2), respectively. The third power divider splits the externally input reference signal into two paths and feeds them back to the first phase-locked loop and the second phase-locked loop, respectively.

4. The system according to claim 1, characterized in that, The system also includes an analog-to-digital converter; The analog-to-digital converter is connected to the phase detector (3) and the controller (4) respectively. The analog-to-digital converter converts the phase difference output by the phase detector (3) into a digital signal and outputs it to the controller (4).

5. A clock control method, characterized in that, Applied to the clock control system according to any one of claims 1-4, the method comprises: The first clock module (1) generates and outputs a first clock signal based on the initial configuration signal, and the second clock module (2) generates and outputs a second clock signal based on the initial configuration signal; The phase detector (3) determines the phase difference between the first clock module (1) and the second clock module (2) based on the first clock signal and the second clock signal, and feeds it back to the controller (4). The controller (4) determines the adjustment signal based on the phase difference and outputs the adjustment signal to the second clock module (2). The first clock module (1) or the second clock module (2) adjusts the corresponding clock signal based on the adjustment signal.

6. The method according to claim 5, characterized in that, The first clock module (1) generates and outputs a first clock signal based on the initial configuration signal, and the second clock module (2) generates and outputs a second clock signal based on the initial configuration signal, including: If the initial configuration signal is the signal output by the controller (4), then in the first clock module (1), the first switch controls the first digital-to-analog converter to connect with the first crystal oscillator, so that the first digital-to-analog converter controls the first crystal oscillator to generate and output the first clock signal based on the initial configuration signal; In the second clock module (2), the second switch controls the second digital-to-analog converter to connect with the second crystal oscillator, so that the second digital-to-analog converter controls the second crystal oscillator to generate and output the second clock signal based on the initial configuration signal.

7. The method according to claim 5, characterized in that, The first clock module (1) generates and outputs a first clock signal based on the initial configuration signal, and the second clock module (2) generates and outputs a second clock signal based on the initial configuration signal, including: If the initial configuration signal is an externally input signal, then in the first clock module (1), the first switch controls the first phase-locked loop to connect with the first crystal oscillator, so that the first phase-locked loop controls the first crystal oscillator to generate and output the first clock signal based on the initial configuration signal; In the second clock module (2), the second switch controls the second digital-to-analog converter to connect with the second crystal oscillator, so that the second digital-to-analog converter controls the second crystal oscillator to generate and output a second clock signal based on the reference signal output by the controller (4), wherein the reference signal is generated by the controller (4) based on the initial configuration signal of the external input.

8. The method according to claim 5, characterized in that, The controller (4) determines the adjustment signal based on the phase difference, including: The controller (4) searches for the correspondence between the phase difference and the adjustment signal based on the phase difference, and determines the adjustment signal corresponding to the phase difference. The correspondence between the phase difference and the adjustment signal is calculated based on gradient descent.

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