A hard relay arbitration circuit for a CAN bus

Abstract

The application discloses a CAN bus hard relay arbitration circuit and relates to the technical field of relay circuits.The application is characterized in that two transceivers, two OR gates and two switching elements are arranged and logically connected;in specific work, when CAN1 is a dominant level, U1 does not drive CAN1, CAN1 keeps receiving, and U2 sends a dominant level to CAN2;when CAN1 is a recessive level, U1 does not drive CAN1, U2 does not drive CAN2, and CAN2 becomes a recessive level, completing logic transmission;when CAN1 and CAN2 are both dominant levels, the circuit competes and arbitrates through logic inversion, and CAN1 and CAN2 simultaneously receive a dominant level;the application realizes the relay of CAN bus signals through hardware, and simultaneously realizes logic arbitration through a logic circuit, can directly process physical layer signals, does not cause time delay when processing signals, automatically arbitrates and relays CAN bus signals through logic arbitration, thereby avoiding signal conflict and realizing real-time communication of the CAN bus.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of relay circuit, in particular to a CAN bus hard relay arbitration circuit. BACKGROUND

[0002] CAN bus (Controller Area Network) is a serial communication protocol bus for real-time applications, which can use twisted pair to transmit signals, and is one of the most widely used field buses in the world; CAN protocol is used for communication between various elements in the car, replacing expensive and bulky power distribution harness, and the robustness of the protocol extends to other automation and industrial applications; the characteristics of CAN protocol include serial data communication integrity, real-time support, transmission rate up to 1Mb / s, 11-bit addressing and error detection capability. CAN bus uses serial data transmission, can run at 1Mb / s on 40m twisted pair, can also use optical cable connection, and the bus protocol supports multiple master controllers on this bus; when a node (station) on the CAN bus sends data, it broadcasts the message to all nodes in the network. For each node, whether the data is sent to itself or not, it is received; when a station wants to send data to other stations, the CPU of the station transmits the data to be sent and its own identifier to the CAN chip of the station, and is in a ready state; when it receives bus allocation, it turns to the state of sending message.

[0003] A repeater is a device that connects network lines, commonly used for bidirectional forwarding of physical signals between two network nodes; the repeater mainly completes the function of the physical layer, responsible for bit-by-bit transmission of information on the physical layer of two nodes, and completes the functions of signal copying, adjustment and amplification, so as to extend the length of the network; hard relay is to realize signal relay through special hardware (not software or protocol), which usually directly processes physical layer signals (such as electromagnetic waves, optical signals, etc.), without decoding or regenerating data; soft relay is to control the forwarding behavior of network equipment through software configuration, realizing transparent transmission and routing selection of data; arbitration in bus communication refers to the process of deciding which device gets the bus control right when multiple devices request to use the bus at the same time, and the core goal is to avoid conflicts (such as data damage or transmission failure) and ensure fair and efficient allocation of bus resources.

[0004] The relay arbitration scheme of the CAN bus at present includes a conventional relay and a soft relay arbitration; the conventional relay is a circuit adopting transceiver cross connection, but when two ports of the receiver simultaneously receive the dominant level, the CAN bus is simultaneously occupied at this time, which means that the communication of the CAN bus will have a large delay; the soft relay arbitration is to use a double CAN controller to perform relay arbitration, but the double CAN controller needs to completely receive a data frame and then forward, which has a large delay and the signal will have a conflict.

[0005] Therefore, the relay arbitration scheme at present is difficult to ensure low delay while avoiding signal conflict, and is difficult to perform real-time communication of the CAN bus. SUMMARY

[0006] The embodiment of the application provides a hard relay arbitration circuit of a CAN bus, which can solve the problem that real-time communication of the CAN bus is difficult to be performed in the prior art.

[0007] The embodiment of the application provides a hard relay arbitration circuit of a CAN bus, which comprises a first CAN transceiver U1, a second CAN transceiver U2, a first OR gate U3, a second OR gate U4, a first switching element Q1 and a second switching element Q2.

[0008] The first CAN transceiver U1 is connected with a first CAN bus CAN1, and the second CAN transceiver U2 is connected with a second CAN bus CAN2.

[0009] One input end of the second OR gate U4 is connected with a receiving end RXD1 of the first CAN transceiver U1, another input end of the second OR gate U4 is connected with a control end of the second switching element Q2, and an output end of the second switching element Q2 is connected with a sending end TXD1 of the first CAN transceiver U1 and an output end of the first OR gate U3.

[0010] One input end of the first OR gate U3 is connected with a control end of the first switching element Q1, an output end of the first switching element Q1 is connected with a sending end TXD2 of the second CAN transceiver U2 and an output end of the second OR gate U4, and another input end of the first OR gate U3 is connected with a receiving end RXD2 of the second CAN transceiver U2.

[0011] When the CAN1 is a dominant level, the TXD1 is 1, the RXD1 is 0, the Q2 is cut off, the U4 outputs 0, the TXD2 is 0, the U2 sends the dominant level to the CAN2, the RXD2 is 0, the Q1 is turned on, the U3 outputs 1, the TXD1 is 1, the U1 does not drive the CAN1, and the CAN1 keeps receiving.

[0012] When CAN1 is recessive level, U1 does not drive CAN1, RXD1 is 1, TXD1 is 1, U2 does not drive CAN2, CAN2 becomes recessive level, RXD2 is 1, TXD2 is 1, completing logic transmission;

[0013] When CAN1 and CAN2 are both dominant level, RXD1 and RXD2 are 0, TXD1 and TXD2 are 1, after competing arbitration by logic inversion, TXD1 and TXD2 become 0, RXD1 and RXD2 become 1, CAN1 and CAN2 receive dominant level at the same time.

[0014] Preferably, it further comprises resistance R1, resistance R2, resistance R3, resistance R4, capacitor C1 and capacitor C2;

[0015] The resistance R1 and the capacitor C1 are connected in parallel, and the resistance R1 and the capacitor C1 are connected to the input end of the first OR gate U3 at the same time, and the other end of the resistance R1 and the capacitor C1 is connected to the ground at the same time; the output end of the first switch element Q1 is connected with the transmitting end TXD2 of the second CAN transceiver U2 through the resistance R3;

[0016] The resistance R2 and the capacitor C2 are connected in parallel, and the resistance R2 and the capacitor C2 are connected to the input end of the second OR gate U4 at the same time, and the other end of the resistance R2 and the capacitor C2 is connected to the ground at the same time; the output end of the second switch element Q2 is connected with the transmitting end TXD1 of the first CAN transceiver U1 through the resistance R4.

[0017] Preferably, the network composed of the resistance R1 and the capacitor C1 in parallel, and the network composed of the resistance R2 and the capacitor C2 in parallel, has a time constant between 150ns and 320ns;

[0018] The time constant is expressed as:

[0019] .

[0020] Preferably, the first switch element Q1 and the second switch element Q2 are triodes or field effect tubes;

[0021] The on-off state of the first switch element Q1 is controlled by the output level of the transmitting end TXD2 of the second CAN transceiver U2;

[0022] The on-off state of the second switch element Q2 is controlled by the output level of the transmitting end TXD1 of the first CAN transceiver U1.

[0023] Preferably, the amplification of the triode is higher than 100.

[0024] Preferably, the logic control circuit composed of the first OR gate U3 and the first switching element Q1, and the logic control circuit composed of the second OR gate U4 and the second switching element Q2 are equivalent to optical isolation circuits.

[0025] The optical isolation circuits perform level logic conversion through inverters and NOR gates.

[0026] Preferably, the optical isolation circuits further comprise optical transmitters and optical receivers.

[0027] The optical transmitters and optical receivers are connected to optical signal channels of the first CAN bus CAN1 or the second CAN bus CAN2.

[0028] Preferably, the first CAN transceiver U1 and the second CAN transceiver U2 are TCAN1051 transceivers.

[0029] Preferably, power supply pins of the first CAN transceiver U1 and the second CAN transceiver U2 are configured with hot plug protection circuits.

[0030] The hot plug protection circuits comprise soft-start MOS tubes and overcurrent protection chips, and are used to support plug operations during bus operation.

[0031] Preferably, the hard relay arbitration circuit is packaged in a metal shielding shell, the inner wall of the shell is coated with a conductive coating, and the shell ground pin GND is grounded through a low-impedance path, so as to isolate electromagnetic interference.

[0032] Compared with the prior art, the embodiment of the present application has the following beneficial effects:

[0033] The application sets the first CAN transceiver U1, the second CAN transceiver U2, the first OR gate U3, the second OR gate U4, the first switch element Q1 and the second switch element Q2, and logically connects these elements; in the specific work, when CAN1 is the dominant level, U1 does not drive CAN1, CAN1 keeps receiving, and U2 sends the dominant level to CAN2; when CAN1 is the recessive level, U1 does not drive CAN1, U2 does not drive CAN2 either, and CAN2 becomes the recessive level, completing the logic transmission; when CAN1 and CAN2 are the dominant level at the same time, after the circuit competes and arbitrates through the logic inversion, CAN1 and CAN2 receive the dominant level at the same time; the application realizes the relay of the CAN bus signal through the hardware, and realizes the logic arbitration of the signal through the first OR gate U3, the second OR gate U4, the first switch element Q1 and the second switch element Q2, can directly process the signal of the physical layer, so that the delay is not generated when the signal is processed, and the CAN bus signal is automatically arbitrated and relayed through the logic arbitration, so as to determine which device obtains the control right of the bus, thereby avoiding the signal conflict and ensuring the effective allocation of the bus resource, and realizing the real-time communication of the CAN bus. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 A general relay circuit schematic diagram shown by the CAN bus hard relay arbitration circuit provided by the embodiment of the application;

[0035] Figure 2 A general soft relay circuit schematic diagram shown by the CAN bus hard relay arbitration circuit provided by the embodiment of the application;

[0036] Figure 3 A punching relay circuit schematic diagram shown by the CAN bus hard relay arbitration circuit provided by the embodiment of the application;

[0037] Figure 4 A relay circuit schematic diagram of the punching relay circuit of the CAN bus hard relay arbitration circuit provided by the embodiment of the application after the equivalent transformation. DETAILED DESCRIPTION

[0038] In order to make the above objectives, features and advantages of the application more apparent, the specific embodiments of the application are described in detail below with reference to the drawings. In the following description, a lot of specific details are set forth in order to fully understand the application. However, the application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the application, so the application is not limited by the specific embodiments disclosed below.

[0039] As Figure 1As shown, this is a typical relay design in a CAN bus. It can be seen that the two TCAN1051 transceivers are cross-connected to transmit and receive signals, thus relaying the signal. However, this design is not feasible in CAN bus communication because when a signal is transmitted through the TXD of the CAN transceiver, the RXD will return the same signal.

[0040] For example, suppose U1 receives a dominant level from the CAN1 bus. Through RXD1 -> TXD2, U2 sends a dominant level to the CAN2 bus. U2's RXD2 also feeds back a dominant level. Through RXD2 -> TXD1, U1 sends a dominant level to the CAN1 bus. In this way, U1 and U2 form a feedback loop, always maintaining a dominant level. Therefore, effective information transmission cannot be carried out between CAN1 and CAN2. Thus, this conventional relay design is unreasonable in CAN bus communication.

[0041] like Figure 2 The diagram shows a typical soft repeater design in a CAN bus, which relies on dual CAN controllers for communication. However, in areas with high interference, communication is interrupted if the controller crashes or resets due to interference. Furthermore, in latency-sensitive environments, the soft repeater receives the entire data frame before forwarding, resulting in significant delays. Additionally, dual CAN controllers are expensive and require numerous external circuits, making them unsuitable for cost- and space-constrained applications. Finally, as communication protocols evolve (CAN1.0 -> CAN2.0 -> CAN FD), the existing soft repeaters must be replaced, which is inconvenient and costly.

[0042] like Figure 3 The diagram shows the relay circuit design with arbitration according to the present invention. It is assumed that initially, the bus is idle, i.e., TXD1=RXD1=TXD2=RXD2=1 (as specified in the standard). Now the CAN1 bus is at a dominant level, so RXD1=0 (as specified in the standard). Since TXD1=1, Q2 is turned off, and the OR gate U4 outputs 0, i.e., TXD2=0. Therefore, U2 sends a dominant level to the CAN2 bus. At this time, RXD2 feedback is 0, but TXD2=0, Q1 is turned on, and the OR gate U3 outputs 1, i.e., TXD1=1. Therefore, U1 does not drive the CAN1 bus to maintain the receive mode (as specified in the standard).

[0043] Now, if CAN1 becomes recessive, RXD1=1, then TXD2=1, and U2 does not drive the bus. If CAN2 becomes recessive, RXD2=1, then TXD1=1; a logic 0 to logic 1 transmission is completed.

[0044] Now if CAN1 and CAN2 bus transmit dominant level at the same time, i.e. RXD1=RXD2=0, TXD1=TXD2=1, TXD1=TXD2=0 can be obtained, and TXD1=TXD2=1 can be obtained continuously, it can be seen that TXD1 and TXD2 quickly flip (compete) logic, as long as CAN1 and CAN2 continue to receive dominant level.

[0045] Now if CAN2 sends a recessive level, RXD2=1, TXD1=1 ->TXD2=0, TXD1=1, RXD2=0, TXD2=0 ->TXD1=1, TXD2=0. CAN1 arbitration victory, i.e. the signal transmission from CAN1 to CAN2 is completed.

[0046] Among them, Q1, Q2, U3, U4 are selected according to the corresponding bandwidth of the CAN bus speed device; since the amplification of the transistor β is generally >100, the range of R3, R4 resistance selection is very wide, i.e. it meets the requirements when selecting that it can be driven by U3, U4 and can quickly fill C1, C2; for the selection of R1, R2, C1, C2, it not only meets the fast flip of the level when competing, but also is slightly larger than the feedback delay (about 150ns) of the transceiver; in Figure 3 , , the actual measurement can well meet the 1Mbps and 5Mbps relay requirements of CAN2.0 FD.

[0047] As Figure 4 shown, it is the equivalent relay circuit after the relay circuit with arbitration shown in Figure 3 , in Figure 4 , U2 is an optical transceiver, and the other end of the optical path also has a relay conversion circuit, and since the double-channel optical transceiver is isolated, NRXD2 does not feedback the signal of NTXD2; this equivalent replacement form makes the arbitration circuit half less, and since U2 and U1 are logically opposite, U3 inverter is added, and U4 becomes NOR gate, and Q1 is changed from PNP to NPN.

[0048] The application adopts hard relay to directly process physical layer signals, avoids the delay caused by software processing, and ensures the real-time performance of signal transmission; the application enhances the transmission distance and anti-interference ability of signals by amplifying or regenerating complete signals, and can significantly improve the reliability of communication; the hard relay circuit of the application is simple in design and does not contain complex software or protocol processing, thereby reducing the system complexity and cost; the application is suitable for occasions with high requirements for real-time performance and reliability, such as automobile electronics and industrial automation, and in these fields, the hard relay technology can ensure the stable transmission of signals and improve the overall performance of the system.

[0049] The CAN bus of the application can ensure that the high-priority device can obtain the bus control right in priority through the arbitration mechanism, and can meet the transmission requirement of the key task; the arbitration process of the application will not destroy the request of the device which has not won, and these devices can re-initiate the request when the bus is idle, thereby ensuring the effective utilization of the bus resource; the application determines which device obtains the bus control right by comparing the logic level (explicit or implicit) of each node on the bus, and the explicit level has priority; in the system in which multiple devices share the bus, the arbitration mechanism designed in the application can ensure the effective utilization of the bus resource, and can avoid the data conflict and the transmission failure.

[0050] The above-mentioned embodiments only express several embodiments of the application, and the description is more specific and detailed, but it cannot be understood as the limitation of the patent scope of the application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the application, several modifications and improvements can be made, which belong to the protection scope of the application. Therefore, the protection scope of the patent of the application should be subject to the appended claims.

Claims

1. A hard relay arbitration circuit for a CAN bus, characterized in that, include: First CAN transceiver U1, second CAN transceiver U2, first OR gate U3, second OR gate U4, first switching element Q1 and second switching element Q2; The first CAN transceiver U1 is connected to the first CAN bus CAN1, and the second CAN transceiver U2 is connected to the second CAN bus CAN2; The receiving terminal RXD1 of the first CAN transceiver U1 is connected to one input terminal of the second OR gate U4, the other input terminal of the second OR gate U4 is connected to the control terminal of the second switching element Q2, and the output terminal of the second switching element Q2 is connected to the transmitting terminal TXD1 of the first CAN transceiver U1 and the output terminal of the first OR gate U3. One input terminal of the first OR gate U3 is connected to the control terminal of the first switching element Q1, the output terminal of the first switching element Q1 is connected to the transmitting terminal TXD2 of the second CAN transceiver U2 and the output terminal of the second OR gate U4, and the other input terminal of the first OR gate U3 is connected to the receiving terminal RXD2 of the second CAN transceiver U2. When CAN1 is at a dominant level, TXD1 is 1, RXD1 is 0, Q2 is off, U4 outputs 0, TXD2 is 0, U2 sends a dominant level to CAN2, RXD2 is 0, Q1 is on, U3 outputs 1, TXD1 is 1, U1 does not drive CAN1, and CAN1 continues to receive. When CAN1 is recessive, U1 does not drive CAN1, RXD1 is 1, TXD1 is 1, U2 does not drive CAN2, CAN2 becomes recessive, RXD2 is 1, TXD2 is 1, and logic transmission is completed. When CAN1 and CAN2 are both dominant, RXD1 and RXD2 are 0, and TXD1 and TXD2 are 1. After logic inversion and contention arbitration, TXD1 and TXD2 become 0, and RXD1 and RXD2 become 1. CAN1 and CAN2 then receive dominant levels simultaneously.

2. The hard relay arbitration circuit for a CAN bus according to claim 1, characterized in that, It also includes resistors R1, R2, R3, and R4, and capacitors C1 and C2; The resistor R1 and capacitor C1 are connected in parallel, and the resistor R1 and capacitor C1 are simultaneously connected to the input terminal of the first OR gate U3. The other ends of the resistor R1 and capacitor C1 are simultaneously grounded. The resistor R3 is connected between the output terminal of the first switching element Q1 and the transmitting terminal TXD2 of the second CAN transceiver U2. The resistor R2 and capacitor C2 are connected in parallel, and the resistor R2 and capacitor C2 are simultaneously connected to the input terminal of the second OR gate U4. The other end of the resistor R2 and capacitor C2 are simultaneously grounded. The resistor R4 is connected between the output terminal of the second switching element Q2 and the transmitting terminal TXD1 of the first CAN transceiver U1.

3. The hard relay arbitration circuit for a CAN bus according to claim 2, characterized in that, The time constant of the network formed by resistor R1 and capacitor C1 in parallel, and the network formed by resistor R2 and capacitor C2 in parallel, is between 150ns and 320ns. The time constant is expressed as: 。 4. The hard relay arbitration circuit for a CAN bus according to claim 1, characterized in that, The first switching element Q1 and the second switching element Q2 are transistors or field-effect transistors; The conduction state of the first switching element Q1 is controlled by the output level of the transmitting terminal TXD2 of the second CAN transceiver U2; The conduction state of the second switching element Q2 is controlled by the output level of the transmitting end TXD1 of the first CAN transceiver U1.

5. A hard relay arbitration circuit for a CAN bus according to claim 4, characterized in that, The amplification factor of the transistor is higher than 100.

6. The hard relay arbitration circuit for a CAN bus according to claim 1, characterized in that, The logic control circuit composed of the first OR gate U3 and the first switching element Q1, and the logic control circuit composed of the second OR gate U4 and the second switching element Q2 can all be equivalent to optical isolation circuits. The optical isolation circuit performs level logic conversion through inverters and NOR gates.

7. A hard relay arbitration circuit for a CAN bus according to claim 6, characterized in that, The optical isolation circuit also includes an optical transmitter and an optical receiver; The optical transmitter and optical receiver can be connected to the optical signal channel of the first CAN bus CAN1 or the second CAN bus CAN2.

8. A hard relay arbitration circuit for a CAN bus according to claim 1, characterized in that, The first CAN transceiver U1 and the second CAN transceiver U2 are both TCAN1051 transceivers.

9. A hard relay arbitration circuit for a CAN bus according to claim 1, characterized in that, The power pins of the first CAN transceiver U1 and the second CAN transceiver U2 are equipped with hot-swap protection circuits. The hot-swap protection circuit includes a soft-start MOSFET and an overcurrent protection chip to support plugging and unplugging operations during bus operation.

10. A hard relay arbitration circuit for a CAN bus according to claim 1, characterized in that, The hard relay arbitration circuit is encapsulated in a metal shielded housing. The inner wall of the housing is coated with a conductive coating, and the housing ground pin GND is grounded through a low-impedance path to isolate electromagnetic interference.

Images