Memory array decoding and interconnects

Abstract

The invention relates to memory array decoding and interconnects. The thin film transistor may access two or more memory cell levels disposed in a cross-point architecture. The fabrication techniques may use one or more via patterns formed at the top layer of the composite stack, which may facilitate the construction of the thin film transistors within the composite stack while using a reduced number of processing steps. By utilizing different groups of the vias, different configurations of the thin film transistors can be constructed using the manufacturing techniques. In addition, circuits and components of memory devices (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors described herein and via-based related fabrication techniques.

Description

[0001] Related application information

[0002] This application is a continuation-in-part of the application for “MEMORY ARRAY DECODING AND INTERCONNECTS” having an application number of “201980083373.0” and an application filing date of December 5, 2019.

[0003] Cross-reference to related applications

[0004] This patent application claims priority to PCT Application No. PCT / US2019 / 064600, Castro et al., titled “MEMORY ARRAY DECODING AND INTERCONNECTS,” filed December 5, 2019, which claims priority to U.S. Patent Application No. 16 / 223,632, Castro et al., titled “MEMORY ARRAY DECODING AND INTERCONNECTS,” filed December 18, 2018, each of which is assigned to the assignee hereof and herein incorporated by reference in its entirety. BACKGROUND

[0005] The following relates generally to decoding memory arrays, and more specifically, the following relates to memory array decoding and interconnects.

[0006] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary devices have two states typically represented by a logical “1” or a logical “0.” In other systems, more than two states can be stored. To access stored information, components of an electronic device can read or sense the storage states in a memory device. To store information, components of an electronic device can write or program states in a memory device.

[0007] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash, phase change memory (PCM), and others. Memory devices can include volatile memory cells or non-volatile memory cells. Non-volatile memory cells can retain their stored logic state for long periods of time even without an external power source. Volatile memory cells lose their stored state over time unless they are periodically refreshed by an external power source.

[0008] Improvements in memory devices can generally include increasing memory cell density, increasing read / write speeds, increasing reliability, enhancing data retention capabilities, reducing power consumption, or reducing manufacturing costs, among other metrics. It can be desirable to build more memory cells per unit area to increase memory cell density and reduce cost per bit without increasing the size of the memory device. It can also be desirable to have improved techniques for manufacturing memory devices, including memory devices with increased memory cell density or other beneficial features, e.g., faster, lower cost. SUMMARY

[0009] An apparatus is described. The apparatus can include a conductive plug extending through a plurality of memory cell levels, a plurality of transistors each at least partially surrounding the conductive plug, and a driver coupled with the conductive plug and configured to selectively couple with an electrode included in a level of the plurality of levels through a transistor of the plurality of transistors.

[0010] Another apparatus is described. The apparatus can include a conductive plug extending through a plurality of memory cell levels, a plurality of transistors each having a source or drain in contact with the conductive plug, and a driver coupled with the conductive plug and configured to selectively couple with an electrode included in a level of the plurality of levels through a transistor of the plurality of transistors.

[0011] A method is described. The method can include receiving an indication of an access operation for a memory cell, identifying a memory cell level including the memory cell, the level included in a plurality of levels, coupling an electrode included in the level with a conductive plug extending through the plurality of levels based at least in part on the identifying and using a first transistor included in the level, and driving the electrode to a voltage associated with the access operation based at least in part on coupling the electrode with the conductive plug.

[0012] An apparatus is described. The apparatus can include a memory array comprising a plurality of electrodes at a first layer and a plurality of memory cells at a second layer; a plurality of transistors configured to select an electrode from the plurality of electrodes, the plurality of transistors each comprising: a gate electrode at the second layer; and a semiconductor material at the first layer.

[0013] Another apparatus is described. The apparatus can include a plurality of memory cell tiers each comprising a first layer, a second layer, a third layer, and a plurality of memory arrays; a plurality of first electrodes extending along a first direction; and a plurality of second electrodes extending along a second direction that intersects the first direction, wherein within a region between memory arrays of the plurality of memory arrays: each first electrode of the plurality of first electrodes comprises a first portion at the second layer, a second portion at the first layer, and a third portion at the second layer; and each second electrode of the plurality of second electrodes comprises a first portion at the second layer, a second portion at the third layer, and a third portion at the second layer. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 An example memory device including a three-dimensional memory cell array supporting memory array decoding and interconnects in accordance with an embodiment of the present disclosure is described.

[0015] Figure 2 An example three-dimensional memory array supporting memory array decoding and interconnects in accordance with an embodiment of the present disclosure is described.

[0016] Figures 3A to 3L An exemplary fabrication technique supporting memory array decoding and interconnects in accordance with an embodiment of the present disclosure is described.

[0017] Figures 4A to 4AA An exemplary fabrication technique supporting memory array decoding and interconnects in accordance with an embodiment of the present disclosure is described.

[0018] Figures 5A to 5N An exemplary fabrication technique supporting memory array decoding and interconnects in accordance with an embodiment of the present disclosure is described.

[0019] Figures 6A to 6R An exemplary fabrication technique supporting memory array decoding and interconnects in accordance with an embodiment of the present disclosure is described.

[0020] Figures 7A to 7D A diagram of an exemplary memory array including active array regions and socket regions supporting memory array decoding and interconnects in accordance with an embodiment of the present disclosure is described.

[0021] Figures 8A to 8CFIG. 1 illustrates a diagram supporting exemplary socket regions and decoding schemes for memory array decoding and interconnects according to embodiments of the present disclosure.

[0022] Figure 9 FIG. 1 illustrates a diagram supporting exemplary socket regions and decoding schemes for memory array decoding and interconnects according to embodiments of the present disclosure.

[0023] Figure 10A and 10B FIG. 1 illustrates a diagram supporting exemplary socket regions and decoding schemes for memory array decoding and interconnects according to embodiments of the present disclosure.

[0024] Figure 11 FIG. 1 illustrates a diagram supporting exemplary socket regions and decoding schemes for memory array decoding and interconnects according to embodiments of the present disclosure.

[0025] Figures 12 to 14 FIG. 1 illustrates a diagram supporting exemplary socket regions and decoding schemes for memory array decoding and interconnects according to embodiments of the present disclosure.

[0026] Figure 15 and 16 FIG. 1 illustrates a diagram supporting exemplary socket regions and decoding schemes for memory array decoding and interconnects according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0027] Building more memory cells per unit area can increase the areal density of memory cells within a memory device. Increasing the areal density of memory cells can facilitate lower cost-per-bit and / or greater memory capacity for a fixed cost of a memory device. Three-dimensional (3D) integration of two or more two-dimensional (2D) arrays of memory cells can increase the areal density while also mitigating difficulties associated with scaling various feature sizes of memory cells. In some cases, a 2D array of memory cells can be referred to as a memory cell level. In some cases, a memory device including multiple memory cell levels can be referred to as a 3D memory device. Each memory cell level of a 3D memory device can be selected (e.g., activated) or inhibited (e.g., deactivated, not selected) by circuitry, which can be configured to determine which level to select and perform access operations to one or more memory cells of the selected level. In some cases, the circuitry can include complementary metal-oxide-semiconductor (CMOS) transistors formed in or on a substrate, and the 3D integrated levels of memory cells can be positioned above (e.g., fabricated on top of) the CMOS circuitry. In some cases, the memory cell levels and associated components positioned above the substrate can be included in a set of layers, which can be collectively referred to as bit array layers.

[0028] The CMOS circuitry can determine the particular tier of the 3D memory device to be selected based on an access command from the host device, such as by decoding an address of a memory cell associated with the access command and included in the particular tier. In some implementations, as the number of tiers in the 3D memory device increases (e.g., 4 tiers, 8 tiers, 16 tiers, 32 tiers) to increase the areal density, the CMOS circuitry can increase in size to support decoding (e.g., determining which tier to select from the increasing tiers) and driving the additional tiers (e.g., providing sufficient current to access the memory cells of the selected tier). This increase in size of the CMOS circuitry (e.g., increasing the substrate area occupied by the CMOS circuitry) can offset the benefits otherwise associated with the 3D integration of two or more 2D arrays of memory cells.

[0029] The fabrication techniques, methods, and related devices described herein can facilitate building thin film transistors (TFTs) that can be positioned within tiers of a 3D memory device (e.g., within an array layer that collectively includes two or more tiers of memory cells). In some cases, multiple sets of TFTs can be fabricated within an array layer at the same time (e.g., two or more array layers each including a set of TFTs). The TFTs positioned within the array layer can be configured to select (e.g., activate) or inhibit (e.g., deactivate) a corresponding tier of memory cells. In some cases, the TFTs can be part of a memory tier decoder (which can also be referred to as a memory tier selector) that can be coupled with CMOS circuitry in the substrate. As such, the TFTs can be coupled with the CMOS circuitry to facilitate the CMOS circuitry performing its functions (e.g., determining a particular tier of multiple tiers of a 3D integration to be selected and driving current to access memory cells of the particular tier). In this way, the TFTs positioned in the array layer can facilitate accommodating additional tiers of memory cells of a 3D memory device while mitigating effects associated with the substrate area occupied by the CMOS circuitry. For example, in some cases, the CMOS circuitry can support one or more additional tiers of memory cells in conjunction with the TFTs while occupying substantially the same area. In some cases, the TFTs positioned in the array layer can mitigate effects of various array parasitic components, such as leakage current, parasitic capacitance.

[0030] In some cases, TFTs can be configured to perform additional functions (e.g., functions other than selecting or inhibiting a memory cell level, such as a full decode function) such that the area of CMOS circuitry below the array levels can be reduced, e.g., by delegating at least some aspects of their decode function to TFTs located in the array levels. Additionally, because TFTs can provide individual levels that are isolated from the remaining levels (e.g., a TFT can select an individual level while inhibiting the remaining levels) to thereby relax current requirements (e.g., drive current requirements) during access operations. Relaxing current requirements can have several benefits related to CMOS circuitry compared to alternative approaches, where the CMOS circuitry can be configured to provide current to multiple levels during access operations. For example, relaxing current requirements can facilitate CMOS circuitry occupying a smaller area, using a simpler circuit configuration, or providing one or more additional functions without increasing the area occupied.

[0031] The fabrication techniques, methods, and related apparatus described herein can be based on techniques, methods, and related apparatus that facilitate simultaneously building multiple memory cell levels and associated array electrodes (e.g., a set of array levels each including a memory cell level and associated array electrodes) using a via (e.g., access via) pattern, as described elsewhere. That is, aspects of building multiple memory cell levels and associated array electrodes are described in Castro et al., U.S. Patent Application No. 15 / 961,540, entitled “Cross-Point Memory Array and Related Fabrication Techniques,” Castro et al., U.S. Patent Application No. 15 / 961,547, entitled “Cross-Point Memory Array and Related Fabrication Techniques,” and Castro et al., U.S. Patent Application No. 15 / 961,550, entitled “Buried Lines and Related Fabrication Techniques,” each of which is incorporated by reference herein in its entirety. The vias can be formed at a top level of a composite stack, which can be used to construct multiple memory cell levels and array electrodes in one region and TFTs in a different region. As used herein, a via can refer to an opening or an opening that can be used to form associated via holes and other structures below a material (layer, surface) that includes an opening, including an opening that is later filled by a material that includes a material that can not be electrically conductive.

[0032] Thus, the fabrication techniques, methods, and related apparatus described herein can facilitate a flexible sequence of constructing TFTs relative to constructing multiple memory cell levels and array electrodes. This flexibility can provide for optimizing process steps to mitigate various undesirable factors associated with various processing conditions, such as thermal impact on memory cells, risk of cross-contamination with materials used for memory cells (e.g., chalcogenide materials), and the like. As an example, TFTs can be formed prior to constructing memory cells to reduce a thermal budget (e.g., a sum of durations of process steps at various temperatures) for holding memory cells. In some cases, the fabrication techniques, methods, and related apparatus described herein can provide for reducing costs of fabricating 3D memory devices, as a same composite stack of materials can be used for constructing TFTs and constructing multiple memory cell levels and array electrodes.

[0033] The fabrication techniques, methods, and related apparatus described herein can support selecting (or inhibiting) memory cell levels disposed in a cross-point architecture. For example, each memory cell level in a cross-point architecture can include a set of first access lines (e.g., word lines, first array electrodes) in a first plane and a set of second access lines (e.g., bit lines, second array electrodes) in a second plane, the first and second access lines extending in different directions, e.g., the first access lines can be substantially perpendicular to the second access lines. Each topological cross-point of the first and second access lines can correspond to a memory cell. Thus, a memory cell level in a cross-point architecture can include a memory array having a set of memory cells disposed at topological cross-points of access lines (e.g., a 3D grid structure of access lines). As described herein, TFTs (e.g., memory level selectors / inhibitors) can be constructed in an array layer including multiple memory cell levels and array electrodes. Thus, the TFTs can be coupled with access lines (e.g., word lines, bit lines, first array electrodes, second array electrodes) and thus support selecting (and accessing) multiple memory cell levels disposed in a cross-point architecture.

[0034] Furthermore, TFTs can support various cross-point architectures, such as a stuffed architecture or derivatives thereof. A stuffed architecture in the context of a memory device can refer to an array of memory cells that includes a set of memory tiles, each of which includes a similar configuration of components (e.g., word line decoders, bit line decoders, sense components, subgroups of the array of memory cells) similar to the arrangement of patches in a stitched stuff. A memory tile can be viewed as a building block (e.g., a modular building block) of the array of memory cells of a memory device that employs a stuffed architecture. In this manner, the array of memory cells of a memory device can be scaled up or down by increasing or decreasing the number of memory tiles. In other words, a cross-point architecture can refer to a memory array that includes topological cross-points of a first access line and a second access line, where each topological cross-point corresponds to a memory cell, and a stuffed architecture can refer to an array constructed by arranging a set of memory tiles that each form a subgroup of the array of memory cells.

[0035] The configuration of TFTs can be varied (e.g., the associated geometry and structure can be varied) to meet various constraints or requirements. In some cases, the relevant constraints and requirements of TFTs can be based on the selection and de-selection (e.g., deselection) functions provided by one or more TFTs. For example, a TFT can be configured to provide a particular current drive capability (e.g., a selection function) when activated. Additionally or alternatively, a TFT can be configured to maintain an acceptably low leakage current (e.g., a de-selection function) when deactivated. In some cases, multiple (e.g., two) sets of TFTs can be constructed for each array electrode within a memory cell tier. For example, one set of TFTs can be configured to actively drive an array electrode of a memory cell tier (e.g., provide a desired or required drive current) when the memory cell tier is selected. Additionally or alternatively, another set of TFTs can be configured to drive a de-selection level (e.g., maintain a low leakage current) when the memory cell tier is de-selected (e.g., not accessed, deselected). In some cases, the multiple sets of TFTs present in a single device can be treated differently from one another to optimize for the current drive capability and voltage range that the multiple sets of TFTs can collectively support (e.g., one set of TFTs can be optimized for drive current capability, while another set of TFTs can be optimized for low leakage current capability).

[0036] In some cases, a control gate (e.g., a gate electrode) of a TFT can be formed within the same layer in which a memory element (e.g., an element that can be configured to store information, such as a chalcogenide element) is formed. The control gate of the TFT can determine a path for current to flow within the TFT between a first electrode (e.g., a drain) of the TFT and a second electrode (e.g., a source) of the TFT. In some cases, based on how the channel of the TFT is formed relative to the gate electrode, the first electrode, and the second electrode of the TFT, the path for current flow can be vertical, horizontal, or a combination of both. In some cases, the channel of the TFT can be coupled with a bulk connection of a node of underlying CMOS circuitry to control electrical properties of the channel that can be different based on various functions (e.g., a select function, an inhibit function, or other functions) that can be performed by the TFT.

[0037] Furthermore, the fabrication techniques, methods, and related apparatus described herein can facilitate constructing one or more composite circuits, such as a circuit that includes various combinations of TFTs within a layer of an array layer (e.g., a TFT-based decoder cell). For example, a TFT-based decoder cell can perform cluster-level decoding to activate (or deactivate) a particular tile within a tile cluster. Additionally or alternatively, another TFT-based decoder cell can perform tile-level decoding to activate a particular access line from a set of access lines included in a tile. The fabrication techniques and methods described herein can also be used to construct crossover regions in which a first set of electrodes of a first group of TFTs can span a second set of electrodes of a second group of TFTs without causing a short between the first set of electrodes and the second set of electrodes.

[0038] The features of the disclosure introduced above are further described herein in the context of various TFT structures and TFT-based circuits in composite stacks that are constructed of materials that can also be used to construct memory arrays in cross-point architectures. Then, particular examples of structures and techniques for fabricating TFT structures and TFT-based circuits are described. These and other features of the disclosure are further illustrated by, and described with reference to, apparatus diagrams, formation method diagrams, and flowcharts related to devices associated with TFTs and related fabrication techniques.

[0039] Figure 1 An example memory device 100 including a three-dimensional array of memory cells that supports memory array decoding and interconnects in accordance with an embodiment of the present disclosure is illustrated. The memory device 100 can also be referred to as an electronic memory apparatus. Figure 1 is an illustration of various components and features of the memory device 100. As such, it should be appreciated that the components and features of the memory device 100 are shown to illustrate functional relationships and not necessarily the order for construction of the memory device 100.

[0040] In Figure 1In the illustrative example of FIG. 1, memory device 100 includes a three- dimensional (3D) memory array 102. 3D memory array 102 includes memory cells 105 that are programmable to store different states. In some embodiments, each memory cell 105 is programmable to store two states represented as a logic 0 and a logic 1. In some embodiments, memory cells 105 can be configured to store more than two logic states (e.g., multi-level cells). In some embodiments, memory cells 105 can include self-selecting memory cells. It should be understood that memory cells 105 can also include another type of memory cell, such as a PCM cell including a storage component and a selection component, a conductive-bridge RAM (CBRAM) cell, or a FeRAM cell. Although TM In some embodiments, memory device 100 includes a memory array 102 that includes a plurality of memory cells 105. In some embodiments, memory array 102 includes a plurality of memory cells 105 that are programmable to store different states. In some embodiments, each memory cell 105 is programmable to store two states represented as a logic 0 and a logic 1. In some embodiments, memory cells 105 can be configured to store more than two logic states (e.g., multi-level cells). In some embodiments, memory cells 105 can include self-selecting memory cells. It should be understood that memory cells 105 can also include another type of memory cell, such as a PCM cell including a storage component and a selection component, a conductive-bridge RAM (CBRAM) cell, or a FeRAM cell. Although Figure 1 In some embodiments, some of the elements included in FIG. 1 are labeled with a numeric designator, and other corresponding elements are not labeled, but are the same or should be understood to be similar in an attempt to improve the visibility and clarity of the depicted features.

[0041] 3D memory array 102 can include two or more two-dimensional (2D) memory arrays (e.g., array tiers including two or more tiers of memory cells and array electrodes) stacked on top of each other. This can increase the number of memory cells that can be placed or produced on a single die or substrate than a single 2D array, which in turn can reduce production costs or increase the performance of the memory device, or both. In some embodiments, 3D memory array 102 can include a plurality of memory cells 105 that are programmable to store different states. In some embodiments, each memory cell 105 is programmable to store two states represented as a logic 0 and a logic 1. In some embodiments, memory cells 105 can be configured to store more than two logic states (e.g., multi-level cells). In some embodiments, memory cells 105 can include self-selecting memory cells. It should be understood that memory cells 105 can also include another type of memory cell, such as a PCM cell including a storage component and a selection component, a conductive-bridge RAM (CBRAM) cell, or a FeRAM cell. Although Figure 1 In the depicted example, memory array 102 includes two levels of memory cells 105 (e.g., memory cells 105-a and memory cells 105-b) and thus can be considered a 3D memory array; however, the number of levels can not be limited to two, and other examples can include additional levels (e.g., 4 levels, 8 levels, 16 levels, 32 levels). Each level can be aligned or positioned such that memory cells 105 can be aligned (fully, overlapping, or approximately) with each other across each level to thus form a stack of memory cells 145. In some cases, a level of memory cells can be referred to as a tier of memory cells.

[0042] In some embodiments, each row of memory cells 105 is connected to a word line 110, and each column of memory cells 105 is connected to a bit line 115. Both word lines 110 and bit lines 115 can also be collectively referred to as access lines. Further, an access line can act as a word line 110 for one or more memory cells 105 at a tier of the memory device 100 (e.g., memory cells 105 below the access line) and as a bit line 115 for one or more memory cells 105 at another tier of the memory device (e.g., memory cells 105 above the access line). Thus, reference to a word line and a bit line, or the like, can be interchanged without loss of understanding or operation. Word lines 110 and bit lines 115 can be substantially perpendicular to each other and can support an array of memory cells.

[0043] Memory cells 105 can generally be located at the intersection of two access lines, such as word lines 110 and bit lines 115. This intersection can be referred to as the address of the memory cell 105. A target memory cell 105 can be a memory cell 105 located at the intersection of an energized (e.g., activated) word line 110 and an energized (e.g., activated) bit line 115; that is, both the word line 110 and the bit line 115 can be energized to read from or write to the memory cell 105 at their intersection. Other memory cells 105 in electronic communication with (e.g., connected to) the same word line 110 or bit line 115 can be referred to as non-target memory cells 105.

[0044] As shown in Figure 1 Two memory cells 105 in a memory cell stack 145 can share a common conductive line, such as a bit line 115, as shown in

[0045] In some cases, an electrode can couple a memory cell 105 to a word line 110 or a bit line 115. The term electrode can refer to an electrical conductor and can include a trace, wire, conductive line, conductive layer, or the like that provides an electrically conductive path between elements or components of a memory device 100. Thus, the term electrode can refer to an access line, such as a word line 110 or a bit line 115, in some cases and can refer to an additional electrically conductive element that serves as an electrical contact between an access line and a memory cell 105 in some cases. In some embodiments, a memory cell 105 can include a chalcogenide material located between a first electrode and a second electrode. The first electrode can couple the chalcogenide material to a word line 110 and the second electrode couples the chalcogenide material to a bit line 115. The first electrode and the second electrode can be the same material, such as carbon, or different materials. In other embodiments, a memory cell 105 can be directly coupled to one or more access lines and electrodes other than the access lines can be omitted.

[0046] Operations such as reads and writes can be performed on a memory cell 105 by activating or selecting a word line 110 and a digit line 115. Activating or selecting a word line 110 or a digit line 115 can include applying a voltage to the respective line. Word lines 110 and digit lines 115 can be made of an electrically conductive material, such as a metal (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), a metal alloy, carbon, an electrically conductive doped semiconductor, or other electrically conductive material, alloy, compound, or the like.

[0047] In some architectures, the logic storage of a cell (e.g., a resistive component in a CBRAM cell, a capacitive component in a FeRAM cell) can be electrically isolated from a digit line by a selection component. A word line 110 can be connected to and can control the selection component. For example, the selection component can be a transistor and the word line 110 can be connected to the gate of the transistor. Alternatively, the selection component can be a variable resistance component, which can include a chalcogenide material. Activating the word line 110 causes an electrical connection or a closed circuit between the logic storage of the memory cell 105 and its corresponding digit line 115. The digit line can then be accessed to read or write the memory cell 105. After selecting the memory cell 105, the resulting signal can be used to determine the stored logic state. In some cases, a first logic state can correspond to no current or a weak current through the memory cell 105, while a second logic state can correspond to a finite current.

[0048] In some cases, the memory cell 105 can include a self-selecting memory cell having two terminals, and a separate selection component can be omitted. As such, a terminal of the self-selecting memory cell can be electrically connected to the word line 110 and another terminal of the self-selecting memory cell can be electrically connected to the digit line 115.

[0049] Accessing the memory cells 105 can be controlled by a row decoder 120 and a column decoder 130. For example, the row decoder 120 can receive a row address from a memory controller 140 and activate the appropriate word line 110 based on the received row address. In some cases, the row decoder 120 can include multiple sets of TFTs for selecting a particular level of the 3D memory array 102. For example, the row decoder 120 can include a first set of TFTs associated with a lower level (e.g., a memory level including memory cells 105-a) to select the lower level and a second set of TFTs associated with an upper level (e.g., a memory level including memory cells 105-b) to inhibit (e.g., deselect) the upper level. In some cases, the TFTs can be co-located in an array layer including the 3D memory array 102. In some cases, the TFTs located in the array layer can be coupled with the row decoder 120, which can be located in a substrate over which the 3D memory array 102 is located. Similarly, the column decoder 130 can receive a column address from the memory controller 140 and activate the appropriate digit line 115. In some cases, similar to the row decoder 120, the column decoder 130 can include additional multiple sets of TFTs for selecting a particular level of the 3D memory array 102. For example, the memory array 102 can include a plurality of word lines 110 labeled WL_1 through WL_M and a plurality of digit lines 115 labeled DL_1 through DL_N, where M and N depend on the array size. Thus, a memory cell 105 at the intersection of an activated word line 110 and digit line 115 (e.g., WL_2 and DL_3) can be accessed.

[0050] After access, the memory cell 105 can be read or sensed by the sensing component 125 to determine the storage state of the memory cell 105. For example, a voltage can be applied to the memory cell 105 (using the corresponding word line 110 and bit line 115), and the resulting current through the memory cell 105 can depend on the applied voltage and the threshold voltage of the memory cell 105. In some cases, more than one voltage can be applied. Additionally, if the applied voltage does not result in current flow, other voltages can be applied until current is detected by the sensing component 125. The storage logic state of the memory cell 105 can be determined by evaluating the voltage that results in current flow. In some cases, the voltage can be ramped in magnitude until current flow is detected. In other cases, predetermined voltages can be applied sequentially until current is detected. Likewise, a current can be applied to the memory cell 105 and the magnitude of the voltage that results in current flow can depend on the resistance or threshold voltage of the memory cell 105.

[0051] In some cases, the memory cell 105 (e.g., a self-selecting memory cell) can include a chalcogenide material. The chalcogenide material of the self-selecting memory cell can remain in an amorphous state during operation of the self-selecting memory cell. In some cases, operating the self-selecting memory cell can include applying programming pulses of various shapes to the self-selecting memory cell to determine a particular threshold voltage of the self-selecting memory cell, i.e., the threshold voltage of the self-selecting memory cell can be modified by varying the shape of the programming pulses, which can alter the local composition of the chalcogenide in the amorphous state. The particular threshold voltage of the self-selecting memory cell can be determined by applying read pulses of various shapes to the self-selecting memory cell. For example, when the applied voltage of the read pulse exceeds the particular threshold voltage of the self-selecting memory cell, a finite amount of current can flow through the self-selecting memory cell. Similarly, when the applied voltage of the read pulse is less than the particular threshold voltage of the self-selecting memory cell, an insignificant amount of current can flow through the self-selecting memory cell.

[0052] In some embodiments, the sensing component 125 can read information stored in the memory cell 105 by detecting current or no current flow through the selected memory cell 105. In this way, the memory cell 105 (e.g., a self-selecting memory cell) can store one bit of data based on a threshold voltage level (e.g., two threshold voltage levels) associated with the chalcogenide material, where the threshold voltage level at which current flows through the memory cell 105 indicates the logic state stored by the memory cell 105. In some cases, the memory cell 105 can exhibit a particular number of different threshold voltage levels (e.g., three or more threshold voltage levels) to thereby store more than one bit of data.

[0053] The sense component 125 can include various transistors or amplifiers to detect and amplify the signal difference associated with the sensed memory cell 105, which can be referred to as latching. The detected logic state of the memory cell 105 can then be output as the output 135 by the column decoder 130. In some cases, the sense component 125 can be part of the column decoder 130 or the row decoder 120. Alternatively, the sense component 125 can be connected to or in electronic communication with the column decoder 130 or the row decoder 120. Figure 1 Alternative options for arranging the sense component 125-a (in dashed boxes) are also shown. One of ordinary skill in the art will appreciate that the sense component 125 can be associated with a column decoder or a row decoder without loss of its functional use.

[0054] The memory cell 105 can be set or written by similarly activating the associated word line 110 and digit line 115, and at least one logic value can be stored in the memory cell 105. The column decoder 130 or the row decoder 120 can accept data for writing to the memory cell 105, such as the input / output 135.

[0055] In some memory architectures, accessing the memory cell 105 degrades or destroys the stored logic state, and a rewrite or refresh operation can be performed to restore the memory cell 105 to the original logic state. For example, in DRAM, the capacitor can be partially or completely discharged during a sense operation to destroy the stored logic state, so the logic state can be rewritten after the sense operation. Additionally, in some memory architectures, activating a single word line 110 causes all memory cells in a row (e.g., coupled with the word line 110) to discharge; thus, several or all memory cells 105 in a row can need to be rewritten. But in non-volatile memory (e.g., self-selecting memory, PCM, CBRAM, FeRAM, or NAND memory), accessing the memory cell 105 does not destroy the logic state, so the memory cell 105 can not need to be rewritten after being accessed.

[0056] Memory controller 140 can control the operation (e.g., reading, writing, rewriting, refreshing, discharging) of memory cell 105 through various components, such as row decoder 120, column decoder 130, and sensing component 125. In some cases, one or more of row decoder 120, column decoder 130, and sensing component 125 can be co-located with memory controller 140. Memory controller 140 can generate row and column address signals to activate desired word lines 110 and digit lines 115. Memory controller 140 can also generate and control various voltages or currents used during operation of memory device 100. In general, the amplitude, shape, polarity, and / or duration of the applied voltages or currents discussed herein can be adjusted or varied and can differ for the various operations discussed in operating memory device 100. Furthermore, one, multiple, or all memory cells 105 within memory array 102 may be accessed simultaneously; for example, multiple or all cells of memory array 102 may be accessed simultaneously during a reset operation in which all memory cells 105 or a group of memory cells 105 are set to a single logic state.

[0057] In some cases, the lower word line 110 ( Figure 1 WL_B1 in the middle), upper word line 110 ( Figure 1 1) and any number of additional layers (not shown). In addition, both the lower word line 110 and the upper word line 110 may be disposed (formed) in a layer initially comprising the same dielectric material, and a single via pattern may be used to simultaneously form one or more processing steps of the lower level word line 110 and the upper level word line 110 at their respective layers, such as removing portions of the dielectric material and replacing them with a conductive material. Similarly, the lower memory cell 105 (e.g., Figure 1 The memory cell 105-a) illustrated as a solid black circle in FIG can be connected to the upper memory cell 105 (eg Figure 1 10. In some cases, the 3D memory array 102 can be positioned above a substrate that includes various circuitry, such as row decoders 120, sensing elements 125, column decoders 130, or the like.

[0058] Figure 2 An example of a 3D memory array 202 supporting memory array decoding and interconnects according to an embodiment of the present disclosure is illustrated. The 3D memory array 202 may be a reference Figure 1The depicted memory array 102 or portion of a 3D memory device including two or more levels of memory cells. The 3D memory array 202 can include a first array or level 205-a of memory cells positioned above a substrate 204 and a second array or level 205-b of memory cells on top of the first array or level 205-a. The 3D memory array 202 can also include word lines 110-a and 110-b and bit lines 115-a, which can be as described with reference to Figure 1 The depicted examples of lines 110 and bit lines 115. As with the illustrative examples depicted in Figure 2 The memory cells of the first level 205-a and the second level 205-b can each include self-selecting memory cells, as with the illustrative examples depicted in Figure 2 Some elements included in are labeled with a numeric designator, while other corresponding elements are not labeled, but are identical or should be understood as analogous in an attempt to improve the visibility and clarity of the depicted features.

[0059] In some cases, the memory cells of the first level 205-a can each include a first electrode 215-a, a chalcogenide material 220-a, and a second electrode 225-a. Additionally, the memory cells of the second level 205-b can each include a first electrode 215-b, a chalcogenide material 220-b, and a second electrode 225-b. In some embodiments, access lines (e.g., word lines 110, bit lines 115) can include electrode layers (e.g., conformal layers) in place of electrodes 215 or 225 and thus can comprise multi-layer access lines. In such embodiments, the electrode layers of the access lines can interface with the memory material (e.g., chalcogenide material 220). In some embodiments, the access lines (e.g., word lines 110, bit lines 115) can directly interface with the memory material (e.g., chalcogenide material 220) without an electrode layer or electrode therebetween.

[0060] In some embodiments, the memory cells of the first level 205-a and the second level 205-b can have common conductive lines such that corresponding (e.g., vertically aligned along the y-direction) memory cells of each level 205-a and 205-b can share a bit line 115 or a word line 110, as described with reference to Figure 1 For example, the first electrode 215-b of the second level 205-b and the second electrode 225-a of the first level 205-a can both be coupled to bit line 115-a such that bit line 115-a is shared by vertically aligned and adjacent memory cells (along the y-direction).

[0061] In some embodiments, 3D memory array 202 can include additional bit lines (not shown) such that first electrodes 215-b of second level 205-b can be coupled with the additional bit lines and second electrodes 225-a of first level 205-a can be coupled with bit lines 115-a. The additional bit lines can be electrically isolated from bit lines 115-a (e.g., insulating material can be inserted between the additional bit lines and bit lines 115-a). Thus, first level 205-a and second level 205-b can be separate and can be operated independently of each other. In some cases, an access line (e.g., word line 110 or bit line 115) can include a select component (e.g., a two-terminal selector device, which can be configured as one or more thin film materials integrated with the access line) for each memory cell at the respective intersection. As such, the access line and select component can together form a composite material layer that functions as both an access line and a select component.

[0062] In some cases, the architecture of 3D memory array 202 can be referred to as an instance of a cross-point architecture because memory cells can be formed at topological intersections between word lines 110 and bit lines 115, as illustrated in Figure 2 This cross-point architecture can provide relatively high density data storage at lower production costs than some other memory architectures. For example, a memory array having a cross-point architecture can have memory cells that take up less area and thus can support increased memory cell density than some other architectures. For example, a DRAM memory array can use transistors (e.g., thin film transistors) as select components for each memory cell, which are three-terminal devices. Thus, a DRAM memory array including a given number of memory cells can have a larger memory cell area than a memory array having a cross-point architecture that includes the same number of memory cells. 2 For example, a cross-point architecture can have a 4F 2 memory cell area, where F is a minimum feature size (e.g., a minimum feature size). For example, a DRAM memory array can use transistors (e.g., thin film transistors) as select components for each memory cell, which are three-terminal devices. Thus, a DRAM memory array including a given number of memory cells can have a larger memory cell area than a memory array having a cross-point architecture that includes the same number of memory cells.

[0063] Although Figure 2Examples of the memory array 202 include two memory levels, but other configurations can include any number of levels (e.g., 4 levels, 8 levels, 16 levels, 32 levels). In some embodiments, one or more of the memory levels can include self-selecting memory cells that include a chalcogenide material 220. In other embodiments, one or more of the memory levels can include FeRAM cells that include a ferroelectric material. In other embodiments, one or more of the memory levels can include CBRAM cells that include a metal oxide or chalcogenide material. For example, the chalcogenide material 220 can include a chalcogenide glass such as, for example, an alloy of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and silicon (Si). In some embodiments, chalcogenide materials having primarily selenium (Se), arsenic (As), and germanium (Ge) can be referred to as SAG alloys.

[0064] In some cases, the lines 110-a, word lines 110-b, and bit lines 115-a of the 3D memory array 202 can be referred to as array electrodes. As described herein, a set of TFTs can be constructed in the array layer such that a subset of the set of TFTs can be coupled with array electrodes (e.g., word lines 110, bit lines 115) of a level of the memory array (e.g., a first level of memory cells 205-a, a second level of memory cells 205-b). In some cases, the set of TFTs can be coupled with circuitry in the substrate 204 (e.g., CMOS circuitry below the array layer) to facilitate various functions of the circuitry. For example, the set of TFTs can select a particular level of the memory array (e.g., a select function) based on input from the circuitry (e.g., a decode result associated with an access command) while not selecting more than two levels of the memory array (e.g., an inhibit function). In some cases, the set of TFTs can perform a higher-level function (e.g., a full decode function) to share one or more functions that can otherwise be implemented by the circuitry.

[0065] FIGS. 3-6 illustrate various aspects of the fabrication techniques of the present disclosure. For example, various cross-sectional views can illustrate the parallel nature of creating particular structures (e.g., source, drain, gate, and channel of a TFT) in the target material at one or more buried target layers of a composite stack, each target layer comprising a target material. As described herein, in some cases, a via (e.g., an access via) can be used to create a structure in the target material at a target buried layer. Various top-down views can illustrate how a particular set of vias can be used to create various structures of a TFT. The fabrication techniques described herein can facilitate the simultaneous formation of the same structure at different underlying layers, such as a set of gate electrode groups of a TFT or a set of channel material elements of a TFT. As such, the fabrication techniques described herein can facilitate the simultaneous formation of a set of TFTs in an array layer that includes two or more levels of memory cells, each level comprising access lines (e.g., word lines, bit lines, array electrodes) and 3D cross-point structures of memory cells.

[0066] Figures 3A to 3L Exemplary manufacturing techniques according to the present disclosure are described. Figures 3A to 3L Aspects of several process steps for simultaneously constructing two or more TFTs (e.g., TFTs that may be referred to as vertical TFTs and in which current flows in a vertical direction relative to a horizontal substrate when the TFT is activated) are described. In some cases, such TFTs may be fabricated in a socket region of an array layer. In some cases, the TFTs may be referred to as array electrode drivers. The socket region may refer to the region where various interconnects (e.g., TFTs and underlying circuitry (e.g., reference electrodes) may be formed). Figure 2 The logic circuitry in the substrate 204 described, the interconnections between the row decoder 120), the TFTs and the array electrodes (e.g., reference Figure 2 The area of ​​the array layer of the interconnects between the ends of the lines 110 and / or bit lines 115 is depicted. Figures 3A to 3L A top view of a portion of the socket area (eg, the layout of the socket area) is included to illustrate that different via groups can be used to simultaneously construct various structures of TFTs. Figures 3A to 3L A cross-sectional side view of a portion of the socket area is also included to illustrate aspects of process features during several process steps used to simultaneously construct the TFT.

[0067] Figure 3A A cross-sectional side view of a stack 305 is shown that may include several different layers of various materials. In some cases, the stack may be referred to as a composite stack. In some cases, the stack 305 may be positioned on a substrate (e.g., a substrate having a plurality of layers). Figure 2 The specific material of stack 305 may be selected based on a number of factors, such as the desired type of memory technology (e.g., self-select memory, FeRAM, CBRAM), the desired number of memory cell levels (e.g., more than two memory cell levels), and the like. Figure 3A As depicted in the illustrative example of FIG, the stack 305 may include a first layer 205-a of memory cells positioned above the substrate 204 and a second array or layer 205-b of memory cells on top of the first array or layer 205-a, as described with reference to FIG. Figure 2 An initial layer stack (described).

[0068] Stack 305 may include layer 310, which may be the top layer of stack 305. In some embodiments, layer 310 includes a dielectric material. In some embodiments, layer 310 includes a hard mask material, such that layer 310 may be referred to as a hard mask (HM) layer. A via pattern may be formed in layer 310 as a result of, for example, a photolithography step. In some cases, this photolithography step may form a first set of vias (e.g., a dielectric layer) through the top layer of stack 305 (e.g., layer 310). Figure 3BThe third group of pathways 340-c) and the second group of pathways (e.g. Figure 3B Paths 340-b of the second group shown in FIG.

[0069] The stack 305 may also include a layer 315. Figure 3A In the illustrative example of FIG, stack 305 includes two layers 315 (i.e., layer 315-a and layer 315-b), but any number of layers is possible. In some embodiments, layers 315 may each include a first dielectric material (which may also be referred to as D1). As described herein, each layer 315 may be modified to include a set of first array electrodes (e.g., electrode sheets or segments, conductive lines, access lines, word lines). In some cases, each layer 315 may be referred to as a first layer, a first electrode layer, or a D1 layer.

[0070] The stack 305 may also include a layer 320. Figure 3A In the illustrative example of FIG, stack 305 includes two layers 320 (i.e., layer 320-a and layer 320-b), but any number of layers 320 is possible. In some embodiments, each layer 320 may include a placeholder material that may later be partially removed and replaced with a desired material (e.g., a memory material, a gate electrode material, a semiconductor material). In some embodiments, each layer 320 may initially include a memory material that may be processed to form one or more memory elements. In some cases, layer 320 may be referred to as a second layer, a memory layer, or a DM layer.

[0071] The stack 305 may also include a layer 325. Figure 3A In the illustrative example of FIG, stack 305 includes a single layer 325, but any number of layers 325 is possible. In some embodiments, each layer 325 may include a second dielectric material (which may be referred to as D2). As described herein, layer 325 may be modified to include a set of second array electrodes (e.g., electrode sheets, conductive lines, access lines, bit lines). In some cases, each layer 325 may be referred to as a third layer, a second electrode layer, or a D2 layer.

[0072] Stack 305 can include layer 330. In some cases, layer 330 can include an etch stop material to withstand the various etching processes described herein. In some cases, layer 330 can include the same hard mask material as layer 310, or can include a different material. In some cases, layer 330 can provide a hard mask relative to a substrate (e.g., a substrate having ... Figure 2 A buffer layer for circuits or other structures in substrate 204 (as depicted) or other layers (not shown) may be located below layer 330. In some cases, layer 330 may provide a buffer layer relative to one or more memory cell levels fabricated in an earlier processing step.

[0073] Figure 3BA top view illustrating a stack 305 in which a socket region containing two or more TFTs (e.g., vertical TFTs) can be constructed is described as described herein. Figure 3B A set of vias 340 in an array pattern (depicted as white, gray, or cross-hatched squares) is illustrated. Figure 3B It is also illustrated that various structures can be formed simultaneously within the stack 305 using different via groups (e.g., first group of vias 340-a, second group of vias 340-b, third group of vias 340-c). For example, Figure 3B A set of array electrodes 350, a set of electrode pads 355 (depicted as dark-shaded rectangles), and a set of gate electrodes 360 (one of which is depicted in top view) can each be formed at different junctions of the sequence of layers to construct TFTs.

[0074] As described elsewhere, a first subset of vias (e.g., first group of vias 340-a) can be used to construct a set of array electrodes 350 (e.g., array electrodes 350-c and 350-d). Further, a second subset of vias (e.g., second group of vias 340-b depicted as gray squares) can be used to construct a set of electrode pads (e.g., electrode pad 355-b). In some cases, the electrode pad 355-b can be a second electrode (e.g., drain) of a TFT at the first layer 315-a. In some cases, the electrode pad can be constructed by forming a channel (e.g., a series of merged cavities in a row) at a first layer (e.g., Dl layer 315-a, Dl layer 315-b) using the second group of vias 340-b, e.g., the channel is aligned with the second group of vias 340-b. An electrode material (e.g., a conductive material) can be used to fill the channel at the first layer. Subsequently, a set of dielectric plugs corresponding to the second group of vias 340-b can be formed to separate the electrode pad within the Dl layer 315-a from another electrode pad within the Dl layer 315-b. The dielectric plugs can extend through the electrode material filling the channel at the first layer.

[0075] Additionally, a third subset of vias (e.g., third group of vias 340-c) can be used to construct a set of gate electrodes 360 as described herein with reference to Figures 3C to 3F Further, one or more vias (e.g., vias depicted as cross-hatched squares including via 340-d, via 340-e) can be used to split an array electrode (e.g., array electrode 350-f) into two or more segments. Thus, in some cases, an electrode pad (e.g., electrode pad 355-b) can be coupled with a single array electrode (e.g., array electrode 350-e). In some cases, the electrode pad (and thus one or more TFTs constructed therein) can be positioned between two ends of a single array electrode. For example, an electrode pad (e.g., electrode pad 355-b) can be positioned approximately in a middle region of a single array electrode (e.g., array electrode 350-e).

[0076] In some cases, the array electrodes 350 can be or can be part of access lines (e.g., word lines, bit lines, conductive lines) coupled with a set of memory cells in an active array region of the array layer. An active region can refer to a region of the array layer in which access lines and sets of memory cells form an array of memory cells. In some cases, the array of memory cells (e.g., access lines and sets of memory cells) can be constructed according to a cross-point architecture in the active array region. In this way, a set of TFTs formed in a plug region of the array layer can be coupled with the array electrodes 350 (and thus the sets of memory cells associated with the array electrodes 350) in the active array region of the array layer.

[0077] Figures 3C to 3F A manufacturing technique is described for forming a set of gate electrodes 360 of TFTs within the stack 305 using the third group of vias 340-c. In some cases, the set of array electrodes 350 and the set of electrode pads 355 can have been formed within the stack 305 prior to forming the set of gate electrodes 360 at the layer 320.

[0078] Figure 3C A cross-sectional side view of the stack 305 shown in FIG. 3B is illustrated. The cross-sectional side view can correspond to a portion of an electrode pad (e.g., electrode pad 355-a) that includes a via 340-f. Figure 3B A cross-sectional side view of the stack 305 shown in FIG. 3B is illustrated. The cross-sectional side view can correspond to a portion of an electrode pad (e.g., electrode pad 355-a) that includes a via 340-f. Figure 3B A cross-sectional side view of the stack 305 shown in FIG. 3B is illustrated. The cross-sectional side view can correspond to a portion of an electrode pad (e.g., electrode pad 355-a) that includes a via 340-f. Figure 3C A cross-sectional side view of the stack 305 shown in FIG. 3B is illustrated. The cross-sectional side view can correspond to a portion of an electrode pad (e.g., electrode pad 355-a) that includes a via 340-f. Figure 3C The electrode pads 355-c and 355-d shown in FIG. 3B can have been previously formed in the Dl layer. The shadow pattern of the original Dl layer (e.g., layer 315-a, layer 315-b) is used to depict the electrode pads 355-c and 355-d to indicate that portions of the Dl layer shown in FIG. 3B have been replaced by electrode material that forms the set of electrode pads 355. Figure 3A The electrode pads 355-c and 355-d shown in FIG. 3B can have been previously formed in the Dl layer. The shadow pattern of the original Dl layer (e.g., layer 315-a, layer 315-b) is used to depict the electrode pads 355-c and 355-d to indicate that portions of the Dl layer shown in FIG. 3B have been replaced by electrode material that forms the set of electrode pads 355. Figure 3C The electrode pads 355-c and 355-d shown in FIG. 3B can have been previously formed in the Dl layer. The shadow pattern of the original Dl layer (e.g., layer 315-a, layer 315-b) is used to depict the electrode pads 355-c and 355-d to indicate that portions of the Dl layer shown in FIG. 3B have been replaced by electrode material that forms the set of electrode pads 355. Figure 3C The electrode pads 355-c and 355-d shown in FIG. 3B can have been previously formed in the Dl layer. The shadow pattern of the original Dl layer (e.g., layer 315-a, layer 315-b) is used to depict the electrode pads 355-c and 355-d to indicate that portions of the Dl layer shown in FIG. 3B have been replaced by electrode material that forms the set of electrode pads 355. Figure 3C An opening 341 that can correspond to a via hole (e.g., a via hole corresponding to the via 340-f included in the third group of vias 340-c) is also illustrated.

[0079] In some cases, a lithography step can transfer the shape of the via 340 onto the stack 305. In some cases, the lithography step can include forming a photoresist layer (not shown) on top of the layer 310 having the shape of the via 340 (e.g., defined by the absence of photoresist material within the via 340). In some examples, an etching treatment step can be performed after the lithography step to transfer the shape of the via 340 onto the layer 310, such that the shape of the via 340 established within the layer 310 can be repeatedly used as an access via during subsequent processing steps, i.e., the layer 310 including the shape of the via 340 can act as a hard mask layer providing an access via in the shape of the via 340 for subsequent processing steps.

[0080] In some cases, the anisotropic etching process step can form an opening 341 through the stack 305 and the width of the opening 341 can be substantially the same as the width of the via (e.g., the via 340-f). The anisotropic etching step can remove a target material along a direction (e.g., an orthogonal direction with respect to the substrate) by applying an etchant (e.g., a mixture of one or more chemical elements) to the target material. Further, the etchant can exhibit selectivity (e.g., chemical selectivity) for removal of only the target material (e.g., the hard mask material at the layer 310) while leaving other materials (e.g., photoresist) exposed to the etchant. The anisotropic etching step can use one or more etchants during a single anisotropic etching step when removing one or more layers of material (e.g., the first dielectric material at the Dl layer 315, the placeholder material at the DM layer 320, the second dielectric material at the D2 layer 325). In some cases, the anisotropic etching step can use an etchant that exhibits selectivity for a group of materials (e.g., oxides and nitrides) that are desired to be removed while leaving a group of other materials (e.g., metals) exposed to the etchant.

[0081] Figure 3D A cross-sectional side view of the stack 305 across the dashed line AA is illustrated after performing at least one etching process step and a deposition process step using the via hole (e.g., the opening 341) that has been formed within the stack 305, as described with reference to Figure 3C

[0082] ​In some cases, the etching process steps can include isotropic etching steps that can remove a target material in all directions. In some cases, the isotropic etching steps can apply an etchant that exhibits selectivity (e.g., chemical selectivity) for removal of only the target material (e.g., the placeholder material in the DM layer 320) while leaving other materials (e.g., the electrode material of the electrode sheet 355-c or 355-d, the second dielectric material of the D2 layer, the hardmask material of the HM layer) exposed to the etchant (e.g., a mixture of one or more chemical elements) intact. The isotropic etching steps can employ different etchants during a single isotropic etching step when removing one or more layers of material. In some cases, the isotropic etching step (e.g., the etchant used in the isotropic etching step) can be chemically selective between the first dielectric material and at least one other material in the stack. In this way, the etching process steps can form a series of cavities within each DM layer, e.g., a series of cavities 342 corresponding to the third group of vias 340-c. When superimposed cavities (e.g., adjacent cavities, such as cavity 342-a and the next cavity (not shown) in the DM layer 320-a) completely overlap, the superimposed cavities can merge to form a trench at the DM layer. In this way, trenches can be formed at a second layer (e.g., layer 320-a, layer 320-b) that can be aligned with a first group of vias (e.g., the third group of vias 340-c shown in FIG. 3B). Figure 3B

[0083] Still referring to Figure 3D A deposition process step can be performed after the etching process steps to form a layer of insulating material (e.g., insulating layer 365) on the surfaces of the cavities 342 (and thus trenches) and via holes (e.g., openings 341). In some cases, the insulating layer 365 can be conformal (e.g., maintain substantially the same thickness) across non-uniform surfaces across at least two layers (e.g., across the electrode sheet 355-c and recessed DM layer 320-a and then D2 layer 325). In some cases, the insulating layer 365 can facilitate crossover region formation, as described herein. In some cases, the deposition process step can form an insulating layer 365 that is conformal with the trenches.

[0084] Figure 3E A cross-sectional side view of the stack 305 across the dashed line AA is illustrated after at least one deposition process step is complete. The deposition process step can be based on using the via holes (e.g., that have been formed by reference to Figure 3D ​The described partially filled openings 341) of the insulating layer 365 are formed to fill the trenches that have been formed at the DM layers (e.g., DM layers 320-a and 320-b). In some cases, a deposition process step can deposit the electrode material 361. The electrode material 361 can form a set of gate electrodes 360. In some cases, the electrode material 361 can include polysilicon, refractory metal elements (e.g., tungsten, titanium, tantalum), or nitrides thereof, or combinations thereof. In some cases, additional electrode material 361 that can be present above the HM layer 310 can be removed by using a chemical mechanical polishing (CMP) process step or an etch back process step.

[0085] Figure 3F A cross-sectional side view of the stack 305 across the dashed line AA after the described at least one etch process step to remove the electrode material 361 from the via hole using the third group of vias 340-c is illustrated. Figure 3F An opening 341-a that can correspond to a cross-sectional side view of a via hole (e.g., a via hole that corresponds to the via 340-f included in the third group of vias 340-c) is also illustrated. In some cases, an anisotropic etch process step can form the opening 341-a and the width of the opening 341-a can be substantially the same as the width of the via (e.g., the via 340-f). As a result of the anisotropic etch process step removing the electrode material 361 from the via hole, the electrode material within the DM layer (e.g., the electrode material 361-a within the DM layer 320-a) can be separated from the electrode material within the other DM layer (e.g., the electrode material 361-b within the DM layer 320-b). In this way, two or more gate electrodes (e.g., the set of gate electrodes 360) can be formed within the stack 305 at the same time.

[0086] Figure 3G A cross-sectional side view of the stack 305 across the dashed line AA after the described at least one etch process step and deposition process step (as described with reference to Figure 3F

[0087] In some cases, the etch process step can include a selective isotropic etch step that can selectively remove the electrode material 361 while leaving the rest of the stack 305 exposed to the isotropic etch process. As a result of the isotropic etch step, the electrode material 361 (e.g., the electrode material 361-a and 361-b) within the DM layers can be recessed, as Figure 3G ​In some cases, the isotropic etch can remove a portion of the gate electrode (e.g., gate electrode 360 including electrode material 361) to form a cavity at the second layer (e.g., layer 320). In some cases, the etching process step can also include an anisotropic etching step that selectively removes a portion of layer 330 (e.g., hardmask material at layer 330) to create a hole (e.g., opening 341-b at layer 330) through layer 330. In some cases, the width of opening 341-b can be substantially the same as the width of opening 341-a. Opening 341-b can be coupled with a conductive element 385 that can be part of a logic circuitry layer. For example, conductive element 385 can represent a node of a circuitry (e.g., row decoder 120 built in substrate 204) in the substrate. In another example, conductive element 385 can be coupled with a node of row decoder 120 (e.g., a node in which a select signal is present) to activate one or more tiers of the array layer.

[0088] Still referring to Figure 3G , the deposition step can use the via (e.g., via hole 341-a) to form oxide material 370 over the exposed surface of electrode material 361. In this way, oxide material 370 can be formed in the cavity at the second layer (e.g., layer 320), where oxide material 370 can be in contact with gate electrode 360 including electrode material 361. In some cases, oxide material 370 can be referred to as a gate oxide that can be present between a gate electrode and an active channel region of a TFT. The deposition step can be a selective oxidation step or a selective deposition step that can be configured to form oxide material 370 only over the exposed surface of electrode material 361.

[0089] Figure 3H A cross-sectional side view of stack 305 across dashed line AA after a first etching process step, a deposition process step, and a second etching process step (as described with reference to Figure 3G ) are performed using the via hole (e.g., opening 341-a) that has been formed within stack 305 is illustrated. The first etching process step can include an isotropic etching step that removes a portion of electrode sheet 355 (e.g., a second electrode of a TFT), such as selectively removing exposed electrode material of electrode sheet 355 within via hole 341-a. The isotropic etching step can form one or more cavities at the first layer (e.g., layer 315).

[0090] Subsequently, an ohmic material 375 can be formed to fill the via hole 341-a and spaces (e.g., cavities) associated with the via hole 341-a, such as the cavity at the Dl layer (e.g., layer 315) created by removing portions of the electrode sheet 355, the space at the DM layer (e.g., layer 320) created by removing the electrode material 361. Thus, the ohmic material 375 can be in contact with the second electrode (e.g., electrode sheet 355). In some cases, the ohmic material 375 can provide an ohmic contact between the electrode material (e.g., electrode sheet 355-c or 355-d) and the semiconductor material (e.g., semiconductor material 380) to be formed later. Figure 3I The ohmic material 375 can be in contact with the second electrode (e.g., electrode sheet 355). In some cases, the ohmic material 375 can provide an ohmic contact between the electrode material (e.g., electrode sheet 355-c or 355-d) and the semiconductor material (e.g., semiconductor material 380) to be formed later.

[0091] The ohmic material can be a material configured to provide a current path between the conductive material (e.g., electrode sheet 355-c or 355-d) and the semiconductor material (e.g., semiconductor material 380) that has a bi-directional uniform or at least substantially uniform resistance. That is, the current path from the conductive material through the ohmic material to the semiconductor material can exhibit the same or substantially the same resistance as the current path from the semiconductor material through the transition material to the ohmic material. Thus, the ohmic material can avoid a rectifying junction or other non-ohmic or directional contact or current path between the conductive material (e.g., electrode sheet 355-c or 355-d) and the semiconductor material (e.g., semiconductor material 380). In some cases, the ohmic material 375 can be referred to as a transition material. The ohmic material 375 can include various compounds including transition metal elements (e.g., titanium, cobalt, nickel, copper, tungsten, tantalum). The second etching process step can include an anisotropic etching step that uses the opening 341-a to remove the ohmic material 375 in the vertical direction within the via hole. In this way, the ohmic material outside the via hole (e.g., ohmic material 375-a, ohmic material 375-b) can remain intact.

[0092] Figure 3I It is noted that the first etching process step, the first deposition process step, the second etching process step, and the second deposition step can be performed using the via hole (e.g., opening 341-a) that has been formed within the stack 305. In some cases, the first etching process step, the first deposition process step, the second etching process step, and the second deposition step can be performed using the via hole (e.g., opening 341-a) that has been formed within the stack 305. Figure 3H341 -a). A cross-sectional side view of stack 305 across dashed line AA after deposition (as described above) may be provided. The first etching process step may include an isotropic etching step that selectively removes portions of ohmic material 375 exposed within opening 341 -a (e.g., ohmic material 375 -a at layer D1 and a portion of ohmic material 375 -b at layer DM). In this manner, the isotropic etching step may form a cavity spanning the first layer (e.g., layer 315) and the second layer (e.g., layer 320). The first etching process step may also include an etching step that selectively removes the insulating layer 365 exposed by the removal of portions of ohmic material 375. The first deposition process step may fill the via hole (e.g., opening 341 -a) and the space created by the first etching process step (e.g., the cavity spanning the first and second layers) with semiconductor material 380. The second etching process step may use opening 341 -a to remove semiconductor material 380 vertically within the via hole. The second deposition step may selectively form insulating material 390 over the exposed surface of semiconductor material 380 within the via hole, such that insulating material 390 may be in contact with semiconductor material 380. In some cases, the thickness of insulating material 390 may be determined based on a second gate effect (e.g., to avoid the second gate effect).

[0093] Figure 3J The invention illustrates performing at least one first etching process step, a deposition process step, and a second etching process step using a via hole (eg, opening 341-a) formed in the stack 305 (eg, reference numeral 341). Figure 3I 1 ). A cross-sectional side view of stack 305 across dashed line AA after the first etching process step may include an anisotropic etching step that selectively removes a portion of the third layer (e.g., layer 325, D2 layer) to create a cavity therein. Subsequently, a deposition process step may fill the via hole and the cavity with ohmic material 375 (e.g., ohmic material 375-e). A second etching process step may remove ohmic material 375 from the via hole in a vertical direction such that ohmic material (e.g., ohmic material 375-e) remains in the cavity at the third layer. The remaining ohmic material (e.g., ohmic material 375-e) at the third layer may contact the third electrode (e.g., reference electrode). Figure 3K and 3L The conductive plug 396 is described as contacting.

[0094] Figure 3K The invention illustrates performing at least one deposition process step (e.g., referring to FIG. 3 ) using a via hole (e.g., opening 341 - a ) already formed in stack 305 . Figure 3JA cross-sectional side view of the stack 305 across the dashed line AA after the deposition process step described above. The deposition process step can fill the via hole with an electrode material 395. In some cases, the electrode material 395 can be the same electrode material as the electrode sheet 355 or the array electrode 350. As a result of filling the via hole with the electrode material 395 (e.g., forming a conductive plug 396), the conductive element 385 (e.g., a node associated with the logic circuitry layer) can be coupled with an ohmic material 375-e that is in contact with the semiconductor material 380-a. The semiconductor material 380-a, which is further coupled with the electrode material 361-a of the gate electrode 360 (e.g., the gate electrode 360 in contact with the oxide material 370-a) through the oxide material 370-a, can form an active channel to cause current to flow based on a voltage applied to the gate electrode 360. In addition, the semiconductor material 380-a is in contact with an ohmic material 375-a that is in contact with the electrode sheet 355-c.

[0095] Thus, Figure 3K A cross-sectional side view of the TFTs (e.g., the two vertical TFTs 335-a and 335-b) built in the socket region of the array layer including the stack 305 can be illustrated. The conductive plug 396 (e.g., the via hole filled by the electrode material 395) can act as a common source of the TFTs, e.g., a third electrode extending through the third layer (e.g., the layer 325). The conductive plug 396 can be further coupled with the conductive element 385 (e.g., a node associated with the logic circuitry). The semiconductor material 380-a surrounding the conductive plug 396 can act as an active channel of the upper TFT 335-a. Similarly, the semiconductor material 380-b surrounding the conductive plug 396 can act as an active channel of the lower TFT 335-b. The electrode sheet 355-c coupled with the semiconductor material 380-a (e.g., through the ohmic material 375-a) can act as a drain of the upper TFT 335-a. Similarly, the electrode sheet 355-d coupled with the semiconductor material 380-b (e.g., through the ohmic material 375-d) can act as a drain of the lower TFT 335-b.

[0096] In some cases, Figure 3K (see Figure 3L ) depicts the ohmic material 375-a at the first layer (e.g., the Dl layer 315), where the ohmic material 375-a surrounds and is in contact with the semiconductor material 380-a at the first layer. Figure 3K The insulating material 390-a interposed between the conductive plug 396 and the semiconductor material 380-a is also depicted. In addition, Figure 3KA portion of the ohmic material (e.g., ohmic material 375-e) at the third layer (e.g., D2 layer 325) is depicted, where the ohmic material 375-e is in contact with the semiconductor material 380-a such that the conductive plug 396 can be coupled with the semiconductor material 380-a. In some cases, the ohmic material 375-e can surround the conductive plug 396.

[0097] Figure 3K The current path 345 is depicted to illustrate some operational aspects of the TFT. For example, a first signal (e.g., a select signal from logic circuitry) at the conductive element 385 can provide a first voltage (e.g., 0 V) to the conductive plug (e.g., the common source of both the upper TFT 335-a and the lower TFT 335-b). Further, a second voltage (e.g., 1 V) applied to the gate electrode (e.g., the upper gate electrode 360 including the electrode material 361-a) can be greater than the threshold voltage (e.g., 0.2 V) of the TFT to form a conductive path (e.g., an active channel region) within the semiconductor material 380-a. Further, a third voltage (e.g., 0.5 V) can be applied to the electrode tab 355-c (e.g., the drain of the upper TFT 335-a) such that current can flow from the source of the TFT (e.g., the conductive plug 396 coupled with a node of the logic circuitry) to the drain of the TFT (e.g., the electrode tab 355-c coupled with an array electrode (i.e., a word line)), which is indicated as the upper current path 345-a. Similarly, the lower current path 345-b can be established when the second voltage is applied to the lower gate electrode including the electrode material 361-b and the third voltage is applied to the electrode tab 355-d (e.g., the drain of the lower TFT 335-b). In some cases, the voltages associated with the TFT (e.g., the first voltage, the second voltage, the third voltage) can not be independent of one another, for example, during the TFT performing a decoding function or a selection function. In some cases, the voltages associated with the TFT can be independent of one another if there is a separate circuit (e.g., a circuit driving the voltages to the TFT, an active memory cell conducting current).

[0098] Figure 3K The TFTs illustrated in FIG. 3B can depict a word line socket region, as the electrode tabs 355 in the Dl layer can be coupled with array electrodes (e.g., word lines) built in the Dl layer. Further, Figure 3K The TFTs illustrated in FIG. 3B can operate to activate or deactivate one of the two memory cell levels in the active cell region of the array layer making up the stack 305. In some cases, the drain of the TFT (e.g., the drain of the upper TFT 335-a connected to the electrode tab 355-c) can be driven through the conductive path (e.g., the active channel region) to a voltage related to the voltage present at the conductive element 385, as described herein.

[0099] Figure 3LA top view of a stack 305 including more than two TFTs (e.g., vertical TFTs) is illustrated, including all gate, source, and drain electrodes. Figure 3L Various structures of a socket region (e.g., a word line socket region) forming an array layer are also illustrated. For example, Figure 3L A set of array electrodes 350, a set of electrode pads 355 (depicted as dark shaded rectangles), and a set of gate electrodes 360 are illustrated in accordance with the description herein.

[0100] For example, Figure 3L A top view of a conductive plug 396 (e.g., a via hole 341-a filled with electrode material 395) extending through a stack 305 is depicted, including a first layer (e.g., a Dl layer 315), a second layer (e.g., a DM layer 320), and a third layer (e.g., a D2 layer 325). The conductive plug 396 can be formed using a via shared between two groups of vias (e.g., a via 340-f shared between a second group of vias 340-b and a third group of vias 340-c, as described with reference to Figure 3B A top view of a conductive plug 396 (e.g., a via hole 341-a filled with electrode material 395) extending through a stack 305 is depicted, including a first layer (e.g., a Dl layer 315), a second layer (e.g., a DM layer 320), and a third layer (e.g., a D2 layer 325). The conductive plug 396 can be formed using a via shared between two groups of vias (e.g., a via 340-f shared between a second group of vias 340-b and a third group of vias 340-c, as described with reference to Figure 3L A semiconductor material 380-a at the first layer (e.g., the Dl layer 315) and the second layer (e.g., the DM layer 320) is further depicted, where the semiconductor material 380-a surrounds the conductive plug 396. Figure 3L An oxide material 370-a at the second layer (e.g., the DM layer 320) and in contact with the semiconductor material 380-a is also depicted. Additionally, Figure 3L A gate electrode 360-a at the second layer (e.g., the DM layer 320) is depicted. The gate electrode 360-a, including electrode material 361-a, is in contact with the oxide material 370-a, as also Figure 3K depicted in FIG. 3. In some cases, the combination of the semiconductor material 380-a, the oxide material 370-a, and the electrode material 361-a can form an active channel within the semiconductor material 380-a of a TFT (e.g., a vertical TFT), where current can flow through the active channel based on a voltage applied to the gate electrode 360-a.

[0101] In some cases, Figure 3L A portion of an ohmic material (e.g., ohmic material 375-a) at the first layer (e.g., the Dl layer 315) is depicted, where the ohmic material 375-a is in contact with the semiconductor material 380-a and surrounds the conductive plug 396, as also Figure 3K depicted in FIG. 3. Figure 3L An insulating material 390-a is also depicted interposed between the conductive plug 396 and the semiconductor material 380-a.

[0102] Figures 4A to 4AA An exemplary fabrication technique in accordance with the present disclosure is illustrated. Figures 4A to 4AAAspects describing several process steps for concurrently fabricating two or more TFTs (e.g., TFTs that can be referred to as planar TFTs and in which current flows in a horizontal (parallel) direction relative to a horizontal substrate when the TFT is activated) are described. In some cases, such TFTs can be fabricated in a socket region of an array layer, as described herein. In some cases, the TFTs can be referred to as array electrode drivers. Figures 4A to 4AA A top view including a portion of a socket region (e.g., a layout of a socket region) to illustrate various structures that can use different groups of vias to concurrently fabricate TFTs. Figures 4A to 4AA A cross-sectional side view also including a portion of a socket region to illustrate aspects of process features during several process steps for concurrently fabricating TFTs.

[0103] Figures 4A to 4AA Exemplary fabrication techniques for fabricating planar TFTs in a composite stack (e.g., reference Figures 3A to 3L to the stack 305 described for fabricating vertical TFTs. As such, the composite stack can be used to fabricate either vertical TFTs or planar TFTs or both in a socket region of an array layer. As described herein, the composite stack can also be used to fabricate a 3D cross-point array of memory cells and associated electrodes in an active array region of an array layer. In this way, the composite stack can provide for fabricating an array layer that includes both a layer of memory cells and electrodes, where the electrodes (and thus the memory cells) can be further coupled with TFTs (e.g., vertical TFTs, horizontal TFTs, a combination of vertical and horizontal TFTs).

[0104] Figure 4A A top view illustrating a stack 405 in which a socket region including two or more TFTs (e.g., horizontal TFTs) can be fabricated, as described herein. The stack 405 can be an example of the stack 305 described with reference to Figures 3A to 3L . Figure 4A A set of vias 440 (depicted as white, gray, or cross-hatched squares) in an array pattern is illustrated. The set of vias 440 can be formed through a top layer (e.g., layer 310 of the stack 305) of the stack 405 that includes a first layer (e.g., layer 315 of the stack 305) and a second layer (e.g., layer 320 of the stack 305). The set of vias 440 can be an example of the set of vias 340 described with reference to Figures 3A to 3L . Figure 4A Various structures that can be concurrently formed within the stack 405 using different groups of vias (e.g., a first group of vias 440-a, a second group of vias 440-b) are also illustrated. For example, Figure 4A A set of array electrodes 450 (which can be an example of the array electrodes 350 described with reference to Figures 3A to 3L ) and a set of gate electrodes 460 (which can be an example of the gate electrodes 360 described with reference to Figures 3A to 3LExamples of gate electrodes 360 are described), each of which can be formed at a different junction in the process sequence to construct a TFT.

[0105] As described elsewhere, a first subset of vias (e.g., first group of vias 440-a) can be used to construct a set of array electrodes 450 (e.g., array electrodes 450-a and 450-b). In some cases, the array electrodes can serve as the third electrode of the TFT. Additionally, a second subset of vias (e.g., second group of vias 440-b) can be used to construct a set of gate electrodes 460 (e.g., gate electrode 460-a), as described herein with reference to FIG. Figures 3C to 3F described.

[0106] In some cases, a subset of array electrodes 450 (e.g., array electrodes 450-b, array electrodes 450-c) can be divided into segments using vias (e.g., vias depicted as gray squares, which include vias 440-z) that can form cavities (e.g., cavity 442-z corresponding to vias 440-z). Subsequently, an etching process step can remove portions of array electrodes 450 exposed within the cavities to divide the subset of array electrodes 450 into two or more segments. As described herein with reference to Figure 4Y As described, dividing the array electrodes into subsets can facilitate the TFT subset formed in the socket region to drive a single array electrode (e.g., array electrode 450-a, array electrode 450-d). In some cases, the TFT subset can be positioned between the ends of a single array electrode. For example, the TFT subset can be positioned approximately in the middle region of a single array electrode.

[0107] Figure 4B Explain the use of the third channel group (e.g. Figure 4A The vias depicted as cross-hatched squares in FIG. 4 include vias 440-c and 440-d) to form via holes (eg, openings 441-d corresponding to vias 440-d) after crossing Figure 4A 4. The cross-sectional side view of the stack 405 shown in FIG. The cross-sectional side view may correspond to a portion of the socket region including gate electrodes 460-a and 460-b. Electrode material 461 (which may be reference Figures 3A to 3L The described examples of electrode material 361 ) may have been previously formed in the DM layer of stack 405 , as described herein. Figure 4B The electrode material 461 depicted in FIG corresponds to Figure 4A In the gate electrode 460 depicted in FIG, for example, the electrode material 461 - a forms the gate electrode 460 - a , and the electrode material 461 - b forms the gate electrode 460 - b . Figure 4B The insulating layer 465 (which may be a reference Figures 3A to 3L4. The example of insulating layer 365 depicted partially surrounds electrode material 461. In some cases, an etching process (eg, an anisotropic etching process) can remove a portion of insulating layer 465 that is exposed to the etching process that forms the via hole.

[0108] Figure 4C Explain the use of the third channel group (e.g. Figure 4A The vias depicted as cross-hatched squares in FIG. 4 include vias 440-c and 440-d) to form via holes (eg, openings 441-d) after crossing the vias. Figure 4A A cross-sectional side view of the stack 405 is shown along the dashed line BB. Figure 4C Describe the same as Figure 4B Different cross-sectional side views of the stack 405 at the process steps depicted in FIG. 4 are provided to highlight various aspects of the fabrication techniques used to form the TFTs. Figure 4C The cross-sectional side view of also corresponds to a portion of the socket region including gate electrodes 460 - a and 460 - b . Figure 4C The insulating layer (eg, insulating layer 465-a) surrounds the electrode material 461-c (which may form the gate electrode 460-b) because Figure 4C The insulating layer 465 captured in the cross-sectional side view of FIG. 4 remains intact when forming the via hole, for example, the anisotropic etching process may not reach the insulating layer 465 - a. Figure 4C It is illustrated that the array electrode 450 may have been formed in the D1 layer of the stack 405 , such as the array electrode 450 - d1 and the array electrode 450 - d2 .

[0109] Figure 4D The invention illustrates performing at least one etching process step and a deposition process step (as shown in FIG. 1 ) using a via hole (eg, opening 441 - d ) formed in stack 405 . Figure 4A and 4B A top view of the stack 405 after (described). Figure 4D Describe the specific pathways used (e.g., reference Figure 4A The via 440-z and corresponding cavity 442-z are used to remove portions of the array electrodes (e.g., array electrodes 450-b and array electrodes 450-c). As a result, some array electrodes (e.g., array electrodes 450-b and array electrodes 450-c) may be disconnected from the array electrodes in the active array region of the array layer.

[0110] Figure 4E Illustrating the traversal after the etching process step and the deposition process step Figure 4D 4. Similarly, Figure 4F Illustrating the traversal after the etching process step and the deposition process step Figure 4Da cross-sectional side view of the stack 405 of dashed lines BB shown in FIG. 4B. In this way, Figures 4D to 4F Various aspects of the structural features formed within the stack 405 due to the etching process steps and the deposition process steps are described.

[0111] In some cases, the etching process steps can include a first isotropic etching process that uses the via holes (e.g., the openings 441-d) to reach layers below a top layer (e.g., the hard mask layer) of the stack 405. The first isotropic etching process can selectively remove the first dielectric material of the Dl layer within the stack 405. The first isotropic etching process can leave other materials exposed in the via holes (e.g., materials other than the first dielectric material of the Dl layer) substantially unchanged, e.g., the insulating layer 465, the electrode material 461, the second dielectric material in the D2 layer. As a result of the first isotropic etching process, the via cavities 442 (e.g., the via cavity 442-b, the via cavity 442-c, the via cavity 442-d) corresponding to the vias 440-d can be formed at the Dl layer. Figure 4D the via cavity 442-b depicted in FIG. 4B, Figure 4E and 4F the via cavity 442-c and the via cavity 442-d depicted in FIG. 4B) can be formed at the Dl layer. Figure 4D It is described that the via cavities (e.g., the via cavity 442-a and the via cavity 442-b depicted as light gray squares in the top view) can reach the array electrodes 450 (e.g., the array electrode 450-c, the array electrode 450-d) to expose the array electrodes 450 at the Dl layer.

[0112] In some cases, the etching process can also include a second isotropic etching process that can selectively remove portions of the array electrodes 450 at the Dl layer, e.g., portions of the array electrodes 450 exposed to the second isotropic etching process as a result of the first isotropic etching process. The second isotropic etching process can leave other materials exposed in the via holes and the via cavities (e.g., materials other than the array electrodes 450 at the Dl layer) substantially unchanged, e.g., the insulating layer 465, the electrode material 461, the first dielectric material at the Dl layer, the second dielectric material at the D2 layer. As a result of the second isotropic etching process, Figure 4F It is described that portions of the array electrodes 450 (e.g., the array electrode 450-dl, the array electrode 450-d2) have been removed to form (e.g., expand) the via cavities (e.g., the via cavity 442-c, the via cavity 442-d). In addition, Figure 4D It is described that the second isotropic etching process can remove portions of the array electrodes, e.g., overlapping regions between the via cavities (e.g., the via cavity 442-a) and the array electrodes (e.g., the array electrode 450-c, the array electrode 450-d).

[0113] In some cases, the etching process may also include a third isotropic etching process that can selectively remove the insulating layer 465 at the DM layer exposed in the via hole and the via cavity. The third isotropic etching process can leave other materials exposed in the via hole and the via cavity (e.g., materials other than the insulating layer 465), such as the electrode material 461, the first dielectric material in the D1 layer, the second dielectric material in the D2 layer, and the array electrode 450 at the D1 layer, substantially unchanged. Due to the third isotropic etching process, portions of the electrode material 461 can become exposed to the deposition process.

[0114] In some cases, the deposition process step may selectively form an oxide material 470 (which may be a reference to the oxide material 470) over the exposed surface of the electrode material 461. Figures 3A to 3L ). In some cases, oxide material 470 can serve as a gate oxide for a TFT.

[0115] In some cases, using vias (e.g., via 440-d) of the second group of vias 440-b that have been used to form gate electrodes (e.g., gate electrode 460-b) of the TFT, a second isotropic etching process can form cavities (e.g., cavities 442-c, 442-d) at the first layer to expose portions of the gate electrodes (e.g., electrode materials 461-b1, 461-b2). Using the vias (e.g., via 440-d), a deposition process step can form oxide materials (e.g., oxide materials 470-e, 470-f) in contact with the gate electrodes (e.g., electrode materials 461-b1, 461-b2).

[0116] Figure 4G The invention illustrates the use of via holes (eg, Figure 4E The opening 441-d) and the passage cavity (eg Figures 4D to 4F and 4F ) to perform at least one deposition process step (as shown in FIG. Figure 4H A top view of the stack 405 after (as described). Figure 4G Describes the traversal following the deposition process step Figure 4I 4. Similarly, Figure 4G Describes the traversal following the deposition process step Figures 3A to 3L A cross-sectional side view of the stack 405 is shown along the dashed line BB.

[0117] In some cases, the deposition process step may use semiconductor material 480 (which may be reference Figure 4G Examples of semiconductor material 380 described herein) are used to fill the via holes and via cavities. Figure 4HA top-down view depicting via cavities filled with semiconductor material 480 (e.g., via cavities 442-a depicted as dark gray squares). Figure 4I A top-down view depicting semiconductor material 480 can be in contact with oxide material 470 (e.g., gate oxide). Figure 4E A top-down view depicting semiconductor material 480 can fill cavities and can be in contact with oxide material 470 (e.g., gate oxide).

[0118] In some cases, a deposition step can be performed in a via (e.g., via 440-d) of a second group of vias 440-b that use a gate electrode (e.g., gate electrode 460-b) that has been used to form a TFT. Figure 4J andA cross-sectional side view of stack 405 taken across dashed line AA shown in 4F semiconductor material (e.g., semiconductor material 480) can be formed in cavities 442-c, 442-d shown in

[0119] Figure 4J A top-down view of stack 405 after at least one etching process step and a deposition process step (as described with reference to Figures 4G to 4I depicted as cross-hatched squares in Figure 4K A cross-sectional side view of stack 405 taken across dashed line AA shown in Figure 4J A cross-sectional side view of stack 405 taken across dashed line AA shown in Figure 4L A cross-sectional side view of stack 405 taken across dashed line BB shown in Figure 4J A cross-sectional side view of stack 405 taken across dashed line BB shown in Figure 4K A cross-sectional side view of stack 405 taken across dashed line BB shown in

[0120] In some cases, the etching process can include a first anisotropic etching process that can selectively remove semiconductor material 480 within a via hole (e.g., a via hole corresponding to the third group of vias) along a vertical direction (e.g., a vertical direction relative to a horizontal substrate). In some cases, the etching process can include a second anisotropic etching process that can selectively remove oxide material 470 in the via hole. As a result of the etching process that removes semiconductor material 480 in the via hole, semiconductor material at an upper D1 layer (e.g., semiconductor material 480-a) can be separated from semiconductor material at a lower D1 layer (e.g., semiconductor material 480-b), as shown in Figure 4K

[0121] In some cases, the deposition process step can include filling the via hole with a dielectric material (e.g., an insulating material). In some cases, a CMP process or an etch-back process can be used to remove additional dielectric material on top of stack 405. Figure 4LA via hole filled by a dielectric material (e.g., dielectric plug 444-a, dielectric plug 444-b) separating a semiconductor material 480-a at an upper D1 layer from a semiconductor material 480-b at a lower D1 layer is depicted. The semiconductor material (e.g., semiconductor material 480-a) at a first layer (e.g., D1 layer of the stack 405) can surround the dielectric plug (e.g., dielectric plug 444-b). Further, a gate electrode (e.g., electrode material 461-b1, electrode material 461-b2) at a second layer (e.g., DM layer of the stack 405) can surround the dielectric plug (e.g., dielectric plug 444-b). Additionally, an oxide material (e.g., oxide material 470-e) can be located between the semiconductor material (e.g., semiconductor material 480-a) and the gate electrode (e.g., electrode material 461-b1). Figure 4I The structural features depicted in Figure 4L remain the same as the structural features depicted in Figure 4L The structural features depicted in Figure 4M are positioned away from the via hole, e.g., the etching process steps and the deposition process steps do not affect the structural features depicted in

[0122] Figure 4M A top-down view of the stack 405 after performing at least one etching process step on a fourth via group (e.g., vias 440-e to 440-i) that are depicted as dot-filled squares in Figures 4J to 4L is illustrated. Some vias of the fourth group (e.g., via 440-e and via 440-f) are in close proximity to a via cavity filled by a semiconductor material (e.g., via cavity 442-a that has been filled by the semiconductor material 480), as described with reference to Figure 4N . Figure 4M A cross-sectional side view of the stack 405 across the dashed line AA shown in Figure 4O is illustrated after the etching process steps. Similarly, Figure 4M A cross-sectional side view of the stack 405 across the dashed line BB shown in Figure 4N is illustrated after the etching process steps.

[0123] In some cases, the etching process steps can include an anisotropic etching process that can remove various materials along a vertical direction (e.g., along a vertical direction with respect to a horizontal substrate) to form via holes corresponding to the fourth via group, e.g., via holes 441-e to 441-i that each correspond to vias 440-e to 440-i, respectively. In some cases, the various materials that can be removed by the anisotropic etching process include the HM layer (top layer) and the D1 layer of the stack 405, the insulating layer 465, the electrode material 461, the D2 layer of the stack 405. In some cases, the anisotropic etching process can stop at the bottom layer of the stack 405, as shown in Figure 4O . Figure 4LThe structural features depicted in Figure 4O remain the same as Figure 4O depicted in Figure 4P are positioned away from the third via hole group (e.g., vias 441-e to 441-i), for example, the anisotropic etching process does not affect depicted in

[0124] Figure 4P depicted in Figure 4M perform at least one etching process step on the stack 405 using via holes (e.g., vias 441-e to 441-i) corresponding to the fourth via group (e.g., Figure 4Q and 4N depicted in Figure 4P depicted in Figure 4R depicted in Figure 4P depicted in Figure 4P depicted in

[0125] In some cases, the etching process step can include a first isotropic etching process. The first isotropic etching process can selectively remove a portion of the first dielectric material at the D1 layer to create a cavity (e.g., cavity 442-e, cavity 442-f) such that the cavity can expose the array electrode 450 at the D1 layer, as Figures 4P to 4R and 4R depicted in Figure 4P depicted in Figure 4R depicted in 4R depicted in

[0126] In some cases, the etching process step can remove any exposed oxide material 470 (e.g., gate oxide) while removing the portion of the dielectric material at the D1 layer or the exposed array electrode 450 at the D2 layer. The etching process can leave substantially intact the semiconductor material (e.g., semiconductor material 480). Additionally, the etching process can leave substantially intact the second dielectric material of the D2 layer of the stack 405. Figures 4Y to 4AAAn etch process step is depicted to extend the cavity to the array electrode 450 at a D1 layer and remove a portion of the array electrode (e.g., array electrode 450-d1, array electrode 450-d2) while the semiconductor material remains substantially intact.

[0127] In some cases, an etch process step (e.g., a first isotropic etch process) can form a second cavity (e.g., trench 443-a1) at a first layer (e.g., D1 layer) using at least via 440-g, which can be used to form a second electrode of a transistor (as will be described in Figure 4S In some cases, an etch process step (e.g., a first isotropic etch process) can form a second cavity (e.g., trench 443-a1) at a first layer (e.g., D1 layer) using at least via 440-g, which can be used to form a second electrode of a transistor (as will be described in

[0128] Figure 4S A top view of the stack 405 after a first deposition process step and a second deposition process step (as described with reference to Figures 4P to 4R A top view of the stack 405 after a first deposition process step and a second deposition process step (as described with reference to Figure 4T A cross-sectional side view of the stack 405 taken across the dashed line AA shown in Figure 4S A cross-sectional side view of the stack 405 taken across the dashed line AA shown in Figure 4U A cross-sectional side view of the stack 405 taken across the dashed line BB shown in Figure 4S A cross-sectional side view of the stack 405 taken across the dashed line BB shown in Figure 4N A cross-sectional side view of the stack 405 taken across the dashed line BB shown in

[0129] In some cases, the first deposition process step can include selectively forming an insulating layer 466 over the exposed surface of the electrode material 461, as shown in Figures 3A to 3L and 4Q In some cases, the insulating layer 466 can be an example of the insulating layer 365 described with reference to Figures 3A to 3L The insulating layer 466 can provide electrical isolation between the electrode material 461 (e.g., the upper layer gate electrode 460 including electrode material 461-a1, the lower layer gate electrode 460 including electrode material 461-a2) and the ohmic material deposited during the second deposition process step.

[0130] In some cases, the second deposition process step can include using an ohmic material 475 (which can be an example of the ohmic material 375 described with reference to Figures 4P to 4RExamples of ohmic materials 375 described herein) to fill the cavities and channels formed in the stack 405 (e.g., reference Figure 4S The cavity 442 and channel 443 are described). Figure 4T A top view illustrating cavities and trenches filled with ohmic material 475 (eg, ohmic material 475 - a , ohmic material 475 - b , ohmic material 475 - c ). Figure 4U and 4U A cross-sectional side view of a cavity and a trench filled with ohmic material 475 (eg, ohmic material 475 - a , ohmic material 475 - b , ohmic material 475 - c ) is illustrated. Figure 4Y The semiconductor material (eg, semiconductor material 480-a1) is in contact with the ohmic material (eg, ohmic material 475-a1), and the ohmic material is in contact with the array electrode (eg, array electrode 450-d1). Figure 4Q and 4Z It is described that when a TFT is fully constructed, the combination of semiconductor material, ohmic material and array electrodes can form a current path of the TFT, and the current path is along a horizontal direction (eg, parallel to a horizontal substrate).

[0131] In some cases, the second deposition process step may use an ohmic material (eg, ohmic material 475-b1, ohmic material 475-c1) to fill the second cavity (eg, reference 475) at the first layer (eg, D1 layer). Figure 4Q and 4R The channel 443-a1) and the third cavity (eg, reference Figure 4V and 4R cavity 442-e1) as described.

[0132] Figure 4V The fourth via group (eg, Figures 4S to 4U The vias depicted as dot-filled squares in FIG. 4, including vias 440-e to 440-i, perform at least one etching process step and a deposition process step (as shown in FIG. Figure 4W A top view of the stack 405 after (as described). Figure 4V Illustrating the traversal after the etching process step and the deposition process step Figure 4X 4. Similarly, Figure 4V Illustrating the traversal after the etching process step and the deposition process step Figure 4W A cross-sectional side view of the stack 405 is shown along the dashed line BB.

[0133] In some cases, the etching process can include an anisotropic etching process that removes the ohmic material along a vertical direction (e.g., a vertical direction relative to a horizontal substrate). As a result of the etching process that removes the ohmic material, via holes (e.g., via holes 441-e to 441-i corresponding to vias 440-e to 440-i, respectively) can be formed to separate the ohmic material at the upper D1 layer (e.g., ohmic material 475-a1, ohmic material 475-c1) from the ohmic material at the lower D1 layer (e.g., ohmic material 475-a2, ohmic material 475-c2). Subsequently, a deposition process can fill the via holes with a dielectric material. Figure 4X The via holes (e.g., via holes 441-e to 441-i) filled with the dielectric material are illustrated. The additional dielectric material above the HM layer of the stack 405 can be removed by a CMP process or an etch-back process. Figure 4U The structural features depicted in Figure 4X remain the same as the structural features depicted in Figure 4X are positioned away from the third via hole group (e.g., via holes 441-e to 441-i), e.g., the anisotropic etching process and the subsequent deposition process do not affect the structural features depicted in Figure 4Y .

[0134] Figures 4V to 4X A top-down view of the stack 405 after at least one etching process step and a deposition process step have been performed on the fifth via group (e.g., the via depicted as a dark gray square, which includes via 440-g) that has been filled with the dielectric material is illustrated, as described with reference to Figure 4Z . Figure 4Y A cross-sectional side view of the stack 405 across the dashed line AA shown in Figure 4AA is illustrated after the etching process step and the deposition process step. Similarly, Figure 4Y A cross-sectional side view of the stack 405 across the dashed line BB shown in Figures 3A to 3L is illustrated after the etching process step and the deposition process step.

[0135] In some cases, the etching process step can include an anisotropic etching process. The anisotropic etching process can remove dielectric material from the via hole (e.g., via hole 441-g corresponding to via 440-g). Further, the anisotropic etching process can selectively remove a portion of a bottom layer (e.g., etch stop layer, HM layer) of the stack 405 to form a hole (e.g., opening 441-j) through the bottom layer of the stack 405. In some cases, the width of the opening 441-j can be substantially the same as the width of the opening 441-g. The opening 441-j can be coupled with a conductive element 485 that can be part of a logic circuitry layer. For example, the conductive element 485 can represent a node of a circuitry (e.g., row decoder 120 built in the substrate 204) in the substrate. In another example, the conductive element 485 can be coupled with a node (e.g., a node where a select signal is present) of the row decoder 120 to activate one or more tiers of the array layer. In some cases, the etching process step can include an isotropic etching process that can follow the anisotropic etching. The isotropic etching process can selectively remove ohmic material exposed within the via hole, e.g., ohmic material at the recessed etch Dl layer (e.g., ohmic material 475-b1, ohmic material 475-b2).

[0136] In some cases, the deposition process can fill the via hole (e.g., via hole 441-g) with electrode material 495 (which can be an example of the electrode material 395 described with reference to Figure 4Z In some cases, the deposition process can fill the via hole (e.g., via hole 441-g) with electrode material 495 (which can be an example of the electrode material 395 described with reference to Figure 4AA In some cases, the conductive plug 496 (e.g., via hole 441-g corresponding to via 440-g that has been filled with electrode material 495) can act as a second electrode of a TFT. Figure 4X The structural features depicted in Figure 4AA In some cases, the conductive plug 496 (e.g., via hole 441-g corresponding to via 440-g that has been filled with electrode material 495) can act as a second electrode of a TFT. Figure 4AA In some cases, the conductive plug 496 (e.g., via hole 441-g corresponding to via 440-g that has been filled with electrode material 495) can act as a second electrode of a TFT. Figures 4Y to 4AA In some cases, the conductive plug 496 (e.g., via hole 441-g corresponding to via 440-g that has been filled with electrode material 495) can act as a second electrode of a TFT.

[0137] As described herein with reference to Figure 4AAAs illustrated, the conductive element 485 may be coupled to an ohmic material (e.g., ohmic material 475-b1, ohmic material 475-b2), which is in contact with a semiconductor material (e.g., semiconductor material 480-a1, semiconductor material 480-a2). The semiconductor material (e.g., semiconductor material 480-a1, semiconductor material 480-a2) is in contact with an ohmic material (e.g., ohmic material 475-a1, ohmic material 475-b2), which is in contact with an array electrode (e.g., array electrode 450-d1, array electrode 450-d2). Figure 4Y In this way, a current path between the conductive element 485 and the array electrode (e.g., array electrode 450-d1, array electrode 450-d2) can be established based on the voltage applied to the gate electrode (e.g., upper-level gate electrode 460 including electrode material 461-a1, lower-level gate electrode 460 including electrode material 461-a2) to form a current flow (e.g., Figures 4Y to 4AA and 4Z An active channel within a semiconductor material (eg, semiconductor material 480 - a1, semiconductor material 480 - a2) of the semiconductor material 480 - a1 is formed.

[0138] Figure 4Z Explain various features of planar TFTs. For example, Figure 4Z The planar TFT depicted in FIG4 may include dielectric plugs (e.g., dielectric plugs 444-a, 444-b) extending through a stack including a first layer and a second layer (e.g., stack 405 including the D1 layer and the DM layer). The planar TFT may also include a semiconductor material (e.g., semiconductor material 480-a1) at a first layer surrounding the dielectric plugs (e.g., dielectric plug 444-a). Furthermore, the planar TFT may include a gate electrode (e.g., electrode material 461-a1 forming gate electrode 460-a) at a second layer surrounding the dielectric plugs (e.g., dielectric plug 444-a). Furthermore, the planar TFT may include an oxide material (e.g., oxide material 470-a) between the semiconductor material 480-a1 and the gate electrode (e.g., electrode material 461-a1 forming gate electrode 460-a).

[0139] Figures 4Y to 4AA The planar TFT depicted in FIG may include a conductive plug (e.g., conductive plug 496) extending through the stack and an ohmic material (e.g., ohmic material 475-b1, ohmic material 475-b2) at a first layer surrounding the conductive plug. The ohmic material (e.g., ohmic material 475-b1) surrounding the conductive plug contacts a semiconductor material (e.g., semiconductor material 480-a1) surrounding a dielectric plug (e.g., dielectric plug 444-a), as shown in FIG. Figures 4Y to 4AAThe planar TFT can also include a second dielectric plug (e.g., dielectric plug 444-b) extending through the stack, and the semiconductor material (e.g., semiconductor material 480-al) surrounding the first layer of the dielectric plug (e.g., dielectric plug 444-a) includes a first segment of semiconductor material, and the ohmic material (e.g., ohmic material 475-bl) surrounding the conductive plug (e.g., conductive plug 496) contacts a second segment of semiconductor material (e.g., semiconductor material 480-bl) surrounding the second dielectric plug (e.g., dielectric plug 444-b), as depicted in FIG. 4B. Figures 5A to 5N The planar TFT can also include a second dielectric plug (e.g., dielectric plug 444-b) extending through the stack, and the semiconductor material (e.g., semiconductor material 480-al) surrounding the first layer of the dielectric plug (e.g., dielectric plug 444-a) includes a first segment of semiconductor material, and the ohmic material (e.g., ohmic material 475-bl) surrounding the conductive plug (e.g., conductive plug 496) contacts a second segment of semiconductor material (e.g., semiconductor material 480-bl) surrounding the second dielectric plug (e.g., dielectric plug 444-b), as depicted in FIG. 4B.

[0140] Figures 5A to 5N Exemplary fabrication techniques according to the present disclosure are described. Figures 5A to 5N Aspects of several process steps for simultaneously fabricating two or more TFTs (e.g., which can be referred to as wrap-around TFTs and in which current flows in a direction along an outer surface of a gate electrode when the TFT is activated) are described. In some cases, such TFTs can be fabricated in a plug region of an array layer, as described herein. Figures 5A to 5N Top-down views (e.g., layouts of a plug region) including portions of the plug region are described to illustrate aspects of various structures that can use different pass groups for simultaneously fabricating TFTs. Figures 5A to 5N Cross-sectional side views also including portions of the plug region are described to illustrate aspects of process features during several process steps for simultaneously fabricating TFTs.

[0141] Figures 3A to 3L Exemplary fabrication techniques for fabricating wrap-around TFTs within a composite stack (e.g., with reference to Figures 4A to 4AA Exemplary fabrication techniques for fabricating wrap-around TFTs within a composite stack (e.g., with reference to Figure 5A Exemplary fabrication techniques for fabricating wrap-around TFTs within a composite stack (e.g., with reference to

[0142] Figure 5A Top-down views of a stack 505 in which a plug region including two or more TFTs (e.g., wrap-around TFTs) can be fabricated are described, as described herein. As an example, Figure 5NTwo groups of TFTs are described, each comprising two subgroups of TFTs. Each group of TFTs can drive a single group of array electrodes. Further, each group of TFTs can include a first subgroup of TFTs coupled with a first node associated with a logic circuitry layer and a second subgroup of TFTs coupled with a second node associated with a logic circuitry layer. In some cases, the first node can correspond to a node configured to supply current to a first circuit active at the level of memory cells. As such, the first node can be referred to as a select node and the first circuit can be referred to as a select driver. In some cases, the second node can correspond to a node of a second circuit configured to maintain a leakage current associated with one or more deactivated memory cells at a level below a threshold. As such, the second node can be referred to as a suppress node and the second circuit can be referred to as a suppress driver. Figures 3A to 3L Additional aspects of TFT operation are described.

[0143] The stack 505 can be referenced Figure 5A Examples of the stack 305 are described. Figures 3A to 3L A group of vias 540 (depicted as white squares, squares with x's, squares with o's) in an array pattern is described. The group of vias 540 can be formed through a top layer (e.g., layer 310 of the stack 305, the HM layer) of the stack 505 including a first layer (e.g., layer 315 of the stack 305, the Dl layer), a second layer (e.g., layer 320 of the stack 305, the DM layer), and a third layer (e.g., layer 325 of the stack 305, the D2 layer). The group of vias 540 can be referenced Figure 5A Examples of the group of vias 340 are described. Figure 5A Various structures that can be formed simultaneously within the stack 505 using different groups of vias are also described. For example, Figures 3A to 3L A group of gate electrodes 560 of TFTs (which can be referenced Figures 3A to 3L Examples of the gate electrodes 360 are described), a group of array electrodes 550 (which can be referenced Figures 3C to 3F Examples of the array electrodes 350 are described), where each can be formed at a different junction of a sequence of processes for fabricating the TFTs.

[0144] A group of gate electrodes 560 (e.g., gate electrode 560-a through gate electrode 560-d) can be fabricated using a first subgroup of vias (e.g., the first group of vias 540-a), as described herein with reference to Figure 5A Further, as described elsewhere, a group of array electrodes 550 (e.g., array electrode 550-a through array electrode 550-j) can be fabricated using vias depicted as squares with x's. Further, a group of electrode patches (e.g., electrode patch 555-a, electrode patch 555-b) can be fabricated using vias depicted as squares with o's. In some cases, a second group of vias can include vias depicted as squares with x's and vias depicted as squares with o's, as described elsewhere. Figure 5LAs depicted in FIG, each electrode sheet (e.g., electrode sheet 555-a) can connect two array electrodes (e.g., electrode 550-a and electrode 550-c), and thus, the array electrode group can include an electrode sheet group. In some cases, the array electrode can serve as the second electrode of the TFT. In addition, a third via (e.g., via 540-b1, via 540-b2) can be used to construct a conductive plug, as described herein with reference to FIG. Figure 5A and 5M In some cases, the conductive plug can serve as a third electrode of the TFT and the conductive plug (eg, third electrode) can extend at least through the third layer (eg, layer 325, D2 layer of stack 305). Figures 5B to 5M Also illustrated is a third group of vias (eg, vias 540 - c1 , 540 - c2 , 540 - c3 ) formed through the top layer of stack 505 .

[0145] ​ A cross-sectional side view may correspond to Figure 5A The dashed line AA in FIG extends through the socket area of ​​fourteen (14) channels. For example, Figure 5B Fourteen vias (e.g., vias depicted as white or gray squares, vias depicted as squares with x's, vias depicted as squares with o's) are illustrated above the cross-sectional side view of stack 505 to use one or more specific vias to match various structural features (e.g., via holes, via cavities, trenches (i.e., adjacent to via cavities), dielectric plugs, conductive plugs) formed within stack 505 to form such structural features in stack 505. Additionally, arrows are added to indicate one or more specific vias at different junctions of the process sequence used to construct a TFT.

[0146] Figure 5B A cross-sectional side view of stack 505 is shown after forming via holes (e.g., corresponding to the vias indicated by arrows) using a third group of vias (e.g., vias 540-c1, 540-c2, and 540-c3). In some cases, an anisotropic etching process can form the via holes, as described herein. Figure 5B It is also illustrated that the electrode material 561 (which may be a reference material) may have been previously formed in the second layer (eg, DM layer) of the stack 505. Figures 3A-3L Examples of electrode materials 361 described herein) as referenced herein Figures 3C-3F described. Figure 5B The electrode material 561 depicted in FIG corresponds to Figure 5A In the gate electrode 560 depicted in FIG, for example, the electrode material 561 - a forms the gate electrode 560 - a , and the electrode material 561 - b forms the gate electrode 560 - b . Figure 5B The insulating layer 565 (which may be a reference Figures 3A-3LThe described insulating layer 365 partially surrounds the electrode material 561. Figure 5B It is also described that electrode pieces (e.g., electrode piece 555-a, electrode piece 555-b) can have been formed in the first layer (e.g., Dl layer) of the stack 505 prior.

[0147] Figure 5C It is described that a cross-sectional side view of the stack 505 after at least one etching process step (as described with reference to Figure 5B to the described) is performed using the formed third via group (e.g., via 540-c1, via 540-c2, via 540-c3) and corresponding via holes and vias. In some cases, the etching process step can include an isotropic etching process that selectively removes the first dielectric material at the Dl layer and the second dielectric material at the D2 layer. The isotropic etching can leave other materials exposed in the via holes and vias (e.g., materials other than the first dielectric material at the Dl layer and the second dielectric material at the D2 layer) substantially unchanged, e.g., the insulating layer 565, the electrode material 561. As a result of the isotropic etching process, via cavities (e.g., via cavity 542-al, via cavity 542-a2, via cavity 542-a3) can be formed. The via cavities 542 can span the first layer (e.g., Dl layer where the array electrodes 550 are present), the second layer (e.g., DM layer where the gate electrodes 560 are present), and the third layer (e.g., D2 layer). Further, the via cavities (e.g., via cavity 542-bl, via cavity 542-b2) can expose array electrodes (e.g., array electrode 550-k1, array electrode 550-k2). Additionally, the via cavities 542 can expose the insulating layer 565 conformal to the gate electrodes 560.

[0148] Figure 5D It is described that a cross-sectional side view of the stack 505 after at least one etching process step (as described with reference to Figure 5C to the described) is performed using the formed third via group (e.g., via 540-c1, via 540-c2, via 540-c3) and corresponding via holes and vias. In some cases, the etching process step can include an isotropic etching process that selectively removes the array electrodes at the Dl layer exposed to the isotropic etching process (e.g., array electrode 550-k1, array electrode 550-k2) as described with reference to Figure 5C to the described). The isotropic etching can leave other materials exposed in the via holes and vias (e.g., materials other than the array electrodes at the Dl layer) substantially unchanged, e.g., the insulating layer 565, the electrode material 561, the first dielectric material at the first layer, the placeholder material at the second layer, the second dielectric material at the third layer.

[0149] Figure 5EThe method of performing at least one etching process step and one deposition process step using the formed third via group (eg, via 540-c1, via 540-c2, via 540-c3) and corresponding via holes and via cavities (using reference 540-c1) is described. Figure 5D 560 , a first dielectric material at the first layer, a placeholder material at the second layer, and a second dielectric material at the third layer. Figures 3A-3L ). In some cases, the oxide material may be referred to as a gate oxide of the TFT.

[0150] Figure 5F The method of performing at least one deposition process step (using reference 5) using the formed third via group (eg, via 540-c1, via 540-c2, via 540-c3) and corresponding via holes and via cavities is described. Figure 5D In some cases, the deposition process step may use semiconductor material 580 (which may be a reference Figures 3A-3L The semiconductor material 580 may be in contact with the oxide material 570, which may be in contact with the gate electrode, as shown in FIG. Figure 5E described.

[0151] Figure 5G A cross-sectional side view of the stack 505 is illustrated after performing at least one etching process step and a deposition process step using a fourth group of vias (eg, a fourth set of vias including the vias indicated by arrows). Figure 5A , the fourth via group may include vias shared by the first via group (e.g., vias 540-a1, 540-a2, 540-a3, and 540-a4) and the third via group (e.g., vias 540-c1, 540-c2, and 540-c3). In some cases, the etching process step may include an anisotropic etching process to remove the semiconductor material 580 that has filled the via hole and the via cavity, as described with reference to FIG. Figure 5FThe anisotropic etch process can remove semiconductor material 580 along a vertical direction (e.g., a vertical direction relative to a horizontal substrate) to form via holes (e.g., via holes to be later filled with a dielectric material) corresponding to the fourth via group. Removing semiconductor material 580 within the via holes corresponding to the fourth via group can remove parasitic current paths having a shorter channel length of the TFTs, such that the main current paths of the TFTs can have a longer channel length, as referenced to FIG. 5B. Figure 5M The deposition process step can fill the via holes with a dielectric material in some cases. The via holes filled with the dielectric material can be referred to as dielectric plugs (e.g., dielectric plug 544-a, dielectric plug 544-b) that extend through the gate electrode (e.g., gate electrode 560-a including electrode material 561-a) in some cases.

[0152] Figure 5H A cross-sectional side view of the stack 505 after at least one etch process step using the fifth via group (e.g., the fifth via group including the vias indicated by the arrows) is illustrated. Reference is made to FIG. 5B. Figure 5A The fifth via group can include via 540-e (e.g., via 540-el including via 540-bl, via 540-e2 including via 540-b2, via 540-e3, via 540-e4) in some cases. The etch process can include an anisotropic etch process that removes the first dielectric material of the first layer (e.g., Dl layer), the placeholder material of the second layer (e.g., DM layer), and the second dielectric material of the third layer (e.g., D2 layer) (e.g., forming via holes corresponding to via 540-bl) in some cases. The anisotropic etch process can also remove the dielectric material that has filled the via holes for forming the array electrodes (e.g., the via holes corresponding to the vias depicted as squares with an x that include via 540-b2). The anisotropic etch process can leave other materials exposed in the via holes substantially unchanged, e.g., insulating layer 565.

[0153] The etch process step can further include an isotropic etch process that selectively removes the first dielectric material of the first layer (e.g., Dl layer) in some cases. The isotropic etch process can leave other materials exposed in the via holes substantially unchanged, e.g., the placeholder material of the second layer (e.g., DM layer), the second dielectric material of the third layer (e.g., D2 layer), insulating layer 565. The isotropic etch process using the fifth via group (e.g., the fifth via group including via 540-bl, via 540-b2) can form via cavities (e.g., via cavity 542-cl, via cavity 542-c2) to expose the semiconductor material (e.g., semiconductor material 580-al) of the TFTs and the second electrodes (e.g., electrode tab 555-al, electrode tab 555-a2) at the first layer (e.g., Dl layer).

[0154] Figure 5I A cross-sectional side view of the stack 505 after at least one deposition process step is performed using via holes formed based on a fifth set of vias (e.g., a fifth set of vias including the vias indicated by the arrows) is illustrated. In some cases, the deposition process step can fill the reference Figures 3A-3L described examples of ohmic material 375) to fill the reference Figure 5H described via cavities (e.g., via cavities 542-c1, 542-c2) so that the ohmic material (e.g., ohmic material 575-a) can be in contact with the semiconductor material (e.g., semiconductor material 580-a) and the second electrode (e.g., array electrode 555-a1). A CMP process or an etch-back process can be used to remove the additional ohmic material on top of the stack 505.

[0155] Figure 5J A cross-sectional side view of the stack 505 after at least one etch process step and deposition process step is performed using a fifth set of vias (e.g., a fifth set of vias including the vias indicated by the arrows) is illustrated. In some cases, the etch process step can include an anisotropic etch process that can remove a portion of the ohmic material along a vertical direction (e.g., a vertical direction relative to a horizontal substrate) to form a via hole (e.g., a via hole corresponding to the fifth set of vias). The anisotropic etch process can leave other materials exposed in the via hole substantially unchanged, such as the occupancy material of the second layer (e.g., a DM layer), the second dielectric material of the third layer (e.g., a D2 layer), the insulating layer 565. In some cases, after the anisotropic etch process, the deposition process step using the via hole (e.g., a via hole corresponding to the fifth set of vias) can form an insulating material 566 in contact with the ohmic material (e.g., ohmic material 575-a1, ohmic material 575-a2) that is retained within a via cavity (e.g., via cavity 542-c1 that has been filled with ohmic material, as described with reference to Figure 5I Figures 3A-3L described examples of materials that can form the insulating layer 365. In some cases, the deposition process step can include a selective deposition process that can deposit the insulating material 566 only on the exposed surface of the ohmic material 575.

[0156] Figure 5K A cross-sectional side view of the stack 505 after at least one etch process step (as described with reference to Figure 5J ​A cross-sectional side view of the stack 505 after the at least one deposition process step and the etching process step is described. In some cases, the etching process step can include an isotropic etching process that can selectively remove the second dielectric material at the third layer (e.g., the D2 layer). The isotropic etching process can leave other materials exposed in the via hole (e.g., materials other than the second dielectric material of the D2 layer) substantially unchanged, such as the insulating material 566, the insulating layer 565, the semiconductor material 580, the placeholder material at the second layer (e.g., the DM layer). Due to the isotropic etching process, a via cavity (e.g., the via cavity 542-d) can be formed such that the semiconductor material 580-a can be exposed to subsequent process steps.

[0157] Figure 5L A cross-sectional side view of the stack 505 after the at least one deposition process step and the etching process step is described. In some cases, the etching process step can include an isotropic etching process that can selectively remove the second dielectric material at the third layer (e.g., the D2 layer). The isotropic etching process can leave other materials exposed in the via hole (e.g., materials other than the second dielectric material of the D2 layer) substantially unchanged, such as the insulating material 566, the insulating layer 565, the semiconductor material 580, the placeholder material at the second layer (e.g., the DM layer). Due to the isotropic etching process, a via cavity (e.g., the via cavity 542-d) can be formed such that the semiconductor material 580-a can be exposed to subsequent process steps. Figure 5K The via cavity 542-d) formed at the third layer (e.g., the D2 layer) such that the ohmic material (e.g., the ohmic material 575-b) can be in contact with the semiconductor material 580-a. In some cases, the etching process step can include an anisotropic etching process that can remove a portion of the ohmic material from the via hole in a vertical direction (e.g., a vertical direction relative to a horizontal substrate). In some cases, the anisotropic etching process can create a hole (e.g., the opening 541-a) at a bottom layer (e.g., the layer 330) of the stack 505. The hole can be coupled with a conductive element (e.g., the conductive element 585-a to the conductive element 585-d) that can be part of a logic circuitry layer. In some cases, the conductive element 585-a can be coupled with an inhibit node of an inhibit driver. In some cases, the conductive element 585-b can be coupled with a select node of a select driver.

[0158] Figure 5M A cross-sectional side view of the stack 505 after the at least one deposition process step is described. In some cases, the deposition step can fill the via holes (e.g., the via holes corresponding to the fifth set of vias) at the bottom layer and the hole (e.g., the opening 541-a) described with the electrode material 595. The additional electrode material 595 on top of the stack can be removed using a CMP process or an etch-back process. The via holes filled with the electrode material 595 can be referred to as conductive plugs (e.g., the conductive plug 596). The conductive plugs can couple the conductive elements 585 with the semiconductor material (e.g., the semiconductor material 580-a) of the TFT through the ohmic material (e.g., the ohmic material 575-b) and can complete the construction of the TFT. Figure 5L The via cavity 542-d) formed at the third layer (e.g., the D2 layer) such that the semiconductor material 580-a can be exposed to subsequent process steps.

[0159] In some cases, Figure 5M The TFTs described in the middle can include a conductive plug extending through a stack including a first layer, a second layer, and a third layer, a gate electrode at the second layer, a second electrode at the first layer, and a semiconductor material at the first and second layers, the semiconductor material coupled with the second electrode via a first segment of an ohmic material at the first layer and coupled with the conductive plug via a second segment of an ohmic material at the third layer. In some cases, the semiconductor material at the first and second layers extends into the third layer. In some cases, the TFTs can include a dielectric plug extending through the gate electrode.

[0160] Figure 5M Two sets of TFTs (e.g., first set of TFTs 535-a, second set of TFTs 535-b) are described. Each set of TFTs can include a first sub-group of TFTs (e.g., a sub-group of TFTs including upper and lower TFTs) coupled with a first node associated with a logic circuitry layer (e.g., by a conductive element 585-a coupled with an inhibit node of an inhibit driver) and a second sub-group of TFTs (e.g., a sub-group of TFTs including upper and lower TFTs) coupled with a second node associated with the logic circuitry layer (e.g., by a conductive element 585-b coupled with a select node of a select driver). As described with reference to Figure 5N Each set of TFTs can drive (e.g., activate, inhibit) a single set of array electrodes (e.g., array electrodes 550-a1 connected with array electrodes 550-d1 in an upper layer, array electrodes 550-a2 connected with array electrodes 550-d2 in a lower layer), as described. In some cases, the two sets of TFTs can be processed differently to adapt their operating characteristics accordingly, e.g., the first sub-group of TFTs can be processed to provide low leakage current characteristics within a particular operating voltage range and the second sub-group of TFTs can be processed to provide high drive current characteristics.

[0161] Figure 5M Current paths (e.g., current path 545-a, current path 545-b) of TFTs (e.g., upper TFTs of the first set of TFTs 535-a) are also described. The current paths describe how a particular TFT can couple a node of a logic circuitry layer with an array electrode to access a memory cell in an active array region of an array layer when the TFT is activated. For example, a conductive element 585-b can be coupled with a select node of a select driver. The conductive element 585-b is coupled with a conductive plug 596 that can act as a common source for TFTs (e.g., upper and lower TFTs of the second sub-group of TFTs of the first set of TFTs 535-a). The conductive plug 596 is in contact with a semiconductor material 580-b by an ohmic material 575-c. The semiconductor material 580-b can form an active channel that causes current to flow based on a voltage applied to a gate electrode 560 (e.g., gate electrode 560-b1 including electrode material 561-b1).

[0162] Additionally, the semiconductor material 580-b is connected to the array electrode 555-a1 through the ohmic material 575-b1. The array electrode 555-a1 can act as a common drain for the upper TFTs of the first set of TFTs 535-a. In this way, when an active channel is formed within the semiconductor material (e.g., the semiconductor material 580-b) (when a voltage applied to the gate electrode (e.g., the gate electrode 560-b1 including the electrode material 561-b1) is greater than a threshold voltage of the upper TFT and when there is a voltage difference between the source (which is coupled to a node of the logic circuitry layer) and the drain (which is coupled to the array electrode) of the upper TFT), current can flow (e.g., the current path 545-b) between the source and the drain of the upper TFT (e.g., the upper TFT of the second sub-group of TFTs of the first set of TFTs 535-a).

[0163] Similarly, when another current path (e.g., the current path 545-a) is activated (e.g., when the upper TFT of the first sub-group of TFTs of the first set of TFTs 535-a is activated), the array electrode 555-a1 can be coupled with the conductive element 585-a, which can be coupled with a different node (e.g., the inhibit node) of the logic circuitry layer. In this way, an array electrode (e.g., the array electrode 555-a1 in the upper layer) can be coupled with more than two nodes (e.g., the inhibit node, the select node) of the logic circuitry layer using the upper TFTs of the first set of TFTs 535-a. More generally, one of the four TFTs of the first set of TFTs 535-a can be activated to couple a node of the logic circuitry layer (e.g., a select node or an inhibit node connected to the source of the TFT) with an array electrode (e.g., an array electrode connected to the drain of the TFT).

[0164] The current flowing within the TFT flows in a manner that encircles the gate electrode and the TFT can be referred to as an encircling TFT. As described in Figure 5M As described in Figure 3K , the channel length of an encircling TFT (e.g., the distance between the source and the drain of a TFT) can be greater than the channel length of a vertical TFT (as described with reference to Figure 4Z , or a horizontal TFT (as described with reference to

[0165] Figure 5N A top-down view illustrating a socket region including a stack 505 of two sets of TFTs (e.g., encircling TFTs) is described herein. Figure 5M The cross-sectional side view of Figure 5N may correspond to the socket region in which the dashed line AA extends (as shown in Figure 5NAspects of structure features constructed using the fabrication techniques described herein are illustrated. For example, Figure 5N A bulk region 581 of a TFT is depicted (e.g., a bulk region 581-a including a semiconductor material 580-a). The bulk region 581 can correspond to the reference Figure 5A and 5F A third group of vias is depicted (e.g., the vias 540-c1 corresponding to the third group of bulk regions 581-a).

[0166] Figure 5N A fifth group of vias is also depicted as a square with horizontal lines (e.g., vias including the vias 540-b1) or a square with vertical lines (e.g., vias including the vias 540-b2). The vias depicted as a square with horizontal lines can correspond to vias coupled to the conductive elements 585-a or the conductive elements 585-d. The vias depicted as a square with vertical lines can correspond to vias coupled to the conductive elements 585-b or the conductive elements 585-c. In some cases, the conductive elements 585-a (or the conductive elements 585-d) can be coupled to an inhibit node of an inhibit driver and the conductive elements 585-b (or the conductive elements 585-c) can be coupled to a select node of a select driver. The vias of the fifth group of vias can include conductive plugs (e.g., the conductive plugs 596 described with reference to Figure 5J surrounded by an insulating material 576 (e.g., an insulating material deposited on a surface of the ohmic material 575 at the D1 layer, as described with reference to Figure 5M However, the conductive plugs can be coupled to corresponding bulk regions 581 at the second layer of the stack through the ohmic material, as described with reference to Figure 5M

[0167] Figure 5N An ohmic material (e.g., the ohmic material 575-a) is also depicted positioned between a bulk region (e.g., the bulk region 581-a) and an electrode tab (e.g., the electrode tab 555-a connected to the array electrode 550-a and the array electrode 550-d). The ohmic material provides a low resistance path for current flow between a bulk region (e.g., in which a channel for current flow can be formed) and an electrode tab (e.g., the electrode tab 555-a) or a conductive plug (e.g., the conductive plug 596).

[0168] Figure 5N Current paths (e.g., the current paths 545-e, the current paths 545-f) are also depicted. The current paths 545-e can correspond to the reference Figure 5M ​The depicted current path 545-a or current path 545-b. In other words, current flow following current path 545-a (or current path 545-b) can reach electrode patch 555-b and continue to flow using array electrode 550-a and array electrode 550-c. Similarly, current path 545-f can correspond to a reference Figure 5M The depicted current path 545-c or current path 545-d.

[0169] Figure 5N It is also illustrated that more than one TFT (e.g., a surround TFT) can be concatenated to provide more current than can be provided by a single TFT. For example, Figure 5N It is depicted that an array electrode (e.g., array electrode 550-a) can be split when connected to an electrode patch (e.g., electrode patch 555-a) that is further connected to another array electrode (e.g., array electrode 550-c). As an example, Figure 5N It is depicted that five (5) individual TFTs concatenated into one TFT (e.g., indicated by five conductive plugs arranged in a single column connected to a single electrode patch 555-a) can supply four times more current than a single TFT. Any number of TFTs can be concatenated to provide any amount of current that can be needed or desired, as described herein.

[0170] Figure 5N The TFT configurations illustrated in FIG. 6 can facilitate providing an electrical connection that is specific to a bulk region 581. Such an electrical connection specific to a bulk region can be beneficial for aspects of TFT operation, such as avoiding issues related to floating bodies of TFTs. For example, bulk region 581-b can be expanded to include additional pass lines (e.g., three rows of pass lines instead of one row of pass lines between gate electrode 560-b and gate electrode 560-c) such that one or more of the additional pass lines (e.g., one or more of the middle rows of the three rows of pass lines) can be coupled with nodes of a logic circuitry layer using the fabrication techniques described herein. In some cases, one or more holes (e.g., pass holes corresponding to the one or more pass lines) can be formed through the bulk region (e.g., bulk region 581-b including semiconductor material 580) to the logic circuitry layer and the one or more holes can be filled with an electrode material (e.g., electrode material 595 referenced in FIG. 6) to form a fourth electrode of a transistor (e.g., a base of a TFT). Additionally or alternatively, bulk region 581-a can be expanded to include an additional pass line (e.g., a pass line positioned to the left boundary of bulk region 581-a) and the additional pass line can be coupled with the logic circuitry layer. In this way, the logic circuitry can provide specific voltages to the bulk region based on various modes of operation of the TFT (e.g., operating in a suppression mode or a selection mode). Figure 5M The depicted electrode material 595) to form a fourth electrode of a transistor (e.g., a base of a TFT). Additionally or alternatively, bulk region 581-a can be expanded to include an additional pass line (e.g., a pass line positioned to the left boundary of bulk region 581-a) and the additional pass line can be coupled with the logic circuitry layer. In this way, the logic circuitry can provide specific voltages to the bulk region based on various modes of operation of the TFT (e.g., operating in a suppression mode or a selection mode).

[0171] Figures 6A-6RExemplary fabrication techniques are described in accordance with the present disclosure. Figures 6A-6R Aspects of several process steps for concurrently building two or more TFTs (e.g., hybrid TFTs in which current flows in a combination of vertical and horizontal directions when the TFT is activated) are described. In some cases, such TFTs can be fabricated in the socket region of an array layer, as described herein. Figures 6A-6R Top-down views including portions of the socket region (e.g., layouts of the socket region) to illustrate various structures in which different pass groups can be used to concurrently build TFTs. Figures 6A-6R Cross-sectional side views also including portions of the socket region to illustrate aspects of process features during several process steps for concurrently building TFTs.

[0172] Figures 6A-6R Exemplary fabrication techniques are described for building hybrid TFTs within a composite stack (e.g., with reference to Figures 3A-3L The stack 305 described for building vertical TFTs, the stack 405 described for building planar TFTs, and the stack 505 described for building surround TFTs. Figures 4A-4AA The stack 305 described for building vertical TFTs, the stack 405 described for building planar TFTs, and the stack 505 described for building surround TFTs. Figures 5A-5N Exemplary fabrication techniques are described for building hybrid TFTs within a composite stack (e.g., with reference to

[0173] Figure 6A Top-down views illustrating stacks 605 in which a socket region including two or more TFTs (e.g., hybrid TFTs) can be built, as described herein. As examples, Figure 6AFour groups of TFTs are illustrated. Each group of TFTs can drive a single group of array electrodes from either end or the other end. In some cases, two groups of TFTs can drive a single group of array electrodes, such as a first group of TFTs from one end and a second group of TFTs from the other end. Further, the first group of TFTs can couple the array electrodes with a first node associated with the logic circuitry layer and a second sub-group of TFTs can couple the array electrodes with a second node associated with the logic circuitry layer. In some cases, the first node can correspond to a select node and the first circuitry can be referred to as a select driver. In some cases, the second node can correspond to a suppress node and the second circuitry can be referred to as a suppress driver. In some cases, the two groups of TFTs can be processed differently to adapt their operating characteristics accordingly, such as the first group of TFTs can be processed to provide high drive current characteristics and the second sub-group of TFTs can be processed to provide low leakage current characteristics within a specific operating voltage range.

[0174] The stack 605 can be a reference Figures 3A-3L to the described example of the stack 305. Figure 6A A group of vias 640 (depicted as white squares, squares with x's, squares with o's) in an array pattern is illustrated. The group of vias 640 can be formed through a top layer (e.g., layer 310 of the stack 305, the HM layer) of the stack 605 including a first layer (e.g., layer 315 of the stack 305, the Dl layer), a second layer (e.g., layer 320 of the stack 305, the DM layer), and a third layer (e.g., layer 325 of the stack 305, the D2 layer). The group of vias 640 can be a reference Figures 3A-3L to the described example of the group of vias 340. Figure 6A Various structures that can be formed simultaneously within the stack 605 using different groups of vias are also illustrated. For example, Figure 6A A group of gate electrodes 660 of TFTs (which can be a reference Figures 3A-3L to the described example of the gate electrodes 360), a group of array electrodes 650 (which can be a reference Figures 3A-3L to the described example of the array electrodes 350) are illustrated, where each can be formed at a different junction of a sequence of processes for fabricating the TFTs.

[0175] A group of gate electrodes 660 (e.g., gate electrode 660-a, gate electrode 660-b) can be fabricated using a first sub-group of vias (e.g., the first group of vias 640-a), as described herein with reference to Figures 3C-3F Further, as described elsewhere, a group of array electrodes 650 (e.g., array electrode 650-a through array electrode 650-d) can be fabricated using vias depicted as squares with x's (e.g., the second group of vias). Further, a group of electrode pads (e.g., electrode pad 655-a, electrode pad 655-b) can be fabricated using a sub-group of the second group of vias (e.g., via 640-b1, via 640-b2). AsFigure 6A As depicted in , each electrode pad (eg, electrode pad 655 - b ) may be connected to an array electrode (eg, array electrode 650 - a ), and thus, an array electrode group may include a group of electrode pads.

[0176] In some cases, according to the manufacturing techniques described herein, a subset of array electrodes (e.g., array electrodes 650-b, array electrodes 650-c) can be separated (e.g., separated, disconnected) from the rest of the array electrodes by using a subset of vias (e.g., via 640-x). In some cases, the array electrodes can serve as the second electrodes of the TFTs. Additionally, a third via (e.g., via 640-c1, via 640-c2) can be used to construct a conductive plug, as described herein with reference to Figure 6P and 6Q In some cases, the conductive plug can serve as a third electrode of the TFT and the conductive plug (eg, third electrode) can extend at least through the third layer (eg, layer 325, D2 layer of stack 305). Figure 6A Also illustrated is a third group of vias (eg, depicted as square vias with o's) formed through the top layer of stack 605 .

[0177] Figures 6B-6Q A cross-sectional side view may correspond to Figure 6A The dashed line AA in FIG extends through the socket area of ​​the via. For example, Figure 6B Nine (9) vias (e.g., vias depicted as white squares, vias depicted as squares with x's, vias depicted as squares with o's) above the cross-sectional side view of stack 605 are illustrated to match various structural features (e.g., via holes, via cavities, trenches (i.e., adjacent to via cavities), dielectric plugs, conductive plugs) formed within stack 605 using one or more specific vias to form such structural features in stack 605. Additionally, arrows are added to indicate one or more specific vias at different junctions of the process sequence used to construct a TFT.

[0178] Figure 6B A cross-sectional side view of the stack 605 is shown, as shown in FIG. Figure 6A described. Figure 6B The electrode material 661 (which may be a reference Figures 3A-3L Examples of electrode materials 361 described herein) as referenced herein Figures 3C-3F described. Figure 6B The electrode material 661 depicted in FIG corresponds to Figure 6A , for example, the electrode material 661 - a forms the gate electrode 660 - a . Figure 6B The insulating layer 665 (which may be a reference Figures 3A-3LThe described insulating layer 365 partially surrounds the electrode material 661. Figure 6B It is also described that electrode patches (e.g., electrode patch 655-b1, electrode patch 655-b2) can have been previously formed in the first layer (e.g., D1 layer) of the stack 605. Further, Figure 6B It is described that via holes filled with a dielectric material, which can be referred to as dielectric plugs (e.g., dielectric plug 644-a1, dielectric plug 644-a2), extend through a gate electrode (e.g., gate electrode 660-a including electrode material 661-a).

[0179] Figure 6C It is described that a cross-sectional side view of the stack 605 after performing at least one etching process step using the third via group (e.g., vias indicated by arrows). In some cases, the etching process step can include an anisotropic etching process that can form via holes (e.g., via hole 641-c1 through via hole 641-c5) corresponding to the third via group (as described herein), e.g., vertically remove various materials through the stack 605 and stop on a bottom layer of the stack 605.

[0180] Figure 6D It is described that a cross-sectional side view of the stack 605 after performing at least one etching process step using the third via group to form a via cavity 642. The via cavity 642 can be concentric with the via holes that have been formed within the stack 605, as described with reference to Figure 6C In some cases, the etching scheme can include an isotropic etching process that selectively removes the first dielectric material of the first layer (e.g., D1 layer) and the second dielectric material of the third layer (e.g., D2 layer). The isotropic etching process can leave other materials exposed in the via holes, e.g., the placeholder material of the second layer (e.g., DM layer), the insulating layer 665, the array electrode patches 655. In some cases, via cavities corresponding to two or more via holes (e.g., via hole 641-c2 through via hole 641-c4) can merge to form a via cavity (e.g., via cavity 643). As a result of the isotropic etching process, the array electrodes (e.g., electrode patches 655) are exposed to subsequent process steps. In some cases, the via cavities (e.g., via cavity 642-c1a, via cavity 642-c1b, via cavity 642-c1c) can span the first layer (e.g., D1 layer), the second layer (e.g., DM layer), the third layer (e.g., D2 layer).

[0181] Figure 6E It is described that a cross-sectional side view of the stack 605 after performing at least one deposition process step using the third via group (e.g., vias indicated by arrows). In some cases, the deposition process step can use an ohmic material 675 (which can be the same as the ohmic material 675 described with reference to Figures 3A-3LThe via holes (e.g., via holes 641-c1 to via holes 641-c5) and associated via cavities and channels (e.g., refer to Figure 6D The ohmic material 675 can be in contact with the array electrode 655 due to the deposition process steps.

[0182] Figure 6F A cross-sectional side view of the stack 605 after at least one etch process step and deposition process step using a third via group (e.g., vias indicated by arrows) is illustrated. In some cases, the etch process step can include an anisotropic etch process that can remove the ohmic material 675 in the via holes (e.g., corresponding to the third via group) vertically to thereby leave the ohmic material 675 (e.g., ohmic material 675-al, ohmic material 675-a2, ohmic material 675-a3) within the via cavities. The etch process step can leave other materials exposed within the via holes, such as the placeholder material of the DM layer, the insulating layer 665. In some cases, the deposition process step can fill the via holes formed by the etch process step (e.g., anisotropic etch process that has removed the ohmic material in the via holes) with an insulating material. In some cases, a CMP process or an etch-back process can be used to remove the additional insulating material on top of the stack 605.

[0183] Figure 6G A cross-sectional side view of the stack 605 after at least one etch process step using a fourth via group (e.g., vias indicated by arrows) is illustrated. Refer to Figure 6A The fourth via group can include via 640-dl or via 640-d2. In some cases, the fourth via group (e.g., via 640-dl) can include a subset of the third via group (e.g., vias depicted as squares with a circle) and a via that can form a third electrode of a TFT (e.g., via 640-cl), as described with reference to Figure 6P and 6Q In some cases, the etch process step can include an anisotropic etch process that can remove a dielectric material (or insulating material) that can be present within the via holes corresponding to the fourth via group vertically. The anisotropic etch process can leave other materials exposed within the via holes substantially unchanged, such as the ohmic material 675, the electrode material 661 forming the gate electrode 660, the insulating layer 665, the first dielectric material of the first layer (e.g., Dl layer), the placeholder material of the second layer (e.g., DM layer), the second dielectric material of the third layer (e.g., D2 layer). Due to the anisotropic etch process, the ohmic material 675 (e.g., ohmic material 675-b that has filled the channel 643 described with reference to Figure 6D may be exposed to subsequent process steps.

[0184] Figure 6H A cross-sectional side view of the stack 605 after at least one etch process step is performed using the fourth via group (e.g., vias indicated by arrows) is illustrated. In some cases, the etch process step can include an isotropic etch process that can selectively remove the ohmic material 675 that has filled the trench (e.g., trench 643 as referenced Figure 6D The isotropic etch process can leave other materials exposed in the via holes and the trench substantially unchanged, such as the electrode material 661 forming the gate electrode 660, the insulating layer 665, the first dielectric material at the first layer (e.g., Dl layer), the placeholder material at the second layer (e.g., DM layer), the second dielectric material at the third layer (e.g., D2 layer). Due to the isotropic etch process, the first dielectric material at the first layer (e.g., Dl layer) and the placeholder material at the second layer (e.g., DM layer) can be exposed to subsequent process steps.

[0185] Figure 6I A cross-sectional side view of the stack 605 after at least one etch process step is performed using the fourth via group (e.g., vias indicated by arrows) is illustrated. In some cases, the etch process step can include an isotropic etch process that can selectively remove the first dielectric material at the first layer (e.g., Dl layer) and the placeholder material at the second layer (e.g., DM layer). The isotropic etch process can leave other materials exposed in the via holes and the trench substantially unchanged, such as the electrode material 661 forming the gate electrode 660, the insulating layer 665, the second dielectric material at the third layer (e.g., D2 layer), the ohmic material 675. Due to the isotropic etch process, some portions of the insulating layer 665 can be exposed to subsequent process steps. In some cases, using the fourth via group, the isotropic etch process can form via cavities (e.g., via cavity 642-dl, via cavity 642-d2) and trenches (e.g., trench 643-a including two or more adjacent via cavities). Such via cavities or trenches can span the first layer (e.g., Dl layer), the second layer (e.g., DM layer), and the third layer (e.g., D2 layer).

[0186] Figure 6J A cross-sectional side view of the stack 605 after at least one etch process step and a deposition process step is performed using the fourth via group (e.g., vias indicated by arrows) is illustrated. In some cases, the etch process step can include an isotropic etch process that can selectively remove exposed portions of the insulating layer 665. The isotropic etch process can leave other materials exposed in the via holes and the trench substantially unchanged, such as the electrode material 661 forming the gate electrode 660, the second dielectric material at the third layer (e.g., D2 layer), the ohmic material 675. In some cases, the deposition step can form an oxide material 670 in contact with the electrode material 661 forming the gate electrode 660 (which can be referenced Figures 3A-3LThe oxide material 370 described. In other words, the exposed portions of the insulating layer 665 can be replaced by the oxide material 670 due to the etching process steps and the deposition process steps. In some cases, the oxide material 670 can be referred to as a gate oxide of the TFT.

[0187] Figure 6K A cross-sectional side view of the stack 605 after at least one deposition process step is performed using the fourth via group (e.g., the vias indicated by the arrows) is illustrated. In some cases, the deposition process step can fill the via cavities or channels (e.g., the via cavities 642, the channels 643) with a semiconductor material 680 described. A CMP process or an etch-back process can be used to remove the additional semiconductor material on top of the stack 605. As a result of filling the via cavities or channels with the semiconductor material 680, the semiconductor material 680 can be in contact with the ohmic material 675 that is further connected to the array electrodes (e.g., the electrode pieces 655, the second electrodes of the TFTs). In addition, the semiconductor material 680 can be in contact with the oxide material 670 that is further connected to the gate electrodes 660 (e.g., the gate electrodes 660 including the electrode material 661). Figure 6I

[0188] Figure 6L A cross-sectional side view of the stack 605 after at least one etching process step and a deposition process step is performed using the fifth via group (e.g., the vias indicated by the arrows) is illustrated. In some cases, the etching process step can remove the semiconductor material 680 that has filled the via cavities or channels (e.g., the via cavities 642, the channels 643) described with reference to Figure 6K The semiconductor material 680 described to form a via hole (e.g., a via hole corresponding to the fifth via group). In some cases, the deposition process step can fill the via hole with an insulating material (or a dielectric material). In some cases, removing the semiconductor material 680 within the via hole corresponding to the fifth via group can remove a parasitic current path with a shorter channel length of the TFT, such that a main current path of the TFT can have a longer channel length, as described with reference to Figure 6Q In some cases, the deposition process step can fill the via hole with a dielectric material. In some cases, the via hole filled with the dielectric material can be referred to as a dielectric plug (e.g., the dielectric plug 644-a, the dielectric plug 644-b) that extends through the gate electrode (e.g., the gate electrode 660-a including the electrode material 661-a). A CMP process or an etch-back process can be used to remove the additional insulating material on top of the stack 605.

[0189] Figure 6M A cross-sectional side view of the stack 605 after at least one etching process step and a deposition process step is performed using the fifth via group (e.g., the vias indicated by the arrows) is illustrated. In some cases, the etching process step can remove the semiconductor material 680 that has filled the via cavities or channels (e.g., the via cavities 642, the channels 643) described with reference to Figure 6A ​The fifth via group can include via 640-c1 or via 640-c2. In some cases, the etching process step can include an anisotropic etching process that can remove insulating material that has filled the via hole (as described with reference to Figure 6L ) vertically to thereby form a via hole (e.g., via hole 641-c2 corresponding to via 640-c2) through the first layer (e.g., D1 layer), the second layer (e.g., DM layer), and the third layer (e.g., D2 layer). The anisotropic etching process using the fifth via group can expose the semiconductor material 680 in the via hole (e.g., via hole 641-c2 corresponding to via 640-c2) to subsequent process steps. In some cases, the deposition step can selectively grow insulating material 690 in contact with the semiconductor material 680 at the first layer (e.g., D1 layer) and the second layer (e.g., DM layer).

[0190] Figure 6N A cross-sectional side view of the stack 605 after at least one etching process step using the fifth via group (e.g., the via indicated by the arrow) is illustrated. In some cases, the etching process step using the fifth via group (e.g., via 640-c2) can laterally remove the semiconductor material 680 at the third layer (e.g., D2 layer) to form a cavity (e.g., cavity 642-e) at the third layer. The insulating material 690 on the surface of the semiconductor material 680 can leave the semiconductor material 680 at the first layer (e.g., D1 layer) and the second layer (e.g., DM layer). The etching process step can expose portions of the semiconductor material 680 to subsequent process steps.

[0191] Figure 6O A cross-sectional side view of the stack 605 after at least one deposition process step using the fifth via group (e.g., the via indicated by the arrow) is illustrated. In some cases, the deposition process step can fill the via hole (e.g., via hole 641-c2 described with reference to Figure 6M ) and the associated via cavity (e.g., via cavity 642-e described with reference to Figure 6N ) with an ohmic material 675-e.

[0192] Figure 6PA cross-sectional side view of the stack 605 after at least one etch process step is performed using the fifth group of vias (e.g., the vias indicated by the arrows) is illustrated. In some cases, the etch process can include an anisotropic etch process that can remove the ohmic material 675-e in the via hole (e.g., the via hole corresponding to via 640-c2). In some cases, the anisotropic etch process can create a hole (e.g., hole 641) at the bottom layer (e.g., layer 330) of the stack 605. The hole can be coupled with a conductive element (e.g., conductive element 685) that can be part of a logic circuitry layer. In some cases, the conductive element 685 can be coupled with an inhibit node of an inhibit driver. In some cases, the conductive element 685 can be coupled with a select node of a select driver.

[0193] Figure 6Q A cross-sectional side view of the stack 605 after at least one deposition process step is performed using the fifth group of vias (e.g., the vias indicated by the arrows) is illustrated. In some cases, the deposition step can fill the via hole (e.g., the via hole corresponding to via 640-c2) at the bottom layer and the hole (e.g., hole 641) with electrode material 695. A CMP process or an etch-back process can be used to remove the extra electrode material 695 on the top of the stack. The via hole filled with electrode material 695 can be referred to as a conductive plug (e.g., conductive plug 696). The conductive plug 696 can couple the conductive element 685 with the semiconductor material (e.g., semiconductor material 680-a) of the TFT through the ohmic material (e.g., ohmic material 675-e) and can complete the construction of the TFT. Figure 6P

[0194] In some cases, Figure 6Q The TFT illustrated in FIG. 6B can include a conductive plug extending through the stack including the first layer, the second layer, and the third layer, the gate electrode at the second layer, the second electrode at the first layer, and the semiconductor material at the first layer and the second layer, the semiconductor material coupled with the second electrode via the first segment of the ohmic material at the first layer and coupled with the conductive plug via the second segment of the ohmic material at the third layer. In some cases, the TFT can include a dielectric plug extending through the gate electrode.

[0195] Figure 6Q Current paths (e.g., current path 645-a, current path 645-b) of the TFTs (e.g., the upper TFT) are also illustrated. The current paths illustrate how a particular TFT can couple a node of the logic circuitry layer with an array electrode to access a memory cell in an active array region of the array layer when the TFT is activated. For example, the conductive element 685 can be coupled with a select node of a select driver. The conductive element 685 and the select node can act as a select line. In some cases, the conductive element 685 can be coupled with an inhibit node of an inhibit driver. In some cases, the conductive element 685 can be coupled with a word line. Figure 6Q ​The conductive plugs 696, which are common to the sources of the TFTs (e.g., both the upper TFT and the lower TFT) depicted in the middle, are coupled. The conductive plugs 696 are in contact with the semiconductor material 680-a through the ohmic material 675-e. The semiconductor material 680-a can form an active channel that causes current to flow based on a voltage applied to the gate electrode 660 (e.g., the gate electrode 660-a including the electrode material 661-a).

[0196] Additionally, the semiconductor material 680-a is connected to the electrode tab 655-al through the ohmic material 675-al. The electrode tab 655-al (and thus the electrode tab 655-a2) is connected to the conductive plug 696 through the ohmic material 675-a2. The conductive plug 696 is in contact with the semiconductor material 680-a through the ohmic material 675-e. Figure 6R The array electrode 650-e depicted in the middle can act as a drain of a TFT (e.g., the left TFT of the upper TFT). In this way, when an active channel is formed within a semiconductor material (e.g., the semiconductor material 680-a) (when a voltage applied to a gate electrode (e.g., the gate electrode 660-a including the electrode material 661-a) is greater than a threshold voltage of the TFT and when there is a voltage difference between a source of the TFT (which is coupled to a node of the logic circuitry layer) and a drain of the TFT (which is coupled to the array electrode)), current can flow (e.g., the current path 645-a) between the source and the drain of the TFT.

[0197] The current flowing within the TFT flows in both a vertical direction and a horizontal direction (e.g., relative to the horizontal substrate) and the TFT can be referred to as a hybrid TFT (e.g., refer to FIG. 6B). As Figure 3K described, the vertical TFT and the horizontal TFT described can be combined to form a hybrid TFT. As Figure 4Z described, the vertical TFT and the horizontal TFT described can be combined to form a hybrid TFT. As Figure 6Q illustrated in the middle, the channel length of the hybrid TFT (e.g., the distance between the source and the drain of the TFT) can be greater than the channel length of the vertical TFT or the horizontal TFT. This increased channel length can be beneficial for some aspects of TFT operation, such as being less susceptible to experiencing leakage current issues related to channel length.

[0198] Figure 6R A top-down view illustrating a stack 605 in which the socket region includes four TFTs (e.g., hybrid TFTs) is illustrated. Figure 6Q A cross-sectional side view of the stack 605 can correspond to the socket region in which the dashed line AA extends, as Figure 6R shown in the middle. Figure 6R Aspects of a structure feature that has been constructed using the fabrication techniques described herein are illustrated. For example, Figure 6R An array electrode 650, which can act as a second electrode (e.g., a drain) of a TFT, a gate electrode 660 of the TFT, and a conductive plug 696 are depicted. Figure 6R A top-down view of a current path (e.g., the current path 645-c, the current path 645-d) is also depicted with reference to Figure 6Q the hybrid TFT described.

[0199] Figures 7A-7D FIG. 1 illustrates a diagram of an exemplary memory array including an active array region and a socket region supporting memory array decoding and interconnects in accordance with an embodiment of the present disclosure. Figures 7A-7D Aspects are described in which a set of TFTs can be concurrently fabricated in a reference Figure 7C Aspects are described of a socket region within a composite stack 705 (e.g., a reference Figures 3A-3L Aspects are described of a socket region within one or more vertically integrated composite stacks 305. Figures 7A-7D A top view including a portion of the socket region (e.g., a layout of the socket region) to illustrate that a subset of the set of TFTs can be configured to couple nodes of a circuitry layer (e.g., row decoders 120 fabricated in the substrate 204) with a subset of array electrodes (e.g., access lines, word lines, bit lines) of the active array region in which memory cells are positioned. Additionally, Figures 7A-7D Cross-sectional side views including different portions of the socket region to illustrate that the set of TFTs can couple array electrodes with nodes of a circuitry layer. In some cases, the circuitry layer can be a portion of a substrate over which the array layer is positioned.

[0200] Figures 7A-7D Circuit representations of the set of TFTs are also included to illustrate that the set of TFTs can facilitate access operations in conjunction with the circuitry layer. Figures 7A-7D The socket region including a set of vertical TFTs is depicted as an illustrative example, but the present disclosure is not so limited, e.g., the socket region can include other kinds of TFTs described herein or any combination thereof. Moreover, Figures 3A-3L Aspects of fabrication techniques and operations of vertical TFTs are described in

[0201] Figure 7A A top view 700 of an array layer including an active array region and two socket regions each including a set of TFTs is illustrated. In some cases, the active array region can include a set of memory cell levels fabricated within a composite stack 705. As described herein, a set of TFTs can also be fabricated in the socket regions of the composite stack 705. In some cases, the set of TFTs can include vertical TFTs as described in reference to Figures 3A-3L The vertical TFTs described. As such, each TFT of the set of TFTs can include a conductive plug 796 (e.g., in reference to Figure 3LThe conductive plugs 396) described. The TFT set can further include a first TFT subset (e.g., TFT 735-a, TFT 735-c) and a second TFT subset (e.g., TFT 735-b, TFT 735-d). In some cases, the first TFT subset (e.g., TFT 735-a) can be configured to couple a first node (e.g., a select node) of a circuitry layer (e.g., a row decoder 120 built in the substrate 204) with one or more array electrodes 750 (which can also be referred to as electrodes, access lines, word lines, or bit lines). Additionally or alternatively, the second TFT subset (e.g., TFT 735-b) can be configured to couple a second node (e.g., a inhibit node) of the circuitry layer with one or more array electrodes 750.

[0202] Further, in some cases, the first TFT subset and the second TFT subset can be built differently based on their operational characteristics. For example, the first TFT subset (e.g., TFTs for selection) can be built to provide a suitable drive current amount, and the second TFT subset (e.g., TFTs for inhibition) can be built to provide an acceptable leakage current (e.g., limit the leakage current to an acceptable amount). In some cases, the second TFT subset can be built using relatively simpler processing steps (e.g., associated with a smaller number of processing steps than the first TFT subset) or built to facilitate lower voltage operation (e.g., configured to support a lower supply voltage than the first TFT subset). In some cases, the first TFT subset and the second TFT subset can be different types of TFTs (e.g., n-type TFTs, p-type TFTs). In some cases, a base terminal (e.g., a fourth terminal of a base of a TFT described) can be incorporated into the composite stack 705 such that the base terminal can facilitate controlling a threshold voltage of the TFT. Figure 5N

[0203] In some cases, the two socket regions shown in the top-down view 700 can account for socket regions associated with word lines (which can also be referred to as a first type of access lines). The array electrodes 750 can correspond to electrodes (e.g., word lines) at a first layer (e.g., a Dl layer of the stack 305) of the composite stack. In other cases, the two socket regions shown in the top-down view 700 can account for socket regions associated with bit lines (which can also be referred to as a second type of access lines). As such, the array electrodes 750 can instead correspond to electrodes (e.g., bit lines) at a third layer (e.g., a D2 layer of the stack 305). Memory cells associated with array electrodes (e.g., word lines, first type of access lines, bit lines, second type of access lines) can be built at a second layer (e.g., a DM layer of the stack 305).

[0204] ​Top-down view 700 also depicts that a first array electrode (e.g., electrode 750-a) can be split into two or more array electrodes (e.g., electrode 750-al, electrode 750-a2) using one or more via cavities (e.g., via cavity 742-a). Further, a second array electrode (e.g., electrode 750-b) can be split into two or more array electrodes (e.g., electrode 750-bl, electrode 750-b2) using one or more via cavities (e.g., via cavity 742-b). In some cases, the first array electrode and the second array electrode can have been constructed using a set of vias (e.g., vias positioned between electrode 750-a and electrode 750-b). In this way, a first array electrode (e.g., electrode 750-al) can be coupled with a first group of two TFTs (e.g., TFT 735-al, TFT 735-bl) and a second array electrode (e.g., electrode 750-bl) can be coupled with a second group of two TFTs (e.g., TFT 735-cl, TFT 735-dl). In some cases, a TFT (e.g., TFT 735-al, TFT 735-bl) can be coupled with an electrode (e.g., electrode 750-al) at a point (e.g., a midpoint within a center region, a center point) between two ends of the electrode. Similarly, a TFT (e.g., TFT 735-cl, TFT 735-dl) can be coupled with an electrode (e.g., electrode 750-bl) between two ends of the electrode (e.g., a midpoint within a center region, a center point).

[0205] In some cases, a first electrode segment (e.g., electrode 750-b2) can be located at a layer of a layer level (e.g., Dl layer) and be shorter than an electrode (e.g., electrode 750-al), where the electrode can be a first type of access line (e.g., a word line) and extend along a first direction at the layer of the layer level, and where a conductive plug (e.g., conductive plug 796-b) can be located between the electrode and the first electrode segment. In some cases, a second access line of the first type (e.g., electrode 750-bl) can extend along the first direction at the layer of the layer level, where the second access line (e.g., electrode 750-bl) can be coaxial with the first electrode segment (e.g., electrode 750-b2). In some cases, a second electrode segment (e.g., electrode 750-a2) can be located at the layer of the layer level and be shorter than the electrode (e.g., electrode 750-al), where the second electrode segment can be coaxial with the electrode.

[0206] Thus, the TFT group can facilitate access operations (e.g., read operations, write operations) to memory cells associated with array electrodes in the active array region. For example, when TFT 735-al is activated, a select node of the circuitry layer (e.g., a row decoder 120 constructed in substrate 204) can be coupled with electrode 750-al (and thus the memory cells associated with electrode 750-al) to perform an access operation. Additionally or alternatively, other TFTs (e.g., TFT 735-d) can be activated to couple a suppression node to a subset of array electrodes (e.g., electrodes including electrode 750-bl that are not selected during the access operation) to maintain a leakage current level associated with the unselected memory cells below an acceptable threshold during the access operation.

[0207] Figure 7A FIGS. 7A and 7B illustrate top views of socket regions each including a group of TFTs. Top view 700-a can be a portion of a word line socket region including array electrodes (e.g., electrodes 750-c in Dl layer of composite stack 705) that can correspond to word lines extending along a first direction. Further, top view 700-a depicts a group of TFTs (e.g., TFT 735-aa, TFT 735-bb) including conductive plugs (e.g., conductive plugs 796-c). As described herein, TFT 735-aa can be coupled with a select node of the circuitry layer and TFT 735-bb can be coupled with a suppression node of the circuitry layer.

[0208] Similarly, top view 700-b can be a portion of a bit line socket region including array electrodes (e.g., electrodes 751 in D2 layer of composite stack 705) that can correspond to bit lines extending along a second direction (e.g., a second direction substantially orthogonal to the first direction). Further, top view 700-b depicts a group of TFTs (e.g., TFT 735-ee, TFT 735-ff) including conductive plugs (e.g., conductive plugs 796-e). As described herein, TFT 735-ee can be coupled with a select node of the circuitry layer and TFT 735-ff can be coupled with a suppression node of the circuitry layer.

[0209] In some cases, a socket region of the array layer can include a first socket region (e.g., a socket region associated with a word line) including a conductive plug (e.g., conductive plug 796-c), where an electrode (e.g., electrode 750-c) can include a first type of access line (e.g., a word line) extending into the first socket region. In some cases, a socket region of the array layer can include a second socket region (e.g., a socket region associated with a bit line) including a second conductive plug (e.g., conductive plug 796-e), where a second electrode (e.g., electrode 751-a) can include a second type of access line (e.g., a bit line) extending into the second socket region.

[0210] Figure 7B An overhead view 701 of a socket region and another overhead view 702 of vertical TFTs that can be included in a socket region. The overhead view 701 depicts a set of array electrodes 750, a set of gate electrodes 760 (which can be a reference Figures 3A-3L described example of gate electrodes 360), a set of via cavities 742, and a set of TFTs 735, where each TFT 735 is in contact with a respective conductive plug 796. In some cases, the overhead view 701 can be a variation of the socket region depicted in the overhead view 700.

[0211] For example, a subset of TFTs (e.g., a group of two TFTs) can be offset from the remaining TFTs, e.g., TFT 735-e1 and TFT 735-e2 are offset relative to TFT 735-e3 and TFT 735-e4. As a result of the offsetting of the subset of TFTs in a zig-zag pattern, the distance between conductive plugs in the socket depicted in the overhead view 701 (e.g., the distance between conductive plug 796-e2 and conductive plug 796-e3) can be greater than the corresponding distance in the socket depicted in the overhead view 700. This increase in distance can facilitate improved results during photolithography steps. In some cases, each TFT (e.g., instead of a group of two TFTs) can be offset from adjacent TFTs such that the minimum distance between conductive plugs can be the diagonal distance between two conductive plugs. For example, although the overhead view 701 illustrates an example in which the TFTs are offset in pairs (zig-zag) (pairs of TFTs are offset from each other), it should be understood that any number of other offset patterns are possible, including configurations in which each TFT within a socket region is offset from every adjacent (immediately adjacent) TFT within the socket region.

[0212] In some cases, a socket region can include a first gate electrode (e.g., gate electrode 760-b) that can surround a conductive plug (e.g., conductive plug 796-e3, conductive plug 796-e4) and a second gate electrode (e.g., gate electrode 760-a) that can surround a first additional conductive plug (e.g., conductive plug 796-e5) that extends through the set of layers and a second additional conductive plug (e.g., conductive plug 796-e2) that extends through the set of layers, where an electrode (e.g., electrode 750-e, electrode 750-f) can extend between the first additional conductive plug and the second additional conductive plug.

[0213] The top-down view 702 of a vertical TFT can depict a variation of the vertical TFT depicted in the top-down view 700. For example, the gate electrode 760-c can be configured to encompass more than one conductive plug (e.g., four conductive plugs 796-f1 through 796-f4). Thus, a vertical TFT can generate a drive current that can be nearly four (4) times greater than a drive current that can be generated by an individual TFT (e.g., TFT 735-a1, TFT 735-c1 shown in the top-down view 700). Other features of the vertical TFT in the top-down view 702 have been omitted for clarity.

[0214] Figure 7C An example schematic cross-sectional side view 703 of an array layer including eight (8) memory cell levels is illustrated. In some cases, the eight (8) memory cell levels can include five (5) groups of word lines each can extend along a first direction (e.g., the x-direction) and four (4) groups of bit lines each can extend along a second direction (e.g., the z-direction). A memory cell level (which is depicted as a cross-hatched rectangle in the cross-sectional side view 703) can be positioned between a sub-group of word lines (e.g., WL1) and a sub-group of bit lines (e.g., BL1). Some access lines (e.g., word lines, bit lines) can be shared by more than one memory cell level. For example, WL2 can be shared by two memory cell levels (i.e., a first memory cell level positioned between WL2 and BL1 and a second memory cell level positioned between WL2 and BL2). Similarly, BL4 can be shared by two memory cell levels (i.e., a third memory cell level positioned between BL4 and WL4 and a fourth memory cell level positioned between BL4 and WL5).

[0215] The cross-sectional side view 703 illustrates various layers of the composite stack 705. For example, the cross-sectional side view 703 depicts five (5) first layers 715 each can include a sub-group of word lines (e.g., WL1) (e.g., see the description of the D1 layers, layers 315) referenced by the dashed lines, eight (8) second layers 720 each can include a memory cell level (e.g., see the description of the DM layers, layers 320) referenced by the dashed lines, and four (4) third layers 725 each can include a sub-group of bit lines (e.g., BL1) (e.g., see the description of the D2 layers, layers 325) referenced by the dashed lines. Figure 3A The cross-sectional side view 703 illustrates various layers of the composite stack 705. For example, the cross-sectional side view 703 depicts five (5) first layers 715 each can include a sub-group of word lines (e.g., WL1) (e.g., see the description of the D1 layers, layers 315) referenced by the dashed lines, eight (8) second layers 720 each can include a memory cell level (e.g., see the description of the DM layers, layers 320) referenced by the dashed lines, and four (4) third layers 725 each can include a sub-group of bit lines (e.g., BL1) (e.g., see the description of the D2 layers, layers 325) referenced by the dashed lines. Figure 3A The cross-sectional side view 703 illustrates various layers of the composite stack 705. For example, the cross-sectional side view 703 depicts five (5) first layers 715 each can include a sub-group of word lines (e.g., WL1) (e.g., see the description of the D1 layers, layers 315) referenced by the dashed lines, eight (8) second layers 720 each can include a memory cell level (e.g., see the description of the DM layers, layers 320) referenced by the dashed lines, and four (4) third layers 725 each can include a sub-group of bit lines (e.g., BL1) (e.g., see the description of the D2 layers, layers 325) referenced by the dashed lines. Figure 3A The cross-sectional side view 703 illustrates various layers of the composite stack 705. For example, the cross-sectional side view 703 depicts five (5) first layers 715 each can include a sub-group of word lines (e.g., WL1) (e.g., see the description of the D1 layers, layers 315) referenced by the dashed lines, eight (8) second layers 720 each can include a memory cell level (e.g., see the description of the DM layers, layers 320) referenced by the dashed lines, and four (4) third layers 725 each can include a sub-group of bit lines (e.g., BL1) (e.g., see the description of the D2 layers, layers 325) referenced by the dashed lines.

[0216] Figure 7C A cross-sectional side view 704 of a socket region of an array layer is also illustrated. The cross-sectional side view 704-a can correspond to a cross-sectional side view of a word line socket region across the dashed line AA as shown in the top-down view 700-a referenced Figure 7A The cross-sectional side view 704-a can correspond to the composite stack 705 and illustrates five (5) array electrodes 750 (e.g., array electrodes 750-f1 through 750-f5 at the D1 layers, which can be referred to as word lines or a first type of access line).

[0217] Cross-sectional side view 704-a also depicts conductive plugs (e.g., conductive plug 796-c, conductive plug 796-d) that can each be coupled with a conductive element (e.g., conductive element 785-al, conductive element 785-bl). Each conductive element can be coupled with a node (e.g., a select node, an inhibit node) of a circuitry layer (e.g., a word line select driver, a word line inhibit driver). Cross-sectional side view 704-a also depicts eight (8) pairs of gate electrodes (e.g., a pair of gate electrodes at each layer 720), where each gate electrode encloses a conductive electrode (e.g., conductive plug 796-c, conductive plug 796-d). As such, cross-sectional side view 704-a depicts a total of sixteen (16) TFTs. Further, cross-sectional side view 704-a illustrates a current path 745-a that can be activated by a TFT group of the word line socket region such that drive current can flow between conductive element 785 and word line 750 during an access operation.

[0218] Similarly, cross-sectional side view 704-b can correspond to a cross-sectional side view of the bit line socket region across dashed line BB, as shown in plan view 700-b described with reference to Figure 7A Cross-sectional side view 704-b also can correspond to composite stack 705 and illustrates four (4) array electrodes 751 (e.g., array electrodes 751-cl to 751-c4 at the D2 layer, which can be referred to as bit lines or a second type of access line). Cross-sectional side view 704-b also depicts conductive plugs (e.g., conductive plug 796-e, conductive plug 796-f) that can each be coupled with a conductive element (e.g., conductive element 785-a2, conductive element 785-b2). Each conductive element can be coupled with a node (e.g., a select node, an inhibit node) of a circuitry layer (e.g., a bit line select driver, a bit line inhibit driver). Cross-sectional side view 704-b also depicts eight (8) pairs of gate electrodes (e.g., a pair of gate electrodes at each layer 720), where each gate electrode encloses a conductive electrode (e.g., conductive plug 796-e, conductive plug 796-f). As such, cross-sectional side view 704-b also depicts a total of sixteen (16) vertical TFTs. Further, cross-sectional side view 704-b illustrates a current path 745-b that can be activated by a TFT group of the bit line socket region such that drive current can flow between conductive element 785 and bit line 751 during an access operation.

[0219] In some cases, a socket region of a memory device (e.g., with reference to Figure 7CThe described line socket region) can include a set of conductive plugs (e.g., conductive plug 796-c) extending through a set of memory cell levels and a set of transistors (e.g., eight (8) vertical TFTs in the word line socket region) each at least partially surrounding a conductive plug. In some cases, the memory device can include a driver (e.g., word line select driver) coupled with the conductive plugs and configured to selectively couple with an electrode (e.g., word line 750-f1) included in a level of the set of levels through a transistor of the set of transistors. In some cases, a second socket region (e.g., reference Figure 7C The described bit line socket region) can include a second set of conductive plugs (e.g., conductive plug 796-e) extending through a set of levels, a second set of transistors (e.g., eight (8) vertical TFTs in the bit line socket region) each at least partially surrounding a conductive plug of the second set of conductive plugs, and a second driver (e.g., bit line select driver) coupled with the second set of conductive plugs and configured to selectively couple with a second electrode (e.g., bit line 751-c1) included in a level through a transistor of the second set of transistors.

[0220] In some cases, an electrode (e.g., word line 750-f1) can be located at a first level (e.g., layer 715 of the composite stack 705) and the socket region can further include a gate electrode (e.g., gate electrode 760-a) for a transistor at a second level (e.g., layer 720 of the composite stack 705) of the level, where the gate electrode at least partially surrounds a conductive plug. In some cases, the vertical TFTs of the socket region can be configured to include a gate electrode (e.g., reference Figure 7B The described gate electrode 760-c) surrounds a set of conductive plugs (e.g., reference Figure 7B The described conductive plug 796-f1 of 796-f4), where the set of conductive plugs can include a conductive plug (e.g., conductive plug 796-c).

[0221] In some cases, a socket region (e.g., a word line socket region) can include a third conductive plug (e.g., conductive plug 796-d) extending through the set of tiers and a third set of transistors (e.g., eight (8) TFTs within the word line socket region) each at least partially surrounding the third conductive plug. In some cases, the memory device can include a third driver coupled with the third conductive plug and configured to selectively couple with a first type of access line included in a subset of tiers of the set through a subset of transistors of the third set. In some cases, a socket region (e.g., a bit line socket region) can include a fourth conductive plug (e.g., conductive plug 796-f) extending through the set of tiers and a fourth set of transistors (e.g., eight (8) TFTs within the bit line socket region) each at least partially surrounding the fourth conductive plug. In some cases, the memory device can include a fourth driver coupled with the fourth conductive plug and configured to selectively couple with a second type of access line included in a subset of tiers of the set through a subset of transistors of the fourth set.

[0222] Figure 7D Description with reference to Figure 7C The described array layer circuit diagrams 738 and schematic cross-sectional side views 703. Circuit diagram 738-a can correspond to a word line socket region including sixteen (16) TFTs described with reference to cross-sectional side view 704-a. Similarly, circuit diagram 738-b can correspond to a bit line socket region including sixteen (16) TFTs described with reference to cross-sectional side view 704-b. Both circuit diagrams 738 depict n-type TFTs for illustration, but the present disclosure is not so limited, e.g., the circuit diagrams 738 can include n-type TFTs, p-type TFTs, or any combination thereof. Further, the gates of the TFTs in circuit diagrams 738 can indicate activation or deactivation of the TFTs, e.g., the gates of the TFTs depicted as gray rectangles indicate that a first gate voltage (e.g., Von) applied to the gates to activate the TFTs is greater than a threshold voltage of the TFTs, the gates of the TFTs depicted as white rectangles indicate that a second gate voltage (e.g., Voff) applied to the gates to deactivate the TFTs is less than the threshold voltage of the TFTs.

[0223] Circuit diagram 738-a also depicts each of the first and second conductive plugs 796-a, 796-b, respectively, as a white rectangle. Circuit diagram 738-b depicts each of the first and second conductive plugs 796-c, 796-d, respectively, as a white rectangle. Circuit diagram 738-b also depicts each of the third and fourth conductive plugs 796-e, 796-f, respectively, as a white rectangle. Figure 7CThe common nodes 797 (e.g., nodes 797-c to 797-f) of the TFTs of the conductive plug 796 are described. In some cases, the common nodes can correspond to the source (or drain) of the TFTs. For example, the common node 797-c corresponds to the conductive plug 796-c coupled with the conductive element 785-al. The conductive element 785-al can be coupled with a node of a driver (e.g., a select node of the word line select driver 736-a). Similarly, the common node 797-d corresponds to the conductive plug 796-d coupled with the conductive element 785-bl. The conductive element 785-bl can be coupled with a node of a driver (e.g., a inhibit node of the word line inhibit driver 737-a). Further, the common node 797-e corresponds to the conductive plug 796-e coupled with the conductive element 785-a2. The conductive element 785-a2 can be coupled with a node of a driver (e.g., a select node of the bit line select driver 736-b). Similarly, the common node 797-f corresponds to the conductive plug 796-f coupled with the conductive element 785-b2. The conductive element 785-b2 can be coupled with a node of a driver (e.g., a inhibit node of the bit line inhibit driver 737-b). It should be appreciated by one skilled in the art that select drivers (e.g., the word line select driver 736-a, the bit line select driver 736-b) and inhibit drivers (e.g., the word line inhibit driver 737-a, the bit line inhibit driver 737-b) can perform different functions (e.g., the word line select driver 736-a performs an inhibit function, the word line inhibit driver 737-a performs a select function) based on access operations of a memory cell or memory technology (e.g., self-selecting memory, FeRAM, CBRAM).

[0224] Figure 7D The TFTs in the word line socket region (e.g., the circuit diagram 738-a) and the TFTs in the bit line socket region (e.g., the circuit diagram 738-b) are described to facilitate access operations (e.g., read operations, write operations) at the level of the memory cells. For example, an access command can access a memory cell located at the sixth memory cell level between BL3 and WL4 (e.g., a memory cell located at the second level 720-f), as indicated in the cross-sectional side view 703. The corresponding BL3 and WL4 in the circuit diagram 738 (e.g., depicted as bolded lines) are highlighted to indicate which TFTs can be activated.

[0225] In some cases, WL4 in circuit diagram 738-a can be coupled to a select node of word line select driver 736-a by activating TFTs above WL4 (e.g., applying Von to gate electrode 760-c6) or activating TFTs below WL4 (e.g., applying Von to gate electrode 760-c7) or both. Similarly, BL3 in circuit diagram 738-b can be coupled to a select node of bit line select driver 736-b by activating TFTs above BL3 (e.g., applying Von to gate electrode 760-d5) or activating TFTs below BL3 (e.g., applying Von to gate electrode 760-d6) or both. In some cases, a driver (e.g., word line select driver 736-a, bit line select driver 736-b) can be configured to selectively couple to an electrode (e.g., word line, bit line) by at least two transistors of a group (e.g., two TFTs in a word line socket region, two TFTs in a bit line socket region).

[0226] Additionally or alternatively, TFTs coupled to the inhibit node of word line inhibit driver 737-a (e.g., TFTs coupled to common node 797-d) can be activated or deactivated (e.g., six TFTs are activated and two TFTs are deactivated, as depicted in circuit diagram 738-a) such that the activated TFTs can couple unselected word lines (e.g., WL1, WL2, WL3, WL5) to the inhibit node of word line inhibit driver 737-a. Similarly, TFTs coupled to the inhibit node of bit line inhibit driver 737-b (e.g., TFTs coupled to common node 797-f) can be activated or deactivated (e.g., six TFTs are activated and two TFTs are deactivated, as depicted in circuit diagram 738-b) such that the activated TFTs can couple unselected bit lines (e.g., BL1, BL2, BL4) to the inhibit node of bit line inhibit driver 737-b. In this way, interference due to unselected word lines or bit lines can be mitigated during an access operation.

[0227] In some cases, a pair of gates of a TFT can be configured to electrically connect (e.g., short) during decoding of an access command such that two TFTs (rather than one TFT) can provide greater current driving capability to a selected memory cell tier. For example, a first subset of access lines (e.g., WL2, WL3, WL4) can be driven by a pair of TFTs rather than a single TFT. Such a pair of TFTs can be positioned above and below an access line (e.g., word line, bit line) and can be activated by a single control signal (e.g., Von) applied to a single gate electrode (e.g., gate electrode 760-c6, gate electrode 760-c7, gate electrode 760-d5, gate electrode 760-d6). Figure 7DSeveral instances of TFT pairs are illustrated using double arrows with gray lines. In some cases, some gates of TFTs (e.g., gate electrode 760-c1, gate electrode 760-c8) can lack an adjacent gate to provide greater current driving capability. In such cases, a second subset of access lines (e.g., WL1, WL5) can be driven by a single TFT rather than a pair of TFTs. This configuration (e.g., selectively connecting two TFTs above and below an access line) can be implemented in crossover regions as described with reference to Figure 10A and 10B .

[0228] Figures 8A-8C FIGS. 1-3 illustrate various aspects of a memory array and associated circuitry in accordance with embodiments of the present disclosure. Figures 8A-8C Various aspects of a socket region in which a group of TFTs can be concurrently constructed within a composite stack 805 (e.g., one or more vertically integrated composite stacks 305 described with reference to Figures 3A-3L are described as described herein. Figures 8A-8C A top view (e.g., a layout of a socket region) including a portion of a socket region to illustrate that a subset of a group of TFTs can be configured to couple with a subset of array electrodes (e.g., access lines, word lines, bit lines) of an active array region in which memory cells are positioned.

[0229] Additionally, Figures 8A-8C A cross-sectional side view including different portions of a socket region to illustrate that a group of TFTs can couple array electrodes with circuitry layers (e.g., row decoders 120 constructed in substrate 204). In some cases, a circuitry layer can be a portion of a substrate above which an array layer is positioned. Moreover, Figures 8A-8C A group of TFTs described in FIGS. 1-3 can operate during access operations in accordance with a circuit representation of a group of TFTs described with reference to Figures 7A-7D . Figures 8A-8C A socket region including a group of surround TFTs is depicted as an illustrative example, but the present disclosure is not so limited, e.g., a socket region can include other kinds of TFTs described herein or any combination thereof. Figures 5A-5N Aspects of manufacturing techniques and operations of surround TFTs are described in FIGS. 4-6.

[0230] Figure 8AA top view 801 of a socket region including two sets of wraparound TFTs is also illustrated. The top view 801 can be a portion of a word line socket region that includes array electrodes (e.g., electrodes 850-a in the D1 layer of the composite stack 805) that can correspond to word lines. In addition, the top view 801 depicts a first conductive plug 896-a and a second conductive plug 896-b. In some cases, the first conductive plug can be coupled with a first node of a first driver (e.g., a select node of a word line select driver) and the second conductive plug can be coupled with a second node of a second driver (e.g., a inhibit node of a word line select driver). The top view 801 also depicts gate electrodes 860 at the second layer of the composite stack 805 (e.g., gate electrode 860-a including electrode material 861-a, gate electrode 860-b including electrode material 861-b).

[0231] In some cases, an electrode (e.g., electrode 850-a) can include a first portion (e.g., electrode tab 855-a) extending in a first direction between a conductive plug (e.g., conductive plug 896-a) and a second conductive plug (e.g., conductive plug 896-b), a second portion (e.g., electrode 850-a1) extending in a second direction coupled with an end of the first portion, and a third portion (e.g., electrode 850-a2) extending in the second direction coupled with a second end of the first portion. In some cases, the first portion (e.g., electrode tab 855-a) can be wider than the second portion (e.g., electrode 850-a1) and the third portion (e.g., electrode 850-a2).

[0232] Figure 8A A cross-sectional side view 802 of a socket region of an array layer is also illustrated. The cross-sectional side view 802-a can correspond to a cross-sectional side view of a word line socket region across the dashed line AA as shown in the top view 801. For clarity, the cross-sectional side view 802-a omits dielectric plugs, e.g., dielectric plugs between the conductive plug 896-a and the conductive plug 896-b, dielectric plugs surrounded by gate electrodes. The cross-sectional side view 802-a illustrates a composite stack 805 including five (5) array electrodes (e.g., word lines, array electrodes including electrode tab 855 at layer 815).

[0233] Cross-sectional side view 802-a also depicts conductive plugs (e.g., conductive plugs 896-a) that can each be coupled with a conductive element (e.g., conductive element 855-al). The conductive plugs can act as a common node (e.g., source or drain) for a TFT group. Each conductive element can be coupled with a node (e.g., select node, inhibit node) of a circuitry layer (e.g., word line select driver, word line inhibit driver). Cross-sectional side view 802-a also depicts eight (8) pairs of gate electrodes (e.g., one pair of gate electrodes at each layer 820). Thus, cross-sectional side view 802-a depicts a total of sixteen (16) surround TFTs. Further, cross-sectional side view 802-a illustrates a current path 845-a that can be activated by a TFT group of a word line socket region such that drive current can flow between conductive element 885 and word line 850 during an access operation.

[0234] Similarly, cross-sectional side view 802-b can correspond to a cross-sectional side view of a bit line socket region. A top view of a bit line socket region can be identical to top view 801 depicting a word line socket region except that a top view of a bit line socket region can be rotated about 90° with respect to top view 801 depicting a word line socket region (as bit lines can extend along a direction that can be substantially orthogonal to word lines). Cross-sectional side view 802-b can also correspond to composite stack 805 and illustrate four (4) array electrodes (e.g., bit lines, including electrode patches 856 at layer 825).

[0235] Cross-sectional side view 802-b also depicts conductive plugs (e.g., conductive plugs 896-c) that can each be coupled with a conductive element (e.g., conductive element 855-a2). Each conductive element can be coupled with a node (e.g., select node, inhibit node) of a circuitry layer (e.g., bit line select driver, bit line inhibit driver). Cross-sectional side view 802-b also depicts eight (8) pairs of gate electrodes (e.g., one pair of gate electrodes at each layer 820). Thus, cross-sectional side view 802-b also depicts a total of sixteen (16) surround TFTs. Further, cross-sectional side view 802-b illustrates a current path 845-b that can be activated by a TFT group of a bit line socket region such that drive current can flow between conductive element 885 and bit line 851 (e.g., bit line including electrode 856 at layer 825) during an access operation.

[0236] In some cases, a socket region of a memory device (e.g., refer to FIG. 1) can include a composite stack (e.g., composite stack 805) that can include a plurality of layers (e.g., layers 820). Each layer can include a plurality of electrodes (e.g., electrodes 856). Each electrode can be coupled with a conductive element (e.g., conductive element 855-a2). Each conductive element can be coupled with a node (e.g., select node, inhibit node) of a circuitry layer (e.g., bit line select driver, bit line inhibit driver). Each conductive element can be coupled with a conductive plug (e.g., conductive plug 896-c). Each conductive plug can be coupled with a common node (e.g., source or drain) of a TFT group. Figure 8AThe depicted line socket region) can include a conductive plug (e.g., conductive plug 896-a) extending through a set of memory cell levels and a set of transistors (e.g., wrap-around TFTs that can be coupled with a select node) each having a source or drain in contact with the conductive plug. In some cases, the memory device can include a driver (e.g., a word line select driver) coupled with the conductive plug and configured to selectively couple with an electrode (e.g., word line 850) included in a level of the set of levels through a transistor of the set of transistors.

[0237] In some cases, the socket region can include a second conductive plug (e.g., conductive plug 896-b) extending through a set of levels and a second set of transistors (e.g., wrap-around TFTs that can be coupled with an inhibit node) each having a source or drain in contact with the conductive plug. In some cases, the memory device can include a second driver (e.g., a word line inhibit driver) coupled with the second conductive plug and configured to selectively couple with a first type of access line included in a subset of levels of the set of levels through a subset of transistors of the second set.

[0238] In some cases, the socket region can include a first set of gate electrodes (e.g., gate electrodes 860-a) of a set of transistors (e.g., wrap-around TFTs that can be coupled with a select node) and a second set of gate electrodes (e.g., gate electrodes 860-b) of a second set of transistors (e.g., wrap-around TFTs that can be coupled with an inhibit node), where a conductive plug (e.g., conductive plug 896-a) and a second conductive plug (e.g., conductive plug 896-b) can be located between the first set of gate electrodes (e.g., gate electrodes 860-a) and the second set of gate electrodes (e.g., gate electrodes 860-b).

[0239] Figure 8B Diagram 803-a illustrates an array level including an active array region and two socket regions (e.g., word line socket regions) each including a set of TFTs. Diagram 803-a depicts some aspects of a top view of the array level (e.g., access lines and structural features of the sets of TFTs) and omits other aspects for visual clarity. In some cases, the active array region can include a set of memory cell levels fabricated within a composite stack 805. As described herein, sets of TFTs can also be fabricated in the socket regions of the composite stack 805. In some cases, the sets of TFTs can include reference Figures 5A-5N The depicted wrap-around TFTs. The lines (e.g., electrodes of word lines) depicted in diagram 803-a are pieced together (e.g., each word line is associated with a wider portion that extends to a narrower portion into the active array region, as referenced with respect to Figure 5A and 8AThe described) to create a surround TFT architecture. For example, the wider portion of the word line extends over eight (8) word lines (e.g., eight (8) group configuration). In some cases, the TFT can be positioned substantially at the center of the word line (e.g., center tap array electrode).

[0240] Figure 803-a includes sixteen (16) word lines as an example and thus includes sixteen (16) groups of surround TFTs, i.e., eight (8) on one side of the active array area and another eight (8) on the opposite side. Further, Figure 803-a depicts an inhibit driver 837 (which can be an example of word line inhibit driver 737) which can be a word line inhibit driver. In some cases, the inhibit driver 837 can be shared by the eight (8) groups of surround TFTs. In other cases, each group of surround TFTs can be coupled with a separate inhibit driver. Figure 803-a also depicts a group of eight (8) select drivers 836 (which can be an example of word line select driver 736). Each select driver can be a word line select driver coupled with one of the eight (8) groups of surround TFTs. In some cases, the inhibit driver 837 and the group of eight (8) select drivers 836 can be positioned under (or over) the memory cell layer group. In some cases, the inhibit driver (e.g., inhibit driver 837) and the select driver (e.g., select driver 736) can perform different functions based on the access operation of the memory cell or memory technology (e.g., self-selecting memory, FeRAM, CBRAM) (e.g., inhibit driver 837 performs a select function, select driver 736 performs an inhibit function).

[0241] Figure 803-a also includes a common level select line 846 and a common level inhibit line 847 that can control the gate electrodes of the surround TFTs, such as the gate electrodes 860 at the layer 820 within the composite stack 805. The common level select line 846 can be configured to couple (e.g., short) all of the gate electrodes of the surround TFTs associated with the select signal for the level, such as the surround TFTs configured to couple with the select node of the word line select driver. Further, the common level select line 846 can be coupled with a first common gate driver positioned below (or above) the group of memory cell levels. Similarly, the common level inhibit line 847 can be configured to couple (e.g., short) all of the gate electrodes of the surround TFTs associated with the inhibit signal for the level, such as the surround TFTs configured to couple with the inhibit node of the word line inhibit driver. Further, the common level inhibit line 847 can be coupled with a second common gate driver positioned below (or above) the group of memory cell levels. In some cases, the common gate drivers, which can be referred to as level select drivers, can be positioned in a location different from the socket region. In some cases, the common gate drivers can be shared between a group of socket regions, where a portion of the memory array includes a group of socket regions and one or more active array regions. In some cases, the socket region can include a group of gate electrodes, such as the gate electrodes 860, that are included in a level and coupled with each other (e.g., common level select line 846, common level inhibit line 847) and with a common gate driver below (or above) the group of memory cell levels. In some cases, the group of gate electrodes includes the gate electrodes of transistors, such as the surround TFTs in the socket region.

[0242] Figure 8CFigure 803-b illustrates an array layer including an active array region and two socket regions (e.g., word line socket regions) each including a set of TFTs. Figure 803-b depicts aspects of a top view of the array layer, such as access lines and structural features of the set of TFTs (e.g., wrap-around TFTs). Figure 803-b includes a word line select driver 836-a (which can be an example of the word line select driver 736-a) and a word line inhibit driver 837-a (which can be an example of the word line inhibit driver 737-a). Additionally, Figure 803-b depicts a decoder circuitry 876. In some cases, the word line select driver 836-a, the word line inhibit driver 837-a, and the decoder circuitry 876 can be located below (or above) the set of memory cell levels. In comparison to Figure 803-a, Figure 803-b can depict an alternative configuration for controlling gate electrodes of wrap-around TFTs (e.g., gate electrodes 860 at layer 820 within the composite stack 805). For example, instead of coupling all gate electrodes of the wrap-around TFTs (e.g., using the common level select line 846 and the common level inhibit line 847 described with reference to Figure 803-a), the decoder circuitry 876 can be configured to decode control signals for each gate electrode. In the example depicted in Figure 803-b, each of the sixty-four (64) TFTs in the two socket regions can be coupled with a driver of a gate electrode. In some cases, a memory device including socket regions can include decoder circuitry located below the set of levels and configured to activate a transistor based on a gate electrode included in the set of gate electrode select transistors.

[0243] Figure 9 Figure 900 illustrates a diagram of an exemplary decoding scheme supporting memory array decoding and interconnects, in accordance with an embodiment of the present disclosure. The TFT-based decoder circuitry depicted in Figure 900 can be constructed within a composite stack (e.g., composite stack 305, composite stack 705, composite stack 805). Such decoder circuitry constructed within a composite stack can perform at least a portion of the decoding functions that can otherwise be performed by a logic circuitry layer. For example, the decoder circuitry can perform additional functions in addition to selecting a level from a set of memory cell levels. In some cases, a logic circuitry layer can be located within a substrate over which a set of memory cell levels can be constructed. In this way, the logic circuitry within the substrate can be simplified to reduce an area corresponding to the logic circuitry or can support additional memory array levels.

[0244] Figure 900 depicts decoder circuitry that can include planar TFTs for illustration, but the present disclosure is not so limited, e.g., the decoder circuitry within a composite stack can include other types of TFTs described herein or any combination thereof. Figures 4A-4AAAspects of a manufacturing technique and operation of planar TFTs are described. Further, the diagram 900 depicts a single-ended driver scheme, e.g., the TFTs provide a drive current to an access line (e.g., word line) positioned at an end of the access line. Those skilled in the art will appreciate that different driver schemes (e.g., the TFTs provide a drive current positioned between two ends of the access line) or more complex driver circuitry can be used without loss of any functionality.

[0245] The diagram 900 depicts a cluster of levels (e.g., a cluster 967 including eight (8) levels (i.e., level 966-a through level 966-h)) stacked on top of one another, where each level can include one or more tiles. The diagram 900 depicts a set of TFTs to perform a decode within a tile, e.g., to activate an access line (e.g., word line) from a set of access lines (e.g., eight (8) word lines) within a tile. In the context of the decoder circuitry described herein, a cluster can refer to a group of tiles, and a tile can refer to an array decode unit. Further, the diagram 900 depicts a select driver 936 (which can be an example of the word line select driver 736-a) and an inhibit driver 937 (which can be an example of the word line inhibit driver 737-a). In some cases, the select driver 936 and the inhibit driver 937 can be positioned within a logic circuitry layer.

[0246] In some cases, an electrode layer (e.g., a layer including access lines (e.g., word lines and bit lines)) within a level (e.g., level 966-a through level 966-h) can include a first set of TFTs providing control signals for gates of a second set of TFTs (e.g., pairs of TFTs coupled with word lines, as shown in Figure 9 In some cases, an electrode layer (e.g., a layer including access lines (e.g., word lines and bit lines)) within a level (e.g., level 966-a through level 966-h) can include a first set of TFTs providing control signals for gates of a second set of TFTs (e.g., pairs of TFTs coupled with word lines, as shown in

[0247] For example, the diagram 900 depicts that the decoder circuitry can perform one of eight (8) decodes within a tile within a level 966 (e.g., level 966-a through level 966-h), e.g., one of eight pairs of TFTs (e.g., two TFTs in a series configuration) can be activated to activate one of eight access lines (e.g., word lines) within a tile. Further, the diagram 900 depicts that the decoder circuitry can perform one of sixty-four (64) decodes in conjunction with a level-level decoder that can perform level-level decoding, e.g., the level-level decoder can select (or activate) one of eight levels (e.g., one of level 966-a through level 966-h) within the cluster 967.

[0248] Figure 10A and 10B A diagram illustrating exemplary crossover regions supporting memory array decoding and interconnects in accordance with embodiments of the present disclosure is illustrated.

[0249] Figure 10AFigure 1000 depicts a top view of an array layer including active array regions (e.g., active array 1055-a through active array 1055-d) and socket regions (e.g., socket region 1065, socket region 1066) in which TFT groups can be constructed, as described herein. Figure 1000 can include references Figure 1 some aspects of the described example of memory device 100. In some cases, Figure 1000 can be part of a 3D memory device that includes two or more memory cell levels constructed within composite stack 1005, which can be a reference Figure 7C to the described example of composite stack 705, as depicted in Figure 10B some aspects of the described example of memory device 100. In some cases, Figure 1000 can be part of a 3D memory device that includes two or more memory cell levels constructed within composite stack 1005, which can be a reference Figures 3A-3L vertically oriented TFTs constructed as described herein, references Figures 4A-4AA horizontally oriented TFTs constructed as described herein, references Figures 5A-5N surrounding TFTs constructed as described herein, or references Figures 6A-6R hybrid TFTs constructed as described herein, or any combination thereof.

[0250] Furthermore, Figure 1000 depicts that active array 1055 can include a first set of access lines (e.g., word lines) of a first type extending along a first direction and a second set of access lines (e.g., bit lines) of a second type extending along a second direction that can be substantially orthogonal to the first direction. The first set of access lines can be located at a first layer (e.g., Dl layer, reference Figure 10B layer 1015) of composite stack 1005. Similarly, the second set of access lines can be located at a third layer (e.g., D2 layer, reference Figure 10B layer 1025) of composite stack 1005. Figure 1000 depicts that the first set of access lines (e.g., word lines) can cross a boundary of the active array (e.g., a boundary of active array 1055-a and active array 1055-b). Similarly, the second set of access lines (e.g., bit lines) can cross a boundary of the active array (e.g., a boundary of active array 1055-a and active array 1055-c).

[0251] Additionally, the TFTs in socket region 1065 can be configured to couple with the first set of access lines (e.g., word lines), and the TFTs in socket region 1066 can be configured to couple with the second set of access lines (e.g., bit lines). In this way, the TFTs in socket region 1065 (e.g., word line sockets) can couple nodes (e.g., select nodes, inhibit nodes) of a circuitry layer with one or more word lines of active array 1055. Similarly, the TFTs in socket region 1066 (e.g., bit line sockets) can couple nodes (e.g., select nodes, inhibit nodes) of a circuitry layer with one or more bit lines of active array 1055.

[0252] In addition, layer select lines 1070 can be defined in socket regions (e.g., socket region 1065, socket region 1066) at a second layer (e.g., DM layer, layer 1020) of the composite stack 1005. In some cases, the layer select lines 1070 can be coupled with gate electrodes of TFTs also fabricated at the second layer (e.g., DM layer, layer 1020), as described herein for various TFTs. As such, the layer select lines 1070 can be coupled with gate electrodes of TFTs and can be referred to as control lines for the gates of TFTs within the socket regions.

[0253] Layer select lines 1070 of two sets of access lines (e.g., word lines and bit lines) can be fabricated at a second layer (e.g., DM layer, layer 1020, of the composite stack 1005), and crossover regions 1075 can be defined to avoid layer select lines 1070 shorting, where two layer select lines can cross (e.g., crossover region 1075-a where layer select line 1070-a crosses layer select line 1070-d, crossover region 1075-b where layer select line 1070-b crosses layer select line 1070-d). Such crossover regions can be located at various locations based on the configuration of the active array arrangement (e.g., the fill-in architecture). As an example, the diagram 1000 depicts crossover regions at corners of the active array 1055.

[0254] Figure 10B Diagram 1001 depicts a magnified top view of a crossover region, and diagram 1002 depicts a cross-sectional side view of the crossover region across various locations within the crossover region. Diagram 1001 includes a crossover region 1075-d where a first set of layer select lines (e.g., layer select lines including layer select line 1070-f1) can cross a second set of layer select lines (e.g., layer select lines including layer select line 1070-g1). The first set of layer select lines can be associated with a word line socket (e.g., socket region 1065) and can be control lines for the gates of TFTs (e.g., TFTs configured to couple with word lines) within the word line socket. Similarly, the second set of layer select lines can be associated with a bit line socket (e.g., socket region 1066) and can be control lines for the gates of TFTs (e.g., TFTs configured to couple with bit lines) within the bit line socket.

[0255] Figure 10B Diagram 1002 also depicts a cross-sectional side view of a layer select line (e.g., layer select line 1070-f1) across the dashed lines (e.g., dashed line AA to dashed line EE turning layer select line 1070-f1 into crossover region 1075-d) shown in diagram 1001. Diagram 1002 depicts a composite stack 1005 including a first layer (e.g., D1 layer, layer 1015), a second layer (e.g., DM layer, layer 1020), and a third layer (e.g., D2 layer, layer 1025).

[0256] Cross-sectional view 1002-a through dashed line AA depicts array electrode 1050 fabricated at Dl layer (e.g., layer 1015). Dashed line AA corresponds to a word line and array electrode 1050 depicted in cross-sectional view 1002-a can be coupled with the word line. Cross-sectional view 1002-a also depicts gate electrode (e.g., gate electrode including electrode material 1061) fabricated at DM layer (e.g., layer 1020). The gate electrode depicted in cross-sectional view 1002-a can be part of layer-level select line 1070-f1 (e.g., control line for the gate of a TFT within word line socket region 1065).

[0257] Cross-sectional view 1002-b through dashed line BB depicts similar structures of cross-sectional view 1002-a except that a first portion of the crossover region including dashed line BB is absent of array electrode 1050 due to the array electrode being further away from the line depicted in cross-sectional view 1002-a.

[0258] Cross-sectional view 1002-c through dashed line CC depicts that a gate electrode (e.g., gate electrode including electrode material 1061) can be fabricated across both Dl layer (e.g., layer 1015) and DM layer (e.g., layer 1020) in a second portion of the crossover region including dashed line CC, e.g., electrode material 1061 spans across Dl layer and DM layer. In this way, a pair of inner gate electrodes (e.g., corresponding to electrode and electrode corresponding to electrode material 1061-c) can be connected (e.g., electrically shorted) as indicated by the grayed arrow.

[0259] Cross-sectional view 1002-d through dashed line DD depicts that a gate electrode (e.g., gate electrode including electrode material 1061) can be fabricated at Dl layer (e.g., layer 1015) in a third portion of the crossover region including dashed line DD. In this way, gate electrodes (e.g., control lines for the gate of a TFT within word line socket region 1065) can be converted from eight (8) gate electrodes at DM layer (e.g., layer 1020) to five (5) gate electrodes at Dl layer (e.g., layer 1015) while transitioning from the first portion of the crossover region to the third portion of the crossover region. As described herein, a pair of inner electrodes can be electrically connected during the transition. The pair of inner gate electrodes can correspond to the pair of gates of the TFT described with respect to Figure 7D circuit diagram 738-a (e.g., the pair of gates represented by the grayed arrow).

[0260] Similarly, the layer select line 1070-g1 (e.g., a control line for the gate of a TFT within the bit line sink region 1066) can be configured to have a different structural configuration through different portions of the crossover region 1075-d. In this way, the gate electrode (e.g., a control line for the gate of a TFT within the bit line sink region 1066) can transition from an eight (8) DM layer (e.g., layer 1020) gate electrode to a four (4) D2 layer (e.g., layer 1025) gate electrode within the crossover region 1075-d, e.g., such that the layer select line 1070-g1 transitions into the crossover region 1075-d along an orthogonal direction with respect to the dashed lines AA to EE. During the transition, the pair of inner gate electrodes can be electrically connected because the electrode material 1062 of the gate electrode can be configured across the DM layer (e.g., layer 1020) and the D2 layer (e.g., layer 1025), e.g., the electrode material 1062 spans the DM layer and the D2 layer at a portion of the crossover region 1075-d corresponding to a second portion of the crossover region including the dashed line CC of the layer select line 1070-f1. The pair of inner gate electrodes can correspond to the pair of gates of the TFT described with reference to the circuit diagram 738-b (e.g., the pair of gates represented by the gray arrows). Figure 7D

[0261] In this way, the cross-sectional view 1002-e across the dashed line EE depicts that the gate electrode of the layer select line 1070-f1 (e.g., a gate electrode including the electrode material 1061-a, the electrode material 1061-i, the electrode material 1061-j, the electrode material 1061-k, the electrode material 1061-h) can be configured at the layer 1015 and the gate electrode of the layer select line 1070-g1 (e.g., a gate electrode including the electrode material 1062-a, the electrode material 1062-b, the electrode material 1062-c, the electrode material 1062-d) can be configured at the layer 1025. As such, the layer select line 1070-f1 and the layer select line 1070-g1 can cross without being electrically shorted to each other.

[0262] The cross-sectional views of the diagram 1002 can also represent a cross-sectional side view of the layer select line 1070-f1 transitioning from the crossover region 1075-d. In other words, the cross-sectional view 1002-d across the dashed line DD can be the same as the cross-sectional view across the dashed line D'D'. Similarly, the cross-sectional view 1002-c across the dashed line CC can be the same as the cross-sectional view across the dashed line C'C'. Further, the cross-sectional view across the dashed line A'A' is the same as the cross-sectional view 1002-a across the dashed line AA.

[0263] In some cases, a memory device (e.g., with reference to the circuit diagram 738-b) can include a layer select line 1070-g1 (e.g., a control line for the gate of a TFT within the bit line sink region 1066) that is configured to have a different structural configuration through different portions of the crossover region 1075-d. In this way, the gate electrode (e.g., a control line for the gate of a TFT within the bit line sink region 1066) can transition from an eight (8) DM layer (e.g., layer 1020) gate electrode to a four (4) D2 layer (e.g., layer 1025) gate electrode within the crossover region 1075-d, e.g., such that the layer select line 1070-g1 transitions into the crossover region 1075-d along an orthogonal direction with respect to the dashed lines AA to EE. During the transition, the pair of inner gate electrodes can be electrically connected because the electrode material 1062 of the gate electrode can be configured across the DM layer (e.g., layer 1020) and the D2 layer (e.g., layer 1025), e.g., the electrode material 1062 spans the DM layer and the D2 layer at a portion of the crossover region 1075-d corresponding to a second portion of the crossover region including the dashed line CC of the layer select line 1070-f1. The pair of inner gate electrodes can correspond to the pair of gates of the TFT described with reference to the circuit diagram 738-b (e.g., the pair of gates represented by the gray arrows). Figure 1 ​The described memory devices, 3D memory devices, can include a set of memory cell levels each including a first tier (e.g., Dl tier), a second tier (e.g., DM tier), a third tier (e.g., D2 tier), and a set of memory arrays, a set of first electrodes extending along a first direction, a set of second electrodes extending along a second direction that intersects the first direction. In some cases, within a region (e.g., crossover region 1075) between memory arrays of the set of memory arrays, each first electrode of the set of first electrodes includes a first portion at the second tier, a second portion at the first tier, and a third portion at the second tier, and each second electrode of the set of second electrodes includes a first portion at the second tier, a second portion at the third tier, and a third portion at the second tier.

[0264] In some cases, each first electrode of the set of first electrodes further includes a fourth portion within the region spanning at least the second tier and the first tier, and each second electrode of the set of second electrodes further includes a fourth portion within the region spanning at least the second tier and the third tier. In some cases, the fourth portion of at least two first electrodes of the set of first electrodes can be shared by the at least two first electrodes, and the fourth portion of at least two second electrodes of the set of second electrodes can be shared by the at least two second electrodes.

[0265] In some cases, each first electrode of the set of first electrodes further includes a fifth portion within the region spanning at least the first tier and the second tier, and each second electrode of the set of second electrodes further includes a fifth portion within the region spanning at least both the third tier and the second tier. In some cases, at least a subset of the first electrodes of the set of first electrodes can be coupled together within the region, and at least a subset of the second electrodes of the set of second electrodes can be coupled together within the region.

[0266] In some cases, the memory device can include a first set of transistors located within the set of memory arrays and configured to select a first type of access line, where the first electrodes of the set can be coupled with gates of the first set of transistors. In some cases, the memory device can include a second set of transistors located within the set of memory arrays and configured to select a second type of access line, where the second electrodes of the set can be coupled with gates of the second set of transistors. In some cases, the first set of transistors and the second set of transistors can be located within the levels of the set.

[0267] Figure 11 A diagram 1100 illustrating an exemplary memory device supporting memory array decoding and interconnects in accordance with an embodiment of the present disclosure is described. In some cases, the memory device can include a set of memory cell levels each including a first tier (e.g., Dl tier), a second tier (e.g., DM tier), a third tier (e.g., D2 tier), and a set of memory arrays, a set of first electrodes extending along a first direction, a set of second electrodes extending along a second direction that intersects the first direction. In some cases, within a region (e.g., crossover region 1075) between memory arrays of the set of memory arrays, each first electrode of the set of first electrodes includes a first portion at the second tier, a second portion at the first tier, and a third portion at the second tier, and each second electrode of the set of second electrodes includes a first portion at the second tier, a second portion at the third tier, and a third portion at the second tier. Figure 1 and 2More than two memory cell layers are described. FIG1100 includes a substrate 1156, one or more array layers 1157 (each of which includes an active array region and a socket region), and a layer of TFT circuitry 1158. The substrate 1156 may be a reference Figure 2 7, 8, and 10. Array layer 1157 may include a composite stack (e.g., a Figure 7C The composite stack 705 described in reference Figure 8A The composite stack 805 described in reference Figure 10B The composite stack 1005 described herein may also include a plurality of memory cell layers in the active array region and a socket region in which a plurality of TFTs are positioned. In some cases, each array layer (e.g., array layer 1157-a, array layer 1157-b) may include a plurality of memory cell layers (e.g., eight (8) layers, sixteen (16) layers, thirty-two (32) layers, sixty-four (64) layers). The plurality of TFTs may include vertical TFTs, planar TFTs, wraparound TFTs, or hybrid TFTs, or any combination thereof. A layer of TFT circuitry 1158 may be a reference to a plurality of memory cell layers. Figure 9 An example of a TFT-based decoder circuitry is described.

[0268] In some cases, a memory device may include a memory array including a first layer (e.g., reference Figure 7C A set of electrodes at the first layer 715) and a second layer (eg, reference Figure 7C 1157 - b).

[0269] In some cases, a first tier of a memory device can be included in a first set of tiers (e.g., a first memory cell tier of an array tier 1157-a that can include a number of memory cell tiers) and a second tier of the memory device can be included in a second set of tiers (e.g., a second memory cell tier of an array tier 1157-b that can include a number of memory cell tiers). In some cases, the memory device can further include a decoder circuitry (e.g., a layer of TFT circuitry 1158) between the first set of tiers (e.g., array tier 1157-a) and the second set of tiers (e.g., array tier 1157-b), where the decoder circuitry can be configured to select one or more tiers from the first set of tiers (e.g., array tier 1157-a) and the second set of tiers (e.g., array tier 1157-b).

[0270] In some cases, a memory array can be located at a tier (e.g., a memory cell tier of an array tier 1157-a that can include a number of memory cell tiers) included in a set of tiers of a memory device, and the memory device can further include a decoder circuitry (e.g., the decoder circuitry described with reference to Figure 9 In some cases, a memory array can be located at a tier (e.g., a memory cell tier of an array tier 1157-a that can include a number of memory cell tiers) included in a set of tiers of a memory device, and the memory device can further include a decoder circuitry (e.g., the decoder circuitry described with reference to

[0271] Figure 12 A method 1200 of supporting thin film transistors and related manufacturing techniques for memory array decoding and interconnects in accordance with embodiments of the present disclosure is described. The operations of method 1200 can be implemented by a method as described herein, for example, with reference to Figures 3A-3L

[0272] In block 1205, a first set of vias and a second set of vias can be formed through a top layer of a stack including a first layer, a second layer, and a third layer. The operations of block 1205 can be performed according to the methods described herein. In a particular example, aspects of the operations of block 1205 can be performed as part of one or more processes described with reference to Figures 3A-3L

[0273] In block 1210, a gate electrode of a transistor can be formed using the first set of vias, the gate electrode located at the second layer. The operations of block 1210 can be performed according to the methods described herein. In a particular example, aspects of the operations of block 1210 can be performed as part of one or more processes described with reference to Figures 3A-3L

[0274] In block 1215, a second electrode of the transistor can be formed using the second set of vias, the second electrode located at the first layer. The operations of block 1215 can be performed according to the methods described herein. In a particular example, aspects of the operations of block 1215 can be performed as part of one or more processes described with reference to​​​Figures 3A-3L Portions of the one or more processes described.

[0275] In block 1220, a third electrode of the transistor can be formed using a via that is common to the first set of vias and the second set of vias, the third electrode extending at least through the third layer. The operations of block 1220 can be performed according to the methods described herein. In certain examples, aspects of the operations of block 1220 can be performed by a via formation system as described with reference to FIGS. 1 through 8D and 9 through 12B to support memory array decoding and interconnects according to embodiments of the present disclosure. Figures 3A-3L Portions of the one or more processes described.

[0276] In some examples of the method 1200 described herein, forming a gate electrode of the transistor can include forming a channel at the second layer aligned with the first set of vias, forming an insulating material conformal to the channel, and filling the channel with an electrode material based on forming the insulating material. In some cases, the method 1200 can also include removing a portion of the gate electrode using a via to form a cavity at the second layer and forming an oxide material located in the cavity at the second layer and in contact with the gate electrode using a via. In some cases, the method 1200 can also include removing a portion of the second electrode using a via to form a cavity at the first layer and forming an ohmic material located in the cavity at the first layer and in contact with the second electrode using a via. In some cases, the method 1200 can also include forming a cavity spanning the first layer and the second layer using a via and forming a semiconductor material in the cavity spanning the first layer and the second layer using a via.

[0277] In some cases, the method 1200 can also include forming an insulating material in contact with the semiconductor material using a via. In some cases, the method 1200 can also include forming a cavity at the third layer using a via and forming an ohmic material located in the cavity at the third layer and in contact with the third electrode using a via. In some examples of the method 1200 described herein, forming a third electrode of the transistor can include forming a hole through the stack to a logic circuitry layer using a via and filling the hole with an electrode material. In some examples of the method 1200 described herein, forming a second electrode of the transistor can include forming a channel at the first layer aligned with a second set of vias, where the second set of vias forms a second row of vias intersecting a first row of vias formed by the first set of vias, filling the channel at the first layer with an electrode material, and forming a set of dielectric plugs corresponding to the second set of vias, where the dielectric plugs extend through the electrode material in the channel at the first layer.

[0278] Figure 13 A method 1300 is described that supports thin film transistors and related manufacturing techniques for memory array decoding and interconnects in accordance with embodiments of the present disclosure. The operations of method 1300 can be performed by a memory array decoding and interconnects system (see FIGS. 1 through 8D and 9 through 12B for example) as described herein. In some examples, aspects of the operations of method 1300 can be performed by one or more processors of a memory array decoding and interconnects system as described with reference to FIGS. 1 through 8D and 9 through 12B to support thin film transistors and related manufacturing techniques for memory array decoding and interconnects according to embodiments of the present disclosure. Figures 4A-4AA The method implementations described.

[0279] In block 1305, a first via, a second via, and a third via through a top layer of a stack including a first layer and a second layer can be formed. The operations of block 1305 can be performed according to the methods described herein. In certain examples, aspects of the operations of block 1305 can be performed by a via formation module as described with reference to FIG. 4A. Figures 4A-4AA part of one or more processes described.

[0280] In block 1310, a gate electrode of a transistor can be formed using the first via. The operations of block 1310 can be performed according to the methods described herein. In certain examples, aspects of the operations of block 1310 can be performed by a gate electrode formation module as described with reference to FIG. 4A. Figures 4A-4AA part of one or more processes described.

[0281] In block 1315, a second electrode of a transistor extending through the first layer and the second layer can be formed using the second via. The operations of block 1315 can be performed according to the methods described herein. In certain examples, aspects of the operations of block 1315 can be performed by a second electrode formation module as described with reference to FIG. 4A. Figures 4A-4AA part of one or more processes described.

[0282] In block 1320, a third electrode of a transistor can be formed using at least the first via and the third via. The operations of block 1320 can be performed according to the methods described herein. In certain examples, aspects of the operations of block 1320 can be performed by a third electrode formation module as described with reference to FIG. 4A. Figures 4A-4AA part of one or more processes described.

[0283] In some examples of the method 1300 described herein, forming a gate electrode of a transistor can include forming a channel at a second layer using a set of vias including a first via, forming an insulating material conformal to the channel at the second layer, and filling the first channel with an electrode material that contacts the insulating material. In some cases, the method 1300 can further include forming a cavity at the first layer using the first via to expose at least a portion of the gate electrode, forming an oxide material in contact with the gate electrode using the first via based on forming the cavity, and forming a semiconductor material in the cavity at the first layer and in contact with the oxide material using the first via.

[0284] In some cases, method 1300 may also include: forming a second cavity at the first layer using at least the second via to expose at least a portion of the third electrode and the semiconductor material; forming a third cavity at the first layer using the third via to expose the semiconductor material; and filling the second cavity and the third cavity at the first layer with an ohmic material. In some examples of method 1300 described herein, forming a third electrode of a transistor may include: forming a first channel at the first layer using at least the first via and the third via; filling the first channel at the first layer with an electrode material; forming a second channel narrower than the first channel in the electrode material within the first channel at the first layer; and filling the second channel with a dielectric material. In some examples of method 1300 described herein, forming a second electrode of the transistor may include forming a hole through the stack to the logic circuitry layer using the second via and filling the hole with the electrode material.

[0285] Figure 14 Method 1400 is described for thin film transistors and related fabrication techniques supporting memory array decoding and interconnects according to embodiments of the present disclosure. The operations of method 1400 may be performed by, for example, reference herein. Figures 5A-5N or Figures 6A-6R The described method is implemented.

[0286] In block 1405, a first set of vias, a second set of vias, and a third via may be formed through the top layer of the stack including the first layer, the second layer, and the third layer. The operations of block 1405 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1405 may be performed as described in reference to FIG. Figures 5A-5N or Figures 6A-6R A portion of one or more processes being described.

[0287] In block 1410, a gate electrode of a transistor may be formed using the first set of vias, the gate electrode being located at the second layer. The operations of block 1410 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1410 may be performed as described in the referenced example. Figures 5A-5N or Figures 6A-6R A portion of one or more processes being described.

[0288] In block 1415, a second set of vias may be used to form a second electrode of the transistor, the second electrode being located at the first layer. The operations of block 1415 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1415 may be performed as described in reference to FIG. Figures 5A-5N or Figures 6A-6R A portion of one or more processes being described.

[0289] In block 1420, a third electrode of the transistor can be formed using the third set of vias, the third electrode extending at least through the third layer. The operations of block 1420 can be performed according to the methods described herein. In certain examples, aspects of the operations of block 1420 can be performed by a forming circuitry as described with reference to Figures 5A-5N or Figures 6A-6R portions of one or more processes described herein.

[0290] In some examples of the method 1400 described herein, forming a gate electrode of a transistor can include: forming a channel at a second layer using a first set of vias; forming insulating material in contact with the channel at the second layer; filling the channel at the second layer with an electrode material; and forming a corresponding set of holes extending through the electrode material using the first set of vias. In some cases, the method 1400 can further include forming a third set of vias through a top layer of the stack and forming a cavity across the first layer, the second layer, and the third layer using the third set of vias, where the cavity across the first layer, the second layer, and the third layer exposes the insulating material conformal to the gate electrode.

[0291] In some cases, the method 1400 can further include: removing a portion of the insulating material in contact with the gate electrode using the third set of vias; after removing the portion of the insulating material, forming an oxide material in contact with the gate electrode using the third set of vias; and filling the cavity across the first layer, the second layer, and the third layer with a semiconductor material in contact with the oxide material. In some cases, the method 1400 can further include forming a hole through the semiconductor material to a logic circuitry layer and filling the hole with an electrode material to form a fourth electrode of the transistor.

[0292] In some cases, the method 1400 can further include: forming a cavity at the first layer to expose the semiconductor material and the second electrode using the third set of vias; filling the cavity at the first layer with an ohmic material in contact with the semiconductor material and the second electrode using the third set of vias; removing a portion of the ohmic material using the third set of vias; forming insulating material in contact with the ohmic material using the third set of vias; and forming the ohmic material at the third layer in contact with the semiconductor material using the third set of vias.

[0293] In some cases, method 1400 may also include: filling a cavity spanning the first, second, and third layers with an ohmic material; forming a second cavity spanning the first, second, and third layers with a subset of the third set of vias and the third via; and filling the second cavity spanning the first, second, and third layers with a semiconductor material. In some cases, method 1400 may also include: forming a hole through the first, second, and third layers using a third via; forming an insulating material in contact with the semiconductor material at the first and second layers using the third via; forming a cavity at the third layer using the third via; and filling the cavity at the third layer with the ohmic material. In some examples of method 1400 described herein, forming a third electrode of a transistor may include forming a hole through the stack to the logic circuitry layer using the third via and filling the hole with the electrode material.

[0294] Figure 15 A method 1500 for supporting memory array decoding and interconnects according to an embodiment of the present disclosure is described. The operations of the method 1500 may be implemented by a controller or components thereof as described herein. For example, the operations of the method 1500 may be implemented by a controller (e.g., reference Figure 1 The memory controller 140 described herein may be executed. In some examples, the controller may execute a set of instructions to control the functional elements of the memory array to perform the functions described herein. Additionally or alternatively, the controller may use dedicated hardware to perform aspects of the functions described herein.

[0295] In block 1505, the controller may receive an indication of an access operation of a memory unit. The operations of block 1505 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1505 may be performed as described in the referenced example. Figure 7C 、 7D , 8A to 8C and part of one or more processes described in 9.

[0296] In block 1510, the controller may identify a memory cell layer including memory cells, the layer being included in a set of layers. The operations of block 1510 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1510 may be performed as referenced. Figure 7C 、 7D , 8A to 8C and part of one or more processes described in 9.

[0297] In block 1515, the controller may couple an electrode included in a layer with a conductive plug extending through the layer group based on identifying and using a first transistor included in the layer. The operations of block 1515 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1515 may be performed as described in reference to Figure 7C 、 7Dpart of one or more processes described in FIGS. 8A-8C and 9.

[0298] In block 1520, the controller can drive the electrode to a voltage associated with the access operation based on coupling the electrode with the conductive plug. The operations of block 1520 can be performed according to the methods described herein. In certain examples, aspects of the operations of block 1520 can be performed by a controller as described with reference to FIGS. 8A-8C and 9. Figure 7C , 7D part of one or more processes described in FIGS. 8A-8C and 9.

[0299] An apparatus for performing one or more methods, such as method 1500, is described. The apparatus can include features, circuitry, means, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for receiving an indication of an access operation for a memory cell; identifying a memory cell tier including the memory cell, the tier included in a set of tiers; coupling, based on the identifying and using a first transistor included in the tier, an electrode included in the tier with a conductive plug extending through the set of tiers; and driving, based on the coupling the electrode with the conductive plug, the electrode to a voltage associated with the access operation.

[0300] Another apparatus for performing one or more methods, such as method 1500, is described. The apparatus can include a memory array and a memory controller in electronic communication with the memory array, where the memory controller is operable to: receive an indication of an access operation for a memory cell; identify a memory cell tier including the memory cell, the tier included in a set of tiers; couple, based on the identifying and using a first transistor included in the tier, an electrode included in the tier with a conductive plug extending through the set of tiers; and drive, based on the coupling the electrode with the conductive plug, the electrode to a voltage associated with the access operation.

[0301] Some examples of the method 1500 and the apparatus described herein can further include a process, a feature, a means, or instructions for coupling a second electrode included in the tier with a second conductive plug extending through the tier set based on identifying and using a second transistor included in the tier. Some examples of the method 1500 and the apparatus described herein can further include a process, a feature, a means, or instructions for driving the second electrode to a second voltage associated with an access operation based on coupling the second electrode with the second conductive plug. Some examples of the method 1500 and the apparatus described herein can further include a process, a feature, a means, or instructions for coupling an electrode included in the tier with a conductive plug based on identifying and using a third transistor included in a second tier of the tier set. Some examples of the method 1500 and the apparatus described herein can further include a process, a feature, a means, or instructions for coupling a second electrode included in the tier with a second conductive plug based on identifying and using a fourth transistor included in a third tier of the tier set, where the tier can be between the second tier and the third tier.

[0302] In some examples of the method 1500 and the apparatus described herein, the electrode can include a first type of access line. Some examples of the method 1500 and the apparatus described herein can further include a process, a feature, a means, or instructions for coupling a first type of access line included in each tier of a subset of the tier set with a third conductive plug extending through the tier set based on identifying and using a transistor included in the subset of tiers, where the subset does not include the tier. Some examples of the method 1500 and the apparatus described herein can further include a process, a feature, a means, or instructions for driving the first type of access line included in each tier of the subset to a third voltage associated with an access operation based on coupling the first type of access line included in each tier of the subset with the third conductive plug.

[0303] Figure 16 A method 1600 that supports memory array decoding and interconnects in accordance with embodiments of the present disclosure is described. The operations of the method 1600 can be implemented by a controller or its components as described herein. For example, the operations of the method 1600 can be performed by a controller (e.g., with reference to the memory controller 140 described Figure 1 In some examples, a controller can execute a set of instructions to control the functional elements of a memory array to perform the functions described herein. Additionally or alternatively, the controller can perform aspects of the functions described herein using special-purpose hardware.

[0304] In block 1605, the controller can receive an indication of an access operation of a memory cell. The operations of block 1605 can be performed according to the methods described herein. In certain examples, aspects of the operations of block 1605 can be performed by a controller (e.g., with reference to the memory controller 140 described Figure 7C ,7D part of one or more processes described in FIGS. 8A-8C and 9.

[0305] In block 1610, the controller can identify a memory cell tier including a memory cell, the tier included in a set of tiers. The operations of block 1610 can be performed according to the methods described herein. In certain examples, aspects of the operations of block 1610 can be performed by a tier identification component as described with reference to FIGS. 1 and 2A-2J with Figure 7C , 7D part of one or more processes described in FIGS. 8A-8C and 9.

[0306] In block 1615, the controller can couple an electrode included in the tier with a conductive plug extending through the set of tiers based on identifying and using a first transistor included in the tier. The operations of block 1615 can be performed according to the methods described herein. In certain examples, aspects of the operations of block 1615 can be performed by a coupling component as described with reference to FIGS. 1 and 2A-2J with Figure 7C , 7D part of one or more processes described in FIGS. 8A-8C and 9.

[0307] In block 1620, the controller can drive the electrode to a voltage associated with an access operation based on coupling the electrode with the conductive plug. The operations of block 1620 can be performed according to the methods described herein. In certain examples, aspects of the operations of block 1620 can be performed by a driving component as described with reference to FIGS. 1 and 2A-2J with Figure 7C , 7D part of one or more processes described in FIGS. 8A-8C and 9.

[0308] Apparatuses for performing one or several methods, such as method 1600, are described. An apparatus can include means for receiving an indication of an access operation for a memory cell, means for identifying a memory cell tier including the memory cell, the tier included in a set of tiers, means for coupling an electrode included in the tier with a conductive plug extending through the set of tiers based on identifying and using a first transistor included in the tier, means for driving the electrode to a voltage associated with the access operation based on coupling the electrode with the conductive plug, means for coupling a second electrode included in the tier with a second conductive plug extending through the set of tiers based on identifying and using a second transistor included in the tier, and means for driving the second electrode to a second voltage associated with the access operation based on coupling the second electrode with the second conductive plug.

[0309] Another apparatus for performing one or more methods (such as method 1600) is described. The apparatus can include a memory array and a memory controller in electronic communication with the memory array, where the memory controller is operable to: receive an indication of an access operation for a memory cell; identify a memory cell tier including the memory cell, the tier included in a set of tiers; based on the identifying and using a first transistor included in the tier, couple an electrode included in the tier with a conductive plug extending through the set of tiers; based on the coupling the electrode with the conductive plug, drive the electrode to a voltage associated with the access operation; based on the identifying and using a second transistor included in the tier, couple a second electrode included in the tier with a second conductive plug extending through the set of tiers; and based on the coupling the second electrode with the second conductive plug, drive the second electrode to a second voltage associated with the access operation.

[0310] It should be noted that the methods described herein describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Further, aspects from two or more of the methods can be combined.

[0311] Information and signals described herein can be represented using various different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate several signals as single signals; however, one of ordinary skill in the art will understand that signals can be represented as buses, and buses can have any combination of bit widths.

[0312] The terms "electronic communication" and "coupled" refer to a relationship between components that supports the flow of electrons between the components. This can include a direct connection between the components or can include intervening components. Components that are in electronic communication or coupled with each other can actively exchange electrons or signals (e.g., in powered circuitry) or can not actively exchange electrons or signals (e.g., in unpowered circuitry) but can be configured and operated to exchange electrons or signals upon circuitry being powered. For example, two components that are physically connected via a switch (e.g., a transistor) are in electronic communication or can be coupled, regardless of the state of the switch (i.e., open or closed).

[0313] As used herein, the term "substantially" means that the modified property (e.g., the verb or adjective modified by the term "substantially") need not be absolute, but is close enough to the property to be economically or otherwise practically realized.

[0314] As used herein, the term "electrode" may refer to an electrical conductor and, in some cases, may serve as an electrical contact for a memory cell or other component of a memory array. An electrode may include a trace, a wire, a conductive line, a conductive layer, or the like that provides a conductive pathway between elements or components of memory device 100.

[0315] The chalcogenide material may be a material or alloy containing at least one of the elements S, Se, and Te. The chalcogenide material may include an alloy of S, Se, Te, Ge, As, Al, Si, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), and platinum (Pt). Example chalcogenide materials and alloys may include, but are not limited to, Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge- As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te- Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd or Ge-Te-Sn-Pt. As used herein, chemical composition symbols connected by hyphens indicate the elements contained in a particular compound or alloy and are intended to represent all stoichiometric amounts involving the indicated elements. For example, Ge-Te may contain Ge x Te y , where x and y can be any positive integer. Other examples of variable resistance materials may include binary metal oxide materials or mixed-valence oxides comprising two or more metals, such as transition metals, alkaline earth metals, and / or rare earth metals. Embodiments are not limited to one or more specific variable resistance materials associated with the memory component of a memory cell. For example, other examples of variable resistance materials may be used to form the memory component and may include chalcogenide materials, giant magnetoresistive materials, or polymer-based materials, among others.

[0316] The term "isolation" refers to a relationship between components where electrons cannot flow between them; if there is an open circuit between the components, they are isolated from each other. For example, when a switch is open, two components physically connected by the switch can be isolated from each other.

[0317] The devices discussed herein, including memory device 100, can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be an epitaxial layer of semiconductor material on an insulator (such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation or any other doping method during initial formation or growth of the substrate.

[0318] One or more transistors discussed herein can represent a field effect transistor (FET) and include a four-terminal device, including a source, a drain, a gate, and a base (or substrate). The terminals can be connected to other electronic elements by conductive material, such as metal. The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel, which can be part of the base. If the channel is n-type (i.e., the majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can cause the channel to become conductive. A transistor can be“turned on” or“activated” when a voltage greater than or equal to the threshold voltage of the transistor is applied to the gate of the transistor. A transistor can be“turned off” or“deactivated” when a voltage less than the threshold voltage of the transistor is applied to the gate of the transistor.

[0319] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the instances that can be implemented or that are within the scope of the claims. The term“exemplary” used herein means“serving as an example, instance, or illustration,” and not“preferred” over other examples. The implementations

[0320] In the drawings, like reference numerals can be used to denote like components throughout the several views. Additionally, components of the same type can be distinguished by a second digit or letter suffix, in combination with the primary reference numeral. If only the primary reference numeral is used in the specification, the description is applicable to any one of the like components having the same primary reference numeral.

[0321] Information and signals described herein can be represented using various different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0322] The various illustrative blocks and modules described in connection with the disclosure can be implemented or performed with a general-purpose processor, a Digital Signal Processor (DSP), an ASIC, a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0323] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or program code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. Also, as used herein, including in the claims, "or" as used in a list of items prefaced by "at least one of indicates a disjunctive list such that, for example, a list of "at least one of A, B, or C" means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as "based on condition A" can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" shall be construed in the same manner as the phrase "based at least in part on."

[0324] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0325] The present disclosure is provided to enable any person skilled in the art to practice the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: a memory array comprising a plurality of electrodes at a first layer and a plurality of memory cells at a second layer; and a plurality of transistors configured to select an electrode from the plurality of electrodes, each of the plurality of transistors comprising: a gate electrode located at the second layer; and A semiconductor material is located at the first layer.

2. The device of claim 1 , wherein the memory array is located at a first level of the device, the device further comprising: The second layer of the device, the second layer comprising: a second memory array comprising a second plurality of electrodes at a first layer of the second level and a second plurality of memory cells at a second layer of the second level; and a second plurality of transistors configured to select electrodes from the second plurality of electrodes, each of the second plurality of transistors comprising: a gate electrode located at the second layer of the second face; and A semiconductor material is located at the first layer of the second level.

3. The apparatus of claim 2, wherein the first level of the apparatus is included in a first plurality of levels and the second level of the apparatus is included in a second plurality of levels, the apparatus further comprising: Decoder circuitry is located between the first plurality of levels and the second plurality of levels, wherein the decoder circuitry is configured to select one or more levels from among levels of the first plurality of levels and levels of the second plurality of levels.

4. The apparatus of claim 1 , wherein the memory array is located at one of a plurality of levels included in the apparatus, the apparatus further comprising: Decoder circuitry is included in the level and is configured to activate a transistor in the plurality of transistors based at least in part on selecting the transistor's gate electrode from a plurality of corresponding gate electrodes included in the level.

5. The apparatus of claim 1 , wherein each transistor of the plurality of transistors further comprises: A dielectric plug extends through the first layer and the second layer, wherein the semiconductor material at the first layer and the gate electrode at the second layer each at least partially surround the dielectric plug.

6. The apparatus of claim 1 , wherein each transistor of the plurality of transistors further comprises: An oxide material is between the semiconductor material and the gate electrode.

7. The apparatus of claim 1 , wherein each transistor of the plurality of transistors further comprises: An ohmic material is located at the first layer, the ohmic material being in contact with the semiconductor material and with an electrode from the plurality of electrodes.

8. The apparatus of claim 7 , wherein each transistor of the plurality of transistors further comprises: A conductive plug extends through the first layer and the second layer, wherein the ohmic material located at the first layer at least partially surrounds the conductive plug.

9. The apparatus of claim 8, wherein each transistor of the plurality of transistors further comprises: said ohmic material at a third layer, wherein said semiconductor material extends into said second layer; and The ohmic material at the third layer contacts the semiconductor material at the second layer and contacts a conductive plug extending through the first layer, the second layer, and the third layer.

10. A device comprising: a plurality of memory cell levels, each comprising a first layer, a second layer, a third layer, and a plurality of memory arrays; a plurality of first electrodes extending along a first direction; and a plurality of second electrodes extending along a second direction intersecting the first direction, wherein in a region between memory arrays of the plurality of memory arrays: Each of the plurality of first electrodes includes a first portion located at the second layer, a second portion located at the first layer, and a third portion located at the second layer; and Each of the plurality of second electrodes includes a first portion located at the second layer, a second portion located at the third layer, and a third portion located at the second layer.

11. The apparatus according to claim 10, wherein: Each of the plurality of first electrodes further includes a fourth portion within the region spanning at least the second layer and the first layer; and Each of the plurality of second electrodes further includes a fourth portion in the region spanning at least the second layer and the third layer.

12. The apparatus of claim 11, wherein: The fourth portion of at least two first electrodes of the plurality of first electrodes is shared by the at least two first electrodes; and The fourth portion of at least two second electrodes among the plurality of second electrodes is shared by the at least two second electrodes.

13. The apparatus of claim 11, wherein: Each of the plurality of first electrodes further includes a fifth portion within the region spanning at least the first layer and the second layer; and Each second electrode of the plurality of second electrodes further includes a fifth portion within the region spanning at least two of the third layer and the second layer.

14. The apparatus of claim 10, wherein: At least a subset of the first electrodes of the plurality of first electrodes are coupled together within the region; and At least a subset of the second electrodes of the plurality of second electrodes are coupled together within the region.

15. The apparatus of claim 10, further comprising: a first plurality of transistors within the memory array of the plurality of memory arrays and configured to select an access line of a first type, wherein the first electrode of the plurality of first electrodes is coupled to gates of the first plurality of transistors; and A second plurality of transistors are located within the memory array of the plurality of memory arrays and are configured to select an access line of a second type, wherein the second electrode of the second plurality of electrodes is coupled to gates of the second plurality of transistors.

16. The apparatus of claim 15, wherein the first plurality of transistors and the second plurality of transistors are located within a level of the plurality of levels.

17. A method for performing an access operation of a memory cell, comprising: receiving an indication of the access operation of the memory cell, the memory cell being located within a memory array and comprising a plurality of electrodes located at a first layer and a plurality of memory cells located at a second layer; coupling one of the plurality of electrodes to a conductive plug extending through the first layer and the second layer using a first transistor of a plurality of transistors configured to select an electrode from the plurality of electrodes; and The electrode is driven to a voltage associated with the access operation based at least in part on coupling the electrode with the conductive plug.

18. The method of claim 17, wherein the memory array is located at a level comprised in a plurality of levels, the method further comprising: The first transistor is activated to couple the electrode to the conductive plug based at least in part on selecting a gate electrode of the first transistor from a plurality of corresponding gate electrodes included in the level.

19. The method of claim 17, further comprising: identifying a level of memory cells of the memory array including the memory cell, the level being included in a plurality of levels; and The layer is selected from the plurality of layers based at least in part on identifying the layer, wherein the electrode is driven to the voltage based at least in part on selecting the layer.

20. The method of claim 17, wherein each transistor of the plurality of transistors comprises a gate electrode at the second layer and a semiconductor material at the first layer.

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