A light emitting diode chip, a preparation method thereof, and an LED package

Abstract

The application discloses a light emitting diode chip and a preparation method and LED packaging body thereof. The light emitting diode chip comprises a substrate and an epitaxial functional layer on the substrate. The side surface of the light emitting diode chip comprises first trapezoidal grooves and second trapezoidal grooves arranged alternately. The surface roughness of the bottom surface and the side wall of the first trapezoidal groove is greater than that of the second trapezoidal groove. In the subsequent packaging process, the packaging material can be embedded into the corresponding first trapezoidal groove and second trapezoidal groove, thereby greatly improving the bonding stability of the packaging layer and the light emitting diode chip. The side surface of the light emitting diode chip comprises the first trapezoidal groove and the second trapezoidal groove arranged alternately, thereby expanding the light emitting angle of the light emitting diode chip and improving the light emitting efficiency of the light emitting diode chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor light-emitting technology, in particular to a light-emitting diode chip, a preparation method thereof and an LED package. BACKGROUND

[0002] In the preparation and cutting process of a light-emitting wafer epitaxial sheet, the light-emitting wafer epitaxial sheet is usually formed through an epitaxial process, then appearance and performance detection is performed on the light-emitting wafer epitaxial sheet, then a protective film is attached to the surface of the epitaxial sheet, then cutting is performed according to a preset cutting pattern and parameters, for some chips that have not been completely separated after cutting, a splitting operation is needed to separate the single chips from the epitaxial sheet, then the protective film, cutting dust and other impurities on the surface of the chips are removed to ensure the cleanliness of the chips, finally appearance and performance detection is performed on the cut chips, and the qualified chips and unqualified chips are sorted to provide qualified chips for subsequent packaging procedures. How to improve the cutting process of the light-emitting wafer epitaxial sheet and thus improve the light-emitting efficiency of the corresponding light-emitting diode chip has attracted widespread attention. SUMMARY

[0003] To solve the above problems in the prior art, the present application provides a light-emitting diode chip, a preparation method thereof and an LED package.

[0004] To achieve the above object, the technical scheme adopted by the present application is as follows:

[0005] The embodiment of the present application provides a preparation method of a light-emitting diode chip, which comprises the following steps:

[0006] A semiconductor light-emitting wafer is provided, which comprises a plurality of light-emitting diode chip areas arranged in an array and a cutting area between any adjacent light-emitting diode chip areas, and comprises a substrate and an epitaxial functional layer on the substrate.

[0007] A plurality of separately arranged openings are formed in the cutting area of the semiconductor light-emitting wafer.

[0008] The semiconductor light-emitting wafer is cut along the cutting area to form a plurality of mutually separated light-emitting diode chips, so that each light-emitting diode chip has a plurality of parallel grooves on the side surface, and each light-emitting diode chip comprises an upper surface and a lower surface.

[0009] A first etching process is performed on a part of the grooves on the upper surface of the light-emitting diode chip to form a first trapezoidal groove.

[0010] Then, a second etching treatment is performed on the rest of the groove from the lower surface of the light emitting diode chip to form a second trapezoidal groove, wherein the first trapezoidal groove and the second trapezoidal groove are arranged alternately.

[0011] Then, a first laser treatment is performed on the bottom surface and the sidewall of the first trapezoidal groove, and a second laser treatment is performed on the bottom surface and the sidewall of the second trapezoidal groove, so that the surface roughness of the bottom surface and the sidewall of the first trapezoidal groove is greater than the surface roughness of the bottom surface and the sidewall of the second trapezoidal groove.

[0012] As a preferred embodiment, the epitaxial functional layer comprises a first semiconductor layer, a quantum well light emitting layer and a second semiconductor layer arranged in layers.

[0013] As a preferred embodiment, the semiconductor light emitting wafer further comprises a back metal electrode layer arranged on the back surface of the semiconductor light emitting wafer and a surface electrode block array arranged on the surface of the epitaxial functional layer.

[0014] As a preferred embodiment, each of the light emitting diode chips comprises one surface electrode block and one back metal electrode.

[0015] As a preferred embodiment, further comprising: performing a passivation treatment on the side surface of the light emitting diode chip to form a passivation layer covering the bottom surface and the sidewall of the first trapezoidal groove and the second trapezoidal groove.

[0016] As a preferred embodiment, from the front surface of the light emitting diode chip, the first trapezoidal groove is a trapezoidal groove with a wide bottom and a narrow top, and the second trapezoidal groove is a trapezoidal groove with a narrow bottom and a wide top.

[0017] As a preferred embodiment, the bottom surface area of the first trapezoidal groove is greater than the bottom surface area of the second trapezoidal groove.

[0018] The present application also provides a light emitting diode chip prepared by the preparation method of the light emitting diode chip, the light emitting diode chip comprising a substrate and an epitaxial functional layer on the substrate, the side surface of the light emitting diode chip comprising first trapezoidal grooves and second trapezoidal grooves arranged alternately, the surface roughness of the bottom surface and the sidewall of the first trapezoidal groove being greater than the surface roughness of the bottom surface and the sidewall of the second trapezoidal groove.

[0019] The present application also provides an LED package comprising a packaging substrate, a plurality of the light emitting diode chips arranged on the packaging substrate, and a packaging layer wrapping the plurality of light emitting diode chips.

[0020] As a preferred embodiment, the encapsulation layer comprises encapsulation glue and fluorescent powder.

[0021] Compared with the prior art, the light emitting diode chip, the preparation method thereof and the corresponding LED package have the following beneficial effects:

[0022] In the preparation method of the light emitting diode chip, a plurality of openings are formed in the cutting area of the semiconductor light emitting wafer in advance, and then a cutting process is performed, so as to effectively reduce the cutting damage of the semiconductor light emitting wafer. In the subsequent process, a first trapezoidal groove is formed by performing a first etching process on a part of the groove from the upper surface of the light emitting diode chip, and then a second trapezoidal groove is formed by performing a second etching process on the remaining part of the groove from the lower surface of the light emitting diode chip. The first trapezoidal groove and the second trapezoidal groove are alternately arranged. In the subsequent packaging process, the packaging material can be embedded into the corresponding first trapezoidal groove and second trapezoidal groove, which greatly improves the bonding stability of the packaging layer and the light emitting diode chip. The side surface of the light emitting diode chip comprises the first trapezoidal groove and the second trapezoidal groove arranged alternately, which can expand the light emitting angle of the light emitting diode chip and improve the light emitting efficiency of the light emitting diode chip.

[0023] Further, the first trapezoidal groove and the second trapezoidal groove are alternately arranged. In the subsequent packaging process, the packaging material can be embedded into the corresponding first trapezoidal groove and second trapezoidal groove, which greatly improves the bonding stability of the packaging layer and the light emitting diode chip. The side surface of the light emitting diode chip comprises the first trapezoidal groove and the second trapezoidal groove arranged alternately, which can expand the light emitting angle of the light emitting diode chip and improve the light emitting efficiency of the light emitting diode chip. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0025] Figure 1 is a top view of a partial region of a semiconductor light emitting wafer in which a plurality of openings are formed in the present application;

[0026] Figure 2 is Figure 1 is a sectional view of the semiconductor light emitting wafer along A-A in the present application;

[0027] Figure 3 is a side view of a light emitting diode chip formed by a cutting process in the present application;

[0028] Figure 4 FIG. 1 is a side view of a light emitting diode chip after a first etching process in the present application;

[0029] Figure 5 FIG. 2 is a side view of a light emitting diode chip after a second etching process in the present application;

[0030] Figure 6 FIG. 3 is a structure view of an LED package in the present application.

[0031] BRIEF DESCRIPTION OF DRAWINGS

[0032] 100, semiconductor light emitting wafer; 101, light emitting diode chip area; 102, cutting area; 103, opening; 200, substrate; 201, first semiconductor layer; 202, quantum well light emitting layer; 203, second semiconductor layer; 204, back metal electrode layer; 205, surface electrode block; 300, light emitting diode chip; 301, groove; 401, first trapezoidal groove; 402, second trapezoidal groove; 500, packaging substrate; 501, packaging layer. DETAILED DESCRIPTION

[0033] The embodiments of the present application will be described in detail hereinafter with reference to the drawings and embodiments, by which the technical means applied by the present application to solve the technical problems and achieve the corresponding technical effects can be fully understood and implemented. The embodiments of the present application and each feature in the embodiments can be combined with each other without conflict, and the technical solutions formed thereby are all within the protection scope of the present application. In the drawings, the sizes and relative sizes of layers and regions can be exaggerated for clarity. The same reference signs represent the same elements throughout.

[0034] It should be understood that although the terms "first", "second", "third", etc. are used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part without departing from the teachings of the present application.

[0035] It will be understood that the spatially relative terms "above", "below", "up", "down", and like terms, are used for ease of description to describe the aspects of the application as illustrated in the drawings. It will be understood that without so limiting, the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the drawings. For example, if the device described is turned over and the bottom surface described as below then can be oriented to be above. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used herein interpreted accordingly.

[0036] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0037] The embodiments of the application can be described with reference to schematic cross-sectional illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. The embodiments of the application are to be construed as not limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing.

[0038] For a thorough understanding of the application, a detailed description will be made in the following description of the embodiments with reference to the accompanying drawings. The preferred embodiments of the application will be described in detail below, however, the application can have other embodiments in addition to those described.

[0039] Embodiments of the application disclose a method of fabricating a light emitting diode chip, the method comprising the steps of:

[0040] As Figure 1 And Figure 2As shown, a semiconductor light-emitting wafer 100 is provided. The semiconductor light-emitting wafer 100 includes a plurality of light-emitting diode chip regions 101 arranged in an array and dicing regions 102 located between any adjacent light-emitting diode chip regions. The semiconductor light-emitting wafer 100 includes a substrate 200 and an epitaxial functional layer located on the substrate 200. A plurality of separately disposed openings 103 are formed in the dicing regions of the semiconductor light-emitting wafer 100.

[0041] In a specific embodiment, the epitaxial functional layer includes a first semiconductor layer 201, a quantum well light-emitting layer 202, and a second semiconductor layer 203 stacked together.

[0042] In a specific embodiment, the semiconductor light-emitting wafer 100 further includes a back metal electrode layer 204 disposed on the back side of the semiconductor light-emitting wafer and a surface electrode block array disposed on the surface of the epitaxial functional layer, the surface electrode block array including surface electrode blocks 205.

[0043] In a specific embodiment, the substrate 200 is a gallium nitride substrate, the first semiconductor layer 201 is an N-type nitride layer or a P-type nitride layer, the quantum well light-emitting layer 202 is a gallium nitride-based multiple quantum well light-emitting layer, and the second semiconductor layer 203 is a P-type nitride layer or an N-type nitride layer; when the first semiconductor layer 201 is an N-type nitride layer, the second semiconductor layer 203 is a P-type nitride layer, and when the first semiconductor layer 201 is a P-type nitride layer and the second semiconductor layer 203 is an N-type nitride layer, preferably the N-type nitride layer is an N-type gallium nitride layer and the P-type nitride layer is a P-type gallium nitride layer.

[0044] In a specific embodiment, photoresist is used as a mask, and a plurality of the separately configured openings 103 are formed by a wet etching process.

[0045] like Figure 3 As shown, the semiconductor light-emitting wafer 100 is cut along the cutting area to form a plurality of mutually separated light-emitting diode chips 300, such that each light-emitting diode chip 300 has a plurality of parallel grooves 301 on its side. Each light-emitting diode chip 300 includes an upper surface and a lower surface, and each light-emitting diode chip 300 includes a surface electrode block 205 and a back metal electrode (not shown).

[0046] In specific embodiments, the cutting process is carried out by a laser cutting process or a mechanical cutting process. In embodiments according to the application, a suitable cutting process is selected according to the size of the LED chip 300. Specifically, when the LED chip 300 is a small-size chip, a laser cutting process is used to form the LED chip 300, and when the LED chip 300 is a large-size chip, a mechanical cutting process is used to form the LED chip 300.

[0047] As shown in Figure 4 a first etching process is carried out on a portion of the groove 301 from the upper surface of the LED chip 300 to form a first trapezoidal groove 401.

[0048] In specific embodiments, the first trapezoidal groove 401 is a trapezoidal groove that is wide at the top and narrow at the bottom as viewed from the front of the LED chip 300.

[0049] In specific embodiments, the first etching process is a first dry etching process. Specifically, the first dry etching process has the following parameters: the etching gas is boron trichloride and chlorine, wherein the gas flow of boron trichloride is 400-600 sccm, and as a preferred embodiment, the gas flow of boron trichloride is specifically 400 sccm, 430 sccm, 460 sccm, 480 sccm, 500 sccm, 530 sccm, 560 sccm, 580 sccm or 600 sccm; the gas flow of chlorine is 20-40 sccm, and as a preferred embodiment, the gas flow of chlorine is specifically 20 sccm, 22 sccm, 25 sccm, 28 sccm, 30 sccm, 33 sccm, 36 sccm, 38 sccm or 40 sccm; and the etching power is 250-380 W, and as a preferred embodiment, the etching power is specifically 250 W, 280 W, 310 W, 340 W, 360 W or 380 W.

[0050] As shown in Figure 5 then a second etching process is carried out on the remaining portion of the groove from the lower surface of the LED chip 300 to form a second trapezoidal groove 402, wherein the first trapezoidal groove 401 and the second trapezoidal groove 402 are arranged alternately.

[0051] In specific embodiments, the second trapezoidal groove 402 is a trapezoidal groove that is narrow at the top and wide at the bottom as viewed from the front of the LED chip 300.

[0052] In specific embodiments, the bottom area of the first trapezoidal groove 401 is larger than the bottom area of the second trapezoidal groove 402.

[0053] In specific embodiments, the second etching treatment is a second dry etching process, and the specific process of the second dry etching process is as follows: the etching gas is boron trichloride and chlorine, wherein the gas flow of boron trichloride is 150-300 sccm, and as a preferred embodiment, the gas flow of boron trichloride is specifically 150 sccm, 170 sccm, 190 sccm, 210 sccm, 230 sccm, 250 sccm, 280 sccm or 300 sccm; the gas flow of chlorine is 5-15 sccm, and as a preferred embodiment, the gas flow of chlorine is specifically 5 sccm, 6 sccm, 7 sccm, 8 sccm, 9 sccm, 10 sccm, 11 sccm, 12 sccm, 13 sccm, 14 sccm or 15 sccm; the etching power is 50-150 W, and as a preferred embodiment, the etching power is specifically 50 W, 70 W, 90 W, 100 W, 120 W or 150 W, that is, the etching power of the second dry etching process is less than the etching power of the first dry etching process.

[0054] Then, the first laser treatment is performed on the bottom surface and the sidewall of the first trapezoidal groove 401, and the second laser treatment is performed on the bottom surface and the sidewall of the second trapezoidal groove 402, so that the surface roughness of the bottom surface and the sidewall of the first trapezoidal groove 401 is greater than the surface roughness of the bottom surface and the sidewall of the second trapezoidal groove 402.

[0055] In specific embodiments, the processing technology of the first laser treatment is as follows: the wavelength range of the laser is 515-532 nm, and the energy density range of the laser is 25-40 J / cm²‌. By adjusting the processing time of the laser on the bottom surface and the sidewall of the first trapezoidal groove 401 and the energy density of the laser, the surface roughness of the bottom surface and the sidewall of the first trapezoidal groove 401 is 1-5 microns, and in a more preferred embodiment, the energy density range of the laser can be 25-30 J / cm²‌, 30-35 J / cm²‌ or 35-40 J / cm²‌, and further adjusting the surface roughness of the bottom surface and the sidewall of the first trapezoidal groove 401 to be 1-2 microns, 2-3 microns, 3-4 microns or 4-5 microns.

[0056] In specific embodiments, the second laser processing has a wavelength range of 515-532 nm, an energy density range of 5-20 J / cm2, and a surface roughness of 0.3-1 microns for the bottom and sidewall of the second trapezoidal groove 402. In more preferred embodiments, the energy density range can be 5-10 J / cm2, 10-15 J / cm2, or 15-20 J / cm2, and the surface roughness of the bottom and sidewall of the second trapezoidal groove 402 can be 0.3-0.5 microns, 0.5-0.7 microns, or 0.7-1 micron.

[0057] In specific embodiments, as shown in FIG. 4, the side surface of the light emitting diode chip 300 is passivated to form a passivation layer (not shown) covering the bottom and sidewall of the first trapezoidal groove 401 and the second trapezoidal groove 402. Figure 5

[0058] In specific embodiments, the passivation layer is formed by an atomic layer deposition process to form an aluminum oxide layer or by a PECVD process to deposit silicon nitride.

[0059] As shown in FIG. 5, the present application further provides a light emitting diode chip 300 prepared by the above method. The light emitting diode chip 300 includes a substrate 200 and an epitaxial functional layer on the substrate 200. The side surface of the light emitting diode chip 300 includes first trapezoidal grooves 401 and second trapezoidal grooves 402 arranged alternately. The surface roughness of the bottom and sidewall of the first trapezoidal groove 401 is greater than that of the second trapezoidal groove 402. Figure 5 As shown in FIG. 6, the present application further provides an LED package including a packaging substrate 500, a plurality of light emitting diode chips 300 arranged on the packaging substrate 500, and a packaging layer 501 wrapping the plurality of light emitting diode chips 300.

[0060] Figure 6 In specific embodiments, the packaging layer includes a packaging gel and phosphor.

[0061] Embodiments of the present application provide a method for preparing a light emitting diode chip, which includes the following steps:

[0062] Embodiments of the present application provide a method for preparing a light emitting diode chip, which includes the following steps:

[0063] ​​A semiconductor light-emitting wafer is provided, which includes a plurality of light-emitting diode chip regions arranged in an array and a plurality of cutting regions between any adjacent light-emitting diode chip regions, and includes a substrate and an epitaxial functional layer on the substrate.

[0064] A plurality of openings are formed in the cutting regions of the semiconductor light-emitting wafer.

[0065] The semiconductor light-emitting wafer is cut along the cutting regions to form a plurality of mutually separated light-emitting diode chips, so that each of the light-emitting diode chips has a plurality of parallel grooves on a side surface thereof, and each of the light-emitting diode chips includes an upper surface and a lower surface.

[0066] A first etching process is performed on a portion of the grooves from the upper surface of the light-emitting diode chip to form first trapezoidal trenches.

[0067] Then, a second etching process is performed on the remaining portion of the grooves from the lower surface of the light-emitting diode chip to form second trapezoidal trenches, wherein the first trapezoidal trenches and the second trapezoidal trenches are alternately arranged.

[0068] Then, a first laser process is performed on the bottom surface and the sidewall of the first trapezoidal trenches, and a second laser process is performed on the bottom surface and the sidewall of the second trapezoidal trenches, so that the surface roughness of the bottom surface and the sidewall of the first trapezoidal trenches is greater than the surface roughness of the bottom surface and the sidewall of the second trapezoidal trenches.

[0069] According to an embodiment of the present application, the epitaxial functional layer includes a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer arranged in a stack.

[0070] According to an embodiment of the present application, the semiconductor light-emitting wafer further includes a back metal electrode layer disposed on a back surface of the semiconductor light-emitting wafer and an array of surface electrode blocks disposed on a surface of the epitaxial functional layer.

[0071] According to an embodiment of the present application, each of the light-emitting diode chips includes one surface electrode block and one back metal electrode.

[0072] According to an embodiment of the present application, further including: performing a passivation process on the side surface of the light-emitting diode chip to form a passivation layer, wherein the passivation layer covers the bottom surface and the sidewall of the first trapezoidal trenches and the second trapezoidal trenches.

[0073] According to an embodiment of the present application, as viewed from a front surface of the light-emitting diode chip, the first trapezoidal trenches are upper-wide lower-narrow trapezoidal trenches, and the second trapezoidal trenches are upper-narrow lower-wide trapezoidal trenches.

[0074] According to one embodiment of the present application, the bottom area of the first trapezoidal groove is larger than the bottom area of the second trapezoidal groove.

[0075] According to one embodiment of the present application, the present application further provides a light emitting diode chip, which is prepared by the above method, and comprises a substrate and an epitaxial functional layer on the substrate, and the side surface of the light emitting diode chip comprises first trapezoidal grooves and second trapezoidal grooves arranged alternately, and the surface roughness of the bottom and the sidewall of the first trapezoidal groove is larger than that of the second trapezoidal groove.

[0076] According to one embodiment of the present application, the present application further provides an LED package, which comprises a packaging substrate, a plurality of the above light emitting diode chips arranged on the packaging substrate, and a packaging layer wrapping the plurality of light emitting diode chips.

[0077] According to one embodiment of the present application, the packaging layer comprises a packaging glue and phosphor.

[0078] In the method for preparing the light emitting diode chip, a plurality of openings are formed in the cutting area of the semiconductor light emitting wafer in advance, and then the cutting process is performed, so as to effectively reduce the cutting damage of the semiconductor light emitting wafer. In the subsequent process, a first etching process is performed on a part of the groove from the upper surface of the light emitting diode chip, so as to form the first trapezoidal groove, and then a second etching process is performed on the remaining part of the groove from the lower surface of the light emitting diode chip, so as to form the second trapezoidal groove. The first trapezoidal groove and the second trapezoidal groove are arranged alternately. In the subsequent packaging process, the packaging material can be embedded into the corresponding first trapezoidal groove and second trapezoidal groove, so as to greatly improve the bonding stability of the packaging layer and the light emitting diode chip. The side surface of the light emitting diode chip comprises the first trapezoidal groove and the second trapezoidal groove arranged alternately, so as to expand the light emitting angle of the light emitting diode chip and improve the light emitting efficiency of the light emitting diode chip.

[0079] Further, the first laser treatment is performed on the bottom and the sidewall of the first trapezoidal groove, and the second laser treatment is performed on the bottom and the sidewall of the second trapezoidal groove, so that the surface roughness of the bottom and the sidewall of the first trapezoidal groove is larger than that of the second trapezoidal groove, and the light emitting uniformity of the whole light emitting diode chip is further improved.

[0080] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method of fabricating a light emitting diode chip, characterized by: The preparation method of the light emitting diode chip comprises the following steps: A semiconductor light emitting wafer is provided, which comprises a plurality of light emitting diode chip regions arranged in an array and a plurality of cutting regions between any adjacent light emitting diode chip regions, and the semiconductor light emitting wafer comprises a substrate and an epitaxial functional layer on the substrate; A plurality of separately arranged openings are formed in the cutting regions of the semiconductor light emitting wafer; The semiconductor light emitting wafer is cut along the cutting regions to form a plurality of mutually separated light emitting diode chips, so that each light emitting diode chip has a plurality of parallel grooves on the side surface, and each light emitting diode chip comprises an upper surface and a lower surface; First etching is performed on a part of the grooves on the upper surface of the light emitting diode chip to form first trapezoidal grooves; Then, second etching is performed on the remaining part of the grooves on the lower surface of the light emitting diode chip to form second trapezoidal grooves, wherein the first trapezoidal grooves and the second trapezoidal grooves are arranged alternately; Then, first laser processing is performed on the bottom surface and the side wall of the first trapezoidal grooves, and second laser processing is performed on the bottom surface and the side wall of the second trapezoidal grooves, so that the surface roughness of the bottom surface and the side wall of the first trapezoidal grooves is greater than the surface roughness of the bottom surface and the side wall of the second trapezoidal grooves.

2. The method of claim 1, wherein the method further comprises: The epitaxial functional layer comprises a first semiconductor layer, a quantum well light emitting layer and a second semiconductor layer arranged in layers.

3. The method of claim 2, wherein the method further comprises forming a passivation layer on the surface of the LED chip. The semiconductor light emitting wafer further comprises a back metal electrode layer arranged on the back surface of the semiconductor light emitting wafer and an array of surface electrode blocks arranged on the surface of the epitaxial functional layer.

4. The method of claim 3, wherein the method further comprises forming a passivation layer on the surface of the LED chip. Each light emitting diode chip comprises one surface electrode block and one back metal electrode.

5. The method of claim 1, wherein the LED chip is formed on a substrate. Further comprising: Passivation is performed on the side surface of the light emitting diode chip to form a passivation layer covering the bottom surface and the side wall of the first trapezoidal grooves and the second trapezoidal grooves.

6. The method of claim 1, wherein the LED chip is formed on a substrate. From the front surface of the light emitting diode chip, the first trapezoidal grooves are upper wide and lower narrow trapezoidal grooves, and the second trapezoidal grooves are upper narrow and lower wide trapezoidal grooves.

7. The method of claim 1, wherein the LED chip is formed on a substrate. The bottom surface area of the first trapezoidal grooves is greater than the bottom surface area of the second trapezoidal grooves.

8. A light emitting diode chip, characterized by The light emitting diode chip is prepared by the preparation method of the light emitting diode chip according to any one of claims 1-7, the light emitting diode chip comprises a substrate and an epitaxial functional layer on the substrate, the side surface of the light emitting diode chip comprises first trapezoidal grooves and second trapezoidal grooves arranged alternately, and the surface roughness of the bottom surface and the side wall of the first trapezoidal grooves is greater than the surface roughness of the bottom surface and the side wall of the second trapezoidal grooves.

9. An LED package, characterized by, The LED package comprises a packaging substrate, a plurality of light emitting diode chips according to claim 8 arranged on the packaging substrate, and a packaging layer wrapping the plurality of light emitting diode chips.

10. The LED package of claim 9, wherein, The packaging layer comprises a packaging gel and a phosphor.

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