Output impedance calibration method, circuit and integrated circuit product

Abstract

The disclosure provides an output impedance calibration method, circuit and integrated circuit product, and relates to the technical field of integrated circuits. The method comprises the following steps: in response to the conduction of a first branch in a plurality of parallel branches, determining a first output impedance of a product to be tested, the first output impedance comprising a first resistance of the first branch and a first contact resistance caused by probe testing; in response to the conduction of a second branch in the plurality of parallel branches, determining a second output impedance of the product to be tested, the second output impedance comprising a second resistance of the second branch and the first contact resistance, the second resistance having a different resistance value from the first resistance; and determining the first contact resistance according to the first output impedance and the second output impedance. The above scheme can improve the calibration accuracy of the output impedance.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to an output impedance calibration method, an output impedance calibration circuit, and an integrated circuit product. BACKGROUND

[0002] In a memory chip, the output impedance of a driving circuit is a key indicator affecting the performance of the memory, and the precision of the output impedance of the driving circuit is extremely high. Generally, a part of trim bits is reserved, and the output impedance is adjusted through test results to eliminate the process influence.

[0003] In the related art, when testing the output impedance of an integrated circuit product such as KGD (KGD is a known good die or a good die) by testing the output impedance of the integrated circuit product, due to the uncertainty of the probe contact resistance, it is difficult to obtain a suitable output impedance through the trim bits, which greatly affects the performance of the integrated circuit product. SUMMARY

[0004] The present disclosure provides an output impedance calibration method, circuit and integrated circuit product, which at least partially overcomes the problem of low output impedance precision in the related art KGD test by the probe method, which affects the performance of the integrated circuit product.

[0005] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0006] According to one aspect of the present disclosure, an output impedance calibration method is provided for calibrating the contact resistance caused by probe testing, the method comprising: determining a first output impedance of a product to be tested in response to a first branch of a plurality of parallel branches being turned on, wherein the first branch is electrically connected to a power supply and a test power supply, and the first output impedance comprises a first resistance of the first branch and a first contact resistance caused by probe testing; determining a second output impedance of the product to be tested in response to a second branch of the plurality of parallel branches being turned on, wherein the second branch is electrically connected to the power supply and the test power supply, and the second output impedance comprises a second resistance of the second branch and the first contact resistance caused by probe testing, and the second resistance has a different resistance value from the first resistance; and determining the first contact resistance according to the first output impedance and the second output impedance.

[0007] In one embodiment of the present disclosure, the parallel branch includes a plurality of parallel pull-up branches, the plurality of parallel pull-up branches are electrically connected with the first power supply through the first probe test component, the plurality of parallel pull-up branches are electrically connected with the test power supply through the second probe test component, the first contact resistance includes a contact resistance of the first probe test component and / or a contact resistance of the second probe test component; or the parallel branch includes a plurality of parallel pull-down branches, the plurality of parallel pull-down branches are electrically connected with the second power supply through the third probe test component, the plurality of parallel pull-down branches are electrically connected with the test power supply through the second probe test component; the first contact resistance includes a contact resistance of the third probe test component and / or a contact resistance of the second probe test component.

[0008] In one embodiment of the present disclosure, the method further includes: controlling the plurality of parallel branches of the product under test to be turned on, and adjusting resistance values of the plurality of parallel branches to determine the output impedance of the product under test according to the first contact resistance.

[0009] In one embodiment of the present disclosure, the plurality of parallel pull-up branches are electrically connected with a first node, the first node is electrically connected with a first end of a self-calibration resistance through a fourth probe test component, a second end of the self-calibration resistance is electrically connected with a third power supply, the first node is electrically connected with a first input end of a first comparator, and a second input end of the first comparator is used to input a first reference voltage value; the method further includes: controlling the plurality of parallel pull-up branches and the self-calibration resistance to be turned on, so that a first self-calibration loop formed by the plurality of parallel pull-up branches and the self-calibration resistance in series is electrically connected between the first power supply and the third power supply, wherein a voltage value of the third power supply is less than a voltage value of the first power supply; adjusting the first reference voltage value of the first comparator and the resistance values of the plurality of parallel pull-up branches to adjust an output impedance of the first self-calibration loop to a first target value, wherein the first target value is determined according to a resistance value of the self-calibration resistance, a contact resistance of the first probe test component and a contact resistance of the fourth probe test component.

[0010] In one embodiment of the present disclosure, the plurality of parallel pull-up branches are connected in series with the plurality of parallel pull-down branches through the first node to form a second self-calibration loop, the first node is electrically connected with a first input terminal of a second comparator, and a second input terminal of the second comparator is used to input a second reference voltage value; after the first reference voltage value of the first comparator and the resistance values of the plurality of parallel pull-up branches are adjusted to adjust the output impedance of the first self-calibration loop to a first target value, the method further comprises: controlling the second self-calibration loop to be turned on so that the second self-calibration loop is electrically connected between the first power supply and the second power supply; and adjusting the second reference voltage value of the second comparator and the resistance values of the plurality of parallel pull-down branches to adjust the output impedance of the second self-calibration loop to a second target value, wherein the second target value is determined according to the resistance value of the self-calibration resistor, the contact resistance of the fourth probe test component, and the contact resistance of the second probe test component.

[0011] In one embodiment of the present disclosure, the contact resistance calibration circuit comprises a first self-calibration pull-down branch and a second self-calibration pull-down branch connected in parallel, one end of the first self-calibration pull-down branch and the second self-calibration pull-down branch connected in parallel is electrically connected with the first node, and the other end of the first self-calibration pull-down branch and the second self-calibration pull-down branch connected in parallel is electrically connected with the second power supply; the method further comprises: controlling the voltage value of the third power supply to be the same as the voltage value of the first power supply and the first self-calibration pull-down branch to be turned on, so that the first self-calibration pull-down branch is connected in series with the self-calibration resistor between the third power supply and the second power supply; determining a first total resistance value of the contact resistance calibration circuit; controlling the voltage value of the third power supply to be the same as the voltage value of the first power supply and the first self-calibration pull-down branch and the second self-calibration pull-down branch to be turned on, so that the first self-calibration pull-down branch and the second self-calibration pull-down branch connected in parallel are connected in series with the self-calibration resistor between the third power supply and the second power supply; determining a second total resistance value of the contact resistance calibration circuit; and determining the contact resistance of the fourth probe test component according to the first total resistance value and the second total resistance value.

[0012] In one embodiment of the present disclosure, the contact resistance calibration circuit further comprises a first self-calibration pull-up branch and a second self-calibration pull-up branch connected in parallel, one end of the first self-calibration pull-up branch and the second self-calibration pull-up branch connected in parallel is electrically connected to the first power supply, and the other end of the first self-calibration pull-up branch and the second self-calibration pull-up branch connected in parallel is electrically connected to the first node; the method further comprises: controlling the voltage value of the third power supply to be the same as the voltage value of the second power supply and the first self-calibration pull-up branch to be turned on, so that the first self-calibration pull-up branch and the self-calibration resistor are connected in series between the third power supply and the first power supply, and the third total resistance value of the contact resistance calibration circuit is determined; controlling the voltage value of the third power supply to be the same as the voltage value of the second power supply and the first self-calibration pull-up branch and the second self-calibration pull-up branch to be turned on, so that the first self-calibration pull-up branch and the second self-calibration pull-up branch connected in parallel and the self-calibration resistor are connected in series between the third power supply and the first power supply; the fourth total resistance value of the contact resistance calibration circuit is determined; and the contact resistance of the first probe test component and the contact resistance of the fourth probe test component during self-calibration are determined according to the third total resistance value and the fourth total resistance value.

[0013] In one embodiment of the present disclosure, the resistance of at least one circuit in the first self-calibration pull-up branch, the second self-calibration pull-up branch, the first self-calibration pull-down branch and the second self-calibration pull-down branch is provided by a metal resistor.

[0014] According to another aspect of the present disclosure, an output impedance calibration circuit for calibrating contact resistance caused by probe testing is provided, the circuit comprising: a plurality of parallel branches connected between a power supply and a test power supply; a gear control circuit for, in response to a first branch in the plurality of parallel branches being turned on, electrically connecting the first branch to the power supply and the test power supply to determine a first output impedance of a product under test, wherein the first output impedance comprises a first resistance of the first branch and a first contact resistance caused by probe testing; in response to a second branch in the plurality of parallel branches being turned on, electrically connecting the second branch to the power supply and the test power supply to determine a second output impedance of the product under test, wherein the second output impedance comprises a second resistance of the second branch and the first contact resistance caused by probe testing, and the second resistance has a different resistance value from the first resistance; and a contact resistance determination circuit for determining the first contact resistance according to the first contact resistance and the second output impedance.

[0015] In one embodiment of the present disclosure, the parallel branch includes a plurality of parallel pull-up branches, a first branch of the plurality of parallel pull-up branches is electrically connected to a first power supply through a first probe test component, the plurality of parallel pull-up branches is electrically connected to the test power supply through a second probe test component, the first contact resistance includes a contact resistance of the first probe test component and / or a contact resistance of the second probe test component; or the parallel branch includes a plurality of parallel pull-down branches, the plurality of parallel pull-down branches is electrically connected to a second power supply through a third probe test component, the plurality of parallel pull-down branches is electrically connected to the test power supply through a second probe test component; the first contact resistance includes a contact resistance of the third probe test component and / or a contact resistance of the second probe test component.

[0016] In one embodiment of the present disclosure, the output impedance calibration circuit further includes an impedance adjustment circuit electrically connected between the gear control circuit and the plurality of parallel branches, for controlling the plurality of parallel branches of the product under test to be turned on, adjusting the resistance value of the plurality of parallel branches, so as to determine the output impedance of the product under test according to the first contact resistance.

[0017] In one embodiment of the present disclosure, the gear control circuit includes a first gear control unit for selecting the pull-up branch to be turned on, the first gear control unit includes a plurality of AND gates, a first input end of each AND gate is used for inputting a selection signal, a second input end of each AND gate is used for inputting test data, an output end of each AND gate is electrically connected to an impedance adjustment circuit, for outputting a pull-up branch selection instruction to the impedance adjustment circuit; the impedance adjustment circuit further includes a first impedance adjustment circuit for adjusting the impedance of the parallel pull-up branch, the first impedance adjustment circuit includes a plurality of NAND gates, a first input end of each NAND gate is used for inputting a pull-up impedance adjustment instruction, a second input end of each NAND gate is electrically connected to an output end of the first gear control unit, an output end of each NAND gate is electrically connected to the plurality of parallel pull-up branches, for outputting the pull-up impedance adjustment instruction to the plurality of parallel pull-up branches.

[0018] In one embodiment of the present disclosure, the gear control circuit comprises a second gear control unit for selecting the on state of the parallel pull-down branch, the second gear control unit comprising a plurality of OR gates, a first input end of each of the OR gates being configured to input a selection signal, a second input end of each of the OR gates being configured to input test data, and an output end of each of the OR gates being electrically connected to an impedance adjustment circuit and configured to output a pull-down branch selection instruction to the impedance adjustment circuit; the impedance adjustment circuit comprises a second impedance adjustment circuit for adjusting the impedance of the parallel pull-down branch, the second impedance adjustment circuit comprising a plurality of NOR gates, a first input end of each of the NOR gates being configured to input a pull-down impedance adjustment instruction, a second input end of each of the NOR gates being electrically connected to the output end of the OR gate, and an output end of each of the NOR gates being electrically connected to the plurality of parallel pull-down branches and configured to output the pull-down impedance adjustment instruction to the plurality of parallel pull-down branches.

[0019] In one embodiment of the present disclosure, the output impedance correction circuit further comprises a self-calibration resistor, a first end of the self-calibration resistor being electrically connected to a first node through a fourth probe test component, a second end of the self-calibration resistor being electrically connected to a third power supply, and the first node being electrically connected to the plurality of parallel pull-up branches; a first comparator, a first input end of the first comparator being electrically connected to the first node, and a second input end of the first comparator being configured to input a first reference voltage value; an impedance adjustment circuit, further configured to control the plurality of parallel pull-up branches and the self-calibration resistor to be turned on, a first self-calibration loop formed by the plurality of parallel branches and the self-calibration resistor in series being electrically connected between the first power supply and the third power supply, and a voltage value of the third power supply being less than a voltage value of the first power supply; adjusting the first reference voltage value of the first comparator and the resistance value of the plurality of parallel pull-up branches to adjust the output impedance of the first self-calibration loop to a first target value, the first target value being determined according to the resistance value of the self-calibration resistor, the contact resistance of the first probe test component, and the contact resistance of the fourth probe test component.

[0020] In one embodiment of the present disclosure, the plurality of parallel pull-down branches are connected in series with the first node, and the plurality of parallel pull-down branches and the plurality of parallel pull-up branches are connected in series between the first power supply and the second power supply to form a second self-calibration loop; the output impedance correction circuit further comprises a second comparator, a first input terminal of the second comparator being electrically connected to the first node, and a second input terminal of the second comparator being configured to input a second reference voltage value; the impedance adjustment circuit is further configured to control the second self-calibration loop to be turned on, the second self-calibration loop being electrically connected between the first power supply and the second power supply; and the second reference voltage value of the second comparator and the resistance values of the plurality of parallel pull-down branches are adjusted to adjust the output impedance of the second self-calibration loop to a second target value, the second target value being determined according to the resistance value of the self-calibration resistor, the contact resistance of the fourth probe test component, and the contact resistance of the second probe test component.

[0021] In one embodiment of the present disclosure, the circuit further comprises a contact resistance calibration circuit comprising a first self-calibration pull-down branch and a second self-calibration pull-down branch connected in parallel, one end of the first self-calibration pull-down branch and the second self-calibration pull-down branch connected in parallel being electrically connected to the first node, and the other end of the first self-calibration pull-down branch and the second self-calibration pull-down branch connected in parallel being electrically connected to the second power supply; the contact resistance calibration circuit is configured to control the voltage value of the third power supply to be the same as the voltage value of the first power supply and the first self-calibration pull-down branch to be turned on, so that the first self-calibration pull-down branch and the self-calibration resistor are connected in series between the third power supply and the second power supply to determine a first total resistance value of the contact resistance calibration circuit; control the voltage value of the third power supply to be the same as the voltage value of the first power supply and the second self-calibration pull-down branch and the second self-calibration pull-down branch to be turned on, so that the first self-calibration pull-down branch and the second self-calibration pull-down branch connected in parallel and the self-calibration resistor are connected in series between the third power supply and the second power supply to determine a second total resistance value of the contact resistance calibration circuit; and determine the contact resistance of the fourth probe test component according to the first total resistance value and the second total resistance value.

[0022] In one embodiment of the present disclosure, the contact resistance calibration circuit further comprises: a first self-calibration pull-up branch and a second self-calibration pull-up branch connected in parallel, one end of the first self-calibration pull-up branch and the second self-calibration pull-up branch connected in parallel is electrically connected to the first power supply, and the other end of the first self-calibration pull-up branch and the second self-calibration pull-up branch connected in parallel is electrically connected to the first node; the contact resistance calibration circuit is configured to control the voltage value of the third power supply to be the same as the voltage value of the second power supply and the first self-calibration pull-up branch to be turned on, so that the first self-calibration pull-up branch and the self-calibration resistor are connected in series between the third power supply and the first power supply to determine a third total resistance value of the contact resistance calibration circuit; control the voltage value of the third power supply to be the same as the voltage value of the second power supply and the first self-calibration pull-up branch and the second self-calibration pull-up branch to be turned on, so that the first self-calibration pull-up branch and the second self-calibration pull-up branch connected in parallel and the self-calibration resistor are connected in series between the third power supply and the first power supply to determine a fourth total resistance value of the contact resistance calibration circuit; and determine the contact resistance of the first probe test component and the contact resistance of the fourth probe test component during self-calibration according to the third total resistance value and the fourth total resistance value.

[0023] In one embodiment of the present disclosure, the resistance of at least one circuit in the first self-calibration pull-up branch, the second self-calibration pull-up branch, the first self-calibration pull-down branch, and the second self-calibration pull-down branch is provided by a metal resistor.

[0024] According to another aspect of the present disclosure, an integrated circuit product is provided, comprising a product to be tested and the output impedance calibration circuit described above.

[0025] In an embodiment of the present disclosure, in response to the first branch of the plurality of parallel branches being turned on, the first branch is electrically connected to the power supply and the test power supply to determine a first output impedance of the product to be tested, the first output impedance comprising a first resistance of the first branch and a first contact resistance caused by probe testing; in response to the second branch of the plurality of parallel branches being turned on, the second branch is electrically connected to the power supply and the test power supply to determine a second output impedance of the product to be tested, the second output impedance comprising a second resistance of the second branch and the first contact resistance, the second resistance having a different resistance value from the first resistance; and the first contact resistance is determined according to the first output impedance and the second output impedance.

[0026] The above-mentioned embodiments have at least one or more of the following beneficial effects:

[0027] By setting multiple parallel branches, and controlling the first branch and the second branch in the multiple parallel branches to be turned on respectively, the corresponding first output impedance and the second output impedance are obtained by testing, and the contact resistance is determined according to the first output impedance and the second output impedance, so that the contact resistance between the probe and the pad can be accurately determined.

[0028] According to the accurately determined contact resistance, the output impedance of the product to be tested is calibrated, which can avoid the influence of the contact resistance caused by the probe test on the output impedance, and greatly improve the calibration accuracy of the output impedance of the product to be tested.

[0029] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0030] The drawings herein are incorporated into the specification and form part of the specification, show embodiments consistent with the present disclosure, and together with the specification serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained according to these drawings without creative labor for those skilled in the art.

[0031] Figure 1 A schematic diagram of the contact resistance of the probe during KGD test of the product to be tested provided by the embodiment of the present disclosure is shown.

[0032] Figure 2 A structural schematic diagram of an output impedance calibration circuit provided by the embodiment of the present disclosure is shown.

[0033] Figure 3 A structural schematic diagram of multiple parallel branches provided by the embodiment of the present disclosure is shown.

[0034] Figure 4 A structural schematic diagram of another output impedance calibration circuit provided by the embodiment of the present disclosure is shown.

[0035] Figure 5 A structural schematic diagram of the series connection of the parallel pull-up branch and the parallel pull-down branch provided by the embodiment of the present disclosure is shown.

[0036] Figure 6 A structural schematic diagram of an output impedance calibration circuit with an added self-calibration resistance provided by the embodiment of the present disclosure is shown.

[0037] Figure 7 A structural schematic diagram of another output impedance calibration circuit with an added self-calibration resistance provided by the embodiment of the present disclosure is shown.

[0038] Figure 8(a) shows a structural schematic diagram of a self-calibration loop provided by the embodiment of the present disclosure.

[0039] FIG. 8(b) shows a structural schematic diagram of another self-calibration loop provided by an embodiment of the present disclosure.

[0040] Figure 9 FIG. 8(b) shows a structural schematic diagram of another self-calibration loop provided by an embodiment of the present disclosure.

[0041] Figure 10 FIG. 8(b) shows a structural schematic diagram of another self-calibration loop provided by an embodiment of the present disclosure.

[0042] Figure 11 FIG. 8(b) shows a structural schematic diagram of another self-calibration loop provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] The preferred embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. Although the preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided so as to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0044] The terms "first", "second", etc. in the present disclosure are only for the purpose of description, and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified.

[0045] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0046] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeatedly refer to numbers and / or letters in different examples. Such repetition is for the purpose of simplification and clarity, and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0047] In memory chips, the output impedance of integrated circuit products needs to be matched with the transmission impedance of transmission lines to reduce the impact of reflection on signal quality. The output impedance of integrated circuit products is a parameter with extremely high precision requirements for driving circuits, and the higher the signal transmission rate, the more stringent the requirements for output impedance.

[0048] Output impedance is typically significantly affected by the manufacturing process. To mitigate the impact of the process on the output impedance of integrated circuit products, trim bits are usually reserved during circuit design. The output impedance of the integrated circuit product is then adjusted based on the KGD (Known Good Die) test results. Each individual small piece on a wafer is a wafer particle; after being cut, it becomes a die.

[0049] For wafer-level integrated circuit products, during KGD testing, the entire wafer (product under test) is placed on a test board. Contact probes extending from the test board make contact with the pads of the product under test, providing corresponding potential information, and the output impedance is measured. Currently, due to the testing process, there is a contact resistance between the probe and the pad that varies in magnitude, typically ranging from a few ohms to tens of ohms. In practice, this contact resistance varies due to differences in probe wear, contact force, and angle. Because of the uncertainty in the probe contact circuit during KGD testing, the method of obtaining an output impedance through trim bits in related technologies is not very accurate.

[0050] like Figure 1 As shown, in related technologies, when testing KGD, the first power pad of the product under test (DUT) is electrically connected to the first power supply VDDQ via a probe, and the input / output I / O pads are connected to the test power supply (0.5) via probes. The second power pad is electrically connected to the second power supply (VDDQ) via a probe, and the second power pad is electrically connected to the second power supply (VSS) via a probe. For example, the product under test (DUT) has power pads and input / output (I / O) pads. The power pads of the DUT are electrically connected to the power supply via a probe, and the I / O pads of the DUT are electrically connected to the test power supply via a probe.

[0051] Due to the influence of probe contact resistance, the output impedance will be... Adjust to the target resistance value Afterwards, the output impedance of the product under test should be:

[0052]

[0053] or

[0054] (Formula 1)

[0055] wherein, the actual output impedance of the product under test, is the contact resistance between the probe and the I / O pad, is the contact resistance between the probe and the first power pad, is the contact resistance between the probe and the second power pad. In an ideal state, the target impedance value should be ; without the contact resistance. The contact resistance only exists when testing the KDG; in the actual application after the product is shipped, there is no contact resistance as described above. Therefore, the actual output impedance of the circuit product is smaller than the target impedance value by the contact resistance . Since the size of the contact resistance , , obtained in the test is a non-fixed value, the measured value is affected by factors such as the force and direction of the probe when testing the KGD probe, and the measured value is usually between a few ohms and tens of ohms, so the estimated contact resistance is not accurate.

[0056] For DDR3 and DRAM products with higher speeds, in order to obtain more accurate output impedance, the chip usually has a built-in self-calibration circuit for output impedance to calibrate the output impedance to the target impedance value. However, due to process deviation, there is still a small amount of misadjustment error between the target impedance value after calibration by the self-calibration circuit and the actual value.

[0057] Therefore, some trim bits still need to be reserved during the circuit design stage, and the misadjustment of the self-calibration circuit of each chip is compensated for during the test stage. In order to obtain more accurate output impedance, manual adjustment is still needed during the test stage, and the adjustment process will also be affected by the contact resistance.

[0058] In order to at least partially solve the above technical problems, a circuit and method for testing the output impedance of KGD are provided, which can eliminate or reduce the influence of contact resistance on output impedance and improve the accuracy of output impedance, which is an urgent technical problem to be solved.

[0059] In the present disclosure, an output impedance calibration method is provided for calibrating the contact resistance caused by probe testing. In response to the conduction of a first branch of a plurality of parallel branches, the first branch is electrically connected to a power supply and a test power supply, and a first output impedance of a product under test is determined, the first output impedance including a first resistance of the first branch and a first contact resistance caused by probe testing. In response to the conduction of a second branch of the plurality of parallel branches, the second branch is electrically connected to the power supply and the test power supply, and a second output impedance of the product under test is determined, the second output impedance including a second resistance of the second branch and the first contact resistance, the second resistance having a different resistance value from the first resistance. The first contact resistance is determined according to the first output impedance and the second output impedance.

[0060] The first contact resistance refers to the contact resistance caused by the probe testing of the product under test (e.g., KGD).

[0061] The above embodiments have at least one or more of the following beneficial effects:

[0062] The present disclosure sets a plurality of parallel branches, and controls the conduction of a first branch and a second branch of the plurality of parallel branches respectively, and tests to obtain corresponding first output impedance and second output impedance, and determines the contact resistance according to the first output impedance and the second output impedance. Specifically, the first output impedance is the first resistance + the first contact resistance, where the first resistance is the resistance value of the first branch; similarly, the second output impedance is the second resistance + the first contact resistance, where the second resistance is the resistance value of the second branch; thereby the contact resistance can be determined more accurately compared with related art.

[0063] According to the accurate determination of the contact resistance and the target impedance value, the output impedance of the product under test can be calibrated to avoid the influence of the contact resistance caused by the probe testing on the output impedance, and the calibration accuracy of the output impedance of the product under test is greatly improved. The implementation manner is illustrated in subsequent embodiments of the present disclosure.

[0064] In all embodiments of the present disclosure, "connection" or "electrical connection" means that two components or circuits are electrically connected, i.e., they can be directly connected or electrically connected through other components or circuits.

[0065] In order to facilitate the understanding of the output impedance calibration method, the output impedance calibration circuit used by the method will be described in detail below.

[0066] Figure 2 An example of an output impedance calibration circuit provided by an embodiment of the present disclosure is shown in the structure schematic diagram. As shown in the figure, Figure 2As shown, in one embodiment, the present disclosure provides an output impedance calibration circuit for calibrating an output impedance of a device under test (DUT). In one possible implementation, the DUT has a power supply pad and an input / output (I / O) pad, the power supply pad of the DUT is electrically connected to a power supply through a probe, and the I / O pad of the DUT is electrically connected to a test power supply through a probe. The first probe test component can be a first power supply pad and a first probe, and the first power supply pad and the first probe are electrically connected to the first power supply. The second probe test component can be an I / O pad and a second probe, and the I / O pad and the second probe are electrically connected to the test power supply. The output impedance calibration circuit includes:

[0067] a plurality of parallel branches 230 connected between the power supply and the test power supply;

[0068] a gear control circuit 210 configured to determine a first output impedance of the DUT in response to a first branch of the plurality of parallel branches 230 being turned on, wherein the first branch is electrically connected between the power supply and the test power supply, and the first output impedance includes a first resistance of the first branch and a first contact resistance caused by the probe test; and determine a second output impedance of the DUT in response to a second branch of the plurality of parallel branches 230 being turned on, wherein the second branch is electrically connected between the power supply and the test power supply, and the second output impedance includes a second resistance of the second branch and the first contact resistance, and the second resistance has a different resistance value than the first resistance.

[0069] a contact resistance determination circuit 220 configured to determine the first contact resistance based on the first contact resistance and the second output impedance.

[0070] The gear control circuit 210 controls the first branch and the second branch of the plurality of parallel branches 230 to be turned on respectively, and is configured to determine the first output impedance of the DUT in the state that the first branch of the plurality of parallel branches 230 is turned on, and determine the second output impedance of the DUT in the state that the second branch of the plurality of parallel branches 230 is turned on, wherein the second output impedance includes the second resistance and the first contact resistance, and the second resistance has a different resistance value than the first resistance.

[0071] In one embodiment, the power supply can include a first power supply VDDQ and a second power supply VSS, the first power supply VDDQ can be a voltage source for providing a voltage value required for normal operation of the DUT, and the second power supply VSS can be a reference potential or ground GND, and the voltage value of the second power supply VSS is less than the voltage value of the first power supply VDDQ. The type of the first power supply VDDQ and the second power supply VSS is not limited in the present disclosure.

[0072] The voltage value of the measured power supply output is between the voltage values of the first power supply VDDQ and the second power supply VSS, for example, the voltage value of the test power supply output is 0.5 The present disclosure does not make specific limitations on the value of the measured voltage value of the power supply output.

[0073] The number of branches in the parallel branch 230 can be determined according to actual needs, for example, the parallel branch 230 includes the first branch and the second branch, and can also include other parallel branches. The resistance values of the resistors in each parallel branch 230 can be the same or different. However, it should be noted that when implementing the technical solutions of the present disclosure, the ratio of the resistance value of the first resistor in the first branch to the resistance value of the second resistor in the second branch is not equal to 1; that is, the resistance value of the first resistor in the first branch is not the same as the resistance value of the second resistor in the second branch.

[0074] In one embodiment, the resistor in one or each of the plurality of parallel branches 230 can be provided by a plurality of parallel-connected transistors, or can be obtained by connecting a resistor unit in series after parallel connection of a plurality of transistors. The resistor unit can be composed of a plurality of series-parallel resistors, or can be obtained by series-parallel connection of a plurality of self-biased transistors.

[0075] When one of the plurality of parallel branches 230 is connected between the first power supply VDDQ and the test power supply, the parallel branch is determined as a parallel pull-up branch; when one of the plurality of parallel branches is connected between the second power supply VSS and the test power supply, the parallel branch is determined as a parallel pull-down branch; wherein the parallel pull-up branch and the parallel pull-down branch are connected in series between the first power supply VDDQ and the second power supply VSS.

[0076] The first branch refers to a branch for calibrating the output impedance of the product DUT to be tested. After the output impedance of the first branch is calibrated, it can represent the output impedance of the product DUT to be tested. The first branch can also be any one of the plurality of parallel branches 230, or can be at least one parallel branch configured in advance.

[0077] The second branch refers to a branch arranged for determining the contact resistance. The second branch can be one or more parallel branches in the plurality of parallel branches 230 except the first branch, or can be at least two parallel branches including the first branch in the plurality of parallel branches. When the second branch includes a plurality of parallel branches, the second resistance is the parallel resistance value of the plurality of parallel branches.

[0078] It should be noted that the ratio of the resistance value of the first resistor to the resistance value of the second resistor is not equal to 1 (i.e., the resistance value of the first resistor is not the same as the resistance value of the second resistor), so as to ensure the calculation accuracy of the first contact resistance.

[0079] For example, the first resistance has a resistance value of 2 times of the second resistance, or the first resistance has a resistance value of 0.5 times of the second resistance, etc., which facilitates the calculation of the first contact resistance.

[0080] The first branch and the second branch are connected between the power supply and the test power supply, and when the voltage value output by the test power supply is unchanged, the first contact resistance includes a contact resistance between the probe and the power supply and / or a contact resistance between the probe and the I / O pad.

[0081] Based on the multiple relationship between the resistance value of the first resistance and the resistance value of the second resistance and the size of the measured first output impedance and the second output impedance, the first contact resistance can be determined. For example, the first contact resistance can be calculated by the following formula 4 or formula 4' or formula 7.

[0082] The contact resistance determination circuit 220 can be a circuit in a chip or a server for calculating the first contact resistance based on the formula 4 or formula 4' or formula 7 for the first output impedance and the second output impedance, which is not specifically limited in the present disclosure.

[0083] For wafer-level integrated circuit products, the output impedance of the wafer-level integrated circuit product can be calibrated as the sum of the first contact resistance and the target impedance value. Of course, after the first contact resistance is determined, the actual output impedance of the product to be tested can be determined in any way .

[0084] For integrated circuit products such as DDR3 and higher-speed DRAM, in addition to the first contact resistance, the contact resistance of the self-calibration circuit also needs to be considered, and the output impedance of the integrated circuit product needs to be calibrated based on the first contact resistance and the contact resistance of the self-calibration circuit.

[0085] In the embodiments of the present disclosure, by setting a plurality of parallel branches 230 and controlling the first branch and the second branch in the plurality of parallel branches 230 to be turned on respectively, the corresponding first output impedance and the second output impedance are determined, and the contact resistance between the probe and the pad is determined according to the first output impedance and the second output impedance, so that the contact resistance between the probe and the pad can be accurately determined. The scheme of the embodiments of the present disclosure can reduce or avoid the influence of the probe contact resistance on the output impedance, and greatly improve the calibration accuracy of the output impedance of the product to be tested.

[0086] For example, the first resistance has a resistance value of 2 times of the second resistance, or the first resistance has a resistance value of 0.5 times of the second resistance, etc., which facilitates the calculation of the first contact resistance. Figure 3 and Figure 4As shown, the parallel branch 230 includes a plurality of parallel pull-up branches 231, the plurality of parallel pull-up branches 231 are electrically connected with the first power supply VDDQ through the first probe test component, the plurality of parallel pull-up branches 231 are electrically connected with the test power supply through the second probe test component, and the first contact resistance includes the contact resistance of the first probe test component and / or the contact resistance of the second probe test component.

[0087] With reference to the foregoing Figure 3 and Figure 4 As shown, the parallel branch 230 includes a plurality of parallel pull-up branches 231, the plurality of parallel pull-up branches 231 are electrically connected with the first power supply VDDQ through the first probe test component, the plurality of parallel pull-up branches 231 are electrically connected with the test power supply through the second probe test component, and the first contact resistance includes the contact resistance of the first probe test component and / or the contact resistance of the second probe test component.

[0088] The first probe test component can include but is not limited to a first probe and a first power supply pad. The second probe test component can include but is not limited to a second probe and an I / O pad. The third probe test component can include but is not limited to a third probe and a second power supply pad. Each parallel pull-up branch 231 includes a plurality of parallelly connected pull-up transistors, and the resistance of the parallel pull-up branch 231 can be adjusted by adjusting the number of pull-up transistors. Each parallel pull-down branch 232 includes a plurality of parallelly connected pull-down transistors, and the resistance of the parallel pull-down branch 232 can be adjusted by adjusting the number of pull-down transistors.

[0089] The following will take two parallel branches as an example to illustrate the process of determining the first contact resistance through the parallel branch 230.

[0090] When measuring the output impedance of the DUT, the output impedance is divided into two parallel branches, and the impedance calibration is controlled to be turned on through a switch. As shown, Figure 3 As shown, the output impedance calibration circuit includes two parallel pull-up branches 231 and two parallel pull-down branches 232, wherein one parallel pull-up branch 231 includes a first pull-up resistor RPU in series with a first pull-up switch SW1_1, defined as a first parallel pull-up branch, and the other parallel pull-up branch 231 includes a second pull-up resistor RPU in series with a second pull-up switch SW1_2, defined as a second parallel pull-up branch; one parallel pull-down branch 232 includes a first pull-down resistor RPD in series with a first pull-down switch SW2_1, defined as a first parallel pull-down branch, and the other parallel pull-down branch 232 includes a second pull-down resistor RPD in series with a second pull-down switch SW2_2, defined as a second parallel pull-down branch.

[0091] ​​In one possible implementation, only the first pull-up switch SW1_1 is turned on, the first pull-up resistor 2 The RPU is electrically connected between the first power supply VDDQ and the test power supply, and a fixed voltage, such as 0.5 VDDQ, is provided at the I / O terminal through the test power supply. The current of the first pull-up resistor 2 RPU is measured, and the first output impedance of the first parallel pull-up branch is obtained, and is expressed as follows:

[0092] (Formula 2)

[0093] wherein, Zout1 is the first output impedance when the first parallel pull-up branch is turned on, 2 RPU is the resistance value of the first pull-up resistor, Rc2 is the contact resistance between the second probe and the I / O pad, that is, the contact resistance of the second probe test component, Rc1 is the contact resistance between the first probe and the first power supply pad, that is, the contact resistance of the first probe test component.

[0094] Then, only the second pull-up switch SW1_2 is turned on, the second pull-up resistor RPU is electrically connected between the first power supply VDDQ and the test power supply, and a fixed voltage, such as 0.5 VDDQ, is provided at the I / O terminal through the test power supply. The current of the second parallel pull-up branch is tested, and the second output impedance of the second parallel pull-up branch is obtained, and is expressed as follows:

[0095] (Formula 3)

[0096] wherein, Zout2 is the second output impedance when the second parallel pull-up branch is turned on;

[0097] According to Formula 2 and Formula 3, the following is obtained:

[0098] (Formula 4)

[0099] That is, the first contact resistance is obtained through Formula 4, and the first contact resistance is the sum of the contact resistance of the first probe test component and the contact resistance of the second probe test component.

[0100] In another possible implementation, the output impedance of Formula 3 can be obtained by turning on the second pull-up switch SW1_2, and the first pull-up switch SW1_1 and the second pull-up switch SW1_2 can also be turned on at the same time. The first pull-up resistor 2 RPU and the second pull-up resistor RPU are connected in parallel between the first power supply VDDQ and the test power supply, a fixed voltage is provided at the I / O end through the test power supply, and the current of the second parallel pull-up branch is tested, so that the output impedance of the second parallel pull-up branch is measured, which is represented as:

[0101] (Formula 2')

[0102] According to formula 3 and formula 2', the following can be obtained:

[0103] (Formula 4')

[0104] That is, the first contact resistance is also obtained through formula 4', and the first contact resistance is the sum of the contact resistance of the first probe test component and the contact resistance of the second probe test component.

[0105] It should be noted that in addition to the above-mentioned method of determining the first contact resistance by connecting two parallel pull-up branches to the first power supply and the test power supply respectively, the first contact resistance can also be calculated by appropriately adjusting the number of parallel pull-up branches. The above-mentioned method is also within the protection scope of the present disclosure, and similar parts will not be described again.

[0106] For the scheme of calibrating the pull-down resistance RPD, similarly to the method of calibrating the pull-up resistance, the first pull-down switch SW2_1 is first turned on, the first pull-down resistance RPD is connected between the test power supply and the second power supply VSS, a fixed voltage is provided at the I / O end through the test power supply, and the current of the first parallel pull-down branch is tested, so that the output impedance of the first parallel pull-down branch is measured, which is represented as: RPD is connected between the test power supply and the second power supply VSS, a fixed voltage is provided at the I / O end through the test power supply, and the current of the first parallel pull-down branch is tested, so that the output impedance of the first parallel pull-down branch is measured, which is represented as:

[0107] (Formula 5)

[0108] wherein, is the third output impedance when the first parallel pull-down branch is turned on, is the resistance value of the first pull-down resistance, is the contact resistance between the second probe and the I / O pad, that is, the contact resistance of the second probe test component, is the contact resistance between the third probe and the second power supply pad, that is, the contact resistance of the third probe test component.

[0109] The second pull-down switch SW2_2 is then turned on, the second pull-down resistance RPD is connected between the test power supply and the second power supply VSS, a fixed voltage is provided at the I / O end through the test power supply, and the current of the second parallel pull-down branch is tested, so that the output impedance of the second parallel pull-down branch is measured, which is represented as:

[0110] (Formula 6)

[0111] wherein, is a fourth output impedance when the second parallel pull-down branch is turned on;

[0112] According to the formula 5 and the formula 6, we have:

[0113] (Formula 7)

[0114] That is, the first contact resistance is obtained by the formula 7, and the first contact resistance is the sum of the contact resistance of the second probe testing component and the contact resistance of the third probe testing component.

[0115] The plurality of parallel pull-down branches are determined in a similar manner to the plurality of parallel pull-up branches and the first contact resistance, which will not be described here.

[0116] In the embodiments of the present disclosure, by connecting different numbers of parallel branches 230 between the power supply and the test power supply in batches, the contact resistance between the probe and the power pad and the contact resistance between the probe and the I / O pad can be quickly and accurately determined, thereby improving the calibration accuracy of the output impedance of the product to be tested.

[0117] As shown in Figure 2 , in one embodiment, the circuit further comprises an impedance adjustment circuit 240 electrically connected between the gear control circuit 210 and the plurality of parallel branches 230, for controlling the plurality of parallel branches 230 of the product to be tested to be turned on, adjusting the resistance value of the plurality of parallel branches 230, and determining the output impedance of the product to be tested according to the first contact resistance.

[0118] As shown in Figure 4 , in one embodiment, the gear control circuit 210 comprises a first gear control unit 211 for selecting the on state of the parallel pull-up branch 231, wherein the first gear control unit 211 comprises a plurality of AND gates, the first input end of each AND gate is used for inputting a selection signal RPU_CTRL, the second input end of each AND gate is used for inputting test data DATAIN, and the output end of each AND gate is electrically connected with the impedance adjustment circuit 240, for outputting a pull-up branch selection instruction to the impedance adjustment circuit 240; the impedance adjustment circuit 240 comprises a first impedance adjustment circuit 241 for adjusting the impedance of the parallel pull-up branch 231, and the first impedance adjustment circuit 241 comprises a plurality of NAND gates, the first input end of each NAND gate is used for inputting a pull-up impedance adjustment instruction, the second input end of each NAND gate is electrically connected with the output end of the first gear control unit 211, and the output end of each NAND gate is electrically connected with the plurality of parallel pull-up branches 231, for outputting the pull-up impedance adjustment instruction to the plurality of parallel pull-up branches 231. ​

[0119] The number of AND gates, the number of NAND gates and the number of parallel pull-up branches 231 are the same, and the AND gate, the NAND gate and the parallel pull-up branch 231 are one-to-one corresponding. In Figure 4 In the first gear control unit 211, the output driving stage includes 4 parallel pull-up branches 231, which are parallel pull-up branches 0-3 respectively, the first gear control unit 211 includes four AND gates, the first impedance adjustment circuit 241 includes four NAND gates, the four AND gates control the opening or closing of the parallel pull-up branches 0-3 respectively, and the four NAND gates control the number of opening of each transistor in the parallel pull-up branches 0-3 respectively.

[0120] In the first contact resistance determination stage, the pull-up impedance adjustment instruction is invalid, the first input end of each AND gate is used to input the selection signal RPU_CTRL<3:0>, and the second input end is used to input the test data DATAIN. When RPU_CTRL<0> is high, the first branch selection instruction DRDPIT20 output by the first AND gate is also high, and the first branch selection instruction DRDPIT20 is still valid after passing through the first NAND gate. DRDPOB0<2:0> controls the conduction of the corresponding transistor in the parallel pull-up branch 0; when RPU_CTRL<3:1> is low, the first branch selection instruction DRDPIT21-DRDPIT23 output by the corresponding three AND gates is low, and after passing through the corresponding NAND gate, the output DRDPOB1-3<2:0> is invalid, and the parallel pull-up branches 1-3 are not conducted.

[0121] It should be noted that the pull-up impedance adjustment instruction can be valid only after the first contact resistance is determined, and the pull-up impedance adjustment instruction is an adjustment instruction generated according to the first contact resistance.

[0122] In the embodiment of the present disclosure, the branch selection instruction output by the AND gate can greatly simplify the circuit structure; the selection and adjustment of the parallel pull-up branch 231 are realized by combining the AND gate and the NAND gate, which further simplifies the control of the parallel pull-up branch 231 and improves the output impedance calibration efficiency.

[0123] Continuing to refer to Figure 4In one embodiment, the gear control circuit 210 includes a second gear control unit 212 for selecting the on state of the parallel pull-down branch 232, the second gear control unit 212 including a plurality of OR gates, each OR gate having a first input end for inputting a selection signal RPU_CTRL and a second input end for inputting test data DATAIN, and an output end electrically connected to the impedance adjustment circuit 240 for outputting a pull-down branch selection instruction to the impedance adjustment circuit 240; the impedance adjustment circuit 240 further includes a second impedance adjustment circuit 242 for impedance adjustment of the parallel pull-down branch 232, the second impedance adjustment circuit 242 including a plurality of NOR gates, each NOR gate having a first input end for inputting a pull-down impedance adjustment instruction and a second input end electrically connected to the output end of the OR gate, and an output end electrically connected to the plurality of parallel pull-down branches 232 for outputting the pull-down impedance adjustment instruction to the plurality of parallel pull-down branches 232.

[0124] It should be noted that the number of OR gates and the number of NOR gates are the same as the number of parallel pull-down branches 232, and the OR gates, the NOR gates and the parallel pull-down branches 232 are one-to-one corresponding. Figure 4 In the embodiment, the second gear control unit 212 includes four OR gates for controlling the on state of the four parallel pull-down branches (such as parallel pull-down branches 0-3), and the second impedance adjustment circuit 242 includes four NOR gates, when the first contact resistance of the pull-down branch is obtained, RPD_CTRL<0> and RPD_TRIM<0> are effective, so that the parallel pull-down branch 0 is turned on, and the corresponding transistors in the parallel pull-down branch 0 are turned on according to the pull-down impedance adjustment instruction DRDNOB0<2:0>, so as to realize the calibration of the output impedance of the pull-down branch.

[0125] In the embodiment of the present disclosure, the branch selection instruction is output by the OR gate, which can greatly simplify the circuit structure; the selection and impedance adjustment of the parallel pull-down branch 232 are realized by the combination of the OR gate and the NOR gate, which further simplifies the control of the parallel pull-down branch 232 and improves the output impedance calibration efficiency.

[0126] As shown in Figure 5 , for the parallel pull-up branch 231, seven PMOS transistors can be connected in parallel and then connected in series with a resistance unit to obtain a 2 RPU resistance value, wherein one PMOS transistor is controlled by DRDPOB<0>, two PMOS transistors are controlled by DRDPOB<1>, and four PMOS transistors are controlled by DRDPOB<2>.

[0127] As shown in Figure 5 , for the parallel pull-down branch 232, three NMOS transistors can be connected in parallel and then connected in series with a resistance unit to obtain a 2 The RPD resistance value is given by the fact that the three NMOS transistors are controlled by DRDNOB<2:0> respectively.

[0128] It should be noted that OR gates, NOR gates, and PMOS transistors can also be used as the control methods corresponding to pull-up branches, and correspondingly, AND gates, NAND gates, and NMOS transistors can be used as the control methods corresponding to pull-down branches. This disclosure does not make specific limitations in this regard.

[0129] In one embodiment, the output impedance calibration circuit of this disclosure can also be used in a high-speed memory chip. The high-speed memory chip has an output impedance self-calibration module (ZQ Calibration). The following description uses Double Data Rate Fourth Generation Synchronous Dynamic Random Access Memory (DDR4) as an example. When performing KGD testing on the DDR4 chip, the calibration method differs from that mentioned in the previous embodiments in order to eliminate the influence of contact resistance. The control signal for the output impedance self-calibration module is generated by the output impedance self-calibration module itself.

[0130] like Figure 6 As shown, the test voltage is 0.8. VDDQ; DDR4 probe contact resistance Including but not limited to the contact resistance between the probe and the first power pad Contact resistance between probe and I / O pad Contact resistance between the probe and the second power pad and the contact resistance between the probe and the self-calibrating pad. wait.

[0131] like Figure 7 As shown, the DDR4 is similar in structure to the level control circuit 210 and impedance adjustment circuit 240 in the aforementioned embodiments. The difference lies in the number of bits in the impedance adjustment command. This is because during self-calibration, multiple parallel pull-up branches 231 or multiple parallel pull-down branches 232 need to be turned on simultaneously so that the impedance adjustment command with more bits can control the turning on of all transistors in the multiple parallel pull-up branches 231 or multiple parallel pull-down branches 232.

[0132] It should be noted that high-speed memory chips are not allowed to perform self-calibration during the calculation of the first contact resistance, in order to prevent a reduction in calibration accuracy.

[0133] As shown in FIG. 8(a) and FIG. 8(b), for the output impedance self-calibration module, an additional self-calibration pad PAD:ZQ is needed, the self-calibration pad PAD:ZQ is connected with a 240 ohm ultra-high precision resistor R 标准 which is connected with the third power supply V3, also called external output impedance self-calibration module. The above-mentioned ultra-high precision resistor is defined as a standard resistor.

[0134] The structure of the output impedance self-calibration module is shown in FIG. 8(a), the external standard resistor R 标准 is connected with the internal four parallel pull-up branches 231 in parallel circuit voltage division, to obtain a voltage division VPAD_ZQ, and the VPAD_ZQ is compared with the first reference voltage value Vref_P, and in the ideal case, Vref_P=0.8 VDDQ, by adjusting ZQPU<4:0>, to adjust the resistance RPU of the four parallel pull-up branches 231, and then change the size of VPAD_ZQ, when VPAD_ZQ=Vref_P, that is, RPU=240Ω.

[0135] As shown in FIG. 8(b), the four parallel pull-up branches 231 and one parallel pull-down branch 232 are further divided by the calibrated, to obtain a second voltage division value VPD, and the second voltage division value VPD is compared with the second reference voltage value Vref_N, and in the ideal case, Vref_N=0.8 VDDQ, by adjusting ZQPD<4:0>, to adjust the resistance RPD of the one parallel pull-down branch 232, so as to change the size of the second voltage division value VPD. When VPD=Vref_N, that is, RPD=240Ω.

[0136] However, due to process deviation, the self-calibration system has random misadjustment, which causes the calibrated RPU and RPD not to be ideal 240Ω, which needs to be adjusted by test means to adjust the values of Vref_P and Vref_N to compensate for the random misadjustment of the self-calibration system, but in KGD test, due to the existence of contact resistance, additional error will be caused.

[0137] In one embodiment, the output impedance calibration circuit of the present disclosure further comprises:

[0138] a self-calibration resistor R 标准 , a first end of the self-calibration resistor R 标准 is electrically connected with the first node N1 through the fourth probe test component, and a second end of the self-calibration resistor R 标准 is electrically connected with the third power supply V3, and the first node N1 is electrically connected with the plurality of parallel pull-up branches 231;

[0139] The first comparator 250 has a first input electrically connected to the first node N1, and a second input for inputting a first reference voltage value Vref_P.

[0140] The impedance adjustment circuit 240 is further configured to control the plurality of parallel pull-up branches 231 and the self-calibration resistance R 标准 to be turned on, and the plurality of parallel pull-up branches 231 and the self-calibration resistance R 标准 The first self-calibration loop formed by the plurality of parallel pull-up branches 231 and the self-calibration resistance R 标准 is electrically connected between the first power supply VDDQ and a third power supply V3, the third power supply V3 has a voltage value smaller than that of the first power supply VDDQ; the first reference voltage value of the first comparator 250 and the resistance values of the plurality of parallel pull-up branches 231 are adjusted to adjust the output impedance of the first self-calibration loop to a first target value, which is determined according to the resistance value of the self-calibration resistance R 标准 , the contact resistance of the first probe test component, and the contact resistance of the fourth probe test component.

[0141] The output impedance of the first self-calibration loop can be adjusted to the first target value by adjusting the first reference voltage value Vref_P and the number of turned-on pull-up transistors of each parallel pull-up branch 231.

[0142] The fourth probe test component can include but is not limited to a fourth probe and a self-calibration pad, the self-calibration resistance R 标准 is an external 240-ohm high-precision standard resistance, one end of the standard resistance is electrically connected to the first node N1 through the fourth probe and the self-calibration pad, and the other end of the standard resistance is electrically connected to the third power supply V3, so that the self-calibration resistance R 标准 is connected in series between the first power supply VDDQ and the third power supply V3.

[0143] When the pull-up output impedance RPU is calibrated in the KGD test, the gear control circuit 210 is adjusted to first turn on the first parallel pull-up branch, control the test power supply to provide a fixed voltage through the I / O pad, and test the current of the first parallel pull-up branch to determine the output impedance R of the first parallel pull-up branch, which is expressed as:

[0144] (Formula 8)

[0145] wherein, R1 is the resistance value of the first parallel pull-up branch, R2 is the contact resistance of the second probe test component, and R3 is the contact resistance of the first probe test component.

[0146] If the adjusted first reference voltage value Vref_P has a value such that . Since there is also a contact resistance between the self-calibration pad and the fourth probe, and the RPU calibration turns on 4 parallel pull-up branches 231, we can get:

[0147] (Formula 9)

[0148] wherein, is the contact resistance of the fourth probe test component, is the contact resistance of the first probe test component in the self-calibration process, .

[0149] In actual application, the self-calibration pad does not have probe contact resistance, so according to Formula 9 we can get:

[0150] (Formula 10)

[0151] (Formula 11)

[0152] Then we get:

[0153]

[0154] Therefore, in the KGD test, when the pull-up resistance RPU is calibrated, Vref_P and the resistance value of the plurality of parallel pull-up branches 231 (for example, the number of turned-on transistors in each parallel pull-up branch 231) can be adjusted so that the first target value is:

[0155]

[0156] wherein, the above is the resistance value of the self-calibration resistance R 标准 , and can be determined by respectively controlling different parallel pull-up branches 231 to be turned on, and can be measured by the contact resistance calibration circuit 270 in Figure 10 , and the specific measurement method will be described later.

[0157] In the embodiments of the present disclosure, when the pull-up resistance RPU is calibrated in the KGD test, by considering the influence of the first contact resistance and the contact resistance introduced in the self-calibration process, the influence of the contact resistance caused by the probe test is effectively avoided, and the calibration accuracy of the pull-up resistance RPU can be further improved.

[0158] With reference back to Fig. 8(b), in one embodiment, the plurality of parallel pull-down branches 232 are electrically connected to the first node N1, and the plurality of parallel pull-down branches 232 are connected in series with the plurality of parallel pull-up branches 231 between the first power supply VDDQ and the second power supply VSS, forming a second self-calibration loop; the output impedance calibration circuit of the present disclosure further comprises:

[0159] a second comparator 260, a first input terminal of the second comparator 260 is electrically connected to the first node N1, and a second input terminal of the second comparator 260 is used for inputting a second reference voltage value Vref_N;

[0160] The impedance adjustment circuit 240 is further used for controlling the second self-calibration loop to be turned on, the second self-calibration loop is electrically connected between the first power supply VDDQ and the second power supply VSS, the second reference voltage value Vref_N of the second comparator 260 and the resistance value of the plurality of parallel pull-down branches 232 are adjusted, and the output impedance of the second self-calibration loop is adjusted to a second target value, the second target value is determined according to the resistance value of the self-calibration resistance R 标准 , the contact resistance of the fourth probe test component and the contact resistance of the second probe test component.

[0161] The output impedance of the second self-calibration loop can be adjusted to the second target value by adjusting the second reference voltage value Vref_N and the opening number of the pull-down transistor of each parallel pull-down branch.

[0162] When the KGD test calibrates the pull-down resistance RPD, the gear adjustment circuit 210 is adjusted, the first parallel pull-down branch is first opened, the test power supply is controlled to provide a fixed voltage to the I / O pad in a test current mode, and the output impedance of the first parallel pull-down branch is measured as:

[0163] (Formula 13)

[0164] wherein, Rpd is the resistance value of the first parallel pull-down branch, Rc2 is the contact resistance between the second probe and the I / O pad, that is, the contact resistance of the second probe test component, Rc3 is the contact resistance between the third probe and the second power supply pad, that is, the contact resistance of the third probe test component.

[0165] If the value of the second reference voltage value Vref_N is adjusted so that .

[0166] When the KGD test calibrates the first pull-up resistance RPU, the following is obtained:

[0167] .

[0168] At this time, the output impedance of one parallel pull-down branch is:

[0169] .

[0170] Since the pull-down resistance RPD calibration is obtained by the pull-up resistance RPU calibration, and the RPU calibration opens four parallel pull-up branches 231, therefore:

[0171] (Formula 14)

[0172] In the actual KGD test of DDR4, the second power pad will have many pad probes, so the contact resistance of the second power pad can be ignored.

[0173] In actual application, the ZQ terminal does not exist probe contact resistance, therefore, formula 14 can be further simplified as:

[0174] (Formula 15)

[0175] Therefore:

[0176]

[0177] Therefore, in the KGD test, the second reference voltage value Vref_N should be adjusted so that . Wherein, the above 240 is the resistance value of the self-calibration resistance R 标准 . By respectively controlling different parallel pull-up branches 231 to determine The contact resistance calibration circuit 270 in the output impedance calibration circuit can be measured, and the specific measurement method is described below. Figure 10

[0178] As shown in Figure 8(a) , 8(b) - Figure 9 The four parallel pull-up branches 231 and one parallel pull-down branch 232 in the output impedance calibration circuit are connected in series between the first power supply VDDQ and the second power supply VSS. For the parallel pull-up branch 231, 32 PMOS transistors can be connected in parallel with a resistance unit in series to adjust the resistance value of the parallel pull-up branch, wherein 31 PMOS transistors are controlled by ZQPU<4:0> respectively; for the parallel pull-down branch 232, 32 NMOS transistors can be connected in parallel with a resistance unit in series to adjust the resistance value of the parallel pull-down branch, wherein 31 NMOS transistors are controlled by ZQPD<4:0> respectively.

[0179] ​In the embodiment of the present disclosure, based on the KGD test for calibrating the pull-up resistor RPU, the pull-down resistor RPD is calibrated through the pull-up resistor RPU, and the contact resistance between the second probe and the I / O pad and the contact resistance between the self-calibration pad and the fourth probe are considered, which is more practical and can further improve the calibration accuracy of the pull-up resistor RPU and the pull-down resistor RPD.

[0180] As shown in Figure 10 In one embodiment, the output impedance calibration circuit of the present disclosure further includes: a contact resistance calibration circuit 270 including a plurality of self-calibration pull-down branches 272 connected in parallel, such as a first self-calibration pull-down branch and a second self-calibration pull-down branch, one end of the first self-calibration pull-down branch and the second self-calibration pull-down branch connected in parallel is electrically connected to the first node N1, and the other end of the first self-calibration pull-down branch and the second self-calibration pull-down branch connected in parallel is electrically connected to the second power supply VSS; the contact resistance calibration circuit 270 is used to control the voltage value of the third power supply V3 to be the same as the voltage value of the first power supply VDDQ and the first self-calibration pull-down branch to be turned on, to determine the first total resistance value of the contact resistance calibration circuit 270, and the first self-calibration pull-down branch and the self-calibration resistor R 标准 connected in series between the third power supply V3 and the second power supply VSS; the voltage value of the third power supply V3 is controlled to be the same as the voltage value of the first power supply VDDQ, and the first self-calibration pull-down branch and the second self-calibration pull-down branch are turned on, to determine the second total resistance value of the contact resistance calibration circuit 270, and the first self-calibration pull-down branch and the second self-calibration pull-down branch connected in parallel are connected to the self-calibration resistor R 标准 connected in series between the third power supply V3 and the second power supply VSS, and the contact resistance of the fourth probe test component is determined according to the first total resistance value and the second total resistance value.

[0181] The plurality of self-calibration pull-down branches have the same structure, and each self-calibration pull-down branch 272 includes an NMOS transistor and a third resistor R1, the gate of the NMOS transistor is used to input a first control signal, the drain of the NMOS transistor is electrically connected to the first node N1, the source of the NMOS transistor is electrically connected to the third resistor R1, and the other end of the third resistor R1 is electrically connected to the second power supply VSS.

[0182] As shown in Figure 10 In order to obtain the influence of the probe contact resistance of the self-calibration pad, the third power supply V3 provides a direct current voltage VTERM, such as VDDQ, and the resistance branch to the second power supply VSS is opened through the first control signal T_ZQPD<1:0>, and the NMOS transistor is equivalent to a switch tube, and the impedance of the switch tube is denoted as Rsw.

[0183] The direct current voltage VTERM of the third power supply V3 is set to VDDQ, T_ZQPD<1:0> is set to 01, and the rest of the parallel branches in the output impedance calibration circuit are turned off; the first total resistance value of the contact resistance calibration circuit 270 is:

[0184] (Formula 17)

[0185] The first control signal T_ZQPD<1:0> is set to 11, and the rest remains unchanged; the second total resistance value of the contact resistance calibration circuit 270 is:

[0186] (Formula 18)

[0187] Then: .

[0188] Since can be ignored, we can get .

[0189] With reference to Figure 10 , in one embodiment, the contact resistance calibration circuit 270 further comprises:

[0190] A plurality of parallel self-calibration pull-up branches 271, for example, including a first self-calibration pull-up branch and a second self-calibration pull-up branch connected in parallel, one end of the first self-calibration pull-up branch and the second self-calibration pull-up branch connected in parallel is electrically connected to the first power supply VDDQ, and the other end of the first self-calibration pull-up branch and the second self-calibration pull-up branch connected in parallel is electrically connected to the first node N1;

[0191] The contact resistance calibration circuit 270 is used to control the voltage value of the third power supply V3 to be the same as the voltage value of the second power supply VSS and the first self-calibration pull-up branch to be turned on, to determine the third total resistance value of the contact resistance calibration circuit 270, and the first self-calibration pull-up branch and the self-calibration resistance R 标准 are connected in series between the third power supply V3 and the first power supply VDDQ; the voltage value of the third power supply V3 is controlled to be the same as the voltage value of the second power supply VSS and the first self-calibration pull-up branch and the second self-calibration pull-up branch are turned on, to determine the fourth total resistance value of the contact resistance calibration circuit 270, and the first self-calibration pull-up branch and the second self-calibration pull-up branch connected in parallel are connected in series with the self-calibration resistance R 标准 between the third power supply V3 and the first power supply VDDQ; and according to the third total resistance value and the fourth total resistance value, the contact resistance of the first probe test component and the contact resistance of the fourth probe test component during self-calibration are determined.

[0192] It should be noted that the structure of the self-calibration pull-up branch is similar to that of the self-calibration pull-down branch, which will not be described here.

[0193] The direct voltage VTERM of the third power supply V3 is set to GND, the control signal T_ZQPU<1:0> is set to 01, and the rest of the parallel branches in the output impedance calibration circuit is turned off; the total resistance of the self-calibration pad PAD_ZQ branch is:

[0194] (Formula 19)

[0195] The control signal T_ZQPU<1:0> is set to 11, and the rest remains unchanged; the total resistance of the self-calibration pad PAD_ZQ branch is:

[0196] (Formula 20)

[0197] Then: That is, the sum of the contact resistance of the fourth probe test component and the contact resistance of the first probe test component during self-calibration is obtained.

[0198] It should be noted that the main resistance of at least one circuit in the first self-calibration pull-down branch, the second self-calibration pull-down branch, the first self-calibration pull-up branch, and the second self-calibration pull-up branch is provided by a metal resistor. Because when the control signal is adjusted, the voltage at the self-calibration pad end will change. If the third resistor R1 and the fourth resistor R2 are MOS resistors, their VDS will change, resulting in a change in the resistance value of a single branch when connected in parallel. The use of a metal resistor can significantly improve the test accuracy.

[0199] It should be noted that the resistance value of the above standard resistor can also be adjusted according to the product, and the reference voltage value, the number of parallel pull-up branches, etc. can be adjusted adaptively, that is, the output impedance calibration circuit can be controlled simply.

[0200] Figure 11 A flow chart of an output impedance calibration method provided by an embodiment of the present disclosure is shown. As shown in Figure 11 In one embodiment, the output impedance calibration method of the present disclosure is used to calibrate the contact resistance caused by probe testing. The method mainly includes the following steps:

[0201] S1102, in response to the conduction of a first branch in a plurality of parallel branches, determining a first output impedance of a product to be tested, wherein the first branch is electrically connected to a power supply and a test power supply, and the first output impedance includes a first resistance of the first branch and a first contact resistance caused by probe testing;

[0202] S1104, in response to the conduction of a second branch in a plurality of parallel branches, determining a second output impedance of a product to be tested, wherein the second branch is electrically connected to a power supply and a test power supply, and the second output impedance includes a second resistance of the second branch and a first contact resistance caused by probe testing, and the resistance value of the second resistance is different from the resistance value of the first resistance.

[0203] S1106, determine the first contact resistance according to the first output impedance and the second output impedance.

[0204] When the plurality of parallel branches 230 are connected between the first power supply VDDQ and the test power supply, the parallel branches 230 are determined as parallel pull-up branches 231, when the plurality of parallel branches 230 are connected between the second power supply VSS and the test power supply, the parallel branches 230 are determined as parallel pull-down branches 232, and the parallel pull-up branches 231 and the parallel pull-down branches 232 are connected in series between the first power supply VDDQ and the second power supply VSS.

[0205] It should be noted that the ratio between the resistance value of the first resistor and the resistance value of the second resistor is not equal to 1, so as to ensure the calculation accuracy of the first contact resistance.

[0206] For example, the resistance value of the first resistor is 2 times the resistance value of the second resistor, or the resistance value of the first resistor is 0.5 times the resistance value of the second resistor, etc., which facilitates the calculation of the first contact resistance.

[0207] The first branch and the second branch are both connected between the power supply and the test power supply, and when the voltage value output by the test power supply is unchanged, the first contact resistance includes at least one of the contact resistance between the probe and the power supply and the contact resistance between the probe and the I / O pad.

[0208] Based on the multiple relationship between the resistance value of the first resistor and the resistance value of the second resistor, and the size between the measured first output impedance and the second output impedance, the first contact resistance can be determined.

[0209] In one embodiment, the parallel branch 230 includes a plurality of parallel pull-up branches 231, the plurality of parallel pull-up branches 231 are electrically connected to the first power supply VDDQ through a first probe test component, the plurality of parallel pull-up branches 231 are electrically connected to the test power supply through a second probe test component, and the first contact resistance includes the contact resistance of the first probe test component and / or the contact resistance of the second probe test component.

[0210] The parallel branch 230 also includes a plurality of parallel pull-down branches 232, the plurality of parallel pull-down branches 232 are electrically connected to the second power supply VSS through a third probe test component, the plurality of parallel pull-down branches 232 are electrically connected to the test power supply through the second probe test component, and the first contact resistance includes the contact resistance of the third probe test component and / or the contact resistance of the second probe test component.

[0211] It should be noted that the first contact resistance of the parallel pull-up branch 231 can be determined in the manner of formula 4 or formula 4', and the first contact resistance of the parallel pull-down branch 232 can be determined by formula 7, which will not be described here.

[0212] In one embodiment, the method further comprises: controlling the plurality of parallel branches 230 of the product under test to be turned on, adjusting the resistance value of the plurality of parallel branches 230, for example, the number of turned-on transistors in the first branch, so that the output impedance of the product under test is determined according to the first contact resistance, for example, the output impedance of the product under test is determined as the sum of the first contact resistance and the target impedance value.

[0213] In the KGD test, the number of turned-on pull-up transistors in the pull-up branch can be adjusted so that close to At this time, the internal RPU is also close to the target impedance value .

[0214] In the KGD test, the number of turned-on pull-down transistors in the pull-down branch can be adjusted so that close to At this time, the internal RPD is also close to the target impedance value .

[0215] In one embodiment, the plurality of parallel pull-up branches 231 are electrically connected to the first node N1, the first node N1 is electrically connected to the first end of the self-calibration resistance through the fourth probe test component, the second end of the self-calibration resistance is electrically connected to the third power supply V3, the first node N1 is electrically connected to the first input terminal of the first comparator 250, and the second input terminal of the first comparator 250 is used to input the first reference voltage value; The output impedance calibration method of the disclosure further comprises:

[0216] Controlling the plurality of parallel pull-up branches 231 and the self-calibration resistance to be turned on so that the plurality of parallel pull-up branches 231 and the self-calibration resistance are connected in series to form a first self-calibration loop electrically connected between the first power supply VDDQ and the third power supply V3, wherein the voltage value of the third power supply V3 is less than the voltage value of the first power supply VDDQ.

[0217] Adjusting the first reference voltage value of the first comparator 250 and the resistance value of the plurality of parallel pull-up branches 231 to adjust the output impedance of the first self-calibration loop to a first target value, wherein the first target value is determined according to the resistance value of the self-calibration resistance, the contact resistance of the first probe test component and the contact resistance of the fourth probe test component.

[0218] It should be noted that the way of adjusting the output impedance to the first target value by adjusting the first reference voltage value of the first comparator and the number of turned-on pull-up transistors in each parallel pull-up branch can refer to the following embodiments:

[0219] Here, no longer described.

[0220] In one embodiment, the first node N1 and the plurality of parallel pull-down branches 232 are connected in series to form a second self-calibration loop, the first node N1 is electrically connected to a first input terminal of a second comparator 260, and a second input terminal of the second comparator 260 is configured to input a second reference voltage value;

[0221] After adjusting the first reference voltage value of the first comparator 250 and the resistance values of the plurality of parallel pull-up branches 231 to adjust the output impedance of the first self-calibration loop to the first target value, the method further comprises:

[0222] controlling the second self-calibration loop to be turned on so that the second self-calibration loop is electrically connected between the first power supply VDDQ and the second power supply VSS;

[0223] adjusting the second reference voltage value of the second comparator 260 and the resistance values of the respective parallel pull-down branches 232 to adjust the output impedance of the second self-calibration loop to a second target value, wherein the second target value is determined according to the resistance value of the self-calibration resistor, the contact resistance of the fourth probe test component, and the contact resistance of the second probe test component.

[0224] It should be noted that the way of adjusting the second reference voltage value of the second comparator 260 and the number of pull-down transistors in the respective parallel pull-down branches 232 to adjust the output impedance to the second target value can refer to the way of adjusting the first reference voltage value of the first comparator 250 and the number of pull-up transistors in the respective parallel pull-up branches 231 to adjust the output impedance to the first target value in the foregoing embodiments. Here, details are not repeated.

[0225] In one embodiment, the contact resistance calibration circuit 270 includes a first self-calibration pull-down branch and a second self-calibration pull-down branch connected in parallel, one end of the first self-calibration pull-down branch and the second self-calibration pull-down branch connected in parallel is electrically connected to the first node N1, and the other end of the first self-calibration pull-down branch and the second self-calibration pull-down branch connected in parallel is electrically connected to the second power supply VSS; the output impedance calibration method provided by the embodiment of the disclosure further comprises:

[0226] controlling the voltage value of the third power supply V3 to be the same as the voltage value of the first power supply VDDQ and turning on the first self-calibration pull-down branch, so that the first self-calibration pull-down branch and the self-calibration resistor R 标准 are connected in series between the third power supply V3 and the second power supply VSS to determine the first total resistance value of the contact resistance calibration circuit 270; controlling the voltage value of the third power supply V3 to be the same as the voltage value of the first power supply VDDQ and turning on the first self-calibration pull-down branch and the second self-calibration pull-down branch, so that the first self-calibration pull-down branch and the second self-calibration pull-down branch connected in parallel and the self-calibration resistor R 标准The second total resistance value of the contact resistance calibration circuit 270 is determined by connecting the third power supply V3 and the second power supply VSS in series; and the contact resistance of the fourth probe test component is determined according to the first total resistance value and the second total resistance value.

[0227] The first total resistance value and the second total resistance value are represented by the formula 17 and the formula 18 in the foregoing embodiment, which will not be repeated here.

[0228] In one embodiment, the contact resistance calibration circuit 270 further comprises a first self-calibration pull-up branch and a second self-calibration pull-up branch connected in parallel, one end of the first self-calibration pull-up branch and the second self-calibration pull-up branch connected in parallel is electrically connected to the first power supply VDDQ, and the other end of the first self-calibration pull-up branch and the second self-calibration pull-up branch connected in parallel is electrically connected to the first node N1; the output impedance calibration method provided by the embodiment of the disclosure further comprises:

[0229] The voltage value of the third power supply V3 is controlled to be the same as the voltage value of the second power supply VSS, and the first self-calibration pull-up branch is turned on, so that the first self-calibration pull-up branch and the self-calibration resistance R 标准 The third total resistance value of the contact resistance calibration circuit 270 is determined by connecting the third power supply V3 and the first power supply VDDQ in series; the voltage value of the third power supply V3 is controlled to be the same as the voltage value of the second power supply VSS, and the first self-calibration pull-up branch and the second self-calibration pull-up branch are turned on, so that the first self-calibration pull-up branch and the second self-calibration pull-up branch connected in parallel and the self-calibration resistance R 标准 The fourth total resistance value of the contact resistance calibration circuit 270 is determined by connecting the third power supply V3 and the first power supply VDDQ in series; and the contact resistance of the first probe test component and the contact resistance of the fourth probe test component are determined according to the third total resistance value and the fourth total resistance value.

[0230] The third total resistance value and the fourth total resistance value can be represented by the formula 19 and the formula 20 in the foregoing embodiment, which will not be repeated here.

[0231] In one embodiment, the resistance of at least one circuit in the first self-calibration pull-up branch, the second self-calibration pull-up branch, the first self-calibration pull-down branch and the second self-calibration pull-down branch is provided by a metal resistance.

[0232] It should be noted that the specific implementation of the output impedance calibration method can refer to the control mode in the foregoing output impedance calibration circuit embodiment, which will not be repeated here.

[0233] In the embodiment of the present disclosure, the method is used for calibrating the contact resistance caused by the probe test. In response to the conduction of a first branch in the plurality of parallel branches, the first branch is electrically connected between the power supply and the test power supply, the first output impedance of the product under test is determined, and the first output impedance includes a first resistance of the first branch and a first contact resistance caused by the probe test. In response to the conduction of a second branch in the plurality of parallel branches, the second branch is electrically connected between the power supply and the test power supply, the second output impedance of the product under test is determined, and the second output impedance includes a second resistance of the second branch and the first contact resistance caused by the probe test, and the resistance values of the second resistance and the first resistance are different. The first contact resistance is determined according to the first output impedance and the second output impedance. The present disclosure can accurately determine the contact resistance between the probe and the solder pad by setting the plurality of parallel branches 230 and controlling the conduction of the first branch and the second branch in the plurality of parallel branches 230 to obtain the corresponding first output impedance and second output impedance. According to the accurately determined contact resistance, the output impedance of the product under test is calibrated, the influence of the probe contact resistance on the output impedance can be avoided, and the calibration accuracy of the output impedance of the product under test is greatly improved.

[0234] According to another aspect of the present disclosure, an integrated circuit product is also provided, which includes a product under test and the output impedance calibration circuit in the above-mentioned embodiments, and the output impedance of the product under test is calibrated by the output impedance calibration circuit. In combination with the above-mentioned output impedance calibration circuit, the test accuracy of the output impedance of the integrated circuit product can be improved, and the performance of the integrated circuit product can be improved.

[0235] In one embodiment, the integrated circuit product can be a wafer-level out-of-chip product, or a DDR3 and a DRAM with higher speed, and the present disclosure does not make specific limitation thereto.

[0236] In the embodiments of the present disclosure, the terms "first", "second", and "third" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance; the term "plurality" refers to two or more, unless otherwise explicitly limited. The terms "mounting", "connecting", "connecting", "fixing" and the like should be understood in a broad sense, for example, "connecting" can be fixed connection, or detachable connection, or integral connection; "connecting" can be direct connection, or indirect connection through an intermediate medium. For those skilled in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to the specific circumstances.

[0237] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "left", "right", "front", "rear", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the embodiments of the present application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular direction, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the embodiments of the present application.

[0238] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "a specific embodiment", and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0239] The above is only the preferred embodiment of the present application, and is not intended to limit the present application. The present application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. An output impedance calibration method, characterized by, A method for calibrating contact resistance caused by probe testing, the method comprising: determining a first output impedance of a product under test in response to a first branch of a plurality of parallel branches being turned on, wherein the first branch electrically connects a power supply and a test power supply, and wherein the first output impedance comprises a first resistance of the first branch and a first contact resistance caused by probe testing; determining a second output impedance of the product under test in response to a second branch of the plurality of parallel branches being turned on, wherein the second branch electrically connects the power supply and the test power supply, and wherein the second output impedance comprises a second resistance of the second branch and the first contact resistance, wherein the second resistance is different from the first resistance; determining the first contact resistance based on the first output impedance and the second output impedance.

2. The method of claim 1, wherein: the parallel branches comprise a plurality of parallel pull-up branches, wherein the plurality of parallel pull-up branches are electrically connected to a first power supply via a first probe testing component, and wherein the plurality of parallel pull-up branches are electrically connected to a test power supply via a second probe testing component, and wherein the first contact resistance comprises a contact resistance of the first probe testing component and / or a contact resistance of the second probe testing component.

3. The method of claim 2, wherein: the first probe testing component comprises a first power supply pad and a first probe, wherein the first power supply pad and the first probe are electrically connected to the first power supply, and wherein the second probe testing component comprises an I / O pad and a second probe, wherein the I / O pad and the second probe are electrically connected to the test power supply.

4. The method of claim 1, wherein: the parallel branches comprise a plurality of parallel pull-down branches, wherein the plurality of parallel pull-down branches are electrically connected to a second power supply via a third probe testing component, and wherein the plurality of parallel pull-down branches are electrically connected to the test power supply via the second probe testing component, and wherein the first contact resistance comprises a contact resistance of the third probe testing component and / or a contact resistance of the second probe testing component.

5. The method of claim 4, wherein: the second probe testing component comprises an I / O pad and a second probe, wherein the I / O pad and the second probe are electrically connected to the test power supply, and wherein the third probe testing component comprises a third probe and a second power supply pad, wherein the third probe and the second power supply pad are electrically connected to the second power supply.

6. The output impedance calibration method of claim 1, wherein, the method further comprises: controlling the plurality of parallel branches of the product under test to be turned on, and adjusting resistances of the plurality of parallel branches to determine an output impedance of the product under test based on the first contact resistance.

7. The output impedance calibration method of any of claims 2-5, wherein, the plurality of parallel pull-up branches are electrically connected to a first node, wherein the first node is electrically connected to a first end of a self-calibration resistance via a fourth probe testing component, wherein a second end of the self-calibration resistance is electrically connected to a third power supply, wherein the first node is electrically connected to a first input of a first comparator, and wherein a second input of the first comparator is configured to input a first reference voltage value; the method further comprises: controlling the plurality of parallel pull-up branches and the self-calibration resistance to be conductive, so that the plurality of parallel pull-up branches and the self-calibration resistance in series form a first self-calibration loop electrically connected between the first power supply and the third power supply, wherein the voltage value of the third power supply is less than the voltage value of the first power supply; adjusting the first reference voltage value of the first comparator and the resistance values of the plurality of parallel pull-up branches to adjust the output impedance of the first self-calibration loop to a first target value, wherein the first target value is determined according to the resistance value of the self-calibration resistance, the contact resistance of the first probe test component, and the contact resistance of the fourth probe test component.

8. The output impedance calibration method of claim 7, wherein, The plurality of parallel pull-up branches are connected in series with the plurality of parallel pull-down branches through the first node to form a second self-calibration loop, the first node is electrically connected with the first input terminal of the second comparator, and the second input terminal of the second comparator is used to input a second reference voltage value; After the adjusting the first reference voltage value of the first comparator and the resistance values of the plurality of parallel pull-up branches to adjust the output impedance of the first self-calibration loop to a first target value, the method further comprises: controlling the second self-calibration loop to be conductive, so that the second self-calibration loop is electrically connected between the first power supply and the second power supply; adjusting the second reference voltage value of the second comparator and the resistance values of the plurality of parallel pull-down branches to adjust the output impedance of the second self-calibration loop to a second target value, wherein the second target value is determined according to the resistance value of the self-calibration resistance, the contact resistance of the fourth probe test component, and the contact resistance of the second probe test component.

9. The output impedance calibration method of claim 8, wherein, Further comprising a contact resistance calibration circuit, the contact resistance calibration circuit comprises a first self-calibration pull-down branch and a second self-calibration pull-down branch connected in parallel, one end of the first self-calibration pull-down branch and the second self-calibration pull-down branch connected in parallel is electrically connected with the first node, and the other end of the first self-calibration pull-down branch and the second self-calibration pull-down branch connected in parallel is electrically connected with the second power supply; The method further comprises: controlling the voltage value of the third power supply to be the same as the voltage value of the first power supply and the first self-calibration pull-down branch to be conductive, so that the first self-calibration pull-down branch and the self-calibration resistance are connected in series between the third power supply and the second power supply; and determining a first total resistance value of the contact resistance calibration circuit; controlling the voltage value of the third power supply to be the same as the voltage value of the first power supply and the first self-calibration pull-down branch and the second self-calibration pull-down branch to be conductive, so that the first self-calibration pull-down branch and the second self-calibration pull-down branch connected in parallel and the self-calibration resistance are connected in series between the third power supply and the second power supply; and determining a second total resistance value of the contact resistance calibration circuit; determining the contact resistance of the fourth probe test component according to the first total resistance value and the second total resistance value.

10. The output impedance calibration method of claim 9, wherein, The contact resistance calibration circuit further comprises a first self-calibration pull-up branch and a second self-calibration pull-up branch connected in parallel, one end of the first self-calibration pull-up branch and the second self-calibration pull-up branch connected in parallel is electrically connected to the first power supply, and the other end of the first self-calibration pull-up branch and the second self-calibration pull-up branch connected in parallel is electrically connected to the first node; The method further comprises: controlling the voltage value of the third power supply to be the same as the voltage value of the second power supply and the first self-calibration pull-up branch to be turned on, so that the first self-calibration pull-up branch and the self-calibration resistor are connected in series between the third power supply and the first power supply; and determining a third total resistance value of the contact resistance calibration circuit; controlling the voltage value of the third power supply to be the same as the voltage value of the second power supply and the first self-calibration pull-up branch and the second self-calibration pull-up branch to be turned on, so that the first self-calibration pull-up branch and the second self-calibration pull-up branch connected in parallel and the self-calibration resistor are connected in series between the third power supply and the first power supply; and determining a fourth total resistance value of the contact resistance calibration circuit; determining the contact resistance of the first probe test component and the contact resistance of the fourth probe test component during self-calibration according to the third total resistance value and the fourth total resistance value.

11. The output impedance calibration method of claim 10, wherein, The resistance of at least one circuit in the first self-calibration pull-up branch, the second self-calibration pull-up branch, the first self-calibration pull-down branch, and the second self-calibration pull-down branch is provided by a metal resistor.

12. An output impedance calibration circuit, comprising: The circuit for calibrating the contact resistance caused by probe testing comprises: a plurality of parallel branches connected between a power supply and a test power supply; a gear control circuit for, in response to a first branch in the plurality of parallel branches being turned on, electrically connecting the first branch to the power supply and the test power supply to determine a first output impedance of a product to be tested, wherein the first output impedance comprises a first resistance of the first branch and a first contact resistance caused by probe testing; and in response to a second branch in the plurality of parallel branches being turned on, electrically connecting the second branch to the power supply and the test power supply to determine a second output impedance of the product to be tested, wherein the second output impedance comprises a second resistance of the second branch and the first contact resistance, and the resistance value of the second resistance is different from the resistance value of the first resistance. a contact resistance determination circuit for determining the first contact resistance according to the first contact resistance and the second output impedance.

13. The output impedance calibration circuit of claim 12, wherein, The parallel branches comprise a plurality of parallel pull-up branches, a first branch in the plurality of parallel pull-up branches is electrically connected to a first power supply through a first probe test component, and the plurality of parallel pull-up branches are electrically connected to the test power supply through a second probe test component, and the first contact resistance comprises the contact resistance of the first probe test component and / or the contact resistance of the second probe test component.

14. The output impedance calibration circuit according to claim 13, wherein, The first probe test component includes a first power supply pad and a first probe; the first power supply pad and the first probe are electrically connected with a first power supply; the second probe test component includes an I / O pad and a second probe; the I / O pad and the second probe are electrically connected with a test power supply.

15. The output impedance calibration circuit of claim 12, wherein, The parallel branch includes a plurality of parallel pull-down branches, the plurality of parallel pull-down branches are electrically connected with a second power supply through a third probe test component, and the plurality of parallel pull-down branches are electrically connected with the test power supply through a second probe test component; The first contact resistance includes a contact resistance of the third probe test component and / or a contact resistance of the second probe test component.

16. The output impedance calibration circuit of claim 15, wherein, The second probe test component includes an I / O pad and a second probe; the I / O pad and the second probe are electrically connected with a test power supply; and the third probe test component includes a third probe and a second power supply pad, the third probe and the second power supply pad are electrically connected with a second power supply.

17. The output impedance calibration circuit of any of claims 13-16, wherein, The output impedance calibration circuit further includes an impedance adjustment circuit electrically connected between the gear control circuit and the plurality of parallel branches, for controlling the plurality of parallel branches of the product under test to be turned on, adjusting the resistance value of the plurality of parallel branches, so as to determine the output impedance of the product under test according to the first contact resistance.

18. The output impedance calibration circuit of any of claims 13-16, wherein, The gear control circuit includes a first gear control unit for selecting the on state of the parallel pull-up branch, the first gear control unit includes a plurality of AND gates, a first input end of each AND gate is used for inputting a selection signal, a second input end of each AND gate is used for inputting test data, and an output end of each AND gate is electrically connected with an impedance adjustment circuit, for outputting a pull-up branch selection instruction to the impedance adjustment circuit; The impedance adjustment circuit includes a first impedance adjustment circuit for adjusting the impedance of the parallel pull-up branch, the first impedance adjustment circuit includes a plurality of NAND gates, a first input end of each NAND gate is used for inputting a pull-up impedance adjustment instruction, a second input end of each NAND gate is electrically connected with an output end of the first gear control unit, and an output end of each NAND gate is electrically connected with the plurality of parallel pull-up branches, for outputting the pull-up impedance adjustment instruction to the plurality of parallel pull-up branches.

19. The output impedance calibration circuit of claim 18, wherein, The gear control circuit includes a second gear control unit for selecting the on state of the parallel pull-down branch, the second gear control unit includes a plurality of OR gates, a first input end of each OR gate is used for inputting a selection signal, a second input end of each OR gate is used for inputting test data, and an output end of each OR gate is electrically connected with an impedance adjustment circuit, for outputting a pull-down branch selection instruction to the impedance adjustment circuit; The impedance adjustment circuit comprises a second impedance adjustment circuit for adjusting the impedance of the parallel pull-down branches, the second impedance adjustment circuit comprising a plurality of NAND gates, a first input end of each NAND gate being configured to input a pull-down impedance adjustment instruction, a second input end of each NAND gate being electrically connected to the output end of the OR gate, and an output end of each NAND gate being electrically connected to the plurality of parallel pull-down branches and configured to output the pull-down impedance adjustment instruction to the plurality of parallel pull-down branches.

20. The output impedance calibration circuit of claim 18, wherein, The output impedance calibration circuit further comprises: a self-calibration resistor, a first end of the self-calibration resistor being electrically connected to the first node through a fourth probe test component, and a second end of the self-calibration resistor being electrically connected to a third power supply, the first node being electrically connected to the plurality of parallel pull-up branches; a first comparator, a first input end of the first comparator being electrically connected to the first node, and a second input end of the first comparator being configured to input a first reference voltage value; The impedance adjustment circuit is further configured to control the plurality of parallel pull-up branches and the self-calibration resistor to be turned on, a first self-calibration loop formed by the plurality of parallel pull-up branches and the self-calibration resistor in series being electrically connected between the first power supply and the third power supply, the voltage value of the third power supply being less than the voltage value of the first power supply; adjust the first reference voltage value of the first comparator and the resistance value of the plurality of parallel pull-up branches, and adjust the output impedance of the first self-calibration loop to a first target value, the first target value being determined according to the resistance value of the self-calibration resistor, the contact resistance of the first probe test component, and the contact resistance of the fourth probe test component.

21. The output impedance calibration circuit of claim 20, wherein, The plurality of parallel pull-down branches are electrically connected to the first node, and the plurality of parallel pull-down branches and the plurality of parallel pull-up branches are connected in series between the first power supply and the second power supply to form a second self-calibration loop. The output impedance calibration circuit further comprises: a second comparator, a first input end of the second comparator being electrically connected to the first node, and a second input end of the second comparator being configured to input a second reference voltage value; The impedance adjustment circuit is further configured to control the second self-calibration loop to be turned on, the second self-calibration loop being electrically connected between the first power supply and the second power supply; adjust the second reference voltage value of the second comparator and the resistance value of the plurality of parallel pull-down branches, and adjust the output impedance of the second self-calibration loop to a second target value, the second target value being determined according to the resistance value of the self-calibration resistor, the contact resistance of the fourth probe test component, and the contact resistance of the second probe test component.

22. The output impedance calibration circuit of claim 21, wherein, The circuit further comprises: a contact resistance calibration circuit comprising a first self-calibration pull-down branch and a second self-calibration pull-down branch connected in parallel, one end of the first self-calibration pull-down branch and the second self-calibration pull-down branch connected in parallel being electrically connected to the first node, and the other end of the first self-calibration pull-down branch and the second self-calibration pull-down branch connected in parallel being electrically connected to the second power supply. The contact resistance calibration circuit is used to control the voltage value of the third power supply to be the same as the voltage value of the first power supply and the first self-calibration pull-down branch to be turned on, so that the first self-calibration pull-down branch and the self-calibration resistance are connected in series between the third power supply and the second power supply, to determine a first total resistance value of the contact resistance calibration circuit; control the voltage value of the third power supply to be the same as the voltage value of the first power supply and the first self-calibration pull-down branch and the second self-calibration pull-down branch to be turned on, so that the first self-calibration pull-down branch and the second self-calibration pull-down branch are connected in series with the self-calibration resistance after being connected in parallel between the third power supply and the second power supply, to determine a second total resistance value of the contact resistance calibration circuit; and determine the contact resistance of the fourth probe test component according to the first total resistance value and the second total resistance value.

23. The output impedance calibration circuit of claim 22, wherein, The contact resistance calibration circuit further comprises: a first self-calibration pull-up branch and a second self-calibration pull-up branch connected in parallel, one end of the first self-calibration pull-up branch and the second self-calibration pull-up branch connected in parallel is electrically connected to the first power supply, and the other end of the first self-calibration pull-up branch and the second self-calibration pull-up branch connected in parallel is electrically connected to the first node; The contact resistance calibration circuit is used to control the voltage value of the third power supply to be the same as the voltage value of the second power supply and the first self-calibration pull-up branch to be turned on, so that the first self-calibration pull-up branch and the self-calibration resistance are connected in series between the third power supply and the first power supply, to determine a third total resistance value of the contact resistance calibration circuit; control the voltage value of the third power supply to be the same as the voltage value of the second power supply and the first self-calibration pull-up branch and the second self-calibration pull-up branch to be turned on, so that the first self-calibration pull-up branch and the second self-calibration pull-up branch are connected in series with the self-calibration resistance after being connected in parallel between the third power supply and the first power supply, to determine a fourth total resistance value of the contact resistance calibration circuit; and determine the contact resistance of the first probe test component and the contact resistance of the fourth probe test component during self-calibration according to the third total resistance value and the fourth total resistance value.

24. The output impedance calibration circuit of claim 23, wherein, The resistance of at least one circuit in the first self-calibration pull-up branch, the second self-calibration pull-up circuit, the first self-calibration pull-down branch, and the second self-calibration pull-down branch is provided by a metal resistance.

25. An integrated circuit product, characterized in that The output impedance calibration circuit comprises a product to be tested and the output impedance calibration circuit according to any one of claims 12-24.

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