Silicon photonic integrated chip with heterogeneous integrated lithium niobate modulator and manufacturing method thereof

Abstract

The application discloses a silicon optical integrated chip of a hetero-integrated thin film lithium niobate modulator, which comprises a silicon substrate, a silicon dioxide buried oxygen layer, a silicon waveguide device layer, a silicon nitride waveguide device layer, a silicon dioxide cladding I, a metal electrode layer I, a thin film lithium niobate waveguide layer, a silicon dioxide cladding II, a metal electrode layer II and a silicon dioxide protective layer, the silicon dioxide buried oxygen layer is arranged on the silicon substrate, the silicon waveguide device layer is arranged on the silicon dioxide buried oxygen layer, the silicon nitride waveguide device layer is arranged on the silicon waveguide device layer, the metal electrode layer I is arranged on the silicon waveguide device layer, the thin film lithium niobate waveguide layer is arranged on the silicon dioxide cladding I, and the metal electrode layer II is arranged on the silicon dioxide cladding II. The application further discloses a manufacturing method of the silicon optical integrated chip of the hetero-integrated thin film lithium niobate modulator. The application hetero-integrates the thin film lithium niobate on a silicon optical process platform containing the silicon nitride waveguide through chip-wafer or wafer-wafer bonding or BCB glue bonding and the like.

Description

Technical Field

[0001] This invention belongs to the field of modulator technology, specifically relating to a silicon photonic integrated chip and its fabrication method for a heterogeneous integrated thin-film lithium niobate modulator. Background Technology

[0002] With the rapid development of emerging technologies such as big data, artificial intelligence, and 5G, people's demands for information capacity and information processing speed are increasing. Currently, high-speed on-chip devices have been realized on photonic integration platforms of different systems, such as silicon photonics, III-V compound semiconductors, and silicon dioxide technology platforms.

[0003] Silicon photonics technology platforms have great potential in optical communication and optical interconnect fields because they can be used to fabricate both active devices (such as high-speed modulators, high-speed germanium detectors, and monitoring detectors) and passive devices (such as optical couplers, optical beamsplitters / combiners, and wavelength division multiplexing / demultiplexing devices). Furthermore, their use of CMOS-compatible processes offers advantages such as low chip cost and strong mass production capabilities. However, the bandwidth of silicon photonic modulators is limited by carrier mobility and the series resistance and capacitance of the PN junction, making it difficult to achieve ultra-high electro-optic bandwidth (above 65 GHz), thus restricting the application of silicon photonic integrated chips in high-speed scenarios.

[0004] Thin-film lithium niobate technology is well-suited for fabricating high-speed, low-loss modulators, but thin-film lithium niobate materials cannot function as detectors, and they are difficult to implement in passive devices such as large-mode-field optical couplers.

[0005] As a core component of optical information processing, the electro-optic modulator's modulation rate determines the information transmission rate. The market demands increasingly higher levels of integration, speed, power consumption, and insertion loss from high-speed modulator chips. However, silicon-based electro-optic modulators operate on the principle of plasma dispersion, and their modulation bandwidth is limited by carrier mobility and the series resistance and capacitance of the PN junction, making it difficult to achieve ultra-high electro-optic bandwidths (above 65 GHz).

[0006] Lithium niobate (LNOI) has attracted much attention due to its high electro-optic effect and ultra-wide transparent wavelength range, making it suitable for fabricating high-bandwidth, high-speed, and low-power electro-optic modulators. Traditional LNOI devices typically utilize waveguides fabricated through ion diffusion or proton exchange, resulting in waveguides with small refractive index differences and large dimensions. With advancements in smart dicing technology, high-quality single-crystal LNOI thin-film wafers can be fabricated, enabling LNOI waveguides with larger refractive index differences and nanoscale waveguide dimensions. However, LNOI cannot be used to fabricate detectors due to its low integration density; furthermore, limitations in material etching lead to higher losses, hindering the realization of passive devices such as large-mode-field optocouplers.

[0007] Application, Publication No. CN 115774300 A, Publication Date 2023.03.10, Invention Title: Heterogeneous Integrated Silicon-Based Thin-Film Lithium Niobate Modulator and its Manufacturing Method. (For example...) Figure 1 As shown, Figure 1 In the diagram, 1-1 is the Si device layer, 2-2 is the SiO2 cladding, 3-3 is the substrate Si, 4-4 is the LNOI layer, and 5-5 is the transmission electrode Ti-Au. This application only mentions the heterogeneous integration of the electro-optic modulator part and does not mention the silicon germanium detector. The lithium niobate waveguide layer is not etched, so the overlap between the optical field and the electric field is poor, resulting in low modulation efficiency. In addition, when the lithium niobate waveguide is not etched, the metal electrode can only be placed above the lithium niobate waveguide layer. There are no electrodes on the silicon optical waveguide, and the single-layer metal results in weak interconnection capability of the electrodes. The lack of etching of the lithium niobate waveguide layer leads to weak light confinement by the waveguide, which is not conducive to light coupling into the optical fiber. Summary of the Invention

[0008] The technical problem to be solved by this invention is that current heterogeneous integrated thin-film lithium niobate modulator solutions do not have compatibility with silicon germanium detectors and have low integration; silicon photonics platforms only fabricate passive devices, with electrodes above the lithium niobate waveguides, resulting in weak electrode interconnection capabilities.

[0009] The purpose of this invention is to propose a silicon photonic integrated chip for a heterogeneous integrated thin-film lithium niobate modulator. This silicon photonic integrated chip heterogeneously integrates thin-film lithium niobate on a silicon photonic process platform containing silicon nitride waveguides through die-to-wafer or wafer-to-wafer bonding or BCB adhesive bonding. The integrated chip includes a high-speed thin-film lithium niobate modulator and a high-speed germanium detector, ensuring high integration while possessing strong performance advantages, which can meet the future demand for optical chips in the high-speed, high-density, and high-capacity communication market.

[0010] The specific technical solutions adopted are as follows:

[0011] A silicon photonic integrated chip for a heterogeneous integrated thin-film lithium niobate modulator includes a silicon substrate, a silicon dioxide buried oxide layer, a silicon waveguide device layer, a silicon nitride waveguide device layer, a silicon dioxide cladding layer I, a metal electrode layer I, a thin-film lithium niobate waveguide layer, a silicon dioxide cladding layer II, a metal electrode layer II, and a silicon dioxide protective layer.

[0012] A silicon dioxide buried oxide layer is placed on a silicon substrate. A silicon waveguide device layer is placed on the silicon dioxide buried oxide layer and within the silicon dioxide cladding layer I. A silicon nitride waveguide device layer is placed on the silicon waveguide device layer and within the silicon dioxide cladding layer I. A metal electrode layer I is placed on the silicon waveguide device layer and within the silicon dioxide cladding layer I, forming radio frequency signal electrodes and DC signal electrodes for circuit connections of the silicon waveguide device. A thin-film lithium niobate waveguide layer is placed on the silicon dioxide cladding layer I and within the silicon dioxide cladding layer II. A metal electrode layer II is placed on the silicon dioxide cladding layer II and within the silicon dioxide protective layer, forming radio frequency signal electrodes and DC signal electrodes for circuit connections of the thin-film lithium niobate waveguide device.

[0013] A further optimization of the technical solution of this invention involves etching end-face couplers, beam splitters, beam combiners, multimode interference couplers, directional couplers, and polarization beam splitters onto the silicon waveguide device layer. Silicon waveguide device layers, three-layer silicon nitride waveguide device layers, and thin-film lithium niobate waveguide device layers can all be used to create passive devices, offering the advantage of flexible link connections. Silicon nitride waveguides have lower losses, making them more suitable for low-loss passive devices.

[0014] In a further preferred embodiment of the technical solution of the present invention, end-face couplers, beam splitters, beam combiners, multimode interference couplers, and directional couplers are etched on the silicon nitride waveguide device layer.

[0015] In a further preferred embodiment of the technical solution of the present invention, the thin-film lithium niobate waveguide layer is obtained by etching the top of a thin-film lithium niobate wafer, and the thin-film lithium niobate wafer is placed on the silicon dioxide buried oxide layer by bonding or BCB adhesive. Wafer bonding requires high wafer surface flatness, and is costly and has a low yield, but it has better stability; BCB bonding is simple and low-cost, but its stability is poor.

[0016] In a further preferred embodiment of the technical solution of the present invention, the thin-film lithium niobate wafer is a silicon substrate or a quartz substrate; the width of the thin-film lithium niobate waveguide layer ranges from 600 to 3000 nm, and the height ranges from 100 to 1000 nm.

[0017] In a further preferred embodiment of the technical solution of the present invention, the metal electrode layer I includes a primary via, a first metal layer, a secondary via, and a second metal layer. The primary via is placed on the silicon waveguide device layer, the first metal layer is placed on the primary via, the secondary via is placed on the first metal layer, and the second metal layer is placed on the secondary via, all of which are placed within the silicon dioxide cladding layer I. The thickness of the first metal layer ranges from 300 to 1000 nm, and the thickness of the second metal layer ranges from 1000 to 3000 nm.

[0018] The second objective of this invention is to propose a method for fabricating a silicon photonic integrated chip with a heterogeneous integrated thin-film lithium niobate modulator. This method involves heterogeneously integrating thin-film lithium niobate on a silicon photonic process platform containing silicon nitride waveguides via die-to-wafer or wafer-to-wafer bonding or BCB adhesive bonding. The integrated chip simultaneously includes a high-speed thin-film lithium niobate modulator and a high-speed germanium detector, ensuring high integration while maintaining strong performance advantages. This method can meet the future demands of the high-speed, high-density, and high-capacity communication market for optical chips.

[0019] The technical solution adopted is as follows:

[0020] A method for fabricating a silicon photonic integrated chip for a heterogeneous integrated thin-film lithium niobate modulator includes the following steps:

[0021] Step 1: Select an SOI wafer;

[0022] Step 2: P+ and P++ regions are formed on the top silicon layer of the SOI wafer using P-type ion implantation;

[0023] Step 3: Etch the top silicon layer of the SOI wafer to obtain a silicon waveguide. Fabricate end-face couplers, beam splitters, beam combiners, multimode interference couplers, directional couplers, and polarization beam splitters on the silicon waveguide to form a silicon waveguide device layer; among them, part of the P++ region serves as a heater.

[0024] Step 4: Epitaxially generate a germanium layer on the P+ region, grow polycrystalline silicon on the germanium layer, and then use N-type ion implantation to form the N+ region; the P+ region, germanium layer and N+ region constitute a silicon-germanium detector.

[0025] Step 5: Using plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD), fabricate silicon nitride waveguides on the silicon waveguide device layer, etch the silicon nitride waveguides, and fabricate passive devices such as end-face couplers, multimode interference couplers, and directional couplers; repeat step 3 to form the silicon nitride waveguide device layer; etch the silicon waveguides and silicon nitride waveguides to fabricate vertical thermally adiabatic couplers;

[0026] Step 6: Prepare metal electrode layer I on both the P++ and N+ regions;

[0027] Step 7: Deposit silicon dioxide cladding layer I on metal electrode layer I to form a complete silicon photonic wafer;

[0028] Step 8: Select a thin-film lithium niobate wafer and invert it onto the silicon dioxide cladding I by chip-wafer or wafer-wafer bonding or BCB adhesive bonding.

[0029] Step 9: Remove the silicon substrate and buried oxide layer of silicon dioxide from the thin-film lithium niobate wafer;

[0030] Step 10: Etch the top of the thin-film lithium niobate wafer to form a thin-film lithium niobate waveguide layer;

[0031] Step 11: Deposit silicon dioxide cladding layer II. In order to fabricate metal electrodes on the lithium niobate waveguide, a portion of silicon dioxide cladding layer II is etched away; and to prepare for pad opening on the silicon photonics wafer: etch silicon dioxide cladding layer II and silicon dioxide cladding layer I.

[0032] Step 12: Grow a metal electrode layer II on the silicon dioxide cladding layer II; wherein, the metal electrode layer II, the thin film lithium niobate waveguide layer, and the vertical thermally insulating coupler constitute a heterogeneous integrated thin film lithium niobate modulator.

[0033] Step 13: Deposit a silicon dioxide protective layer, etch the silicon dioxide protective layer on the metal electrode layer II, and deposit metal to form a pad.

[0034] In a further preferred embodiment of the technical solution of the present invention, in step 5, a vertical thermally adiabatic coupler is fabricated between two adjacent silicon nitride waveguides. The vertical thermally adiabatic coupler can be a tapered coupling structure, a directional coupler structure, or other types of coupler structures, which helps to reduce the loss and crosstalk of the coupler.

[0035] In a further preferred embodiment of the technical solution of the present invention, in step 12, the material of the metal electrode layer II is gold or aluminum. Gold and aluminum are common metal electrode materials.

[0036] A further optimization of the technical solution of the present invention is that the radio frequency signal electrode on the metal electrode layer II is a common rectangular electrode or a capacitive load electrode structure; this helps to further improve the bandwidth of the modulator.

[0037] The advantages of this invention compared to the prior art are as follows:

[0038] The silicon photonic integrated chip of this invention heterogeneously integrates thin-film lithium niobate on a silicon photonic process platform containing silicon nitride waveguides through die-to-wafer or wafer-to-wafer bonding or BCB adhesive bonding. The integrated chip also includes a high-speed thin-film lithium niobate modulator and a high-speed germanium detector, ensuring high integration while also possessing strong performance advantages such as high speed and low loss.

[0039] The silicon photonic integrated chip of the present invention involves fabricating metal electrodes on a silicon photonic platform (i.e., metal electrode layer I) and then heterogeneously integrating lithium niobate. The multilayer metal improves the electrode interconnection capability, which helps the modulator and detector on the integrated chip to operate in parallel with multiple DC signals and radio frequency signals.

[0040] The present invention proposes multiple methods for heterogeneous integration of silicon photonic wafers and thin-film lithium niobate wafers, providing a pathway to achieve low-cost, high-yield heterogeneous integration. In addition, the present invention uses multilayer metal electrodes and multilayer silicon nitride as vertical couplers on silicon photonic wafers, which improves electrode interconnection capability while ensuring low loss. The combination of single-layer metal electrodes and double-layer silicon nitride processes helps to reduce process difficulty and further reduce link loss. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of a chip structure based on existing technology;

[0042] Figure 2 This is a schematic diagram of the silicon photonics integrated chip in Example 1;

[0043] Figures 3(a)-3(h) are schematic diagrams of the fabrication process of the silicon photonic integrated chip in Example 1 (Figure 3(a) is the processed silicon photonic wafer, Figure 3(b) is the thin-film lithium niobate wafer, Figure 3(c) is wafer bonding, Figure 3(d) is removing the oxide layer from the substrate of the thin-film lithium niobate wafer, Figure 3(e) is preparing the thin-film lithium niobate waveguide layer, Figure 3(f) is depositing the silicon oxide cladding layer, Figure 3(g) is preparing the metal electrode, and Figure 3(h) is opening the pad).

[0044] Figure 4 This is a schematic diagram of the silicon photonics integrated chip in Example 3;

[0045] Among them, 1-silicon substrate, 2-silicon dioxide buried oxide layer, 3-silicon waveguide, 4-silicon nitride waveguide I, 5-silicon nitride waveguide II, 6-silicon nitride waveguide III, 7-germanium layer, 8-silicon dioxide cladding I, 9-thin-film lithium niobate waveguide layer, 10-primary via, 11-first metal layer, 12-secondary via, 13-secondary metal layer, 14-silicon dioxide cladding II, 15-metal electrode layer II, 16-silicon dioxide protective layer, 17-vertical thermally adiabatic coupler, 18-heater, 19-silicon germanium detector, 20-thin-film lithium niobate modulator. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this invention clearer, the following description is provided in conjunction with the appendix. Figures 1-4 The present invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0047] Example 1

[0048] like Figure 2As shown, this embodiment is a silicon photonic integrated chip for a heterogeneous integrated thin-film lithium niobate modulator, including a silicon substrate 1, a silicon dioxide buried oxide layer 2, a silicon waveguide device layer, a silicon nitride waveguide device layer, a silicon dioxide cladding layer I 8, a metal electrode layer I, a thin-film lithium niobate waveguide layer 9, a silicon dioxide cladding layer II 14, a metal electrode layer II 15, and a silicon dioxide protective layer 16.

[0049] A silicon dioxide buried oxide layer 2 is placed on a silicon substrate 1. A silicon waveguide device layer is placed on the silicon dioxide buried oxide layer 2 and located within a silicon dioxide cladding layer I 8. A silicon nitride waveguide device layer is placed on the silicon waveguide device layer and located within a silicon dioxide cladding layer I 8. A metal electrode layer I is placed on the silicon waveguide device layer and located within a silicon dioxide cladding layer I 8, forming radio frequency signal electrodes and DC signal electrodes for circuit connection of the silicon waveguide device. A thin-film lithium niobate waveguide layer 9 is placed on a silicon dioxide cladding layer I 8 and located within a silicon dioxide cladding layer II 14. A metal electrode layer II 15 is placed on a silicon dioxide cladding layer II 14 and located within a silicon dioxide protective layer 16, forming radio frequency signal electrodes and DC signal electrodes for circuit connection of the thin-film lithium niobate waveguide device.

[0050] In this embodiment, the top silicon layer of the SOI wafer is etched using a CMOS-compatible process to form a silicon waveguide 3. The silicon waveguide 3 preferably has a width range of 300-1000nm and a waveguide height range of 100-500nm.

[0051] SOI wafers, as known to those skilled in the art, include a silicon substrate, a buried oxide layer, and a top silicon layer.

[0052] In this embodiment, the silicon nitride waveguide device layer is fabricated on the silicon waveguide device layer using plasma enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) and then etched.

[0053] In this embodiment, three layers of silicon nitride waveguides are fabricated on the silicon waveguide device layer. The silicon waveguide 3 and silicon nitride waveguides are etched between the layers of silicon waveguide 3 and silicon nitride waveguides to form the specific structure of vertical thermally adiabatic coupler 17.

[0054] In this embodiment, the vertical thermally adiabatic coupler 17 guides the light from the silicon waveguide 3 into the silicon nitride waveguide I 4, the silicon nitride waveguide I 4 into the silicon nitride waveguide II 5, the silicon nitride waveguide II 5 into the silicon nitride waveguide III 6, and the silicon nitride waveguide III 6 into the thin-film lithium niobate waveguide layer 9. The structure of the vertical thermally adiabatic coupler 17 can be a tapered coupling structure, a directional coupler structure, or other types of structures.

[0055] In this embodiment, the silicon nitride thickness of the silicon nitride waveguide is 100-400nm.

[0056] Furthermore, in this embodiment, directional coupler structures can be fabricated on each of the silicon waveguide 3, silicon nitride waveguide I 4, silicon nitride waveguide II 5, and silicon nitride waveguide III 6.

[0057] In this embodiment, the heater 18 is formed by doped silicon waveguide 3. Preferably, a P++ region is formed on the top silicon layer of the SOI wafer by P-type ion implantation.

[0058] Furthermore, the heater 18 can also be formed on the metal electrode layer on the thin-film lithium niobate waveguide layer 9 through processes such as metal deposition and etching.

[0059] In this embodiment, the metal electrode layer I includes a primary via 10, a first metal layer 11, a secondary via 12, and a second metal layer 13. The primary via 10 is placed on the silicon waveguide device layer, the first metal layer 11 is placed on the primary via 10, the secondary via 12 is placed on the first metal layer 11, and the second metal layer 13 is placed on the secondary via 12, all within the silicon dioxide cladding layer I 8. The thickness of the first metal layer 11 ranges from 300 to 1000 nm, and the thickness of the second metal layer 13 ranges from 1000 to 3000 nm. These two metal layers constitute the electrode structure of the silicon-germanium detector 19.

[0060] In this embodiment, the silicon-germanium detector 19 has an epitaxial germanium layer 7 on the silicon waveguide 3, which is compatible with CMOS technology. The thickness of the germanium layer 7 ranges from 300 to 1000 nm, and the width ranges from 1 to 20 μm.

[0061] In this embodiment, the thin-film lithium niobate waveguide layer 9 is obtained by etching the top of a thin-film lithium niobate wafer, which is then placed on the silicon dioxide buried oxide layer 2 using bonding or BCB adhesive. The thin-film lithium niobate wafer is a silicon substrate or a quartz substrate; the thin-film lithium niobate wafer is a product known to those skilled in the art.

[0062] In this embodiment, the silicon photonic integrated chip of the heterogeneous integrated thin-film lithium niobate modulator is heterogeneously integrated on a silicon photonic process platform containing silicon nitride waveguides through chip-to-wafer or wafer-to-wafer bonding or BCB adhesive bonding.

[0063] In this embodiment, the thin-film lithium niobate modulator 20 includes a thin-film lithium niobate waveguide layer 9 and a metal electrode layer II 15. The metal electrode layer II 15 is placed on a silicon dioxide cladding layer II 14 and within a silicon dioxide protective layer 16. The metal electrode layer II 15 serves as the traveling wave electrode of the thin-film lithium niobate modulator 20, and the material can be gold or aluminum. The traveling wave electrode structure can be a rectangular waveguide structure, a T-shaped structure, or other types of electrodes.

[0064] This embodiment proposes a method for fabricating a silicon photonic integrated chip for a heterogeneous integrated thin-film lithium niobate modulator, comprising the following steps:

[0065] Step 1: Select an SOI wafer;

[0066] Step 2: By implanting group III elements into the top silicon layer, a P-type medium-doped region P+ is formed, with a preferred doping concentration range of approximately 1E17~1E19, and a P-type heavily doped region P++ is formed, with a preferred doping concentration range of approximately 1E20~1E23. The doping concentration of the heavily doped P++ region is higher than that of the medium-doped P+ region; rapid thermal annealing is then performed for ion activation.

[0067] Step 3: Etch the top silicon layer of the SOI wafer using a CMOS-compatible process to obtain silicon waveguide 3. Fabricate end-face couplers, multimode interference couplers, directional couplers, and polarization beam splitters on silicon waveguide 3 to form the silicon waveguide device layer. Etch the heavily doped region to form a doped P++ silicon waveguide and fabricate heater 18. Etch the intermediately doped region to form a doped P+ waveguide and fabricate the P-type doped region of the silicon-germanium detector. Heater 18 can also be formed by depositing metallic TiN on top of the silicon waveguide layer and then etching. Heater 18 can also be formed by depositing metallic TiN on the metal electrode layer II 15 on the thin-film lithium niobate waveguide layer 9 and then etching.

[0068] Step 4: Epitaxially grow a germanium layer 7 on a P+ silicon waveguide, compatible with CMOS processes, to fabricate a silicon-germanium detector 19. The thickness of the germanium layer 7 ranges from 300-1000 nm, and the width ranges from 1-20 μm. Polycrystalline silicon is grown on the Ge layer, and group V elements are implanted into the polycrystalline silicon to form an N-type doped region (N+ region), with a preferred doping concentration range of approximately 1E17~1E19. The doped region is etched to form a doped P+ waveguide, fabricating the N-type doped region of the silicon-germanium detector. The N-type doped region, germanium layer 7, and P-type doped region constitute the silicon-germanium detector 19.

[0069] Step 5: Deposit a silicon dioxide cladding layer on the silicon waveguide layer. Prepare the first silicon nitride waveguide layer using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD), etch to form silicon nitride waveguide I4, and then deposit silicon dioxide. Prepare the second silicon nitride layer using LPCVD or PECVD, etch to form silicon nitride waveguide II5, and then deposit silicon dioxide. Prepare the third silicon nitride layer using LPCVD or PECVD, etch to form silicon nitride waveguide III6, and then deposit silicon dioxide. The preferred thickness of the silicon nitride waveguide is 100-400 nm.

[0070] Furthermore, in this embodiment, silicon waveguide 3, silicon nitride waveguide I 4, silicon nitride waveguide II 5, and silicon nitride waveguide III 6 can each be used to fabricate passive optical devices such as silicon nitride end-face couplers, silicon nitride multimode interference couplers, and silicon nitride directional couplers. Using silicon nitride waveguides results in lower losses and makes them more suitable for fabricating passive optical devices. Silicon nitride end-face couplers or grating couplers can be used for coupling chips to optical fibers or lasers. Silicon nitride beam splitters, silicon nitride beam combiners, silicon nitride multimode interference couplers, and silicon nitride directional couplers can be used for beam splitting, combining, and routing of light.

[0071] In this embodiment, three silicon nitride waveguides are fabricated on the silicon waveguide device layer: silicon waveguide 3, silicon nitride waveguide I 4, silicon nitride waveguide II 5, and silicon nitride waveguide III 6, forming the specific structure of the vertical thermally adiabatic coupler 17. The vertical thermally adiabatic coupler 17 guides light from silicon waveguide 3 into silicon nitride waveguide I 4, silicon nitride waveguide I 4 into silicon nitride waveguide II 5, silicon nitride waveguide II 5 into silicon nitride waveguide III 6, and silicon nitride waveguide III 6 into the thin-film lithium niobate waveguide layer 9. The structure of the vertical thermally adiabatic coupler 17 can be a tapered coupling structure, a directional coupler structure, or other types of structures. The vertical thermally adiabatic coupler 17 can be used for the coupling and transmission of light between the silicon waveguide and the thin-film lithium niobate waveguide layer 9.

[0072] Step 6: Etch silicon dioxide above the P++ and N+ regions, deposit metal, and form primary vias 10. After chemical mechanical polishing, deposit metal and etch to prepare the first metal layer 11. The material can be Al or Cu.

[0073] Step 7: Deposit a silicon dioxide cladding layer on the first metal layer 11, etch the silicon dioxide above the first metal layer 11, deposit metal, and form a secondary via 12. After chemical mechanical polishing, deposit metal and etch to prepare a second metal layer 13, the material of which can be Al or Cu. Deposit a silicon dioxide cladding layer I8 and perform chemical mechanical polishing to reduce surface roughness, forming a complete silicon photonic wafer. As shown in Figure 3(a).

[0074] Step 8: Select a thin-film lithium niobate wafer, as shown in Figure 3(b), and perform chemical mechanical polishing. Heterogeneous integration is achieved through wafer-to-wafer bonding: the two wafers are cleaned and then plasma activated; or heterogeneous integration is achieved using BCB adhesive: BCB adhesive is spin-coated onto the silicon photonics wafer surface from Step 7. Then, alignment is performed: the thin-film lithium niobate wafer is inverted on the silicon dioxide cladding I8, as shown in Figure 3(c); the lithium niobate waveguide needs to be aligned with the silicon nitride waveguide to allow light from the silicon nitride waveguide to couple into the thin-film lithium niobate waveguide; rapid thermal processing is then performed.

[0075] Step 9: The silicon substrate and silicon dioxide buried oxide layer of the thin-film lithium niobate wafer are removed by mechanical grinding and selective etching; the lithium niobate film is attached to the surface of the silicon photonics wafer from step 7, and then annealed and chemically mechanically polished. As shown in Figure 3(d).

[0076] Step 10: Etch the remaining top layer of lithium niobate on the thin-film lithium niobate wafer to form the thin-film lithium niobate waveguide layer 9. The waveguide etching angle is 60-90 degrees. The width of the thin-film lithium niobate waveguide in the thin-film lithium niobate waveguide layer 9 ranges from 600-3000 nm, and the height ranges from 100-900 nm, as shown in Figure 3(e). Thin-film lithium niobate waveguides, thin-film lithium niobate multimode interference couplers, and thin-film lithium niobate directional couplers can be fabricated on the thin-film lithium niobate waveguide layer 9. The structure of the Mach-Zehnder interferometer consists of a thin-film lithium niobate multimode interference coupler, a silicon nitride waveguide, a thin-film lithium niobate waveguide layer 9, and a vertical thermally adiabatic coupler 17. The silicon nitride waveguide is used for optical transmission and can be located in either a silicon waveguide or a three-layer silicon nitride waveguide. The thin-film lithium niobate multimode interference coupler is used for beam splitting and combining. Such a beam splitter or combiner can be a multimode interference coupler or a directional coupler and can be located in either a silicon waveguide or a three-layer silicon nitride waveguide.

[0077] Step 11: Deposit silicon dioxide cladding layer II 14. Etch silicon dioxide cladding layer II 14 above the lithium niobate waveguide plate area; then etch silicon dioxide cladding layer II 14 and silicon dioxide cladding layer I 8 to expose the second metal layer 13 of the silicon photonic wafer. As shown in Figure 3(f).

[0078] Step 12: Deposit metal to form metal electrode layer II 15, preferably with a thickness ranging from 0.5 μm to 3 μm, as shown in Figure 3(g). The metal electrode layer II 15, together with the Mach-Zehnder interferometer structure consisting of the thin-film lithium niobate multimode interference coupler, silicon nitride waveguide, thin-film lithium niobate waveguide layer 9, and vertical thermally adiabatic coupler 17, constitute the heterogeneous integrated thin-film lithium niobate modulator 20.

[0079] Step 13: Deposit silicon dioxide protective layer 16, etch silicon dioxide on metal electrode layer II 15, deposit metal, and form Pad. As shown in Figure 3(h).

[0080] Example 2

[0081] Based on Example 1, this example differs from it in that the preceding steps are the same; the different steps are as follows:

[0082] Step 8: Select a thin-film lithium niobate wafer, dic the wafer to form a thin-film lithium niobate chip, and invert the thin-film lithium niobate chip onto the silicon dioxide cladding I8 by chip-wafer bonding. The lithium niobate waveguide needs to be aligned with the silicon nitride waveguide in order for the light from the silicon nitride waveguide to be coupled into the thin-film lithium niobate waveguide.

[0083] Step 9: Peel off the silicon substrate 1 and the buried oxide layer 2 of the thin-film lithium niobate chip;

[0084] Step 10: Etch the remaining top layer of the thin-film lithium niobate chip to form the thin-film lithium niobate waveguide layer 9. Thin-film lithium niobate waveguides, thin-film lithium niobate multimode interference couplers, and thin-film lithium niobate directional couplers can be fabricated on the thin-film lithium niobate waveguide layer 9. The thin-film lithium niobate multimode interference coupler, silicon nitride waveguide, thin-film lithium niobate waveguide layer 9, and vertical thermally adiabatic coupler 17 constitute a Mach-Zehnder interferometer structure. The silicon nitride waveguide is used for optical transmission and can be any layer of a silicon waveguide or a three-layer silicon nitride waveguide. The function of the thin-film lithium niobate multimode interference coupler is for beam splitting and combining; such a beam splitter and combiner can be a multimode interference coupler or a directional coupler and can be any layer of a silicon waveguide or a three-layer silicon nitride waveguide.

[0085] Step 11: Deposit silicon dioxide cladding layer II14. Etch silicon dioxide cladding layer II14 above the lithium niobate waveguide plate area; then etch silicon dioxide cladding layer II14 and silicon dioxide cladding layer I8 to expose the second metal layer 13 of the silicon photonics wafer.

[0086] Step 12: Deposit metal to form metal electrode layer II 15, wherein the metal electrode layer II 15, together with the Mach-Zehnder interferometer structure consisting of thin film lithium niobate multimode interference coupler, silicon nitride waveguide, thin film lithium niobate waveguide layer 9 and vertical thermal adiabatic coupler 17, constitute thin film lithium niobate modulator 20.

[0087] Step 13: Deposit silicon dioxide protective layer 16, etch silicon dioxide on metal electrode layer II 15, deposit metal, and form Pad.

[0088] Example 3

[0089] like Figure 4 As shown, the difference between this embodiment and Embodiment 1 is that:

[0090] The structural difference of the "silicon photonic integrated chip for a heterogeneous integrated thin-film lithium niobate modulator" proposed in this embodiment is that two layers of silicon nitride waveguides are provided, and at the same time, only a first-level through-hole 10 and a first metal layer 11 are provided in the metal electrode layer I, and both are placed in the silicon dioxide cladding layer I8.

[0091] The difference in the fabrication method of the silicon photonic integrated chip for the heterogeneous integrated thin-film lithium niobate modulator proposed in this embodiment is:

[0092] Step 5: Deposit a silicon dioxide cladding layer on the silicon waveguide layer. Prepare the first silicon nitride waveguide layer using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD), etch to form silicon nitride waveguide I4, and then deposit silicon dioxide again. Prepare the second silicon nitride layer using LPCVD or PECVD, etch to form silicon nitride waveguide II5, and then deposit silicon dioxide again. The preferred thickness of the silicon nitride waveguide is 100-400 nm.

[0093] Furthermore, in this embodiment, silicon waveguide 3, silicon nitride waveguide I 4, and silicon nitride waveguide II 5 can each be used to fabricate passive optical devices such as silicon nitride end-face couplers, silicon nitride multimode interference couplers, and silicon nitride directional couplers. Using silicon nitride waveguides results in lower losses, making them more suitable for fabricating passive optical devices. Silicon nitride end-face couplers or grating couplers can be used for coupling chips to optical fibers or lasers. Silicon nitride beam splitters, silicon nitride beam combiners, silicon nitride multimode interference couplers, and silicon nitride directional couplers can be used for beam splitting, combining, and routing of light.

[0094] In this embodiment, two silicon nitride waveguides, silicon waveguide 3, silicon nitride waveguide I 4, and silicon nitride waveguide II 5, are fabricated on the silicon waveguide device layer to form the specific structure of the vertical thermally adiabatic coupler 17. The vertical thermally adiabatic coupler 17 guides light from silicon waveguide 3 into silicon nitride waveguide I 4, silicon nitride waveguide I 4 into silicon nitride waveguide II 5, and silicon nitride waveguide II 5 into the thin-film lithium niobate waveguide layer 9. The structure of the vertical thermally adiabatic coupler 17 can be a tapered coupling structure, a directional coupler structure, or other types of structures. The vertical thermally adiabatic coupler 17 can be used for the coupling and transmission of light between the silicon waveguide and the thin-film lithium niobate waveguide layer 9.

[0095] Step 6: Etch silicon dioxide above the P++ and N+ regions, deposit metal, and form primary vias 10. After chemical mechanical polishing, deposit metal and etch to prepare the first metal layer 11. The material can be Al or Cu.

[0096] Step 7: Deposit a silicon dioxide cladding layer I8 on the first metal layer 11, and perform chemical mechanical polishing to reduce surface roughness, forming a complete silicon photonic wafer. For example... Figure 4 As shown.

[0097] The difference between this embodiment and Embodiment 1 lies in their usage or purpose:

[0098] This embodiment reduces one metal layer, which in turn reduces one silicon nitride waveguide layer. While ensuring electrode interconnection capability, the process is simpler, and reducing one silicon nitride waveguide layer helps reduce the loss of the vertical coupler.

[0099] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a silicon photonic integrated chip for a heterogeneous integrated thin-film lithium niobate modulator, characterized in that, The silicon photonic integrated chip includes a silicon substrate (1), a silicon dioxide buried oxide layer (2), a silicon waveguide device layer, a silicon nitride waveguide device layer, a silicon dioxide cladding layer I (8), a metal electrode layer I, a thin-film lithium niobate waveguide layer (9), a silicon dioxide cladding layer II (14), a metal electrode layer II (15), and a silicon dioxide protective layer (16). A silicon dioxide buried oxide layer (2) is placed on a silicon substrate (1). The silicon waveguide device layer is placed on the buried oxide layer (2) and located within the silicon dioxide cladding layer I (8). The silicon nitride waveguide device layer is placed on the silicon waveguide device layer and located within the silicon dioxide cladding layer I (8). Metal electrode layer I is placed on the silicon waveguide device layer and located within silicon dioxide cladding layer I (8) to fabricate radio frequency signal electrodes and DC signal electrodes for circuit connection of silicon waveguide devices; A thin-film lithium niobate waveguide layer (9) is placed on silicon dioxide cladding layer I (8) and located inside silicon dioxide cladding layer II (14); Metal electrode layer II (15) is placed on silicon dioxide cladding layer II (14) and located inside silicon dioxide protective layer (16) to make radio frequency signal electrode and DC signal electrode for circuit connection of thin film lithium niobate waveguide device; The method for fabricating the silicon photonics integrated chip includes the following steps: Step 1: Select an SOI wafer; Step 2: P+ and P++ regions are formed on the top silicon layer of the SOI wafer using P-type ion implantation; Step 3: Etch the top silicon layer of the SOI wafer to obtain a silicon waveguide (3). On the silicon waveguide (3), fabricate end-face couplers, beam splitters, beam combiners, multimode interference couplers, directional couplers and polarization beam splitters to form a silicon waveguide device layer; wherein, part of the P++ region serves as a heater (18). Step 4: Epitaxially generate a germanium layer (7) on the P+ region, grow polycrystalline silicon on the germanium layer (7), and then use N-type ion implantation to form an N+ region; the P+ region, the germanium layer (7) and the N+ region constitute a silicon-germanium detector (19). Step 5: Using plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD), a silicon nitride waveguide is fabricated on the silicon waveguide device layer. The silicon nitride waveguide is etched to fabricate end couplers, beam splitters, beam combiners, multimode interference couplers, and directional couplers, forming the silicon nitride waveguide device layer. The silicon waveguide (3) and silicon nitride waveguide are etched to fabricate a vertical thermally adiabatic coupler (17). Step 6: Prepare metal electrode layer I on both the P++ and N+ regions; Step 7: Deposit silicon dioxide cladding layer I (8) on metal electrode layer I, and perform chemical mechanical polishing to reduce surface roughness and form a complete silicon photonic wafer; Step 8: Select a thin-film lithium niobate wafer, and invert it onto the silicon dioxide cladding layer I (8) by chip-wafer or wafer-wafer bonding or BCB adhesive bonding; specifically: Select a thin-film lithium niobate wafer, perform chemical mechanical polishing, and achieve heterogeneous integration through wafer-to-wafer bonding: after cleaning the two wafers, perform plasma activation; or achieve heterogeneous integration by using BCB adhesive bonding: spin-coat BCB adhesive on the surface of the silicon photonics wafer; then align: invert the thin-film lithium niobate wafer on the silicon dioxide cladding I (8), and the lithium niobate waveguide needs to be aligned with the position of the silicon nitride waveguide in order to couple the light from the silicon nitride waveguide into the thin-film lithium niobate waveguide; perform rapid thermal treatment; Step 9: Remove the silicon substrate and buried oxide layer of silicon dioxide from the thin-film lithium niobate wafer; Step 10: Etch the top of the thin-film lithium niobate wafer to form a thin-film lithium niobate waveguide layer (9). Step 11: Deposit silicon dioxide cladding layer II (14). In order to fabricate metal electrodes on the lithium niobate waveguide, a portion of silicon dioxide cladding layer II (14) is etched away. In preparation for opening the pad on the silicon photonics wafer, silicon dioxide cladding layer II (14) and silicon dioxide cladding layer I (8) are etched. Step 12: Grow a metal electrode layer II (15) on the silicon dioxide cladding layer II (14); wherein the metal electrode layer II (15), the thin film lithium niobate waveguide layer (9), and the vertical thermal coupler (17) constitute a heterogeneous integrated thin film lithium niobate modulator (20). Step 13: Deposit a silicon dioxide protective layer (16), etch the silicon dioxide protective layer (16) on the metal electrode layer II (15), and deposit metal to form a pad.

2. The method according to claim 1, characterized in that, End-face couplers, beam splitters, beam combiners, multimode interference couplers, directional couplers, and polarization beam splitters are etched onto silicon waveguide device layers.

3. The method according to claim 1, characterized in that, End-face couplers, beam splitters, beam combiners, multimode interference couplers, and directional couplers are etched onto the silicon nitride waveguide device layer.

4. The method according to claim 1, characterized in that, The thin-film lithium niobate waveguide layer (9) is obtained by etching the top of the thin-film lithium niobate wafer, which is placed on the silicon dioxide buried oxide layer (2) by bonding or BCB glue.

5. The method according to claim 4, characterized in that, The thin-film lithium niobate wafer is a silicon substrate or a quartz substrate; the width of the thin-film lithium niobate waveguide layer (9) ranges from 600 to 3000 nm, and the height ranges from 100 to 1000 nm.

6. The method according to claim 1, characterized in that, The metal electrode layer I includes a primary via (10), a first metal layer (11), a secondary via (12), and a second metal layer (13). The primary via (10) is placed on the silicon waveguide device layer, the first metal layer (11) is placed on the primary via (10), the secondary via (12) is placed on the first metal layer (11), and the second metal layer (13) is placed on the secondary via (12), and all are placed in the silicon dioxide cladding layer I (8). The thickness of the first metal layer (11) ranges from 300 to 1000 nm, and the thickness of the second metal layer (13) ranges from 1000 to 3000 nm.

7. The method according to claim 1, characterized in that, In step 5, vertical thermally adiabatic couplers (17) are fabricated between adjacent silicon nitride waveguides. The vertical thermally adiabatic coupler (17) is a tapered coupling structure, a directional coupler structure, or other types of coupler structure.

8. The method according to claim 1, characterized in that, In step 12, the material of the metal electrode layer II (15) is gold or aluminum.

9. The method according to claim 8, characterized in that, The radio frequency signal electrodes on the metal electrode layer II (15) are ordinary rectangular electrodes or capacitive load electrode structures.

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