Computing array integrated circuit and chip

Abstract

The embodiment of the invention discloses a computing array integrated circuit and a chip, the integrated circuit comprises at least one clock buffer, the clock buffer is used for delaying an input clock signal for a specified time length and outputting a delayed clock signal, and the delayed clock signals output by different clock buffers are not synchronous; and a plurality of calculation array sub-circuits, each clock buffer is coupled with at least one calculation array sub-circuit in the plurality of calculation array sub-circuits, and each calculation array sub-circuit obtains the delayed clock signal output by the respective corresponding clock buffer. According to the embodiment of the invention, the instantaneous dynamic power consumption pressure can be reduced, and the circuit safety is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to integrated circuit technology, in particular to a computing array integrated circuit and chip. BACKGROUND

[0002] In an integrated circuit including an acceleration processing function hardware circuit, a large-scale multiply-add circuit is usually included in the hardware circuit for accelerating the processing process, the multiply-add circuit includes a large number of transistors, and during the operation of the circuit, a large number of transistors will be flipped when the state of the clock signal changes, which will also cause the jump of the combinational logic circuit, and a large current will be generated on the entire circuit in a short time, which is easy to cause a large dynamic IR DROP. The dynamic IR DROP refers to the voltage drop phenomenon caused by the current fluctuation of the power supply when the circuit switches, which mainly occurs at the trigger edge of the clock signal. The dynamic IR DROP will adversely affect the behavior of the standard cells (such as selectors MUX, logic gates, etc.) in the circuit, bring uncertainty to the circuit, and affect the safety of the circuit. SUMMARY

[0003] Embodiments of the present disclosure provide a computing array integrated circuit and chip to reduce the instantaneous dynamic power consumption pressure and improve the safety of the circuit.

[0004] In a first aspect, the present disclosure provides a computing array integrated circuit, comprising: at least one clock buffer, the clock buffer being configured to delay an input clock signal for a specified time length and output a delayed clock signal, and different clock buffers output different delayed clock signals; and a plurality of computing array sub-circuits, each clock buffer being coupled to at least one computing array sub-circuit in the plurality of computing array sub-circuits, and each computing array sub-circuit obtains a delayed clock signal output by a corresponding clock buffer.

[0005] In a second aspect, the present disclosure provides a chip, comprising: the computing array integrated circuit according to any one of the above embodiments.

[0006] Based on the computing array integrated circuit and the chip provided by the above-mentioned embodiments of the present disclosure, at least one clock buffer is arranged in the computing array integrated circuit, each clock buffer can output a delayed clock signal after delaying the input clock signal for a specified time length, and each clock buffer is coupled to at least one computing array sub-circuit in the plurality of computing array sub-circuits, so that each computing array sub-circuit can obtain the delayed clock signal output by the corresponding clock buffer. Since the delayed clock signals output by different clock buffers are not synchronized, the clock signals obtained by at least part of the computing array sub-circuits in the plurality of computing array sub-circuits of the integrated circuit are not synchronized with the clock signals obtained by other computing array sub-circuits, so that the transistors in the computing array integrated circuit can be flipped at different times, the simultaneous flipping of a large number of transistors in the plurality of computing array sub-circuits can be avoided, the current generated by the overall circuit in a short time can be reduced, the dynamic IR DROP of the circuit can be reduced, the IR DROP can be prevented from being too large, and the safety of the circuit can be ensured. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is an exemplary application scenario of the computing array integrated circuit provided by the present disclosure;

[0008] Figure 2 is a structural schematic diagram of the computing array integrated circuit provided by an exemplary embodiment of the present disclosure;

[0009] Figure 3 is a structural schematic diagram of the computing array integrated circuit provided by another exemplary embodiment of the present disclosure;

[0010] Figure 4 is a structural schematic diagram of the computing array integrated circuit provided by still another exemplary embodiment of the present disclosure;

[0011] Figure 5 is a structural schematic diagram of the computing array integrated circuit provided by yet another exemplary embodiment of the present disclosure;

[0012] Figure 6 is a structural schematic diagram of the computing array integrated circuit provided by still another exemplary embodiment of the present disclosure;

[0013] Figure 7 is a structural schematic diagram of the computing array integrated circuit provided by still another exemplary embodiment of the present disclosure;

[0014] Figure 8 is a structural schematic diagram of the computing array integrated circuit provided by yet another exemplary embodiment of the present disclosure;

[0015] Figure 9 is a structural schematic diagram of the computing array integrated circuit provided by still another exemplary embodiment of the present disclosure;

[0016] Figure 10 is a structural diagram of a computing array integrated circuit provided by yet another exemplary embodiment of the present disclosure;

[0017] Figure 11 is a structural diagram of a computing array integrated circuit provided by yet another exemplary embodiment of the present disclosure;

[0018] Figure 12 is a structural diagram of a computing array integrated circuit provided by yet another exemplary embodiment of the present disclosure;

[0019] Figure 13 is a structural diagram of a computing array integrated circuit provided by yet another exemplary embodiment of the present disclosure;

[0020] Figure 14 is a diagram of clock signals provided by an exemplary embodiment of the present disclosure;

[0021] Figure 15 is a structural diagram of a chip provided by an exemplary embodiment of the present disclosure;

[0022] Figure 16 is a structural diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] For the purpose of explaining the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments of the present disclosure. It is to be understood that the present disclosure is not limited by the example embodiments.

[0024] It should be noted that the relative arrangement, numerical expressions, and numerical values of the components and steps set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0025] Summary of the disclosure

[0026] In the process of implementing the present disclosure, the inventors found that in an integrated circuit including an acceleration processing function hardware circuit, a large-scale multiplication-addition circuit is usually included in the hardware circuit for accelerating the processing process, the multiplication-addition circuit includes a large number of transistors, and when the state of a clock signal changes, i.e., at a clock edge, a large number of transistors will be flipped, which will also cause the transition of the combinational logic circuit in the integrated circuit, the combinational logic circuit includes one or more standard cells, for example, the standard cells can include selectors, comparators, AND gates, OR gates, NOT gates, etc., and a large number of standard cells in the combinational logic circuit work at the same time in a short time, causing excessive instantaneous power consumption, a large current will be generated on the entire circuit in a short time, which will cause excessive power supply pressure and easily cause excessive dynamic IR DROP. Dynamic IR DROP refers to the voltage drop phenomenon caused by the current fluctuation of the power supply when the circuit switches, which mainly occurs at the trigger edge of the clock. Dynamic IR DROP will adversely affect the behavior of the standard cells in the circuit, bring uncertainty to the circuit, and affect the safety of the circuit.

[0027] Exemplary overview

[0028] Figure 1 is an exemplary application scenario of the computing array integrated circuit provided by the present disclosure. As Figure 1As shown, the computing array integrated circuit in the chip 10 can include m (m is an integer greater than 1) computing array sub-circuits, such as the computing array sub-circuit 111, the computing array sub-circuit 112, the computing array sub-circuit 113, …, and the computing array sub-circuit 11m in the figure. The computing array integrated circuit can be referred to as an integrated circuit, an overall circuit, or a circuit. Each computing array sub-circuit is a sub-circuit with the same or similar function. For example, the computing array sub-circuit can include one or more of a sub-circuit for image processing acceleration (i.e., an image processing accelerator), a sub-circuit for neural network acceleration (i.e., a neural network accelerator), and other types of accelerators. Alternatively, the computing array sub-circuit can be a smaller granularity computing array unit in the image processing accelerator, the neural network accelerator, and other types of accelerators, such as a computing array unit for convolution operation, a computing array unit for matrix multiplication operation, and the like. The specific computing array sub-circuit is not limited. Any two computing array sub-circuits can be independent of each other, or any two computing array sub-circuits can have a certain data dependency relationship. With the computing array integrated circuit of the embodiments of the present disclosure, at least one clock buffer can be set on the basis of the plurality of computing array sub-circuits, such as the clock buffer 121, the clock buffer 122, …, and the clock buffer 12n in the figure, n is a positive integer, that is, the computing array integrated circuit (or chip) can include at least one clock buffer and a plurality of computing array sub-circuits. The clock buffer 12i is used to delay the input clock signal for a specified time and output the delayed clock signal, i = 1, 2, …, n, and the delayed clock signals output by different clock buffers are not synchronized; each clock buffer 12i is coupled to at least one computing array sub-circuit in the plurality of computing array sub-circuits, and each computing array sub-circuit 11j obtains the delayed clock signal output by the clock buffer corresponding thereto, j = 1, 2, …, m. Since the delayed clock signals output by different clock buffers are not synchronized, the clock signals obtained by at least part of the plurality of computing array sub-circuits of the computing array integrated circuit are not synchronized with the clock signals obtained by other computing array sub-circuits, for example, the clock signals obtained by the computing array sub-circuit 112 and the computing array sub-circuit 113 in the figure are not synchronized, so that the transistors in the computing array integrated circuit flip at different times, which can avoid a large number of transistors in the plurality of computing array sub-circuits from flipping at the same time, thereby reducing the current generated by the overall circuit in a short time, reducing the dynamic IR DROP of the circuit, avoiding excessive IR DROP, and ensuring the safety of the circuit.

[0029] Exemplary circuit or device

[0030] Figure 2is a structural schematic diagram of a computing array integrated circuit provided by an example embodiment of the present disclosure. The embodiment can be applied in an electronic device, a chip (or a system on chip), such as a vehicle-mounted computing platform (or a vehicle-mounted terminal, a vehicle-mounted platform), a mobile phone, a tablet computer, and the like. The chip can be a smart driving chip, a smart cockpit chip, and the like, and a chip in a mobile phone, a tablet computer, and other terminal devices, as shown in Figure 2 The computing array integrated circuit 20 of the embodiment of the present disclosure can include a plurality of computing array sub-circuits 21 and at least one clock buffer 22, for example. Figure 2 The plurality of computing array sub-circuits 21 include a computing array sub-circuit 211, a computing array sub-circuit 212, …, and a computing array sub-circuit 21m, where m is an integer greater than 1. The at least one clock buffer 22 includes a clock buffer 221, a clock buffer 222, …, and a clock buffer 22n, where n is a positive integer.

[0031] The clock buffer 22i is configured to delay an input clock signal CKIi for a specified time length and output a delayed clock signal CKOi, where i=1, 2, …, n. The delayed clock signals output by different clock buffers are not synchronized. Each clock buffer 22i is coupled to at least one computing array sub-circuit in the plurality of computing array sub-circuits. Each computing array sub-circuit 21j obtains a delayed clock signal output by a clock buffer corresponding to the computing array sub-circuit, where j=1, 2, …, m.

[0032] Each of the computation array sub-circuits 21j is a sub-circuit with the same or similar function, j = 1, 2, …, m. For example, the computation array sub-circuits can include one or more of sub-circuits for image processing acceleration (i.e., image processing accelerators), sub-circuits for neural network acceleration (i.e., neural network accelerators), and other types of accelerators. Alternatively, the computation array sub-circuits can be smaller granularity computation array units of image processing accelerators, neural network accelerators, and other types of accelerators, such as computation array units for convolution operations, computation array units for matrix multiplication operations, and the like. These computation array sub-circuits are typically implemented based on multiply-accumulate arrays and thus have the same or similar function. The specific computation array sub-circuits are not limited. The clock buffers (or delay buffers) 22i are devices (or sub-circuits) with the function of delaying clock signals. Optionally, the clock buffers 22i can also have the function of shaping the clock signals to eliminate distortion caused by line attenuation or interference and ensure the effectiveness of the clock signals. The delayed clock signals output by different clock buffers are out of sync, meaning that the triggering edges of the delayed clock signals output by different clock buffers are not at the same time, for example, CKO1 jumps from low (or 0) to high (or 1) at time t1, CKO2 jumps from low to high at time t2, the periods of CKO1 and CKO2 are the same, but CKO2 has a certain delay relative to CKO1. The specified time length is the length of time that the clock buffer delays the input clock signal, which can be set according to the power consumption requirements of the computation array integrated circuit, and the specific specified time length is not limited.

[0033] In some optional embodiments, the number m of computation array sub-circuits can be determined according to actual application requirements. For example, m can be 2, 3, 4, ….

[0034] In some optional embodiments, the number n of clock buffers can be set according to the requirements for dynamic power consumption in actual applications. For example, n can be 1, 2, 3, …, and n is less than or equal to m.

[0035] In some optional embodiments, the delayed clock signals output by different clock buffers can be made out of sync by any control method, i.e., CKO1, CKO2, …, CKOn are out of sync. For example, CKO1, CKO2, …, CKOn are made out of sync by connecting the clock buffers in series, or CKO1, CKO2, …, CKOn are made out of sync by connecting the clock buffers in parallel and making the specified time lengths of the delays of the clock buffers different, and the specific control method is not limited.

[0036] In some optional embodiments, coupling refers to the transmission of energy or signals between circuits through any medium, and coupling includes direct electrical connection, indirect electrical connection, non-contact coupling, and the like. Each clock buffer is coupled to at least one of the plurality of computing array sub-circuits, such as clock buffer 221 coupled to computing array sub-circuit 213, clock buffer 222 coupled to computing array sub-circuit 214, and so on. The number of computing array sub-circuits coupled to each clock buffer can be set according to actual needs, for example, the number of computing array sub-circuits coupled to each clock buffer can be determined according to the principle of balancing circuit power consumption. Without limitation Figure 2 to the coupling relationship in the figure.

[0037] In some optional embodiments, CKI1 can be used as the clock signal of part of the computing array sub-circuits, such as computing array sub-circuit 211 and computing array sub-circuit 212 in the figure. Alternatively, in the case where the number of clock buffers is more than one, CKI1 can be used only as the input clock signal of clock buffer 221. Without limitation Figure 2 to the coupling relationship in the figure.

[0038] In some optional embodiments, CKI1, CKI2, …, CKIn can be set according to the coupling of each clock buffer, for example, if each clock buffer is connected in parallel, CKI1, CKI2, …, CKIn can be the same clock signal, for example, all CKI1. If each clock buffer is connected in series, then CKIi = CKOi-1.

[0039] In some optional embodiments, for the case where there is only one clock buffer, taking clock buffer 221 in the figure as an example, the delayed clock signal CKO1 output by the clock buffer 221 is not synchronized with the clock signal CKI1 input into the clock buffer, the clock buffer 221 is coupled to part of the plurality of computing array sub-circuits, and the other part of the computing array sub-circuits can be coupled to the clock signal transmitter outputting CKI1 to obtain CKI1, so as to ensure that there is at least part of the computing array sub-circuits obtaining a clock signal that is not synchronized with the clock signal obtained by the other part of the computing array sub-circuits.

[0040] In some optional embodiments, the specified delay of each clock buffer can be set according to the series or parallel connection of each clock buffer and the clock period of the clock signal. The setting principle is to ensure that the delay of the delayed clock signal output by each clock buffer relative to the undelayed clock signal is within one clock period of the clock signal, so as to avoid the influence of transistor cross-period flipping on the normal work of the circuit during the work of the computing array integrated circuit.

[0041] The computing array integrated circuit provided by the embodiment is configured with at least one clock buffer, each clock buffer can delay the input clock signal for a specified time length and then output the delayed clock signal, and each clock buffer is coupled to at least one computing array sub-circuit in a plurality of computing array sub-circuits, so that each computing array sub-circuit can obtain the delayed clock signal output by the corresponding clock buffer. Since the delayed clock signals output by different clock buffers are not synchronized, the clock signals obtained by at least part of the computing array sub-circuits in the plurality of computing array sub-circuits of the integrated circuit are not synchronized with the clock signals obtained by other computing array sub-circuits, so that the transistors in the computing array integrated circuit can be flipped at different times, the simultaneous flipping of a large number of transistors in the plurality of computing array sub-circuits can be avoided, the current generated by the overall circuit in a short time can be reduced, the dynamic IR DROP of the circuit can be reduced, the IR DROP can be prevented from being too large, and the safety of the circuit can be ensured.

[0042] Figure 3 FIG. 1 is a structural schematic diagram of a computing array integrated circuit provided by another exemplary embodiment of the present disclosure.

[0043] In some optional embodiments, based on the above-mentioned Figure 2 As shown in the above-mentioned Figure 3 The at least one clock buffer includes a plurality of clock buffers, and the computing array integrated circuit 20 of the embodiment of the present disclosure further includes a clock signal transmitter 23.

[0044] The clock signal transmitter 23 is coupled to each clock buffer and is configured to output a first clock signal CK1.

[0045] Any clock buffer 22i in the plurality of clock buffers is configured to delay the input first clock signal CK1 for a specified time length and then output a delayed clock signal CKOi, and the values of the specified time lengths delayed by different clock buffers are different.

[0046] The clock signal transmitter 23 can be a clock source or a clock divider in the computing array integrated circuit 20, or the clock signal transmitter 23 can be a clock buffer coupled to an external clock source of the computing array integrated circuit 20. The specific limitation is not made.

[0047] In some optional embodiments, referring to Figure 3As shown, each clock buffer is in parallel, and the input clock signal of each clock buffer is CK1. By delaying CK1 by different specified time lengths, the delayed clock signals output by each clock buffer are out of synchronization. The value of the specified time length delayed by each clock buffer can be set according to the clock period of CK1. For example, if the clock period of the first clock signal is T, and the number of clock buffers is n, the value of the delay time length of the clock buffer 221 can be T / n, the value of the delay time length of the clock buffer 222 can be 2*T / n, and the value of the delay time length of the clock buffer 22n can be T. Here, this is only an example, and in actual applications, the value of the specified time length delayed by each clock buffer 22i is not limited to i*T / n. For example, the value can be unequal intervals, which is not limited in specific.

[0048] In some optional embodiments, the clock signal transmitter 23 is further coupled with at least one computing array subcircuit, such as Figure 3 In the clock signal transmitter 23 is coupled with the computing array subcircuit 211, so that the computing array subcircuit 211 obtains the first clock signal CK1 output by the clock signal transmitter 23. CK1 is out of synchronization with each CKOi. Therefore, the transistors of the computing array subcircuit coupled with the clock signal transmitter 23 and the computing array subcircuit coupled with each clock buffer flip at different times, which can reduce the number of clock buffers.

[0049] In the embodiments of the present disclosure, by connecting multiple clock buffers in parallel and controlling the values of the specified time lengths delayed by each clock buffer to be different, the delayed clock signals output by each clock buffer are out of synchronization, which ensures that the transistors of multiple computing array subcircuits in the computing array integrated circuit can flip at multiple times, improves the power consumption balance, effectively avoids the simultaneous flipping of a large number of transistors of multiple computing array subcircuits, thereby reducing the current generated by the overall circuit in a short time, reducing the dynamic IR DROP of the circuit, avoiding excessive IR DROP, and ensuring the safety of the circuit.

[0050] In some optional embodiments, Figure 4 is a structural schematic diagram of a computing array integrated circuit provided by still another exemplary embodiment of the present disclosure. As shown in Figure 4 As shown, in Figure 3 On the basis of the embodiment shown, the clock signal transmitter 23 can not be coupled with the computing array subcircuit. Each computing array subcircuit obtains the delayed clock signal output by the clock buffer corresponding thereto, which ensures that a large number of transistors of multiple computing array subcircuits flip at multiple times, and improves the power consumption balance.

[0051] Figure 5 is a structural schematic diagram of a computing array integrated circuit provided by still another exemplary embodiment of the present disclosure.

[0052] In some optional embodiments, on the basis of any of the above embodiments, as shown in Figure 5 The computing array integrated circuit of the embodiments of the present disclosure further includes a clock signal transmitter 23.

[0053] The clock signal transmitter 23 is coupled with a preset clock buffer, and is configured to output a first clock signal CK1.

[0054] In the case where the at least one clock buffer includes only one clock buffer, the clock buffer is configured to delay the input first clock signal CK1 for a specified time length to output a delayed clock signal, the clock buffer is coupled with a first computing array sub-circuit in the plurality of computing array sub-circuits, and the clock signal transmitter 23 is coupled with a second computing array sub-circuit in the plurality of computing array sub-circuits, the second computing array sub-circuit being a computing array sub-circuit other than the first computing array sub-circuit in the plurality of computing array sub-circuits.

[0055] The clock signal transmitter 23 can refer to the aforementioned embodiments and will not be described herein. The preset clock buffer is a clock buffer at a preset position in the at least one clock buffer, as shown in Figure 5 In the case where the at least one clock buffer includes only one clock buffer, the preset clock buffer is the clock buffer 221. The clock buffer 221 is coupled with a part of first computing array sub-circuits in the plurality of computing array sub-circuits, and the clock signal transmitter 23 is coupled with another part of second computing array sub-circuits in the plurality of computing array sub-circuits. As shown in the figure, the second computing array sub-circuits coupled with the clock signal transmitter 23 include the computing array sub-circuit 211 and the computing array sub-circuit 212, and the first computing array sub-circuits coupled with the clock buffer 221 can include the computing array sub-circuit 213, the computing array sub-circuit 214, …, and the computing array sub-circuit 21m. In actual applications, the number of computing array sub-circuits coupled with the clock signal transmitter 23 and the clock buffer 221 can be the same or different, and can be set according to the requirement of power consumption balance.

[0056] In some optional embodiments, in the case that the at least one clock buffer comprises a plurality of clock buffers, for any one first clock buffer 22i in the plurality of clock buffers, in response to the first clock buffer 22i being a preset clock buffer, the first clock buffer 22i is configured to delay the input first clock signal CK1 by a specified time length to output a delayed clock signal CKOi; or, in response to the first clock buffer 22i not being the preset clock buffer, delay a second clock signal CKOi-1 output by a second clock buffer 22i-1 cascaded in front of the first clock buffer 22i by the specified time length to output a delayed clock signal; the second clock signal CKOi-1 is the delayed clock signal output by the second clock buffer 22i-1.

[0057] In some optional embodiments, in the case that the at least one clock buffer comprises a plurality of clock buffers, for any one first clock buffer 22i in the plurality of clock buffers, in response to the first clock buffer 22i being a preset clock buffer, the first clock buffer 22i is configured to delay the input first clock signal CK1 by a specified time length to output a delayed clock signal CKOi; or, in response to the first clock buffer 22i not being the preset clock buffer, delay a second clock signal CKOi-1 output by a second clock buffer 22i-1 cascaded in front of the first clock buffer 22i by the specified time length to output a delayed clock signal; the second clock signal CKOi-1 is the delayed clock signal output by the second clock buffer 22i-1. Figure 5 In some optional embodiments, in the case that the at least one clock buffer comprises a plurality of clock buffers, for any one first clock buffer 22i in the plurality of clock buffers, in response to the first clock buffer 22i being a preset clock buffer, the first clock buffer 22i is configured to delay the input first clock signal CK1 by a specified time length to output a delayed clock signal CKOi; or, in response to the first clock buffer 22i not being the preset clock buffer, delay a second clock signal CKOi-1 output by a second clock buffer 22i-1 cascaded in front of the first clock buffer 22i by the specified time length to output a delayed clock signal; the second clock signal CKOi-1 is the delayed clock signal output by the second clock buffer 22i-1.

[0058] In some optional embodiments, for the case of multiple clock buffer series connection, the specified duration value of each clock buffer delay can be the same or different. Taking the case of the same specified duration corresponding to each clock buffer as an example, if the number of clock buffers is n and the clock period of the first clock signal is T, the specified duration corresponding to each clock buffer can be T / n, that is, on the basis of the first clock signal CK1, each clock buffer in series connection delays T / n in turn, that is, the first clock buffer 221 delays the first clock signal CK1 by T / n and outputs the delayed clock signal CKO1; the second clock buffer 222 delays CKO2 by T / n again and outputs the delayed clock signal CKO2, at this time, the delay duration of CKO2 relative to the first clock signal CK1 is 2T / n; and the like, which will not be repeated here. For the case of different specified durations corresponding to each clock buffer, it is only required to ensure that the sum of the specified durations corresponding to each clock buffer is less than the clock period of the first clock signal CK1.

[0059] In some optional embodiments, in the case of n greater than 1, the clock signal transmitter 23 can be coupled with at least one computing array subcircuit, or the clock signal transmitter 23 can not be coupled with the computing array subcircuit, which can be set according to actual needs, and is not limited to the coupling relationship shown in the figure. Figure 5 The transistors of each computing array subcircuit can be scattered in n different time flips; for example, n = 2, a part of the computing array subcircuits in each computing array subcircuit obtain the delayed clock signal output by the first clock buffer, and another part of the computing array subcircuits obtain the delayed clock signal output by the second clock buffer. Alternatively, the transistors of each computing array subcircuit can be scattered in n+1 different time flips, that is, a part of the computing array subcircuits obtain the first clock signal output by the clock signal transmitter, and the remaining computing array subcircuits obtain the delayed clock signal output by the corresponding clock buffer. For example, n = 2, then each computing array subcircuit can be divided into three parts (or three groups), wherein the first part of the computing array subcircuits obtains the first clock signal, the second part of the computing array subcircuits obtains the delayed clock signal output by the first clock buffer, and the third part of the computing array subcircuits obtains the delayed clock signal output by the second clock buffer.

[0060] In some optional embodiments, the number of computing array subcircuits coupled with each clock buffer can be set according to actual needs, and the embodiments of the present disclosure are not limited. The number of computing array subcircuits coupled with different clock buffers can be the same or different.

[0061] The computing array integrated circuit provided in this embodiment utilizes a clock signal transmitter and a clock buffer to disperse the transistor flipping of multiple computing array sub-circuits to two different times. Alternatively, by connecting multiple clock buffers in series, the transistor flipping of multiple computing array sub-circuits can be dispersed to multiple different times. Alternatively, the clock signal transmitter and multiple clock buffers can be used to disperse the transistor flipping of multiple computing array sub-circuits to multiple different times. This prevents a large number of transistors in multiple computing array sub-circuits from flipping simultaneously, improves the power consumption balance of the integrated circuit, and ensures the security of the integrated circuit. Furthermore, by cascading multiple clock buffers, the number of clock signal transmission lines can be reduced.

[0062] Figure 6 2 is a schematic structural diagram of a computing array integrated circuit provided by yet another exemplary embodiment of the present disclosure.

[0063] In some optional embodiments, based on any of the above embodiments, Figure 6 As shown, the plurality of computing array subcircuits 21 include a first number (denoted as m) of computing array subcircuits; the at least one clock buffer 22 includes a second number (denoted as n) of clock buffers; the second number n is less than or equal to the first number m.

[0064] The plurality of computing array sub-circuits 21 are divided into a second number of groups, each group including at least one computing array sub-circuit; and each clock buffer is coupled to a group of computing array sub-circuits.

[0065] Among them, the first number m and the second number n can be set according to actual needs. The grouping method of multiple computing array sub-circuits 21 can be set according to the size relationship between the second number n and the first number m, and the need for power consumption balancing. For example, when m is equal to n, each computing array sub-circuit is a group, that is, each computing array sub-circuit corresponds to a clock buffer. When n is less than m, the second number of groups can be determined in a uniform grouping or approximately uniform grouping manner. For example, if m is an integer multiple of n, each group can include m / n computing array sub-circuits, and each group corresponds to a clock buffer. If m is not an integer multiple of n, some groups include floor(m / n) computing array sub-circuits, and the other part of the group includes floor(m / n)+1 computing array sub-circuits, where floor() represents a rounding-down function. In actual applications, multiple computing array sub-circuits 21 can also be determined as the second number of groups in other ways, not limited to the grouping method of the above examples. As Figure 6As shown, the m computing array sub-circuits are determined as n groups, i.e., a first group, a second group, a third group, …, and an nth group. The first group includes k computing array sub-circuits of the computing array sub-circuit 211 to the computing array sub-circuit 21k, k is greater than or equal to 1, the second group includes j-k computing array sub-circuits of the computing array sub-circuit 21(k+1) to the computing array sub-circuit 21j, j is greater than k, the third group includes s-j computing array sub-circuits of the computing array sub-circuit 21(j+1) to the computing array sub-circuit 21s, s is greater than j, …, and the nth group includes m-t computing array sub-circuits of the computing array sub-circuit 21(t+1) to the computing array sub-circuit 21m, t is greater than or equal to s and less than m.

[0066] In some optional embodiments, the plurality of computing array sub-circuits can include a plurality of rows and a plurality of columns of computing array sub-circuits, which are not limited to the arrangement of the computing array sub-circuits in the figure. For the plurality of rows and the plurality of columns of computing array sub-circuits, the plurality of computing array sub-circuits can be determined as the second number of groups according to the row and column relationship of the computing array sub-circuits. For example, the 48 computing array sub-circuits of 6 rows and 8 columns are determined as 8 groups. Each column can be a group, or each 3 rows and 2 columns can be a group, i.e., each of the two parts of 3 rows is divided into 4 groups according to the column, and the two parts are 8 groups in total, so as to ensure that the computing array sub-circuits in each group are close to the corresponding clock buffer, and the signal transmission path is reduced.

[0067] It should be noted that, Figure 6 In the above embodiment, the plurality of clock buffers are connected in series. In actual application, the embodiment is also applicable to the scenario that the plurality of clock buffers are connected in parallel, which is not limited to Figure 6 The coupling relationship shown.

[0068] In the embodiment of the present disclosure, the plurality of computing array sub-circuits are determined as the second number of groups, each group includes one or more computing array sub-circuits, and each clock buffer is coupled to a group of computing array sub-circuits, so that the transistors of the plurality of computing array sub-circuits are flipped at different times, which effectively reduces the dynamic power consumption of the integrated circuit.

[0069] Figure 7 FIG. 6 is a structural schematic diagram of a computing array integrated circuit provided by another exemplary embodiment of the present disclosure.

[0070] In some optional embodiments, on the basis of any of the above embodiments, as Figure 7As shown, the plurality of computing array sub-circuits 21 can be determined as n+1 groups, each group including at least one computing array sub-circuit, and then one computing array sub-circuit of one group is coupled with the clock signal transmitter 23 to obtain the first clock signal CK1 from the clock signal transmitter 23, and the other n groups are respectively coupled with one clock buffer. As shown in the figure, Figure 7 In the embodiment, the first group obtains the first clock signal CK1, the second group is coupled with the clock buffer 221, the third group is coupled with the clock buffer 222, and the n+1 group is coupled with the clock buffer 22n. In the embodiment, the clock signal transmitter 23 is coupled with the clock buffer 221, the clock buffer 221 is coupled with the clock buffer 222, and the clock buffer 222 is coupled with the clock buffer 22n. Figure 6 In the embodiment of the integrated circuit, the same grouping can reduce one clock buffer.

[0071] It should be noted that, Figure 7 In the embodiment, only the case of connecting the plurality of clock buffers in series is taken as an example, and the embodiment is also applicable to the case of connecting the plurality of clock buffers in parallel in actual application, and is not limited to Figure 7 The coupling relationship shown in the figure.

[0072] In some optional embodiments, the at least one clock buffer 22 includes a second number of clock buffers; the values of the specified time length of each clock buffer are the same; the first clock period corresponding to the first clock signal CK1 is M times of the specified time length corresponding to each clock buffer, and M is the second number, that is, n in the above.

[0073] In the embodiment, the first clock period refers to one complete period of the first clock signal, and the first clock period can be determined according to the frequency of the first clock signal. For example, if the first clock signal is a 1GHZ clock signal, the first clock period corresponding to the first clock signal is 1 nanosecond, and the specified time length corresponding to each clock buffer is 1 / M, that is, 1 / n. On the basis of the cascade (or series) of the clock buffers, the specified time length corresponding to each clock buffer is determined based on the principle that the first clock period corresponding to the clock signal CK1 is M times of the specified time length of each clock buffer.

[0074] In the embodiment of the disclosure, the specified time length corresponding to the clock buffer is determined based on the principle that the first clock period corresponding to the first clock signal is M times of the specified time length corresponding to each clock buffer. On the one hand, it can ensure that each computing array sub-circuit is triggered to work within the same clock period, avoiding excessive delay. On the other hand, the transistors of each computing array sub-circuit are uniformly dispersed to different time points within one clock period for flipping, improving the balance of dynamic power consumption of the integrated circuit, and effectively reducing the instantaneous dynamic power consumption of the integrated circuit.

[0075] Figure 8 FIG. 1 is a structural schematic diagram of a computing array integrated circuit provided by another exemplary embodiment of the disclosure.

[0076] In some optional embodiments, on the basis of any of the above embodiments, as shown in Figure 8 The plurality of computing array sub-circuits 21 includes a first number (denoted as m) of computing array sub-circuits; the at least one clock buffer 22 includes a first number (m) of clock buffers; and each clock buffer is coupled with one computing array sub-circuit.

[0077] The clock buffers correspond to the computing array sub-circuits one by one, that is, the clock buffer 221 is coupled with the computing array sub-circuit 211, the computing array sub-circuit 211 obtains the delayed clock signal CKO1 output by the clock buffer 221, the clock buffer 222 is coupled with the computing array sub-circuit 212, the computing array sub-circuit 212 obtains the delayed clock signal CKO2 output by the clock buffer 222, and so on, which will not be described one by one.

[0078] In the embodiments of the present disclosure, by corresponding the clock buffers to the computing array sub-circuits one by one, the transistor flips of each computing array sub-circuit are more evenly dispersed to different time points, and the dynamic power consumption of the integrated circuit at the moment is further reduced.

[0079] Figure 9 FIG. 4 is a structural schematic diagram of a computing array integrated circuit provided by another exemplary embodiment of the present disclosure.

[0080] In some optional embodiments, on the basis of any of the above embodiments, as shown in Figure 9 The plurality of computing array sub-circuits 21 includes m (m is an integer greater than 1) computing array sub-circuits; the at least one clock buffer 22 includes m-1 clock buffers; each clock buffer is coupled with one computing array sub-circuit, and the clock signal transmitter 23 is coupled with one computing array sub-circuit.

[0081] The number of the computing array sub-circuits is one more than the number of the clock buffers, one of the computing array sub-circuits obtains the first clock signal CK1 output by the clock signal transmitter 23, and the remaining m-1 computing array sub-circuits correspond to the m-1 clock buffers one by one, and compared with the structure shown in Figure 8 In the embodiments, one clock buffer can be reduced.

[0082] In some optional embodiments, on the basis of any of the above embodiments, the specified time length of each clock buffer is the same; the first clock period corresponding to the first clock signal is N times of the specified time length corresponding to each clock buffer, which can be called a constraint condition of the specified time length, and N is the first number, that is, m in the above description. Figure 8 and Figure 9The integrated circuit shown can determine the designated duration corresponding to each clock buffer based on the designated duration constraint of this embodiment. For example, if the first clock cycle is T, the designated duration is T / N (ie, T / m).

[0083] In the embodiments of the present disclosure, the designated duration corresponding to the clock buffer is determined based on the number of computing array sub-circuits and the clock cycle of the first clock signal, ensuring that each computing array sub-circuit can be triggered to operate within one clock cycle, thereby avoiding excessive delays that affect the operating efficiency of the integrated circuit.

[0084] In some optional embodiments, based on any of the above embodiments, Figure 2 、 Figures 5-9 As shown in FIG. 1 , at least one clock buffer includes multiple clock buffers; the integrated circuit of the embodiment of the present disclosure further includes: a clock signal transmitter 23 .

[0085] The clock signal transmitter 23 is configured to output a first clock signal CK1 . A first clock buffer among a plurality of clock buffers is coupled to the clock signal transmitter, and the first clock buffer is configured to delay the input first clock signal CK1 by a specified time length to output a delayed clock signal.

[0086] The output end of the i-th clock buffer is coupled to the input end of the i+1-th clock buffer; i=1, 2, ..., n-1, where n is the number of clock buffers; the output end of the i-th clock buffer is also coupled to the calculation array sub-circuit corresponding to the i-th clock buffer; the output end of the n-th clock buffer is coupled to the calculation array sub-circuit corresponding to the n-th clock buffer.

[0087] Among them, the first clock buffer refers to the clock buffer in the first place when multiple clock buffers are cascaded, such as Figure 2 or Figure 5 The clock buffer 221 is the first clock buffer, the second clock buffer is the clock buffer 222, .... The input clock signal of the first clock buffer is the first clock signal CK1. The output end of the first clock buffer is coupled to the input end of the second clock buffer, the output end of the second clock buffer is coupled to the input end of the third clock buffer, and so on. The output end of the n-1th clock buffer is coupled to the input end of the nth clock buffer. The clock buffers are connected in series to achieve multiple delays of the clock signal. The output end of each clock buffer is coupled to the calculation array sub-circuit corresponding to the clock buffer, such as Figure 5 The output end of the clock buffer 221 is coupled to the calculation array sub-unit 213 corresponding to the clock buffer 221 , . . . , the output end of the clock buffer 22n is coupled to the calculation array sub-circuit 21m corresponding to the clock buffer 22n.

[0088] In the embodiments of the present disclosure, the cascade delay of the clock signal is realized by the series connection of the plurality of clock buffers, so that the transistors of the plurality of computing array sub-circuits can be flipped at different times, the instantaneous dynamic power consumption of the integrated circuit is reduced, and the instantaneous dynamic IR DROP is avoided.

[0089] Figure 10 is a structural schematic diagram of the computing array integrated circuit provided by another exemplary embodiment of the present disclosure.

[0090] In some optional embodiments, on the basis of any of the above embodiments, as shown in Figure 10 The integrated circuit of the embodiments of the present disclosure can further include:

[0091] Each computing array sub-circuit 21j corresponds to a first register 24j; j = 1, 2, …, m, and m is the number of computing array sub-circuits.

[0092] The first register 24j is coupled with the clock buffer corresponding to the computing array sub-circuit 21j, and is configured to store the to-be-computed data corresponding to the computing array sub-circuit.

[0093] The clock buffer 22i is configured to delay the input clock signal for a specified time and then output the delayed clock signal to the first register, i = 1, 2, …, n, and n is the number of computing array sub-circuits.

[0094] The first register 24j can be any type of register, such as a general-purpose register, a shift register, etc., and the specific type can be set according to actual needs, which is not limited in the embodiments of the present disclosure. The to-be-computed data corresponding to the computing array sub-circuit 21j is the data required for the computing array sub-circuit to perform the computing task, for example, if the computing array sub-circuit 21j is a sub-circuit for convolution operation, the to-be-computed data can include at least one of feature data for convolution operation and weight data of a convolution kernel. The delayed clock signal output by the clock buffer 22i is transmitted to the first register coupled with the clock buffer 22i. As shown in Figure 10 The delayed clock signal CKO1 output by the clock buffer 221 is transmitted to the first register 243 of the computing array sub-circuit 213 coupled with the clock buffer 221 to trigger the first register 243 to work.

[0095] In some optional embodiments, the delayed clock signal output by the clock buffer 22i can be transmitted in parallel to the computing array sub-circuit corresponding to the clock buffer 22i and the first register corresponding to the computing array sub-circuit.

[0096] In the embodiments of the present disclosure, the first registers corresponding to the computing array sub-circuits are included in the integrated circuit, so as to store the to-be-computed data required by the computing array sub-circuit to work, and ensure that the computing array sub-circuit can work normally.

[0097] In some optional embodiments, the first register 24j is a shift register; as shown in Figure 10 The first registers corresponding to the computing array sub-circuits are coupled in a preset order.

[0098] Any first register 24j is configured to transmit the data in the first register 24j to another first register coupled behind the first register by shifting.

[0099] As shown in Figure 10 The first register 241, the first register 242, the first register 243, …, and the first register 24m are sequentially connected in series, the data in the first register 241 can be transmitted to the first register 242 coupled behind the first register 241 by shifting, the data in the first register 242 can be transmitted to the first register 243 coupled behind the first register 242 by shifting, and so on, and the shifting transmission of data can be performed between the first registers. For example, when the computing array sub-circuits need to share some data, the multiplexing of the shared data can be realized by register shifting. Taking convolution operation as an example, the weight data of the convolution kernel needs to participate in the weighted summation of different feature sub-data in the feature data, and the weight data of the convolution kernel can be respectively taken as the to-be-computed data of different computing array sub-circuits by register shifting, so as to realize the multiplexing of the data. Taking matrix multiplication operation as another example, each row of the first matrix needs to be multiplied and added with each column of the second matrix, and the multiplexing of each row of the first matrix can be realized by register shifting.

[0100] In the embodiments of the present disclosure, the shift register is used as the first register corresponding to the computing array sub-circuit, the first registers are coupled in a preset order, and a data shifting transmission path is formed, so as to realize the multiplexing of the to-be-computed data between the computing array sub-circuits.

[0101] Figure 11 FIG. 4 is a structural schematic diagram of a computing array integrated circuit according to another exemplary embodiment of the present disclosure.

[0102] In some optional embodiments, on the basis of any of the above embodiments, the computing array integrated circuit according to the embodiments of the present disclosure can further include at least one clock switch 25. As shown in Figure 11 For example, the at least one clock switch 25 includes n clock switches, i.e., clock switch 251, clock switch 252, …, and clock switch 25n.

[0103] Each clock switch 25i (i = 1, 2, …, n) is connected in series at the output of one clock buffer 22i in the at least one clock buffer 22.

[0104] The clock switch 25i is configured to: in the case of opening of the clock switch 25i, cut off the delayed clock signal output by the clock buffer 22i connected to the clock switch 25i; or in the case of closing of the clock switch 25i, connect the delayed clock signal output by the clock buffer 22i connected to the clock switch 25i, so as to transmit the delayed clock signal to the corresponding computing array sub-circuit.

[0105] The clock switch 25i is a switch for controlling the on-off of the clock signal transmission path. In the case of opening of the clock switch, the clock signal transmission path is in an off state, and the clock signal cannot be transmitted to the corresponding computing array sub-circuit. In the case of closing of the clock switch, the clock signal transmission path is in an on state, and the clock signal can be transmitted to the corresponding computing array sub-circuit. Each clock switch 25i is connected in series at the output of one clock buffer 22i or at the input of the computing array sub-circuit, so as to control whether the delayed clock signal output by the clock buffer is transmitted to the corresponding computing array sub-circuit. For example, Figure 11 The clock switch 251 is connected in series at the output of the clock buffer 221 leading to the computing array sub-circuit 211 and the computing array sub-circuit 212, and controls whether CKO1 is transmitted to the computing array sub-circuit 211 and the computing array sub-circuit 212.

[0106] In some optional embodiments, any switch capable of controlling the on-off of the signal transmission path can be used as the clock switch, and the embodiments of the present disclosure are not limited thereto.

[0107] In the embodiments of the present disclosure, by providing the clock switch, the working state of the computing array sub-circuit can be controlled by controlling the opening and closing of the clock switch. For example, when some computing array sub-circuit(s) is / are not needed to work, the clock switch corresponding to the computing array sub-circuit(s) can be controlled to be opened, so as to cut off the clock signal of the computing array sub-circuit(s), which is helpful to further reduce the energy consumption. When some computing array sub-circuit(s) is / are needed to work, the clock switch corresponding to the computing array sub-circuit(s) can be controlled to be closed, so as to connect the clock signal of the computing array sub-circuit(s). Thus, the flexibility of the integrated circuit in application can be improved.

[0108] Figure 12 FIG. 1 is a structural schematic diagram of a computing array integrated circuit provided by another exemplary embodiment of the present disclosure.

[0109] In some optional embodiments, as shown in FIG. 1, the computing array integrated circuit can include a plurality of computing array sub-circuits 21i (i = 1, 2, …, n), a plurality of clock buffers 22i (i = 1, 2, …, n), and a plurality of clock switches 25i (i = 1, 2, …, n). Figure 12As shown, the number of clock switches can be n+1, wherein one clock switch (for example, clock switch 251) is the clock switch corresponding to the first clock signal CK1. The other n clock switches, namely, clock switch 252, clock switch 253, …, clock switch 25(n+1) are respectively connected in series at the output end of the corresponding clock buffer. For example, clock switch 252 is connected in series at the output end of clock buffer 221, clock switch 253 is connected in series at the output end of clock buffer 222, and so on. The function of the clock switch is described in the foregoing embodiment, which is not repeated here.

[0110] Figure 13 is a structural schematic diagram of a computing array integrated circuit provided by another exemplary embodiment of the present disclosure. As shown in the figure, Figure 13 the computing array integrated circuit 20 of the embodiment of the present disclosure can include m computing array sub-circuits, m clock switches, and m-1 clock buffers. The specific functions of each component can be referred to the foregoing embodiment, which is not repeated here.

[0111] In some optional embodiments, each computing array sub-circuit can further include a second register for storing the intermediate calculation result during the operation of the computing array sub-circuit or the calculation result after the completion of the calculation, and / or, in the case of data dependency between the computing array sub-circuits, the second register can store the calculation result of the previous stage of the computing array sub-circuit. Optionally, the second registers in each computing array sub-circuit can be shift registers electrically connected in a preset order, and the data in the second register in one computing array sub-circuit is transmitted to the second register in another computing array sub-circuit through the shift of the shift registers, so as to realize the transmission of the calculation result of one computing array sub-circuit to another computing array sub-circuit, or realize the multiplexing of the internal data of the computing array sub-circuit. The structure of the specific computing array sub-circuit is not limited.

[0112] Figure 14 is a schematic diagram of each clock signal provided by an exemplary embodiment of the present disclosure. Based on the foregoing embodiment, as shown in the figure, Figure 14 the first clock signal CK1 can be a clock signal from a preset clock source (i.e., a clock signal transmitter). The first clock signal CK1 is taken as an undelayed clock signal, the clock buffer 221 delays CK1 for a specified time length to obtain CKO1, the clock buffer 222 delays CKO1 for a specified time length to obtain CKO2, and so on, so that the trigger edges of each clock signal are all different, such as the rising edges in Figure 14 , where the horizontal direction represents time, and the vertical dotted lines represent the time corresponding to each rising edge. The time interval between two adjacent dotted lines is the specified time length of the corresponding clock buffer, for example, the specified time length is 1 / n of the first clock period T of CK1.

[0113] In the related art, each computing array sub-circuit is triggered to work at the trigger edge of the first clock signal CK1, that is, the standard cells in each computing array sub-circuit work at the same time in a short time, a large number of transistors flip at the same time, causing excessive transient power consumption, which brings excessive pressure on the power supply of the integrated circuit, is easy to cause excessive IR DROP, and leads to functional errors of the integrated circuit.

[0114] In view of these problems in the related art, based on Figure 14 As shown in the clock signal, the computing array integrated circuit of the embodiment of the present disclosure derives a plurality of clock signals of the same frequency and different phases through the clock buffer, that is, the frequencies of the delayed clock signals output by each clock buffer are the same, but the trigger edges are not at the same time, there is a certain phase difference between the delayed clock signals output by each clock buffer, and the delayed clock signals of different phases output by the plurality of clock buffers are transmitted to the corresponding computing array sub-circuit, so that the computing array sub-circuit corresponding to different clock buffers is triggered to work at different trigger edges, avoiding that all computing array sub-circuits are triggered to work intensively at the trigger edge of the same clock signal, effectively reducing the transient power consumption of the integrated circuit, and avoiding the problem of excessive IR DROP.

[0115] The above-mentioned embodiments of the present disclosure can be implemented alone or in any combination without conflict, and can be set according to actual needs, and the present disclosure is not limited.

[0116] Exemplary chip

[0117] Figure 15 is a structural schematic diagram of a chip provided by an exemplary embodiment of the present disclosure. As shown in Figure 15 The chip 30 provided by the embodiment of the present disclosure can include the computing array integrated circuit 20 provided by any of the above-mentioned embodiments.

[0118] In some optional embodiments, the chip 30 can further include a processor, a memory and the like. The memory can store computer program instructions, and the processor can read and execute the computer program instructions stored in the memory to configure the computing array integrated circuit 20 and control the computing array integrated circuit 20 to complete corresponding computing tasks.

[0119] The beneficial technical effects corresponding to the exemplary chip embodiment can be referred to the corresponding beneficial technical effects of the above-mentioned exemplary method, which will not be repeated here.

[0120] Exemplary electronic device

[0121] Figure 16is a structural diagram of an electronic device provided by an embodiment of the present disclosure, comprising at least one processor 91 and a memory 92, and the computing array integrated circuit 20 provided by any of the above embodiments.

[0122] The processor 91 can be a central processing unit (CPU) or other form of processing unit having data processing and / or instruction execution capabilities, and can control other components in the electronic device 90 to perform desired functions.

[0123] The memory 92 can comprise one or more computer program products, which can comprise various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may, for example, include random access memory (RAM), cache, and / or the like. Non-volatile memory may, for example, include read-only memory (ROM), hard disk, flash memory, and / or the like. One or more computer program instructions can be stored on the computer-readable storage media, and the processor 91 can run the one or more computer program instructions to control the integrated circuit of various embodiments of the present disclosure to implement desired functions.

[0124] In one example, the electronic device 90 can further comprise an input device 93 and an output device 94, which are interconnected through a bus system and / or other forms of connection mechanism (not shown).

[0125] The input device 93 can further comprise, for example, a touch screen, a microphone, various sensors, and the like. The sensors may, for example, comprise an image sensor (such as a camera, a video camera, and the like), a laser radar, a millimeter wave radar, an ultrasonic radar, a positioning sensor, a pressure sensor, an air quality sensor, a temperature sensor, and the like. The image sensor, laser radar, millimeter wave radar, ultrasonic radar, and the like can be used for perception of the surrounding environment, i.e. detecting dynamic and static objects in the surrounding environment. The dynamic and static objects may, for example, comprise static objects such as lane lines, road edges, arrows, signboards, trees, buildings, and the like, and dynamic objects such as surrounding vehicles, pedestrians, cyclists, and the like. The positioning sensor is used to realize positioning of a movable device (such as a self-driving vehicle, a robot, and the like) in which the electronic device is located. The positioning sensor may, for example, comprise an inertial measurement unit (IMU), a global positioning system (GPS), and the like. The pressure sensor can be used to detect seat pressure. The temperature sensor can be used to detect temperature in the vehicle cabin. The air quality sensor can be used to detect air quality in the vehicle cabin.

[0126] The output device 94 can output various information to the outside, which may, for example, comprise a display, a speaker, a communication network and a remote output device connected thereto, and the like.

[0127] Of course, in order to simplify, Figure 16 Only some of the components of the electronic device 90 related to the present disclosure are shown in the figure, and components such as buses, input / output interfaces, and the like are omitted. In addition, the electronic device 90 can include any other appropriate components according to the specific application.

[0128] Exemplary computer program product and computer readable storage medium

[0129] In addition to the above-mentioned method and device, embodiments of the present disclosure can also provide a computer program product including computer program instructions, which, when executed by a processor, cause the processor to control the integrated circuit of various embodiments of the present disclosure described in the above-mentioned "Exemplary Circuit or Device" section to achieve the desired function.

[0130] The computer program product can be written in any combination of one or more programming languages, including an object-oriented programming language such as Java, C++, and the like, and conventional procedural programming languages, such as the "C" programming language, or the like. Program code can execute entirely on a user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server.

[0131] In addition, embodiments of the present disclosure can also be a computer readable storage medium having stored thereon computer program instructions, which, when executed by a processor, cause the processor to control the integrated circuit of various embodiments of the present disclosure described in the above-mentioned "Exemplary Circuit or Device" section to achieve the desired function.

[0132] The computer readable storage medium can take any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium, for example, but not limited to, includes an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples (non-exhaustive list) of readable storage medium include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any appropriate combination of the above.

[0133] The basic principles of the present disclosure are described above with reference to specific embodiments, but the advantages, benefits and effects mentioned in the present disclosure are only examples and are not considered to be mandatory for each embodiment of the present disclosure. In addition, the specific details of the above disclosure are only for the purpose of illustration and understanding, and are not considered to limit the present disclosure to the above specific details. It is necessary to implement the present disclosure.

[0134] Those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A computing array integrated circuit, comprising: At least one clock buffer, the clock buffer being configured to delay an input clock signal by a specified time length and output the delayed clock signal, wherein the delayed clock signals output by different clock buffers are not synchronized; There are a plurality of computing array sub-circuits, each of the clock buffers is coupled to at least one computing array sub-circuit among the plurality of computing array sub-circuits, and each of the computing array sub-circuits obtains the delayed clock signal output by the corresponding clock buffer.

2. The integrated circuit according to claim 1, wherein: The at least one clock buffer includes a plurality of clock buffers, the integrated circuit further comprising: A clock signal transmitter, configured to output a first clock signal; Any one of the multiple clock buffers is used to delay the input first clock signal for a specified time period and output the delayed clock signal. Different clock buffers have different values ​​of the specified time period for delay.

3. The integrated circuit according to claim 1, wherein: The integrated circuit further comprises: A clock signal transmitter, configured to output a first clock signal; In a case where the at least one clock buffer includes only one clock buffer, the clock buffer is used to delay the input first clock signal by a specified time length and output the delayed clock signal, the clock buffer is coupled to a first computing array sub-circuit among the multiple computing array sub-circuits, and the clock signal transmitter is coupled to a second computing array sub-circuit among the multiple computing array sub-circuits, where the second computing array sub-circuit is a computing array sub-circuit among the multiple computing array sub-circuits except the first computing array sub-circuit; or In the case where the at least one clock buffer includes multiple clock buffers, for any first clock buffer among the multiple clock buffers, in response to the first clock buffer being a preset clock buffer, the first clock buffer is used to delay the input first clock signal by a specified time length and output the delayed clock signal; or, in response to the first clock buffer not being the preset clock buffer, delay the second clock signal output by a second clock buffer cascaded with the first clock buffer in front by a specified time length and output the delayed clock signal; the second clock signal is the delayed clock signal output by the second clock buffer.

4. The integrated circuit according to claim 1, wherein: said plurality of computation array subcircuits comprising a first number of said computation array subcircuits; said at least one clock buffer comprising a second number of said clock buffers; the second amount is less than or equal to the first amount; determining the plurality of computing array sub-circuits into a second number of groups, each group including at least one of the computing array sub-circuits; Each of the clock buffers is coupled to a group of the computing array sub-circuits.

5. The integrated circuit according to claim 3, wherein: The at least one clock buffer includes a second number of clock buffers; the value of the specified time length of delay of each clock buffer is the same; the first clock cycle corresponding to the first clock signal is M times the specified time length corresponding to each clock buffer, and M is the second number.

6. The integrated circuit according to claim 3, wherein: said plurality of computation array subcircuits comprising a first number of said computation array subcircuits; said at least one clock buffer including said first number of said clock buffers; Each of the clock buffers is coupled to one of the computing array sub-circuits.

7. The integrated circuit according to claim 6, wherein: The designated time lengths of delay of each of the clock buffers are the same; the first clock cycle corresponding to the first clock signal is N times the designated time length corresponding to each of the clock buffers, where N is the first number.

8. The integrated circuit according to claim 1, wherein: The at least one clock buffer comprises a plurality of clock buffers; The integrated circuit further comprises: A clock signal transmitter, configured to output a first clock signal; A first clock buffer among the plurality of clock buffers is coupled to the clock signal transmitter, and the first clock buffer is configured to delay the input first clock signal by a specified time length and output the delayed clock signal; The output terminal of the i-th clock buffer is coupled to the input terminal of the i+1-th clock buffer; i=1, 2, ..., n-1, where n is the number of clock buffers; The output terminal of the i-th clock buffer is also coupled to the calculation array sub-circuit corresponding to the i-th clock buffer; The output end of the nth clock buffer is coupled to the calculation array sub-circuit corresponding to the nth clock buffer.

9. The integrated circuit of claim 1 , further comprising: a first register corresponding to each of the computing array sub-circuits; The first register is coupled to the clock buffer corresponding to the calculation array sub-circuit and is configured to store the to-be-calculated data corresponding to the calculation array sub-circuit; The clock buffer is used to delay the input clock signal for a specified time period and then output it to the first register.

10. The integrated circuit according to claim 9, wherein: The first register is a shift register; the first registers corresponding to the calculation array sub-circuits are coupled in a preset order; Any of the first registers is used to transfer the data in the first register to another first register cascaded with the first register through shifting.

11. The integrated circuit according to any one of claims 1 to 10, further comprising: at least one clock switch; Each of the clock switches is connected in series to an output end of one of the at least one clock buffers; The clock switch is configured as follows: When the clock switch is turned on, cutting off the delayed clock signal output by the clock buffer connected to the clock switch; or, When the clock switch is closed, the delayed clock signal output by the clock buffer connected to the clock switch is connected to transmit the delayed clock signal to the corresponding calculation array sub-circuit.

12. A chip comprising: A computing array integrated circuit as claimed in any one of claims 1 to 11.

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