Memory access latency measurement method and program product, storage medium, electronic device

Abstract

The application discloses a memory access delay measurement method and program product, a storage medium and an electronic device. The method comprises the following steps: binding a test execution thread to a first node, allocating a test memory area on a second node, creating a first pointer array on the first node and creating a second pointer array on the second node, and randomly generating a first random sequence and a second random sequence; determining a random access chain for bidirectional jumping between the first node and the second node based on a first mapping relationship, a second mapping relationship, the first pointer array and the second pointer array; performing a double-jump pointer dereferencing operation for a first preset number of times based on the random access chain, and determining a total time for completing the double-jump pointer dereferencing operation; and determining a memory access delay based on the total time and the first preset number of times. The method can eliminate the interference of cache prefetching and out-of-order execution on delay measurement, and improve the accuracy of memory access delay measurement.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory latency measurement, and particularly relates to a memory access latency measurement method and program product, a storage medium and an electronic device. BACKGROUND

[0002] With the development of multi-core processors, the NUMA (Non-Uniform Memory Access) architecture is widely used in server and high-performance computing fields. In the NUMA architecture, the processor accesses the memory of the local node at a faster speed, and accesses the memory of the remote node at a slower speed. Accurate measurement of the memory access delay across nodes is crucial for system performance optimization.

[0003] Currently, the method for measuring the memory delay usually adopts a sequential access mode, which sequentially traverses the memory in the target memory region by a fixed step size (such as a cache line size), and then obtains the memory delay by multiple reading operations and calculating the average time. However, this mode cannot effectively simulate the random memory access behavior in the real scene, resulting in a deviation between the measurement result and the actual application performance. SUMMARY

[0004] The present application provides a memory access latency measurement method and program product, a storage medium and an electronic device, to at least solve the problem in the related art that the random memory access behavior in the real scene cannot be effectively simulated, resulting in a deviation between the measurement result and the actual application performance, and to eliminate the interference of cache prefetching and out-of-order execution on the delay measurement, and to improve the precision of the memory access latency measurement.

[0005] The present application provides a memory access latency measurement method, comprising:

[0006] binding a test execution thread to a first node, and allocating a test memory region on a second node, wherein the first node is a node initiating a memory access operation, and the second node is a node where the accessed data is stored in the memory;

[0007] creating a first pointer array on the first node and a second pointer array on the second node, and generating a first random sequence and a second random sequence randomly, wherein, an element in the first pointer array represents a target address of a memory access request initiated from the first node, and points to a memory location of the test memory region on the second node, an element in the second pointer array represents a memory location of the test memory region on the second node, and the memory location is pointed to by an element in the first pointer array on the first node, the first random sequence is used to define a first mapping relationship in which elements in the first pointer array point to elements in the second pointer array, and the second random sequence is used to define a second mapping relationship in which elements in the second pointer array point back to elements in the first pointer array;

[0008] determining a random access chain for bidirectional jumping between the first node and the second node based on the first mapping relationship, the second mapping relationship, the first pointer array and the second pointer array;

[0009] performing a double jump pointer dereferencing operation a first preset number of times based on the random access chain, and determining a total time for completing the double jump pointer dereferencing operation;

[0010] determining a memory access delay based on the total time and the first preset number.

[0011] The application further provides a computer program product comprising computer programs / instructions, which, when executed by a processor, implement the memory access delay measurement method described above.

[0012] The application further provides a non-volatile computer readable storage medium having a program stored thereon, which, when executed by a processor, implements the memory access delay measurement method described above.

[0013] The application further provides an electronic device comprising a memory, a processor, and a program stored on the memory and executable on the processor, wherein the processor implements the memory access delay measurement method described above when executing the program.

[0014] By the application, the test execution thread is bound to the first node, and a test memory region is allocated on the second node, wherein the first node is a node initiating a memory access operation, and the second node is a node where the accessed data is stored; a first pointer array is created on the first node, and a second pointer array is created on the second node, and a first random sequence and a second random sequence are randomly generated, wherein the elements in the first pointer array represent target addresses of memory access requests initiated from the first node, and point to a memory location of the test memory region on the second node, the elements in the second pointer array represent a memory location of the test memory region on the second node, and the memory location is pointed to by the elements in the first pointer array on the first node, the first random sequence is used to define a first mapping relationship in which the elements in the first pointer array point to the elements in the second pointer array, and the second random sequence is used to define a second mapping relationship in which the elements in the second pointer array point back to the elements in the first pointer array; a random access chain for bidirectional jumping between the first node and the second node is determined based on the first mapping relationship, the second mapping relationship, the first pointer array and the second pointer array; a double-jump pointer dereferencing operation is performed for a first preset number of times based on the random access chain, and a total time for completing the double-jump pointer dereferencing operation is determined; and a memory access delay is determined based on the total time and the first preset number. Thus, the method can eliminate the interference of cache prefetching and out-of-order execution on delay measurement, and improve the accuracy of memory access delay measurement. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0016] Figure 1 Flowchart of the memory access delay measurement method according to an embodiment of the present application;

[0017] Figure 2 Flowchart of the memory access delay measurement method according to one specific example of the present application;

[0018] Figure 3 Block schematic diagram of the electronic device according to an embodiment of the present application.

[0019] Reference signs: 200-electronic device, 210-memory, 220-processor. DETAILED DESCRIPTION

[0020] Embodiments of the present application are described below in detail with reference to the accompanying drawings, wherein the same or similar components or elements are denoted throughout the drawings by the same or similar reference numerals. The embodiments described below are exemplary and are intended to explain the present application, and should not be understood as limiting the present application.

[0021] The memory access latency measurement method, computer program product, computer readable storage medium and electronic device according to the embodiments of the present application are described below with reference to the accompanying drawings.

[0022] Figure 1 A flowchart of the memory access latency measurement method according to the embodiments of the present application.

[0023] As shown in Figure 1 the memory access latency measurement method according to the embodiments of the present application can include the following steps:

[0024] S1, binding a test execution thread to a first node, and allocating a test memory region on a second node, wherein the first node is a node initiating a memory access operation, and the second node is a node where the accessed data is stored.

[0025] S2, creating a first pointer array on the first node, and creating a second pointer array on the second node, and randomly generating a first random sequence and a second random sequence, wherein the elements in the first pointer array represent the target addresses of the memory access requests initiated from the first node, and point to a memory location of the test memory region on the second node, the elements in the second pointer array represent a memory location of the test memory region on the second node, and the memory location is pointed to by the elements in the first pointer array on the first node, the first random sequence is used to define a first mapping relationship of the elements in the first pointer array pointing to the elements in the second pointer array, and the second random sequence is used to define a second mapping relationship of the elements in the second pointer array pointing back to the elements in the first pointer array.

[0026] S3, determining a random access chain for bidirectional jumping between the first node and the second node based on the first mapping relationship, the second mapping relationship, the first pointer array and the second pointer array.

[0027] S4, performing a double jump pointer dereferencing operation for a first preset number of times based on the random access chain, and determining a total time for completing the double jump pointer dereferencing operation.

[0028] S5, determining the memory access latency based on the total time and the first preset number.

[0029] Specifically, when measuring the memory access latency, first, the test execution thread is bound to the first node, and the test memory region is allocated on the second node, wherein the first node is the node initiating the memory access operation, and the second node is the node where the accessed data is stored. That is, the test execution thread is bound to the first node (the source NUMA node), which is the node initiating the memory access operation, and the test memory region is allocated on the second node (the target NUMA node), which is the node where the accessed data is stored, to ensure that the test thread runs on the source node and the test data is located on the target node, simulating the cross-node memory access situation.

[0030] Then a first pointer array can be created on the first node, and a second pointer array can be created on the second node, and a first random sequence and a second random sequence can be randomly generated. The elements in the first pointer array represent the target addresses of the memory access requests initiated from the first node, pointing to a memory location of the test memory region on the second node, and the elements in the second pointer array represent a memory location of the test memory region on the second node, which is pointed to by the elements in the first pointer array on the first node. For example, a pointer array SRC_PTRS is created on the first node. Each element in this array is a pointer, which is used to store the target address of the memory access request initiated from the source node. Another pointer array DST_PTRS is created on the target node, and each element in this array is also a pointer, which is used to store the memory address of the test memory region on the target node. A random permutation (the first random sequence PERM1) can be generated by a random function, which is used to define a first mapping relationship of the elements in the first pointer array pointing to the elements in the second pointer array, i.e., the first mapping relationship is used to determine how the pointers in the SRC_PTRS array point to the elements in the DST_PTRS array. The size of this sequence is the same as the number of array elements, and another random permutation (the second random sequence PERM2) is generated, which is used to define a second mapping relationship of the elements in the second pointer array pointing back to the elements in the first pointer array, i.e., the second mapping relationship is used to determine how the pointers in the DST_PTRS array point back to the elements in the SRC_PTRS array.

[0031] After determining the first mapping relationship, the second mapping relationship, the first pointer array, and the second pointer array, a random access chain for bidirectional jumping between the first node and the second node can be determined according to the first mapping relationship, the second mapping relationship, the first pointer array, and the second pointer array. That is, the first mapping relationship is defined by a first random sequence (PERM1) and is used to randomly map each element in the first pointer array (SRC_PTRS) to an element in the second pointer array (DST_PTRS). This step ensures that the access from the first node to the second node is random. The second mapping relationship is defined by a second random sequence (PERM2) and is used to randomly map each element in the second pointer array (DST_PTRS) back to an element in the first pointer array (SRC_PTRS), which ensures that the access from the second node back to the first node is also random.

[0032] Through the two mapping relationships, a bidirectional random access chain is constructed. For example, according to the first random sequence PERM1, each element in the SRC_PTRS array is set through the first mapping relationship to point to the element at the corresponding position in the DST_PTRS array. This means that SRC_PTRS[i] will point to DST_PTRS[PERM1[i]], and according to the second random sequence PERM2, each element in the DST_PTRS array is set through the second mapping relationship to point to the element at the corresponding position in the SRC_PTRS array, which means that DST_PTRS[i] will point to SRC_PTRS[PERM2[i]]. Through the above mapping, a bidirectional jumping path is formed, in which the memory access request is initiated from the source node, jumps to the memory location of the target node, and then jumps back to the memory location of the source node. This bidirectional jumping path simulates the complex memory access pattern that may occur in a NUMA system. That is, this structure ensures the randomness of memory access and avoids the possibility of compiler or processor optimizing the memory access order, thereby making the measurement result more accurate and reliable. By simulating the real memory access pattern, the memory access delay in the NUMA system can be more accurately measured and evaluated.

[0033] After determining the random access chain, the first preset number of double jump pointer dereferencing operations can be performed according to the random access chain, and the total time for completing the double jump pointer dereferencing operations is determined. For example, starting from the first element of the SRC_PTRS array of the source node, which is a pointer to an element in the DST_PTRS array of the target node, the corresponding memory location in the DST_PTRS array is accessed through the pointer in the SRC_PTRS array, which is equivalent to a memory access request initiated from the source node jumping to the memory location of the target node. Then, the element in the DST_PTRS array is dereferenced again to jump back to the next element in the SRC_PTRS array. This is equivalent to jumping back from the memory location of the target node to the memory location of the source node, updating the current pointer variable to point to the next element in the SRC_PTRS array for the next double jump operation. Repeat the above double jump operation until the first preset number of cycles are completed, each cycle involving a complete jump from the source node to the target node and back to the source node.

[0034] Moreover, before starting the double jump pointer dereferencing operation, a high-precision timer can be used to record the current time point as the start time, and after all double jump operations are completed, the high-precision timer is used again to record the current time point as the end time, so that the difference between the end time and the start time is calculated to obtain the total time for completing all double jump pointer dereferencing operations. By measuring the total time for completing the double jump pointer dereferencing operation, the memory access delay from the source NUMA node to the target NUMA node and back to the source node can be obtained, which will be used to calculate the average delay per memory access to evaluate the performance of memory access in the NUMA system.

[0035] After determining the total time, the memory access delay can be determined according to the total time and the first preset number. For example, the memory access delay can be determined by a pre-established correspondence, for example, the relationship between the total time, the first preset number and the memory access delay is determined in advance, and after the total time and the first preset number are determined, the corresponding relationship is directly called to obtain the memory access delay.

[0036] Thus, the delay experienced when accessing the memory of another node in a NUMA system can be accurately measured. This method helps to evaluate and optimize the memory access performance in a multi-node system, providing important data support for system design and resource allocation.

[0037] According to one embodiment of the present application, determining the random access chain for bi-directional jumping between the first node and the second node based on the first mapping relationship, the second mapping relationship, the first pointer array and the second pointer array comprises: pointing the elements in the first pointer array to the corresponding elements in the second pointer array based on the first mapping relationship; after the corresponding elements in the second pointer array are determined, pointing the corresponding elements in the second pointer array back to the corresponding elements in the first pointer array based on the second mapping relationship, until the elements in the first pointer array and the second pointer array are accessed to each other, and the random access chain is determined.

[0038] Specifically, when determining the random access chain for bi-directional jumping between the first node and the second node based on the first mapping relationship, the second mapping relationship, the first pointer array and the second pointer array, the elements in the first pointer array can be pointed to the corresponding elements in the second pointer array based on the first mapping relationship. That is, according to the first random sequence PERM1, the mapping relationship (the first mapping relationship) from SRC_PTRS to DST_PTRS is established, which means that each element (pointer) in the SRC_PTRS array will be set to point to the element at the corresponding position in the DST_PTRS array according to the first mapping relationship. For example, for each index i, SRC_PTRS[i]=&DST_PTRS[PERM1[i]] is set. In this way, each pointer in the SRC_PTRS array points to the memory location specified by PERM1 in the DST_PTRS array. After the corresponding elements in the second pointer array are determined, the corresponding elements in the second pointer array are pointed back to the corresponding elements in the first pointer array based on the second mapping relationship, until the elements in the first pointer array and the second pointer array are accessed to each other, and the random access chain is determined. That is, after the corresponding elements in the second pointer array are determined, the mapping relationship (the second mapping relationship) from DST_PTRS to SRC_PTRS is established according to the second random sequence PERM2, which means that each element (pointer) in the DST_PTRS array will be set to point to the element at the corresponding position in the SRC_PTRS array according to the second mapping relationship. For example, for each index i, DST_PTRS[i]=&SRC_PTRS[PERM2[i]] is set. In this way, each pointer in the DST_PTRS array points to the memory location specified by PERM2 in the SRC_PTRS array.

[0039] When all elements in the SRC_PTRS and DST_PTRS arrays have been visited once in a random sequence, i.e., the random access chain with bidirectional jumps is completed. It ensures that each element in the SRC_PTRS array is visited at least once, and each element points to an element in the DST_PTRS, and vice versa. In this way, the mutual access between the elements of the two arrays is completed. Through the above operation, we determine the complete access path from the source node to the target node and back to the source node, i.e., the random access chain.

[0040] Thus, through the above two-step operation, the bidirectional jump path from SRC_PTRS to DST_PTRS and back to SRC_PTRS is completed. This path simulates the memory access process from the first node to the second node and back to the first node, which ensures the randomness of memory access, because the access order is determined by two independent random sequences, rather than a fixed or predictable pattern. Simulates the complex memory access pattern that may occur in a NUMA system, which helps to more accurately measure memory access latency.

[0041] According to an embodiment of the present application, before performing the first preset number of double jump pointer dereference operations based on the random access chain, the memory access latency measurement method further comprises: determining that the current pointer variable used to traverse the random access chain is of a preset variable type, and inserting a memory barrier at the target position.

[0042] Specifically, before performing the double jump pointer dereference operation based on the random access chain, it is necessary to ensure the accuracy and reliability of the memory access latency measurement. That is, the current pointer variable used to traverse the random access chain is determined to be of a preset variable type, and a memory barrier is inserted at the target position. For example, before starting to perform the double jump pointer dereference operation, a variable is needed to track the current pointer position traversed. This variable is called the "current pointer variable". In order to ensure that the value of this variable is not optimized out by the compiler during execution, it needs to be declared as a preset type (such as volatile type). The volatile keyword tells the compiler that the variable may be changed anywhere in the program, so the compiler should not optimize it. By using the volatile type of the current pointer variable, it is ensured that the value of the variable can be accurately tracked and updated during execution, thereby ensuring the accuracy of the test.

[0043] Memory barrier is a synchronization mechanism used to control the execution order of memory operations. Inserting a memory barrier at the target position can prevent the compiler and processor from reordering memory access operations, ensuring the order of memory access. Inserting a memory barrier at the target position of the double jump pointer dereference operation ensures that the memory operations before the barrier are completed before the memory operations after the barrier are executed.

[0044] It should be noted that in each loop of traversing the double random pointer chain, only two actions really complete the cross-node memory access: the first dereference, the CPU jumps from the current node to the target node, and the second dereference, the CPU jumps from the target node back to the source node, so the target position is before and after the two dereference instructions. A "read barrier" is inserted before dereferencing to ensure that all previous instructions have been completed; a "general memory barrier" is inserted again after dereferencing to ensure that the results of this memory access are immediately visible to all CPU cores, preventing out-of-order execution from advancing subsequent timing instructions. Moreover, inserting barrier instructions can prevent the compiler from rearranging, that is, volatile prevents the compiler from optimizing away memory access statements; barrier instructions prevent the compiler from swapping the order of the previous and subsequent instructions. And prevent CPU out-of-order execution, that is, modern CPUs will rearrange instructions to improve parallelism, and the barrier forces "complete memory access before executing the next instruction", making the timing interval accurately correspond to the two real cross-node accesses. It can ensure that the cache coherence protocol has pulled the latest data from the remote node to the CPU, avoiding the measurement of old data in the cache. Thus, it can prevent the compiler and processor from unnecessarily optimizing memory access operations, thereby ensuring the accuracy and reliability of the test results.

[0045] According to one embodiment of the present application, the double jump pointer dereference operation is performed, including: starting from the first node, performing the first dereference jump to the second node according to the current pointer; after the first dereference jump to the second node, performing the second dereference jump back to the first node based on the determined second node, and updating the current pointer after jumping back to the first node.

[0046] Specifically, the double jump pointer dereference operation is a method for measuring memory access delay in a NUMA system, which simulates the complexity of cross-node memory access. That is, when performing the double jump pointer dereference operation, starting from the first node, the first dereference jump is performed to the second node according to the current pointer, that is, the first node (the source NUMA node) is the starting node of the memory access request, and the test thread runs here. On this node, there is a pointer array SRC_PTRS, and each element in the array is a pointer to a memory location on the second node. The test thread obtains the first pointer from the starting position of the SRC_PTRS array, and uses the pointer to access the memory on the second node (the target NUMA node). This is equivalent to initiating a memory access request from the source node to the memory on the target node, and through the dereference operation, the test thread realizes the jump from the first node to the second node.

[0047] After the first dereference jump to the second node, a second dereference jump back to the first node can be made based on the determined second node, and the current pointer can be updated after jumping back to the first node. That is, after the first jump, the test thread is now on the second node and holds a pointer to the memory location within the second node, and using this pointer, a second dereference is made to jump back to the first node. This is equivalent to accessing the memory of the source node from the target node, and through the second dereference operation, the test thread achieves a jump from the second node back to the first node.

[0048] After completing the second dereference, the test thread is back to the first node and holds a new pointer to the next element in the SRC_PTRS array. The current pointer held by the test thread is updated to point to the next element in the SRC_PTRS array, in preparation for the next double jump operation. Thus, this double jump operation simulates a memory access pattern that can occur in a NUMA system, which helps to evaluate the performance of the system when accessing memory across nodes.

[0049] According to one embodiment of the present application, the memory access delay is determined based on the total time and the first preset number of times, including: in a non-uniform memory access mode, determining the memory access delay based on one half of the ratio of the total time to the first preset number of times; in a single node mode, determining the memory access delay based on the ratio of the total time to the first preset number of times.

[0050] Specifically, when performing a double jump pointer dereference operation, the start and end times can be recorded by a high-precision timer to calculate the total time of the operation, which represents the time required to complete all preset numbers of memory accesses. When determining the total time, the current memory mode can be judged, and in a non-uniform memory access mode (NUMA mode), the memory access delay can be determined based on one half of the ratio of the total time to the first preset number of times. That is, in this mode, the test thread initiates memory access from the source NUMA node, jumps to the target NUMA node, and then jumps back to the source NUMA node, each jump including two memory accesses (one to the target node and one back to the source node). In NUMA mode, if two memory accesses are performed, the memory access delay is the total time divided by twice the preset number of times, because two memory accesses are performed in each loop.

[0051] In a single node mode, the memory access delay can be determined based on the ratio of the total time to the first preset number of times. That is, in this mode, the test thread performs memory access operations on the same NUMA node without cross-node jumps, and in a single node mode, only one memory access is performed per loop, so the memory access delay is the total time divided by the preset number of times.

[0052] For example, starting from the first element of the SRC_PTRS array, the current pointer is used for the first dereference to access the corresponding element in the DST_PTRS array. The second dereference from the element in the DST_PTRS array jumps back to the next element in the SRC_PTRS array. The current pointer is updated to point to the next element in the SRC_PTRS array, and the above operations are repeated until a preset number of loops is completed. Before starting to perform the double jump operations, the starting point of the high-precision timer is recorded, and after completing all the double jump operations, the ending point is recorded, i.e., the total time = ending point - starting point. In the NUMA mode: memory access delay = total time / (2 x preset number), in the single-node mode: memory access delay = total time / preset number.

[0053] Thus, this method can accurately measure the memory access delay in different modes, providing data support for system performance tuning. Through this measurement, performance bottlenecks such as high cross-node access delay can be identified, thereby guiding optimization strategies such as data and task affinity optimization.

[0054] According to one embodiment of the present application, the memory access delay measurement method further comprises: before testing the memory access delay, sequentially accessing a test memory region allocated on the second node and performing a second preset number of jump pointer dereference operations, wherein the second preset number is a preset proportion of the first preset number, and the second preset number is not counted in the number of times of calculating the memory access delay.

[0055] Specifically, a series of preparatory operations can also be performed before formal measurement, which aims to ensure the stability and consistency of the test environment. That is, before testing the memory access delay, the test memory region allocated on the second node can be sequentially accessed, that is, a certain amount of test memory region is allocated on the target NUMA node. This memory region will be used to simulate actual memory access operations. Before formally testing the random access mode, the test memory region allocated on the second node is sequentially accessed. The purpose of this is to trigger the page scheduling and possible page error handling of the operating system, ensuring that all needed memory pages have been loaded into the physical memory.

[0056] and performing a second preset number of jump pointer dereference operations, wherein the second preset number is set as a preset number, which is a preset proportion of the first preset number (i.e., the number of loops in the formal test), for example, 10% or 20%. And performing a second preset number of jump pointer dereference operations, which are not counted in the final memory access delay calculation. The purpose of these operations is to further stabilize the state of the CPU cache and branch predictor, ensuring that they are in a predictable state during the formal test.

[0057] Thus, by sequentially accessing and performing a certain number of pointer jumping dereferencing operations, the memory and CPU cache can be warmed up, reducing the possibility of cache miss and branch prediction error, which helps to stabilize the running state of the system, making the results of the formal test more reliable and consistent.

[0058] According to one embodiment of the present application, binding the test execution thread to the first node comprises: determining the processor core on which the test execution thread should run based on a processor set bitmask; and associating the test execution thread with the processor core based on a thread library function to bind the test execution thread to the first node, wherein the thread library function is used to set the affinity of the processor core.

[0059] Specifically, when binding the test execution thread to the first node, the processor core on which the test execution thread should run can be determined based on a processor set bitmask, for example, a bitmask representing a specific set of CPU cores is created using the processor set bitmask (such as through the cpu_set_t data structure), and in a NUMA system, each node contains a specific set of CPU cores. By setting specific bits in the bitmask, the CPU cores on which the test thread is expected to run can be selected. For example, if the thread is expected to run on core 0 and core 1, the positions in the bitmask corresponding to core 0 and core 1 will be set to 1.

[0060] And associating the test execution thread with the processor core based on a thread library function to bind the test execution thread to the first node, wherein the thread library function is used to set the affinity of the processor core. For example, a function provided by the thread library (such as the POSIX thread library) (such as sched_setaffinity) is used to set the CPU affinity of the thread, and this function allows the thread to be associated with a specific set of CPU cores. Through the above setting, the test thread is bound to specific CPU cores on the first node (the source NUMA node). This means that all execution of the test thread will be limited to these cores.

[0061] Thus, by binding the test thread to specific CPU cores, the overhead of context switching can be reduced, and the locality of the cache can be improved, thereby more accurately measuring memory access latency, ensuring that the test is performed in a controllable environment, and avoiding unstable test results due to thread migration between different cores.

[0062] According to one embodiment of the present application, allocating a test memory region on the second node comprises: in the case of a measurement initialization phase, allocating memory to the second node based on a memory allocation strategy of the specified node or a round-robin allocation strategy between multiple nodes; and in the case of completion of the measurement initialization phase, allocating memory to the second node based on a forced binding memory allocation strategy.

[0063] Specifically, in a NUMA system, memory allocation strategy is crucial for optimizing memory access latency and overall system performance. When allocating test memory regions on the second node, two main memory allocation strategies can be chosen during the initialization phase of the test, namely the node-specific memory allocation strategy: using the MPOL_BIND policy, forcing memory allocation on a specific second node (target NUMA node). Alternatively, the multi-node round-robin allocation strategy: using the MPOL_INTERLEAVE policy, allocating memory round-robin across multiple nodes, which helps to balance the load and improve memory bandwidth utilization.

[0064] After the measurement initialization phase is completed, in order to ensure the accuracy and repeatability of the test, the forced binding memory allocation strategy can be used. Using the MPOL_BIND policy, memory is forced to be allocated to the second node, ensuring that all test memory accesses are directed to this node. Thus, according to the selected strategy, memory allocation operations can be performed. For example, using standard library functions such as malloc or calloc to allocate memory.

[0065] In this way, by forcing memory allocation to the second node, it can be ensured that all memory accesses are directed to this node, thus accurately measuring the memory access latency from the source node to the target node. Using the round-robin strategy in the initialization phase can balance the load, while using the forced binding strategy in the measurement phase can ensure the consistency and repeatability of the test results.

[0066] According to an embodiment of the present application, the memory access latency measurement method further comprises: in the case of the measurement initialization phase, allocating a fixed memory block larger than a preset capacity to the second node at a target location, wherein the target location is a non-local first node location. Wherein the preset capacity can be determined according to actual conditions.

[0067] In particular, in a NUMA (Non-Uniform Memory Access) system, a key step in the initialization phase of the memory access latency measurement method is to allocate a fixed memory block larger than the preset capacity to the second node at the target location. This process helps to ensure the stability and consistency of the test environment, thereby obtaining more accurate memory access latency data. That is, in a NUMA system, the target location refers to the location of a non-local first node, that is, any other NUMA node except the source NUMA node. In the case of measurement initialization, according to the needs of the test, a memory capacity is preset, which can be based on the purpose of the test and the performance characteristics of the system, for example, the preset capacity is hundreds of MB or even GB level, far exceeding the tens of MB capacity of a typical LLC (Last Level Cache). In the measurement initialization phase, a memory block larger than the preset capacity is allocated. The size of this memory block needs to be large enough to ensure that it cannot be completely cached, so as to truly reflect the memory access latency.

[0068] A target NUMA node is selected, and a memory block is allocated to this node. This node should be non-local, that is, not the node where the source NUMA node is located. For example, the memory block is allocated to the second node using system calls. This process can involve specific NUMA library functions that can ensure that the memory is allocated to the specified NUMA node. In addition, after confirming that the memory block has been successfully allocated to the second node at the target location, this step can involve checking the allocated memory address to ensure that it is within the memory region of the second node. It should be noted that the target location is not limited to the farthest node, but can be specified by the user or traversed in a matrix, and the access latency of any remote NUMA node can be tested, including: the physically farthest node (across two or more interconnection levels), and any non-local node (only across one interconnection) logically.

[0069] Therefore, by allocating a fixed memory block at the target location, the test environment can be stabilized, and the delay fluctuations caused by memory allocation and page scheduling can be reduced, ensuring the accuracy of the test results, because the size and location of the memory block are carefully selected to reflect the true memory access latency.

[0070] According to an embodiment of the present application, the memory access latency measurement method further comprises: determining the topology of the non-uniform memory access based on a preset instruction; in the case that the topology is not successfully acquired, stopping the measurement of the memory access latency and generating a corresponding error code; in the case that the topology is successfully acquired, taking the largest node number as the topology reference to construct a non-uniform memory access node topology mapping table and output a visual structure.

[0071] Specifically, the topology of non-uniform memory access is determined according to the preset instruction, for example, the NUMA topology of the system is probed using the preset instruction (such as the numactl command). This involves identifying how many NUMA nodes there are in the system, how many CPU cores are on each node, and how these nodes are connected to each other. For example, the output can include: the number of each NUMA node, the number of CPU cores included in each node, the total amount of memory of each node, the distance between nodes, etc. In the case of unsuccessful acquisition of the topology, the measurement of the memory access delay can be stopped, and the corresponding error code can be generated. That is, if for some reason (such as the system not supporting NUMA or the instruction execution error), the NUMA topology is not successfully acquired, the memory access delay measurement process should be stopped. In this case, the system should generate a corresponding error code or message indicating that the topology acquisition has failed, and may provide the reason for the error or suggested steps to resolve the problem.

[0072] In the case of successful acquisition of the topology, the largest node number can be used as the topology reference, and a non-uniform memory access node topology mapping table can be constructed and a visual structure can be output. That is, once the NUMA topology of the system is successfully acquired, this information can be used to construct a mapping table that describes the layout of the NUMA nodes in detail. Using the largest node number as the topology reference means selecting the highest numbered node as the reference point to construct the topology mapping table of the entire system. According to the collected information, a mapping table can be constructed, which can be a data structure or a graphical interface, to show the topology of the NUMA nodes, and the output of the visual structure can help users more intuitively understand the NUMA topology of the system and identify the location of each node and their connection relationship.

[0073] Thus, by considering the NUMA topology, the memory access delay can be more accurately measured and analyzed, and understanding the topology of the system helps to optimize the memory access pattern of the application program, thereby improving the performance of the system.

[0074] According to one embodiment of the present application, the memory access delay measurement method further comprises: determining the number of topology nodes in the topology, and taking the topology nodes as the first nodes, and sequentially taking the current first node as the second node on the first node for delay measurement to form a visual structure.

[0075] Specifically, the total number of NUMA nodes (topology nodes) present in the system is identified, which are groups of processor cores with independent memory regions. For example, using system tools (such as numactl) or system calls (such as sched_getaffinity) to probe and confirm the number of NUMA nodes in the system, record the number of each NUMA node present in the system and their characteristics (such as CPU core number, memory size, etc.). Select one NUMA node as the starting measurement point (first node) and initiate memory access requests from this node to other nodes. That is, select a NUMA node as the first node, which can be an arbitrary node in the system, and can be selected based on test requirements or system configuration.

[0076] Measure the memory access delay from the selected first node to all other nodes (second nodes) in the system. That is, for each other NUMA node in the system, in turn, take them as the second node, initiate memory access requests from the first node to these nodes, measure and record the memory access delay from the first node to each second node, and display the measurement results in a graphical manner to facilitate analysis and understanding of the memory access delay between different nodes. For example, the available node list can be extracted using regular expressions, and the physical node number is converted to the internal label of the test system. The test system automatically generates a test matrix according to the number of nodes found, such as the table header: the first row title: Target, and the subsequent column titles: "N0", "N1",..., "Nn" (n is the maximum node number), and the row title is generated: each row starts with "Source", followed by the fields: "N0", "N1",..., "Nn". And through format control, use fixed-width fields (8 characters), left-aligned to ensure consistent display across platforms.

[0077] Thus, using the measured data, a delay matrix is constructed, where the rows and columns of the matrix represent the NUMA nodes in the system, and each element in the matrix represents the memory access delay from a row node to a column node. This delay matrix is visualized in the form of a chart or graph, such as a heat map or network diagram, to visually display the access delay between different nodes.

[0078] According to one embodiment of the present application, the memory access delay measurement method further comprises: after the memory access delay measurement is completed, releasing the first pointer array and the second pointer array based on a target release function.

[0079] Specifically, in the memory access delay measurement method, it is very important to ensure that the allocated memory is released correctly after the measurement is completed. This not only helps to avoid memory leaks, but also ensures the stability and reliability of the program. That is, after the measurement of memory access delay is completed, the first pointer array and the second pointer array can be released based on the target release function. For example, the target release function refers to a function used to release a specific memory region. In different programming languages and environments, these functions can have different names and implementations. For example, in C language, the free function can be used. Release the first pointer array (SRC_PTRS, SRC_PTRS is a pointer array allocated on the source node, used to store pointers to the target node. After the test is completed, this part of memory must be released, that is, use the target release function to release SRC_PTRS, to ensure that the entire array is released, not a single pointer in the array.

[0080] Release the second pointer array (DST_PTRS), DST_PTRS is a pointer array allocated on the target node, used to store pointers to the source node. After the test is completed, this part of memory must be released. DST_PTRS can be released using the target release function, ensuring that the entire array is released, not a single pointer in the array.

[0081] In this way, the key steps to ensure the stable operation of the program and avoid memory leaks can be ensured. By immediately releasing memory, checking the correctness of the release operation, and using memory management tools, the problem of memory leaks can be effectively avoided.

[0082] In addition, the memory delay measurement tool in the related art (such as Intel Memory Latency Checker) can usually only run on an x86 platform, the source code is closed, and there is only a binary program, which cannot be used on an ARM (Advanced RISC Machine) platform, lacking cross-platform support. That is, the x86 platform: using the rdtsc (Read Time-Stamp Counter) instruction, which is a high-precision hardware timer that can provide nanosecond-level timing accuracy. ARM platform: using cntvct_el0 (Counter Virtual Count Register), which is a system counter in the ARM architecture, also capable of providing high-precision timing. In an embodiment of the present application, the appropriate timing source can be automatically selected according to the running platform. That is, the user does not need to manually configure the timer, and the system will automatically select rdtsc or cntvct_el0 according to the current running platform, thereby ensuring accurate timing on different platforms. That is, conditional compilation instructions can be used to distinguish the code implementation of different platforms. This ensures that the code can be correctly compiled and run on x86 and ARM platforms. By defining an abstract timing interface, the specific timing function is called through the interface. This can hide the specific implementation details of different platforms, so that the upper-layer code remains consistent on different platforms.

[0083] And to ensure the accuracy of the timer readings, the timer readings can be converted to nanosecond-level absolute time. This step is crucial for cross-platform measurement, as the timer frequencies of different platforms may be different. Through the calibration mechanism, it can be ensured that the results measured on different platforms are comparable. That is, the delay can be calculated by taking the median of a predetermined number of measurements (such as 10,000 times), which can effectively reduce measurement errors and random fluctuations. The specific calculation formula is: latency_ns=(end-start) / cpu_freq. Where end and start are the readings of the timer, and cpu_freq is the frequency of the timer. By automatically selecting a high-precision timing source (rdtsc and cntvct_el0), accurate timing can be performed on x86 and ARM platforms, and by calibrating the timer frequency, the results measured on different platforms are comparable. Thus, the problem of lack of cross-platform support in the prior art is solved, and the accuracy and consistency of the measurement are improved.

[0084] The method of the present application will be described below in conjunction with Figure 2 .

[0085] As a specific example, the memory access delay measurement method of the present application can include the following steps:

[0086] S101, binding a test execution thread to a first node and allocating a test memory region on a second node, wherein the first node is a node initiating a memory access operation and the second node is a node where a memory storing accessed data is located.

[0087] S102, creating a first pointer array on the first node and a second pointer array on the second node, and randomly generating a first random sequence and a second random sequence, wherein the first random sequence is used to define a first mapping relationship of elements in the first pointer array pointing to elements in the second pointer array, and the second random sequence is used to define a second mapping relationship of elements in the second pointer array pointing back to elements in the first pointer array.

[0088] S103, based on the first mapping relationship, pointing elements in the first pointer array to corresponding elements in the second pointer array.

[0089] S104, after the corresponding elements in the second pointer array are determined, based on the second mapping relationship, pointing back the corresponding elements in the second pointer array to the corresponding elements in the first pointer array, until the elements in the first pointer array and the second pointer array complete mutual access, and determining a random access chain.

[0090] S105, determining that a current pointer variable used to traverse the random access chain is a preset variable type, and inserting a memory barrier at a target position.

[0091] S106, performing a double jump pointer dereferencing operation a first preset number of times based on the random access chain, and determining a total time of completing the double jump pointer dereferencing operation.

[0092] S107, performing a double jump pointer dereferencing operation a first preset number of times based on the random access chain, and determining a total time of completing the double jump pointer dereferencing operation.

[0093] S108, determining whether the current is a non-uniform memory access mode. If yes, performing step S109; if no, performing step S111.

[0094] S109, determining a memory access delay based on half of a ratio of the total time to the first preset number of times.

[0095] S110, after completing the measurement of the memory access delay, releasing the first pointer array and the second pointer array based on a target release function.

[0096] S111, in a single node mode, determining a memory access delay based on a ratio of the total time to the first preset number of times, and entering step S110.

[0097] In summary, according to the memory access delay measurement method of the embodiment of the present application, the test execution thread is bound to the first node, and the test memory region is allocated on the second node, wherein the first node is the node initiating the memory access operation, and the second node is the node where the accessed data is stored; the first pointer array is created on the first node, and the second pointer array is created on the second node, and the first random sequence and the second random sequence are randomly generated, wherein the element in the first pointer array represents the target address of the memory access request initiated from the first node, and points to a memory location of the test memory region on the second node, the element in the second pointer array represents a memory location of the test memory region on the second node, and the memory location is pointed to by the element in the first pointer array on the first node, the first random sequence is used to define the first mapping relationship of the element in the first pointer array pointing to the element in the second pointer array, and the second random sequence is used to define the second mapping relationship of the element in the second pointer array pointing back to the element in the first pointer array; the random access chain for bidirectional jumping between the first node and the second node is determined based on the first mapping relationship, the second mapping relationship, the first pointer array and the second pointer array; the double jump pointer dereferencing operation is performed for the first preset number of times based on the random access chain, and the total time for completing the double jump pointer dereferencing operation is determined; and the memory access delay is determined based on the total time and the first preset number. Thus, the method can eliminate the interference of cache prefetching and out-of-order execution on delay measurement, and improve the accuracy of memory access delay measurement.

[0098] Corresponding to the above embodiment, the present application also provides a computer program product.

[0099] The computer program product of the embodiment of the present application comprises computer programs / instructions, which, when executed by a processor, implement the above-mentioned memory access delay measurement method.

[0100] According to the computer program product of the embodiment of the present application, by executing the above-mentioned memory access delay measurement method, the interference of cache prefetching and out-of-order execution on delay measurement can be eliminated, and the accuracy of memory access delay measurement can be improved.

[0101] Corresponding to the above embodiment, the present application also provides a non-volatile computer readable storage medium.

[0102] The non-volatile computer readable storage medium of the embodiment of the present application has a program stored thereon, which, when executed by a processor, implements the above-mentioned memory access delay measurement method.

[0103] According to the non-volatile computer readable storage medium of the embodiment of the present application, by executing the above-mentioned memory access delay measurement method, the interference of cache prefetching and out-of-order execution on delay measurement can be eliminated, and the accuracy of memory access delay measurement can be improved.

[0104] Corresponding to the above embodiment, the present application also provides an electronic device.

[0105] As shown in Figure 3 the electronic device 200 of the embodiment of the present application can include a memory 210, a processor 220, and a program stored in the memory 210 and executable on the processor 220, and the processor 220 implements the memory access latency measurement method described above when executing the program.

[0106] According to the electronic device of the embodiment of the present application, by executing the memory access latency measurement method described above, the interference of cache prefetch and out-of-order execution on delay measurement can be eliminated, and the accuracy of memory access latency measurement can be improved.

[0107] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a list of executable instructions for implementing logic functions, and can be specifically embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus or device, such as a computer-based system, a system including a processor, or other system that can fetch the instructions from the instruction execution system, apparatus or device and execute the instructions, or in conjunction with these instruction execution systems, apparatus or devices. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transport programs for use by or in connection with an instruction execution system, apparatus or device, or in conjunction with these instruction execution systems, apparatus or devices. More specific examples (non-exhaustive list) of computer-readable medium include the following: electrical connections having one or more wires (electronic devices), portable computer diskette (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable compact disc read-only memory (CD ROM). In addition, the computer-readable medium can even be paper or other suitable medium on which the program can be printed, as the program can be electronically obtained, for example, by optical scanning of the paper or other medium, followed by electronic conversion, interpretation or processing, if necessary, in other suitable manner, and then stored in a computer memory.

[0108] It should be understood that parts of the present application can be realized in hardware, software, firmware or a combination thereof. In the above-described embodiments, a plurality of steps or methods can be realized by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if realized in hardware, and as in another embodiment, any one or a combination of the following technologies known in the art can be used: discrete logic circuit with logic gates for implementing logic functions on data signals, application specific integrated circuit with suitable combination logic gates, programmable gate array (PGA), field programmable gate array (FPGA), etc.

[0109] In the description of the application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the application. In the description of the application, the illustrative description of the above terms does not necessarily mean the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0110] In addition, the terms "first", "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise explicitly specified and limited.

[0111] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection", "fixing" and other terms should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integral; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, it can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0112] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. A method of measuring memory access latency, the method comprising: The method comprises: binding a test execution thread to a first node, and allocating a test memory area on a second node, wherein the first node is a node initiating a memory access operation, and the second node is a node where data accessed is stored in a memory; creating a first pointer array on the first node and a second pointer array on the second node, and randomly generating a first random sequence and a second random sequence, wherein elements in the first pointer array represent target addresses of memory access requests initiated from the first node, pointing to a memory location of the test memory area on the second node, elements in the second pointer array represent a memory location of the test memory area on the second node, which is pointed to by elements in the first pointer array on the first node, the first random sequence is used to define a first mapping relationship of elements in the first pointer array pointing to elements in the second pointer array, and the second random sequence is used to define a second mapping relationship of elements in the second pointer array pointing back to elements in the first pointer array; determining a random access chain for bidirectional jumping between the first node and the second node based on the first mapping relationship, the second mapping relationship, the first pointer array and the second pointer array; performing a double jump pointer dereferencing operation for a first preset number of times based on the random access chain, and determining a total time for completing the double jump pointer dereferencing operation; determining a memory access delay based on the total time and the first preset number.

2. The memory access latency measurement method of claim 1, wherein, The determining of the random access chain for bidirectional jumping between the first node and the second node based on the first mapping relationship, the second mapping relationship, the first pointer array and the second pointer array comprises: pointing elements in the first pointer array to corresponding elements in the second pointer array based on the first mapping relationship; after the corresponding elements in the second pointer array are determined, pointing the corresponding elements in the second pointer array back to the corresponding elements in the first pointer array based on the second mapping relationship, until the elements in the first pointer array and the second pointer array access each other, the random access chain is determined.

3. The memory access latency measurement method of claim 1, wherein, Before the performing of the double jump pointer dereferencing operation for the first preset number of times based on the random access chain, the method further comprises: determining that a current pointer variable used to traverse the random access chain is of a preset variable type, and inserting a memory barrier at a target position.

4. The memory access latency measurement method of claim 3, wherein, The performing of the double jump pointer dereferencing operation comprises: starting from the first node, performing a first dereferencing jump to the second node according to a current pointer; after the first dereferencing jump to the second node, performing a second dereferencing jump back to the first node based on the determined second node, and updating the current pointer after jumping back to the first node.

5. The memory access latency measurement method of claim 1, wherein, The determining of the memory access delay based on the total time and the first preset number comprises: in a non-uniform memory access mode, determining the memory access delay based on one half of a ratio of the total time to the first preset number. In the single-node mode, the memory access latency is determined based on a ratio of the total time to the first preset number of times.

6. The memory access latency measurement method of claim 5, wherein, The method further comprises: Before testing the memory access latency, sequentially accessing a test memory region allocated on the second node and performing a second preset number of times of pointer dereferencing operations, wherein the second preset number of times is a preset proportion of the first preset number of times, and the second preset number of times is not counted in the number of times for calculating the memory access latency.

7. The memory access latency measurement method of claim 1, wherein, The binding of the test execution thread to the first node comprises: Determining, based on a processor set bit mask, a processor core on which the test execution thread should run; Associating, based on a thread library function, the test execution thread with the processor core to bind the test execution thread to the first node, wherein the thread library function is used to set the affinity of the processor core.

8. The memory access latency measurement method of claim 1, wherein, The allocation of the test memory region on the second node comprises: In the case of a measurement initialization phase, allocating memory to the second node based on a memory allocation strategy of a specified node or a round-robin allocation strategy between multiple nodes; In the case of completion of the measurement initialization phase, allocating memory to the second node based on a forced binding memory allocation strategy.

9. The memory access latency measurement method of claim 8, wherein, The method further comprises: In the case of the measurement initialization phase, allocating a fixed memory block larger than a preset capacity to the second node at a target location, wherein the target location is a location other than the first node.

10. The memory access latency measurement method of claim 1, wherein, The method further comprises: Determining, based on a preset instruction, a topology of non-uniform memory access; In the case of unsuccessful acquisition of the topology, stopping the measurement of the memory access latency and generating a corresponding error code; In the case of successful acquisition of the topology, taking the largest node number as a topology reference to construct a non-uniform memory access node topology mapping table and output a visualized structure.

11. The memory access latency measurement method of claim 10, wherein, The method further comprises: Determining the number of topology nodes in the topology and taking the topology nodes as the first nodes, sequentially taking the current first node as the second node on the first node for delay measurement to form the visualized structure.

12. The memory access latency measurement method of claim 1, wherein, The method further comprises: After completion of the measurement of the memory access latency, releasing the first pointer array and the second pointer array based on a target release function.

13. A computer program product comprising computer programs / instructions, characterized in that, The computer program / instruction is executed by a processor to implement the memory access latency measurement method according to any one of claims 1-12.

14. A non-transitory computer readable storage medium, comprising: A computer program / instruction is executed by a processor to implement the memory access latency measurement method according to any one of claims 1-12.

15. An electronic device, comprising: Comprise: a memory, a processor, and a program stored on the memory and executable on the processor, wherein the processor executes the program to implement the memory access latency measurement method according to any one of claims 1-12.

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