Clock synchronization method, chip, and multi-chip interconnection system

Abstract

The application provides a clock synchronization method, a chip and a multi-chip interconnection system. The clock synchronization method of a slave chip connected with a master chip through a high-speed general interconnection bus and a clock special physical pin includes the following steps: receiving a first synchronization signal periodically sent by the master chip through the high-speed general interconnection bus, updating high M bits of a timer of the slave chip according to the first synchronization signal, so that the high M bits of the timer of the slave chip are equal to those of the master chip; receiving a second synchronization signal periodically sent by the master chip through the clock special physical pin, updating low N bits of the timer of the slave chip according to the second synchronization signal, so that the low N bits of the timer of the slave chip are equal to those of the master chip; wherein the sum of M and N is less than or equal to K, K is the bit number of the timer, and M, N and K are all positive integers. The method no longer needs to occupy a special low-speed interface such as I2C or SPI, and the demand for pins is reduced from at least 4 to 1.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the chip technical field, and in particular to a clock synchronization method, a chip, and a multi-chip interconnection system. BACKGROUND

[0002] The multi-chip interconnection system is composed of one master chip (Mst) and multiple slave chips (Slv). Due to factors such as power-on sequence, start-before-and-after sequence, and timer jitter of the multi-chip interconnection system, the system time in each chip will be inconsistent, which leads to the upper-layer operating system being unable to work. Therefore, the timers in each chip need to be synchronized.

[0003] Generally, a dedicated low-speed Inter Integrated Circuit (I2C) bus or Serial Peripheral Interface (SPI) bus on the chip, as well as a REQuest (REQ) and ACKnowledge (ACK) physical pin, are used to perform time synchronization between chips in the multi-chip interconnection system, which occupies a large number of physical resources on the chip. SUMMARY

[0004] In view of this, embodiments of the present application provide a clock synchronization method, a chip, and a multi-chip interconnection system to at least solve or alleviate the above problems.

[0005] According to a first aspect of embodiments of the present application, a clock synchronization method is provided, applied to a slave chip, the slave chip being connected with a master chip through a high-speed general-purpose interconnection bus and a clock-specific physical pin, and the method comprising:

[0006] receiving a first synchronization signal periodically sent by the master chip through the high-speed general-purpose interconnection bus, and updating high M bits of a timer of the slave chip according to the first synchronization signal, so that the high M bits of the timer of the slave chip are equal to those of the master chip;

[0007] receiving a second synchronization signal periodically sent by the master chip through the clock-specific physical pin, and updating low N bits of the timer of the slave chip according to the second synchronization signal, so that the low N bits of the timer of the slave chip are equal to those of the master chip;

[0008] wherein the sum of M and N is less than or equal to K, K is the number of bits of the timer, and M, N, and K are all positive integers.

[0009] According to a second aspect of the embodiments of the present application, a clock synchronization method is provided, which is applied to a master chip, and the master chip is connected with a slave chip through a high-speed general interconnection bus and a clock special physical pin, and the method comprises the following steps of:

[0010] periodically sending a first synchronization signal to the slave chip through the high-speed general interconnection bus, and the first synchronization signal is used for instructing to update high M bits of a timer of the slave chip, so that the high M bits of the timer of the slave chip are equal to the high M bits of the timer of the master chip;

[0011] periodically sending a second synchronization signal to the slave chip through the clock special physical pin, and the second synchronization signal is used for instructing to update low N bits of the timer of the slave chip, so that the low N bits of the timer of the slave chip are equal to the low N bits of the timer of the master chip;

[0012] wherein, the sum of M and N is less than or equal to K, K is the bit number of the timer, and M, N and K are all positive integers.

[0013] According to a third aspect of the embodiments of the present application, a chip is provided, which is used for executing the clock synchronization method provided in the first aspect above, or executing the clock synchronization method provided in the second aspect above.

[0014] According to a fourth aspect of the embodiments of the present application, a multi-chip interconnection system is provided, which comprises a master chip and a plurality of slave chips, and the master chip is interconnected with the slave chips through a high-speed general interconnection bus and a clock special physical pin;

[0015] the slave chip is used for executing the clock synchronization method provided in the first aspect above;

[0016] the master chip is used for executing the clock synchronization method provided in the second aspect above.

[0017] According to the clock synchronization scheme provided in the embodiment of the present application, the master chip and the slave chip are connected through the high-speed general-purpose interconnection bus and a clock special physical pin. During the clock synchronization process, the master chip periodically sends the first synchronization signal to the slave chip through the high-speed general-purpose interconnection bus, so that the slave chip updates the high M bits of the local timer according to the first synchronization signal, to synchronize the high M bits of the timers of the master chip and the slave chip. The master chip periodically sends the second synchronization signal to the slave chip through the clock special physical pin, so that the slave chip updates the low N bits of the local timer according to the second synchronization signal, to synchronize the low N bits of the timers of the master chip and the slave chip. The clock synchronization is realized through the high-speed general-purpose interconnection bus and the clock special physical pin, and a special low-speed interface such as I2C or SPI is no longer needed, and the requirement for the pin is reduced from the minimum of 4 (including 2 of I2C, and REQ and ACK) to 1, greatly reducing the physical resources occupied by the clock synchronization. Meanwhile, it is also ensured that the decimal field monotonically increases and the Gray code field single-bit flips during the timer value updating process of the slave chip in the typical application. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can also be obtained by those skilled in the art according to these drawings.

[0019] Figure 1 is a schematic diagram of a multi-chip interconnection system provided by an exemplary embodiment of the present application;

[0020] Figure 2 is a schematic diagram of a clock synchronization path of the interconnected chips provided by an exemplary embodiment of the present application;

[0021] Figure 3 is a flowchart of a clock synchronization method provided by an exemplary embodiment of the present application;

[0022] Figure 4 is a process diagram of aligning each bit of the timer using the Gray code approximation algorithm provided by an exemplary embodiment of the present application;

[0023] Figure 5 is a schematic diagram of periodic alignment of the high bits and the low bits of the timer provided by an exemplary embodiment of the present application;

[0024] Figure 6 is a flowchart of a clock synchronization method provided by another exemplary embodiment of the present application;

[0025] Figure 7is a schematic diagram of a clock synchronization device provided by an example embodiment of the present application;

[0026] Figure 8 is a schematic diagram of a clock synchronization device provided by another example embodiment of the present application;

[0027] Figure 9 is a structural schematic diagram of an electronic device provided by an example embodiment of the present application. DETAILED DESCRIPTION

[0028] The present application is described below based on examples, but the present application is not limited to only these examples. In the following detailed description of the present application, some specific details are described in detail. The present application can also be fully understood without the description of these details by those skilled in the art. In order to avoid confusion of the essence of the present application, well-known methods, processes, and procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0029] Reference is made to Figure 1 , which shows a multi-chip interconnection system 100 provided by an example embodiment of the present application, which includes a master chip 110 and a plurality of slave chips 120.

[0030] As shown in Figure 1 , the multi-chip interconnection system includes Q+1 slave chips 120: Slv 0, Slv 1, …, Slv Q, Q is a positive integer. The master chip 110 is interconnected with each slave chip 120. The master chip 110 and the slave chip 120 are connected at least through a high-speed general interconnection bus and a clock dedicated physical pin. Among them, the high-speed general interconnection bus is also called high-speed general cross-chip communication bus, abbreviated as D2D (Die-to-Die), which is used for transmitting data and synchronization signals between the master chip and the slave chip.

[0031] As shown in Figure 2 , the master chip 110 includes a timer 111, a prescaler 112, an instruction unit 113, and an instruction unit 114. The timer 111 can be a 64-bit timer with a working frequency of 24 megahertz (MHz), which is used to generate a time reference. The prescaler 112 is used to adjust the counting frequency of the timer 111. The binary number output by the timer 111 needs to be converted to Gray code before entering the prescaler 112, in order to reduce the synchronization error caused by the simultaneous flipping of multiple bits inside the chip.

[0032] More instruction units can also be included in the chip, Figure 2Only instruction unit 113 and instruction unit 114 are shown. Instruction unit 114 includes an asynchronous module 115 and a conversion module 116; the asynchronous module 115 is used to process asynchronous communication and ensure correct transmission of data between different clock domains; the conversion module 116 is used to convert data from one format (such as Gray code) to another format (such as binary). Instruction unit 113 has the same structure as instruction unit 114, and will not be described here.

[0033] Chip 120 includes a timer 121, a pre-divider 122, an instruction unit 123, and an instruction unit 124. Timer 121 has the same number of bits and operating frequency as timer 111, and can be a 64-bit timer operating at 24MHz, used to generate a time reference. Pre-divider 122 is used to adjust the counting frequency of timer 121. The binary number output by timer 121 needs to be converted to Gray code before entering pre-divider 122, in order to reduce errors when the counter flips. Instruction unit includes an asynchronous module and a conversion module; the asynchronous module is used to process asynchronous communication and ensure correct transmission of data between different clock domains; the conversion module is used to convert data from one format (such as Gray code) to another format (such as binary).

[0034] Master chip 110 and slave chip 120 are interconnected by D2D 130 and clock dedicated physical pin 140. Timer 111 of master chip 110 and timer 121 of slave chip 120 operate independently to generate their respective time references. Master chip 110 periodically sends a synchronization signal to slave chip 120 through D2D 130 and clock dedicated physical pin 140, and slave chip 120 adjusts timer 121 according to the synchronization signal, so that the system time of slave chip 120 is synchronized with that of master chip 110.

[0035] The clock synchronization method provided by the embodiments of the present application is applied to the multi-chip interconnection system described above, and the implementation of the clock synchronization method will be described in detail through multiple embodiments.

[0036] Figure 3 is a flowchart of the clock synchronization method provided by an exemplary embodiment of the present application. As shown in Figure 3 the clock synchronization method is applied to a slave chip, and the method includes the following steps:

[0037] In step 201, a first synchronization signal periodically sent by a master chip through a high-speed general-purpose interconnection bus is received, and the high M bits of a timer of the slave chip are updated according to the first synchronization signal, so that the high M bits of the timer of the slave chip are equal to those of the master chip, M being a positive integer.

[0038] First, the master chip and the slave chip are powered on at the same time, and the high-speed general interconnection bus is initialized. Then, the master chip configures the module to enable: the time synchronization module of the master chip is enabled, and the time synchronization is prepared; the slave chip configures the module to enable: the time synchronization module of the slave chip is enabled, and the synchronization signal is prepared to be received. After the above steps are completed, the master chip and the slave chip are clocked, the master chip initiates the synchronization operation, and the high M bits of the timers of the master chip and the slave chip are synchronized first; subsequently, the periodic synchronization of the high M bits of the timers and the periodic synchronization of the low N bits of the timers are performed, respectively.

[0039] For the synchronization of the high M bits of the timers between the master chip and the slave chip, the slave chip receives the first synchronization signal periodically sent by the master chip through the high-speed general interconnection bus, and obtains the value of the high M bits of the master chip carried by the first synchronization signal; according to the value of the high M bits of the master chip, the high M bits of the timer of the slave chip are updated, so that the value of the high M bits of the timer of the slave chip is equal to that of the master chip.

[0040] Optionally, the first synchronization signal carries the value of the high M bits of the master chip; a first reference value on the K bits of the timer is determined according to the value of the high M bits of the master chip, and a first value of the timer of the slave chip is obtained in real time; a difference between the first reference value and the first value is calculated to obtain a first difference value; if the first difference value is greater than a first threshold value, the timer of the slave chip is incrementally assigned until the value of the high M bits of the slave chip is equal to that of the master chip; if the first difference value is less than a second threshold value, the high M bits of the timer of the slave chip are directly assigned to the value of the high M bits of the master chip; wherein the first threshold value is a positive number, and the second threshold value is a negative number.

[0041] In a possible implementation manner, if the first difference value is greater than or equal to the second threshold value and less than or equal to the first threshold value, the update of the timer of the slave chip is skipped.

[0042] After updating the high M bits of the timer of the slave chip, the counting continues.

[0043] In step 202, the second synchronization signal periodically sent by the master chip through the clock dedicated physical pin is received, and the low N bits of the timer of the slave chip are updated according to the second synchronization signal, so that the low N bits of the timer of the slave chip are equal to those of the master chip, and the sum of M and N is less than or equal to K, K is the number of bits of the timer, and N and K are both positive integers.

[0044] The timers of the slave chip and the master chip are counters with the same number of bits, such as 64-bit timers.

[0045] For the low N-bit synchronization of the timer between the master chip and the slave chip, the slave chip receives a second synchronization signal periodically sent by the master chip through a clock dedicated physical pin, the second synchronization signal is used to indicate the value of the low (K-M) bit of the master chip; according to the value of the low (K-M) bit of the master chip, the low N-bit of the timer of the slave chip is updated, so that the value of the low N-bit of the timer of the slave chip is equal to that of the master chip. Wherein, the timer of the slave chip is the local timer of the slave chip.

[0046] Optionally, a second reference value on the low (K-M) bit of the timer is determined according to the second synchronization signal, and a second value of the low (K-M) bit of the timer of the slave chip is obtained in real time; a difference between the second reference value and the second value is calculated to obtain a second difference; if the second difference is greater than a third threshold, the timer of the slave chip is incrementally assigned until the value of the low N-bit of the slave chip is equal to that of the master chip; if the second difference is less than a fourth threshold, the low N-bit of the slave chip is assigned to zero; wherein the third threshold is a positive number and the fourth threshold is a negative number.

[0047] In a possible implementation, if the second difference is greater than or equal to 0 and less than or equal to the third threshold, the update of the timer of the chip is skipped this time; if the second difference is greater than or equal to the fourth threshold and less than 0, the timer of the slave chip is controlled to wait for S reference clock cycles, and the value of S is the absolute value of the second difference.

[0048] The transmission delay of the second synchronization signal on the clock dedicated physical pin is fixed, so the slave chip can calculate the second reference value on the low (K-M) bit of the timer according to the value of the low (K-M) bit indicated by the second synchronization signal and the known transmission delay. Optionally, if the second difference is greater than the third threshold, an update delay is also obtained, which is used to indicate the time required to update the low N-bit of the timer of the slave chip; according to the second reference value and the update delay, a target value on the low (K-M) bit is determined; the timer of the slave chip is incrementally assigned, and the value of the low N-bit of the timer of the slave chip is updated to equal to the value of the low N-bit of the target value. Exemplarily, the update delay is a pre-set value; it can be an empirical value, which can make the delay between the updated timer of the slave chip and the timer of the master chip less than a delay threshold. Alternatively, the update delay is determined according to the second reference value and the second value on the low (K-M) bit, for example, if the timer of the slave chip is updated by using a Gray code approximation algorithm, the number of update bits on the low N-bit of the timer is determined according to the second reference value and the second value, and the update delay is determined according to the number of update bits, for example, if 2 levels on the low N-bit are different, 4 reference clock cycles are required for each level to be leveled, and then the update delay is 2*4 reference clock cycles.

[0049] If the sum of M and N is less than K, the assignment is incremented to update the low N bits of the timer of the slave chip, and there can also be a carry calculation to the middle (K-M-N) bits. If the maximum value is reached on the low N bits, the assignment is still incremented, and a carry is generated to the middle (K-M-N) bits. Therefore, the clock synchronization scheme provided in this embodiment ensures timely updating of the middle (K-M-N) bits of the timer. If there is no carry to the middle (K-M-N) bits, the middle (K-M-N) bits of the timer are not updated.

[0050] Optionally, the second synchronization signal is a synchronization signal sent by the master chip when the low N bits of the timer take the value 0; or a synchronization signal sent by the master chip when the low N bits of the timer take the maximum value. For example, the master chip sends the second synchronization signal to the slave chip when the low 16 bits of a 64-bit timer take the value 0; or the master chip sends the second synchronization signal to the slave chip when the low 16 bits of a 64-bit timer take the value 0xFFFF.

[0051] After updating the low N bits of the timer of the slave chip, the counting continues.

[0052] If the sum of M and N is less than K, the K-bit timer is represented as timer[(K-1):0], the high M bits of the timer are represented as timer[(K-1):(K-M)], the middle (K-M-N) bits of the timer are represented as timer[(K-M-1):N], and the low N bits of the timer are represented as timer[(N-1):0]. cnt[(K-M-1):N] represents the number of times of updating the LSB recorded locally by the slave chip. The timer of the master chip is represented as Mst_timer, and the timer of the slave chip is represented as Loc_timer.

[0053] If the value of K is 64, the value of M is 43, and the value of N is 16, the updating process of the master chip and the slave chip is shown in Table 1.

[0054] The first threshold value is set to 128, the second threshold value is set to -128, the third threshold value is set to 16, and the fourth threshold value is set to -16. The first reference value is the value of Mst_timer[63:0] determined by the slave chip according to the first synchronization signal; the first value is the value of Loc_timer[63:0] of the slave chip; and the first difference value is Mst_timer[63:0]-Loc_timer[63:0]. For updating the high 43 bits of the timer of the slave chip:

[0055] 1) If 0≤Mst_timer[63:0]-Loc_timer[63:0]≤128, it indicates that the time of Mst_timer slightly lags behind that of Loc_timer, and Loc_timer is not updated.

[0056] 2) If Mst_timer[63:0] - Loc_timer[63:0] > 128, it means that the time of Mst_timer is greatly ahead of the time of Loc_timer, then the Gray code algorithm is used to incrementally assign Loc_timer[63:21] to Mst_timer[63:21]; after the incremental assignment, Loc_timer is normally accumulated.

[0057] 3) If -128 < Mst_timer[63:0] - Loc_timer[63:0] < 0, it means that the time of Loc_timer is slightly ahead of the time of Mst_timer, and Loc_timer is not updated.

[0058] 4) If Mst_timer[63:0] - Loc_timer[63:0] < -128, it means that the time of Loc_timer is greatly ahead of the time of Mst_timer, and Mst_timer[63:21] is directly assigned to Loc_timer[63:21].

[0059] When the system is started, if the slave chip is started first, the case 4) will occur.

[0060] Table 1

[0061]

[0062] The second reference value is the value of Mst_timer[20:0] determined by the slave chip according to the second synchronization signal, if the second synchronization signal is the synchronization signal sent by the master chip when the value of the low N bits of the timer is the largest, then the second reference value is {cnt[20:16], 0xFFFF}, cnt[20:16] represents the local recording of the slave chip LSB update times, which is equal to the value of Mst_timer[20:16], and 0xFFFF represents the value of Mst_timer[15:0]; the second value is the value of Loc_timer[20:0] of the slave chip; and the second difference is {cnt[20:16], 0xFFFF} - Loc_timer[20:0]. For the update of the low 16 bits of the timer of the slave chip:

[0063] 5) If 0 < {cnt[20:16], 0xFFFF} - Loc_timer[20:0] < 16, it means that the time of Mst_timer is slightly ahead of the time of Loc_timer, and Loc_timer is not updated.

[0064] 6) If {cnt[20:16], 0xFFFF} - Loc_timer[20:0] > 16, it means that the time of Mst_timer is far ahead of Loc_timer, then the Gray code algorithm is used to incrementally assign Loc_timer[15:0] to Mst_timer[15:0], and after the incremental assignment, Loc_timer is normally accumulated.

[0065] As shown in FIG. 1, the timer is updated by using the Gray code approximation algorithm, and the following cases exist. Figure 4

[0066] 1. In the alignment stage of the most significant bit (MSB), if the 64-bit levels of Mst_timer and Loc_timer are all different, it is the worst case. At the MSB alignment time (marked as MSB_UPD in FIG. 1), since each bit of the timer needs 4 reference clock periods for reading, comparing, adjusting and writing, the present update needs 64x4 reference clock periods for bit-by-bit alignment. After the alignment, Slv_timer lags behind Mst_timer by about 256 REF (reference clock) periods. Considering the transmission delay, it can be considered that the lag is less than 512 REF periods. In the present embodiment, the MSB refers to the high 43 bits of the timer. Figure 4

[0067] 2. First LSB alignment. Assuming that the worst case of MSB has occurred, resulting in V<512T, the number of bits involved in the difference in binary is not more than 9 bits, and then there are at most 10 bits different in the Gray code. At the LSB alignment time (marked as LSB_UPD in FIG. 1), about 10x4 REF periods are needed for alignment, resulting in that after the alignment, Slv_timer lags behind Mst_timer by about 40 REF periods. In the present embodiment, the LSB refers to the low 16 bits of the timer. Figure 4

[0068] 3. The worst case of the second LSB alignment. V<64T, then there are at most 7 bits different in the Gray code, resulting in that after the alignment, Slv_timer lags behind Mst_timer by about 28 REF periods.

[0069] 4. The worst case of the third LSB alignment. V<32T, then there are at most 6 bits different in the Gray code, resulting in that after the alignment, Slv_timer lags behind Mst_timer by about 24 REF periods.

[0070] ​​​5. Since 16 < 24 < 32, if the worst case is always maintained, the value of V is pushed in the above manner, and V is maintained at 24, which leads to the worst case of repeatedly entering the LSB. Wherein, T represents the REF period, and V represents Mst_timer-Slv_timer.

[0071] 7) If -16 < {cnt[20:16], 0xFFFF} - Loc_timer[20:0] < 0, wait for S reference clock cycles; after the waiting is over, Loc_timer normally accumulates the time.

[0072] 8) If {cnt[20:16], 0xFFFF} - Loc_timer[20:0] < -16, it indicates that the time of Loc_timer relative to Mst_timer is greatly ahead, and Loc_timer[15:0] is directly cleared.

[0073] In a possible implementation manner, if {cnt[20:16], 0xFFFF} - Loc_timer[20:0] < -16, Loc_timer[20:0] is directly cleared.

[0074] Generally, after the update of Loc_timer[64:21] and Mst_timer[64:21] is aligned, there is no case that Loc_timer[20:0] is greatly ahead of Mst_timer[20:0]; if there is, the chip system cannot normally run, and Loc_timer[15:0] is directly cleared.

[0075] It should be noted that "Gray" in Table 1 indicates the application case of Gray code, if it is "Y", it indicates that the timer can apply Gray code for counting update; if it is "N", it indicates that the timer cannot apply Gray code for counting update. Incr indicates the case of increment operation, if it is "Y", it indicates that the timer can normally increment assignment, if it is "N", it indicates that the timer cannot increment assignment.

[0076] 1), 2), 3), 5), 6) and 7) are the cases that the timer can apply Gray code for counting update; and the timer can normally increment assignment; 4) and 8) are the cases that the timer cannot apply Gray code for counting update; and the timer cannot increment assignment.

[0077] In summary, the clock synchronization method provided in this embodiment connects the master chip and the slave chip via a high-speed universal interconnect bus and a dedicated clock physical pin. During clock synchronization, the master chip periodically sends a first synchronization signal to the slave chip via the high-speed universal interconnect bus, causing the slave chip to update the high M bits of its local timer according to the first synchronization signal, thereby synchronizing the high M bits of the timers of the master chip and the slave chip. The master chip periodically sends a second synchronization signal to the slave chip via the dedicated clock physical pin, causing the slave chip to update the low N bits of its local timer according to the second synchronization signal, thereby synchronizing the low N bits of the timers of the master chip and the slave chip. Clock synchronization is achieved through the high-speed universal interconnect bus and the dedicated clock physical pin, eliminating the need for dedicated low-speed interfaces such as I2C or SPI, and reducing the requirement for dedicated physical pins from a minimum of 4 to 1, greatly reducing the physical resources required for clock synchronization.

[0078] In addition, this clock synchronization method uses hardware to achieve fully automatic initial and periodic clock synchronization between the master chip and the slave chip, without the need for software program perception and intervention. This avoids the uncertain delays caused by software program perception and intervention, as well as the occupation of computing resources by software program perception and intervention, thus improving the efficiency of clock synchronization.

[0079] In one possible implementation, the relationship between the transmission period of the first synchronization signal and the transmission period of the second synchronization signal is expressed as:

[0080] T1 = a × T2;

[0081] T2=b×2 N / f;

[0082] Where T1 represents the transmission period of the first synchronization signal, T2 represents the transmission period of the second synchronization signal, a is a positive integer greater than 1, b is a positive integer, and f is the reference clock frequency of the chip.

[0083] The transmission period of the first synchronization signal is the update period of the high M bits of the timer; the transmission period of the second synchronization signal is the update period of the low N bits of the timer.

[0084] Alternatively, if the sum of M and N is less than the number of bits in the timer, then the value of a is:

[0085] a = a0 × 2 K-M-N ;

[0086] Where a0 takes the value of a positive integer.

[0087] For example, such as Figure 5 As shown, the chip's reference clock frequency is 24MHz, and the reference clock period is 1 / 24 microsecond (µm), approximately equal to 4.167 × 10⁻⁶.-5 milliseconds (ms); and K is 64, M is 43, and N is 16. mst_ref_clk represents a reference clock pulse of the master chip, slv_ref_clk represents a reference clock pulse of the slave chip; Mst_tick_iss represents a pulse sent on a clock dedicated physical pin (PAD) of the master chip, and Slv_tick_sam represents a pulse received on a clock dedicated physical pin of the slave chip.

[0088] When the MSB of the master chip is 0 and the LSB is 0, the MSB of the master chip and the slave chip is aligned through D2D initial alignment, the MSB represents the high 43 bits of the timer, the LSB represents the low 16 bits of the timer, and the sending time and the receiving time of the MSB value exist a delay, and the delay is uncertain. The MSB can be aligned when the MSB value is odd or even. Figure 5 Taking the MSB as an example when the MSB is even, when the MSB is 2 and the LSB is 0, the MSB of the master chip and the slave chip is aligned through D2D re-alignment, and so on, when the MSB is 2J and the LSB is 0, the MSB of the master chip and the slave chip is aligned through D2D, and J is a non-negative integer.

[0089] When the LSB[0:15] of the master chip is 0xFFFF, the LSB of the master chip and the slave chip is aligned through the PAD, and the sending time of the pulse on the PAD of the master chip and the receiving time of the pulse on the PAD of the slave chip exist a delay, and the delay is certain.

[0090] If the value of b is 1, the update period of the high 43 bits of the timer is about 87.38 ms; if the value of a is 32, the update period of the low 16 bits of the timer is 2.73 ms.

[0091] The clock synchronization method provided by the embodiment updates the high M bits and the low N bits of the timer with different periods respectively. Since the high M bits of the timer will cause the values of the master chip and the slave chip to be unable to be aligned only when the delay is large, the update period of the high M bits of the timer can be smaller than the update period of the low N bits of the timer. By reducing the number of times of updating the high M bits of the timer, the resource occupation of the clock synchronization on the chip can be reduced, such as the occupation of the high-speed general-purpose interconnection bus. In addition, compared with aligning the K bits of the timer each time, periodically updating the high M bits and the low N bits of the timer respectively can reduce the calculation resources occupied each time. In addition, by synchronizing the high bits and the low bits respectively, the accurate alignment of the time counter is ensured.

[0092] Figure 6 is a flowchart of the clock synchronization method provided by another exemplary embodiment of the application. As shown in Figure 6As shown, the clock synchronization method is applied to a master chip, which is interconnected with a slave chip as described in the above embodiment. The method comprises the following steps:

[0093] In step 301, a first synchronization signal is periodically sent to the slave chip through a high-speed general-purpose interconnection bus. The first synchronization signal is used to instruct updating high M bits of a timer of the slave chip, so as to make the high M bits of the timer of the slave chip equal to those of the master chip. M is a positive integer.

[0094] In step 302, a second synchronization signal is periodically sent to the slave chip through a clock-specific physical pin. The second synchronization signal is used to instruct updating low N bits of the timer of the slave chip, so as to make the low N bits of the timer of the slave chip equal to those of the master chip. The sum of M and N is less than or equal to K, K is the number of bits of the timer, and N and K are positive integers.

[0095] Optionally, the relationship between the sending period of the first synchronization signal and the sending period of the second synchronization signal is represented as:

[0096] T1=a×T2;

[0097] T2=b×2 N / f;

[0098] Wherein, T1 represents the sending period of the first synchronization signal, T2 represents the sending period of the second synchronization signal, a is a positive integer greater than 1, b is a positive integer, and f is the reference clock frequency of the chip.

[0099] The sending period of the first synchronization signal is the updating period of the high M bits of the timer, and the sending period of the second synchronization signal is the updating period of the low N bits of the timer.

[0100] Optionally, if the sum of M and N is less than the number of bits of the timer, the value of a is:

[0101] a=a0×2 K-M-N ;

[0102] Wherein, a0 is a positive integer.

[0103] For example, as shown in the figure, the master chip sends the first synchronization signal to the slave chip once every 87.38 ms, and sends the second synchronization signal to the slave chip once every 2.73 ms. Figure 5

[0104] ​The master chip also periodically reads the value of the counter (cnt) of the slave chip to perform alignment verification of the timers of the master chip and the slave chip; if the high-order counter of the slave chip is consistent with the count of the high-order counter of the master chip, and the low-order counter of the slave chip is consistent with the count of the low-order counter of the master chip, it is determined that the system time synchronization is completed. The high-order counter is a counter corresponding to the high M bits of the timer, and the low-order counter is a counter corresponding to the low (K-M) bits of the timer. The value of the low (K-M) bits of the timer in the process of updating the low N bits of the timer of the slave chip is determined according to the count of the low-order counter. As shown in FIG. 8, the master chip also periodically reads the value of the counter (cnt) of the slave chip through D2D to perform alignment verification of the timers of the master chip and the slave chip. The master chip periodically reads the state of the slave chip to ensure the reliability of the synchronization operation. Figure 5

[0105] In summary, the clock synchronization method provided in the embodiment, the master chip and the slave chip are connected through the high-speed general-purpose interconnection bus and a clock dedicated physical pin. In the clock synchronization process, the master chip periodically sends a first synchronization signal to the slave chip through the high-speed general-purpose interconnection bus, so that the slave chip updates the high M bits of the local timer according to the first synchronization signal, to synchronize the high M bits of the timers of the master chip and the slave chip. The master chip periodically sends a second synchronization signal to the slave chip through the clock dedicated physical pin, so that the slave chip updates the low N bits of the local timer according to the second synchronization signal, to synchronize the low N bits of the timers of the master chip and the slave chip. The clock synchronization is realized through the high-speed general-purpose interconnection bus and the clock dedicated physical pin, without occupying a dedicated low-speed interface such as I2C or SPI, and the requirement for the dedicated physical pin is reduced from a minimum of 4 to 1, greatly reducing the physical resources required for clock synchronization.

[0106] In addition, the clock synchronization method realizes full-automatic initial and periodic synchronization of the master chip and the slave chip through hardware, without the perception and intervention of software programs, avoids the uncertain delay caused by the perception and intervention of software programs, and avoids the occupation of computing resources caused by the perception and intervention of software programs, thereby improving the efficiency of clock synchronization.

[0107] ​This clock synchronization method also updates the high M bits and low N bits of the timer at different intervals. Since the high M bits of the timer only cause misalignment between the master and slave chips when there is a significant delay compared to the low N bits, the update period for the high M bits can be shorter than the update period for the low N bits. By reducing the number of high M bit updates, the resource consumption of clock synchronization on the chip can be reduced, such as reducing the occupation of the high-speed general-purpose interconnect bus. Furthermore, compared to aligning the K bits of the timer each time, periodically updating the high M bits and low N bits separately reduces the computational resources consumed during each update. In addition, synchronizing the high and low bits separately ensures accurate alignment of the time counter.

[0108] Figure 7 A schematic diagram of a clock synchronization device provided in an exemplary embodiment of this application is shown. Figure 7 As shown, this clock synchronization device is used in a slave chip, which is connected to the master chip via a high-speed universal interconnect bus and a dedicated clock physical pin. The device includes:

[0109] The first high-order synchronization module 401 is used to receive the first synchronization signal periodically sent by the master chip through the high-speed universal interconnect bus, and update the high M bits of the slave chip's timer according to the first synchronization signal so that the high M bits of the slave chip's timer are equal to those of the master chip's timer.

[0110] The first low-order synchronization module 402 is used to receive the second synchronization signal periodically sent by the master chip through the dedicated clock physical pin, and update the low N bits of the slave chip's timer according to the second synchronization signal so that the low N bits of the slave chip's timer are equal to those of the master chip's timer; wherein, the sum of M and N is less than or equal to K, K is the number of bits of the timer, and M, N and K are all positive integers.

[0111] In another possible implementation, the relationship between the transmission period of the first synchronization signal and the transmission period of the second synchronization signal is expressed as: T1 = a × T2; T2 = b × 2 N / f; where T1 represents the transmission period of the first synchronization signal, T2 represents the transmission period of the second synchronization signal, a is a positive integer greater than 1, b is a positive integer, and f is the reference clock frequency of the chip.

[0112] In another possible implementation, if the sum of M and N is less than the number of bits in the timer, then the value of a is: a = a0 × 2 K-M-N ; where a0 takes the value of a positive integer.

[0113] In another possible implementation, the first synchronization signal carries a value of high M bits of the master chip; the first high-bit synchronization module 401 is configured to determine a first reference value on K bits of the timer according to the value of the high M bits of the master chip, and acquire a first value of the timer of the slave chip in real time; calculate a difference between the first reference value and the first value to obtain a first difference; if the first difference is greater than a first threshold, incrementally assign the timer of the slave chip until the high M bits of the slave chip are equal to the value of the high M bits of the master chip; if the first difference is less than a second threshold, directly assign the high M bits of the timer of the slave chip to the value of the high M bits of the master chip; wherein the first threshold is a positive number and the second threshold is a negative number.

[0114] In another possible implementation, the first high-bit synchronization module 401 is configured to, if the first difference is greater than or equal to the second threshold and less than or equal to the first threshold, skip the update of the timer of the slave chip this time.

[0115] In another possible implementation, the first low-bit synchronization module 402 is configured to determine a second reference value on low (K-M) bits of the timer according to the second synchronization signal, and acquire a second value of the low (K-M) bits of the timer of the slave chip in real time; calculate a difference between the second reference value and the second value to obtain a second difference; if the second difference is greater than a third threshold, incrementally assign the timer of the slave chip until the low N bits of the timer of the slave chip are equal to the value of the low N bits of the master chip; if the second difference is less than a fourth threshold, assign the low N bits of the slave chip to zero; wherein the third threshold is a positive number and the fourth threshold is a negative number.

[0116] In another possible implementation, the first low-bit synchronization module 402 is configured to, if the second difference is greater than or equal to 0 and less than or equal to the third threshold, skip the update of the timer of the chip this time; if the second difference is greater than or equal to the fourth threshold and less than 0, control the timer of the slave chip to wait for S reference clock cycles, and the value of S is an absolute value of the second difference.

[0117] Figure 8 A schematic diagram of another clock synchronization device provided by an example embodiment of the present application is shown. As shown in the figure, the clock synchronization device is applied to a master chip, the master chip and a slave chip are connected through a high-speed general interconnection bus and a clock dedicated physical pin, and the device comprises: Figure 8

[0118] The second high-bit synchronization module 501 is configured to periodically send a first synchronization signal to the slave chip through the high-speed general interconnection bus, and the first synchronization signal is used to instruct to update high M bits of the timer of the slave chip so as to make the high M bits of the timer of the slave chip equal to the high M bits of the timer of the master chip.

[0119] ​The second low bit synchronization module 502 is configured to periodically send a second synchronization signal to the slave chip through a clock dedicated physical pin, and the second synchronization signal is used to indicate to update the low N bits of the timer of the slave chip, so that the low N bits of the timer of the slave chip are equal to the low N bits of the timer of the master chip; wherein the sum of M and N is less than or equal to K, K is the bit number of the timer, and M, N and K are all positive integers.

[0120] In another possible implementation, the relationship between the sending period of the first synchronization signal and the sending period of the second synchronization signal is represented as: T1=a×T2; T2=b×2 N ; wherein T1 represents the sending period of the first synchronization signal, T2 represents the sending period of the second synchronization signal, the value of a is a positive integer greater than 1, the value of b is a positive integer, and f is the reference clock frequency of the chip.

[0121] In another possible implementation, if the sum of M and N is less than the bit number of the timer, the value of a is: a=a0×2 K-M-N ; wherein the value of a0 is a positive integer.

[0122] It should be noted that the clock synchronization device in the embodiment is used to implement the corresponding clock synchronization method in the foregoing method embodiment, and has the beneficial effects of the corresponding method embodiment, which will not be described here.

[0123] Figure 9 is a schematic block diagram of an electronic device provided by the embodiment of the present application, and the embodiment of the present application does not limit the specific implementation of the electronic device. Now, a structure block diagram of the electronic device 600 which can be used as the electronic device of the present application will be described, which is an example of a hardware device that can be applied to various aspects of the present application. The components shown in the text, their connections and relationships, and their functions are only as examples, and are not intended to limit the implementation of the present application described and / or claimed herein.

[0124] As Figure 9As shown, the electronic device 600 includes a master chip 110 and a plurality of slave chips 120. The master chip 110 and the plurality of slave chips 120 can be integrated on the same substrate in a stacked, tiled, or plugged manner. For example, the master chip and the plurality of slave chips are placed side by side on the same lead frame or substrate; or the master chip and the plurality of slave chips are stacked on the same substrate. The electronic device 600 includes a plurality of functional units: a computing unit 601, a ROM 602, a RAM 603, an I / O interface 605, an input unit 606, an output unit 607, a storage unit 608, and a communication unit 609, at least one of which is integrated on each chip. The electronic device 600 includes a computing unit 601, which can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 602 or a computer program loaded from the storage unit 608 into a Random Access Memory (RAM) 603. Various programs and data required for the operation of the device 600 can also be stored in the RAM 603. The computing unit 601, the ROM 602, and the RAM 603 are connected to each other through a bus 604. An Input / Output (I / O) interface 605 is also connected to the bus 604.

[0125] A plurality of components in the electronic device 600 are connected to the I / O interface 605, including: an input unit 606, an output unit 607, a storage unit 608, and a communication unit 609. The input unit 606 can be any type of device capable of inputting information to the electronic device 600, and can receive inputted digital or character information, and generate key signal inputs related to user settings and / or function controls of the electronic device. The output unit 607 can be any type of device capable of presenting information, and can include, but is not limited to, a display, a speaker, a video / audio output terminal, a vibrator, and / or a printer. The storage unit 608 can include, but is not limited to, a magnetic disk, an optical disk. The communication unit 609 allows the electronic device 600 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks, and can include, but is not limited to, a modem, a network card, an infrared communication device, a wireless communication transceiver, and / or a chipset, such as a Bluetooth™ device, a WIreless Fidelity (WiFi) device, a Worldwide Interoperability for Microwave Access (WiMax) device, a cellular communication device, and / or the like.

[0126] The computing unit 601 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a Central Processing Unit (CPU), a Graphic Processing Unit (GPU), various special-purpose AI computing chips, various computing units running machine learning model algorithms, a Digital Signal Processing (DSP), and any appropriate processor, controller, microcontroller, etc. For example, in some embodiments, the clock synchronization method of the various embodiments described above can be implemented as a computer software program, which is tangibly embodied in a machine-readable medium, such as the storage unit 608. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 600 via the ROM 602 and / or the communication unit 609. In some embodiments, the computing unit 601 can be configured to perform the clock synchronization method by any other appropriate means, such as by means of firmware. For example, the computing unit on the master chip performs the master chip side steps of the clock synchronization method, and the computing unit on the slave chip performs the slave chip side steps of the clock synchronization method.

[0127] Program code to implement methods of the present application can be written in any combination of one or more programming languages. The program code can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, produces a means for implementing the functions / operations specified in the flowchart diagrams and / or block diagrams. The program code can be retrieved from the storage unit and / or the storage unit and executed by a processor or controller to cause the functions / operations of the flowchart diagrams and / or block diagrams to be implemented. The program code can be executed entirely on a machine, partly on a machine, partly on a machine as a stand-alone software package, partly on a machine and partly on a remote machine or entirely on a remote machine or server.

[0128] In the context of this application, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium would include a lined- up electrical connection, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM) or flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0129] As used in this application, the terms "machine-readable medium" and "computer- readable medium" refer to any computer program product, apparatus and / or device (e.g., magnetic discs, optical disks, memory, Programmable Logic Devices (PLDs)) used to provide machine instructions and / or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal that can be used to provide machine instructions and / or data to a programmable processor.

[0130] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a Cathode Ray Tube (CRT) or a Liquid Crystal Display (LCD) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0131] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0132] The computer system can include clients and servers. This description uses the terms "client" and "server" to describe the roles of these computers in the interactions

[0133] The present application also provides a computer-readable storage medium storing instructions for causing a machine to perform the clock synchronization method as described herein. Specifically, a system or apparatus equipped with a storage medium on which a software program code for realizing the functions of any one of the above-described embodiments is stored, and causing a computer (or CPU or MPU) of the system or apparatus to read and execute the program code stored in the storage medium can be provided.

[0134] In this case, the program code read from the storage medium can itself implement the functions of any one of the above-described embodiments, and thus the program code and the storage medium storing the program code constitute a part of the present application.

[0135] Storage medium embodiments for providing program code include floppy disks, hard disks, magneto-optical disks, CD-ROMs, CD-Rs, CD-RWs, DVDs, DVD-ROMs, DVD-RAMs, DVD-RWs, DVD+RWs, flash memories, and ROMs. Program code can also be downloaded from a network, e.g., the Internet, to a server computer and then to a user's computer over a communication network, e.g., a telephone line, a LAN, or a WAN.

[0136] The embodiments of the present application also provide a computer program product, comprising computer instructions, which instruct a computing device to perform any corresponding operation of the above-mentioned method embodiments.

[0137] It should be noted that, according to the needs of implementation, each component / step described in the embodiments of the present application can be split into more components / steps, or two or more components / steps or partial operations of the components / steps can be combined into new components / steps, to achieve the purpose of the embodiments of the present application.

[0138] The methods according to the embodiments of the present application described above can be implemented in hardware, firmware, or software, or be implemented as software or computer code that can be stored in a recording medium such as a CD-ROM, a RAM, a floppy disk, a hard disk, or an optical disk, or be implemented by computer code originally stored in a remote recording medium or a non-transitory machine-readable medium downloaded over a network and stored in a local recording medium, so that the methods described herein can be stored on a recording medium in such software processing using a general-purpose computer, a special-purpose processor, or programmable or special-purpose hardware such as an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA). It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component (for example, a RAM, a ROM, a flash memory, and the like) that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the methods described herein are implemented. Furthermore, when a general-purpose computer accesses the code for implementing the methods shown herein, the execution of the code will convert the general-purpose computer into a special-purpose computer for executing the methods shown herein.

[0139] Those skilled in the art can realize that the units and method steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware, or in a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of the present application.

[0140] The above embodiments are only used to illustrate but not limit the embodiments of the present application, and a person of ordinary skill in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application, therefore all equivalent technical solutions belong to the scope of the embodiments of the present application, and the patent protection scope of the embodiments of the present application should be defined by the claims.

Claims

1. A clock synchronization method, characterized in that, Applied to a slave chip, wherein the slave chip and the master chip are connected via a high-speed universal interconnect bus and a dedicated clock physical pin, the method includes: The system receives a first synchronization signal periodically sent by the master chip through the high-speed universal interconnect bus, and updates the high M bits of the slave chip's timer according to the first synchronization signal so that the high M bits of the slave chip's timer are equal to those of the master chip's timer. The system receives a second synchronization signal periodically sent by the master chip through the dedicated clock physical pin, and updates the lower N bits of the slave chip's timer according to the second synchronization signal, so that the lower N bits of the slave chip's timer are equal to those of the master chip's timer; wherein, the sum of M and N is less than or equal to K, K is the number of bits of the timer, and M, N and K are all positive integers; The relationship between the transmission period of the first synchronization signal and the transmission period of the second synchronization signal is represented as: T1=a×T2; T2=b×2 N T1 represents the transmission period of the first synchronization signal, T2 represents the transmission period of the second synchronization signal, the value of a is a positive integer greater than 1, the value of b is a positive integer, and f is the reference clock frequency of a chip.

2. The method according to claim 1, characterized in that, If the sum of M and N is less than the number of bits in the timer, then the value of a is: a=a0×2 K-M-N ; Where a0 takes the value of a positive integer.

3. The method according to claim 1, characterized in that, The first synchronization signal carries the value of the high M bits of the main chip; The step of updating the high M bits of the timer of the slave chip according to the first synchronization signal includes: The first reference value on the K bit of the timer is determined based on the value of the high M bit of the main chip, and the first value of the timer of the slave chip is obtained in real time; the difference between the first reference value and the first value is calculated to obtain the first difference. If the first difference is greater than the first threshold, the timer of the slave chip is incremented until the value of the high M bits of the slave chip is equal to that of the master chip; If the first difference is less than the second threshold, the high M bits of the timer of the slave chip are directly assigned the value of the high M bits of the master chip; Wherein, the first threshold is a positive number, and the second threshold is a negative number.

4. The method according to claim 3, characterized in that, The method further includes: If the first difference is greater than or equal to the second threshold and less than or equal to the first threshold, skip the update of the slave chip's timer.

5. The method according to claim 1, characterized in that, The step of updating the lower N bits of the slave chip's timer according to the second synchronization signal includes: The second reference value on the low (KM) bit of the timer is determined according to the second synchronization signal, and the second value of the low (KM) bit of the timer of the slave chip is obtained in real time; the difference between the second reference value and the second value is calculated to obtain the second difference; If the second difference is greater than the third threshold, the timer of the slave chip is incremented until the lower N bits of the timer of the slave chip and the timer of the master chip are equal. If the second difference is less than the fourth threshold, the lower N bits of the chip are assigned a value of zero; The third threshold is a positive number, and the fourth threshold is a negative number.

6. The method according to claim 5, characterized in that, The method further includes: If the second difference is greater than or equal to 0 and less than or equal to the third threshold, skip the update of the chip's timer. If the second difference is greater than or equal to the fourth threshold and less than 0, the timer of the slave chip is controlled to wait for S reference clock cycles, where S is the absolute value of the second difference.

7. A clock synchronization method, characterized in that, Applied to a master chip, wherein the master chip and slave chip are connected via a high-speed universal interconnect bus and a dedicated clock physical pin, the method includes: A first synchronization signal is periodically sent to the slave chip via the high-speed universal interconnect bus. The first synchronization signal is used to indicate the updating of the high M bits of the slave chip's timer so that the high M bits of the slave chip's timer are equal to those of the master chip's timer. A second synchronization signal is periodically sent to the slave chip via the dedicated clock physical pin. The second synchronization signal is used to indicate the updating of the lower N bits of the slave chip's timer so that the lower N bits of the slave chip's timer are equal to those of the master chip's timer. Wherein, the sum of M and N is less than or equal to K, K is the number of bits in the timer, and M, N and K are all positive integers. The relationship between the transmission period of the first synchronization signal and the transmission period of the second synchronization signal is expressed as: T1 = a × T2; T2 = b × 2 N / f; T1 represents the transmission period of the first synchronization signal, T2 represents the transmission period of the second synchronization signal, a is a positive integer greater than 1, b is a positive integer, and f is the reference clock frequency of the chip.

8. The method according to claim 7, characterized in that, If the sum of M and N is less than the number of bits in the timer, then the value of a is: a=a0×2 K-M-N ; Where a0 takes the value of a positive integer.

9. A chip, characterized in that, The chip is used to perform the clock synchronization method as described in any one of claims 1-6 or 7-8.

10. A multi-chip interconnect system, characterized in that, The multi-chip interconnect system includes a master chip and multiple slave chips, and the master chip and the slave chips are interconnected through a high-speed universal interconnect bus and a dedicated clock physical pin. The slave chip is used to perform the clock synchronization method as described in any one of claims 1-6; The main chip is used to execute the clock synchronization method as described in any one of claims 7-8.

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