Shared cache component and implementation method thereof, electronic equipment and storage medium

Abstract

The invention discloses a shared cache component and an implementation method thereof, electronic equipment and a storage medium, relates to the technical field of servers, and realizes effective management of cache data of a plurality of controllers by setting an exchanger chip, a conversion chip and a control chip. The component can accurately store the cache data of each controller in a specified area of the cache memory, and the control chip can automatically migrate the cache data of the affected controller to the nonvolatile memory under the emergency condition of power failure of the controller. Therefore, the data loss risk caused by the power supply fault is obviously reduced; and a standby power supply of each controller is omitted, so that the space occupied by equipment is reduced, and the overall cost is greatly reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of servers, and in particular to a shared cache component and an implementation method thereof, an electronic device, and a storage medium. BACKGROUND

[0002] In related technologies, a storage system usually has multiple networking schemes such as two-control and four-control, and can implement system networking topology through networking such as one-frame two-control, one-frame four-control, and two-frame four-control. Taking one-frame two-control as an example, one-frame two-control refers to inserting two controllers in one chassis and implementing multi-control interconnection using an NTB (Non-Transparent Bridging) scheme or an ROCE (RDMA over Converged Ethernet) interconnection scheme. However, the NTB scheme or the ROCE interconnection scheme has poor latency and performance for storage system interconnection, which affects the overall machine performance. In addition, when the controller power supply fails, backup cache data is needed to prevent loss, and a BBU (Battery Backup Unit) battery needs to be provided for each controller to be ready for power, which increases space occupation and cost and has low cost performance. SUMMARY

[0003] The present application provides a shared cache component and an implementation method thereof, an electronic device, and a storage medium to at least solve the problems of poor latency and performance of a storage system in related technologies and the problem of increased space occupation and cost of a controller backup power supply.

[0004] The present application provides a shared cache component, which includes a switch chip, a conversion chip, a control chip, a cache memory, and a non-volatile memory. The switch chip is connected to a plurality of controllers respectively. The conversion chip is connected to the switch chip and the control chip respectively and is configured to implement conversion between a computing high-speed interconnection technology protocol and a protocol corresponding to the cache memory. The control chip is connected to the cache memory and the non-volatile memory respectively. The control chip is configured to divide the cache memory into a plurality of first sub-intervals according to the number of the plurality of controllers, and the first sub-intervals correspond to the controllers one by one. The first sub-intervals are configured to store cache data of the corresponding controllers. In the case of a power supply failure of the controller, the cache data of the controller is moved to the non-volatile memory.

[0005] The application further provides an implementation method of the shared cache component, and the method comprises: dividing a cache memory into a plurality of first subintervals according to the number of the plurality of controllers, the first subintervals corresponding to the controllers one by one, and the first subintervals being used for storing cache data of the corresponding controllers; and in the case of power failure of a controller, moving the cache data of the controller to a non-volatile memory.

[0006] The application further provides an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the implementation method of the shared cache component.

[0007] The application further provides a computer readable storage medium, and the computer readable storage medium stores a computer program, wherein the computer program is executed by a processor to implement the steps of the implementation method of the shared cache component.

[0008] The application further provides a computer program product, comprising a computer program, wherein the computer program is executed by a processor to implement the steps of the implementation method of the shared cache component.

[0009] The shared cache component of the application achieves effective management of cache data of a plurality of controllers by setting an exchanger chip, a conversion chip and a control chip, the component can accurately store cache data of each controller in a specified area of a cache memory, and in the case of emergency of power failure of a controller, the control chip can automatically migrate cache data of the affected controller to a non-volatile memory, thereby significantly reducing the risk of data loss caused by power failure; and the backup power supply of each controller is saved, thereby reducing the space occupied by the device and greatly reducing the overall cost. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0011] Figure 1 Communication topology diagram between integrated circuits of a storage system according to some embodiments of the application; Figure 2 Mesh topology structure diagram of a ROCE network according to some embodiments of the application; Figure 3 Schematic diagram of a shared cache component according to some embodiments of the application; Figure 4 Schematic diagram of a shared cache component according to some other embodiments of the application; Figure 5 Flow chart for implementation method of shared cache component according to some embodiments of the present application; Figure 6 Block schematic diagram of electronic device according to some embodiments of the present application. DETAILED DESCRIPTION

[0012] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, any other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0013] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are applicable to distinguish similar objects, and are not used to describe a specific order or sequence.

[0014] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0015] In the related art, when a storage device is designed in hardware, a two-control or four-control scheme design can be supported in a chassis, but to realize data sharing between multiple controllers, the NTB scheme or the ROCE scheme can be used to realize the data sharing, and at the same time, to solve the problem that after the power supply of the controller fails, the cache data of the controller needs to be written to the data disk to realize that the data is not lost after the system is powered off.

[0016] Next, a four-control sharing scheme design in a chassis is described using the ROCE scheme. Referring to Figure 1 , controller A can use three ROCE chips (memory access chips) to be connected to other three controllers, such as controller B, controller C and controller D, to form a mesh topology. Referring to Figure 2The mesh ROCE structure can also be implemented by using CX6 chips (a kind of network card chip), and a four-control sharing scheme is achieved, that is, each controller uses three CX6 chips (for example, CX6_0, CX6_1 and CX6_2) to be connected to other controllers, to realize the network interconnection of the controller and the other three controllers. For example, the controller A uses the CX6_0 chip, the CX6_1 chip and the CX6_2 chip to be connected to the controller B, the controller C and the controller D respectively, specifically, the CX6_0 chip of the controller A is connected to the CX6_0 chip of the controller D, the CX6_1 chip of the controller A is connected to the CX6_1 chip of the controller C, and the CX6_2 chip of the controller A is connected to the CX6_2 chip of the controller B. As can be seen, one or more ROCE chips or CX6 chips need to be placed on each controller, which has an impact on the PCB layout and wiring of the board card, and the cost.

[0017] Further, the ROCE delay is tested by using network performance measurement tools such as ib_send_lat, ib_read_lat and ib_write_lat, and the delay time is different when different data packet sizes are used. For example, when the data packet size is 8k, the maximum delay time can reach 5us, when the data packet size is 32k, the maximum delay time can reach 8us, and when the data packet size is 36k, the maximum delay time can reach 10us. The longer the delay time is, the greater the impact on the performance. In view of the above, the ROCE networking scheme is relatively complex, and the delay time reaches 10us, which has a greater impact on the performance.

[0018] In addition, after the power supply of one of the controllers fails, the cache data in the controller needs to be backed up, and the data can be restored next time the system starts to prevent data loss. Therefore, in the design of the storage system, each controller has a corresponding BBU battery, which can provide backup power through the BBU after the AC (Alternating Current) power supply of the controller fails, to ensure that the cache data can be written to the system disk when the BBU provides backup power. However, each controller needs to have a corresponding BBU battery, which not only occupies space but also increases the cost, and the use and cost performance are low.

[0019] Based on this, the application provides a shared cache assembly, which realizes effective management of cache data of multiple controllers by setting a switch chip, a conversion chip and a control chip. The assembly can accurately store the cache data of each controller in a specified area of the cache memory, and in the case of a power failure of the controller, the control chip can automatically migrate the cache data of the affected controller to the non-volatile memory.

[0020] In some embodiments, reference is made to Figure 3The shared cache assembly 1 comprises an interchanger chip 11, a conversion chip 12, a control chip 13, a cache memory 14 and a non-volatile memory 15. The interchanger chip 11 is connected with a plurality of controllers 2 respectively. The conversion chip 12 is connected with the interchanger chip 11 and the control chip 13 respectively, and is configured to realize conversion between a protocol supported by a compute express link (CXL) 3.x technology and a protocol corresponding to the cache memory 14. The control chip 13 is connected with the cache memory 14 and the non-volatile memory 15 respectively. The control chip 13 is configured to divide the cache memory 14 into a plurality of first sub-intervals (not shown in the figure) according to a number of the plurality of controllers 2, so that each of the first sub-intervals corresponds to one of the controllers 2. The first sub-interval is configured to store cache data of the corresponding controller 2, and to move the cache data of the corresponding controller 2 to the non-volatile memory 15 in case of power failure of the controller 2.

[0021] In the embodiments of the present application, four controllers, for example, a controller A, a controller B, a controller C and a controller D are taken as an example for illustration, but this is not a limitation to the present application.

[0022] Specifically, the interchanger chip 11 can be an interchanger chip supporting CXL 3.x. The interchanger chip 11 supports a multihost function, that is, the interchanger chip 11 can be connected with a plurality of controllers 2. That is, the interchanger chip 11 is connected with the controller A, the controller B, the controller C and the controller D respectively, so as to realize simultaneous reading and writing of cache data in the memory by the controller A, the controller B, the controller C and the controller D.

[0023] The conversion chip 12 can be a DDR controller chip supporting CXL 3.x. The conversion chip 12 is connected with the interchanger chip 11 and the control chip 13 respectively, and serves as a bridge between the interchanger chip 11 and the control chip 13. The conversion chip 12 is configured to realize conversion between a protocol supported by a compute express link (CXL) 3.x technology and a protocol corresponding to the cache memory 14, that is, the conversion chip 12 realizes interaction and data conversion of the CXL protocol between the interchanger chip 11 and the conversion chip 12, and realizes connection of a DDR interface between the conversion chip 12 and the control chip 13.

[0024] The control chip 13 can be an FPGA (Field Programmable Gate Array) chip. The control chip 13 is connected with the conversion chip 12 through a DDR interface, and is connected with the cache memory 14 and the non-volatile memory 15 to realize a data saving function. Specifically, referring to Figure 4 , the control chip 13 needs to realize interactive data communication between a cache memory interface (not shown) and a non-volatile memory interface (not shown) inside the control chip 13.

[0025] The cache memory 14 connected below the control chip 13 is shared by the plurality of controllers 2. Each controller 2 has its own storage space, that is, the control chip 13 can divide the cache memory 14 into a plurality of first subintervals according to the number of the plurality of controllers 2, the first subintervals correspond to the controllers 2 one by one, and the first subintervals are used to store cache data of the corresponding controllers 2. For example, assuming that there are four controllers 2 including a controller A, a controller B, a controller C and a controller D, the control chip 13 can divide the cache memory 14 into four first subintervals, for example, a first subinterval A, a first subinterval B, a first subinterval C and a first subinterval D. The controller A corresponds to the first subinterval A, the controller B corresponds to the first subinterval B, the controller C corresponds to the first subinterval C, and the controller D corresponds to the first subinterval D. The first subinterval A is used to store cache data of the controller A, the first subinterval B is used to store cache data of the controller B, the first subinterval C is used to store cache data of the controller C, and the first subinterval D is used to store cache data of the controller D.

[0026] The controllers 2 are powered by corresponding power supplies. In the case that the power supplies are normally powered, the controllers 2 write data into the corresponding first subintervals through the switcher chip 11 and the conversion chip 12. For example, the controller A can write data into the first subinterval A through the switcher chip 11 and the conversion chip 12 when normally working, the controller B can write data into the first subinterval B through the switcher chip 11 and the conversion chip 12 when normally working, the controller C can write data into the first subinterval C through the switcher chip 11 and the conversion chip 12 when normally working, and the controller D can write data into the first subinterval D through the switcher chip 11 and the conversion chip 12 when normally working.

[0027] In the case of a power failure of the power supply corresponding to the controller 2, the control chip 13 can identify the power failure of the controller 2 through the CXL bus. The CXL bus has a built-in device state management mechanism. When the controller 2 is in normal operation, the controller 2 actively feeds back a “normal working” state through a protocol. If the controller 2 is powered off, it cannot respond to bus transactions, such as read / write request timeout. The power management state register will mark a “power failure” flag, thereby determining that the power supply corresponding to the controller 2 has failed. The control chip 13 can move the cache data stored in the cache memory 14 of the controller 2 that has failed to the non-volatile memory 15. For example, assuming that the power supply corresponding to the controller A has failed, the control chip 13 can move the cache data in the first sub-interval A in the cache memory 14 to the non-volatile memory 15 to avoid loss of cache data. In the case of a power failure of the power supplies corresponding to the controller B, the controller C, and the controller D, the cache data is moved to the non-volatile memory 15 in the above-described manner, which will not be described herein.

[0028] In the test using the network performance measurement tools such as ib_send_lat, ib_read_lat, and ib_write_lat, the delay time of the cache data from the controller to the cache memory 14 through the switch chip 11 is 400 ns to 500 ns for data packets of different sizes, which is greatly improved compared with the original ROCE scheme of 5 us to 10 us.

[0029] The shared cache assembly of the present application can effectively manage the cache data of multiple controllers by arranging the switch chip, the conversion chip, and the control chip. The assembly can accurately store the cache data of each controller in the specified area of the cache memory. In the case of a power failure of a controller, the control chip can automatically migrate the cache data of the affected controller to the non-volatile memory, thereby significantly reducing the risk of data loss caused by a power failure. The shared cache assembly also eliminates the need for a backup power supply for each controller, thereby reducing the space occupied by the device and significantly reducing the overall cost, and exhibiting significant advantages in improving system reliability and economic benefits. Moreover, the shared cache assembly significantly reduces the delay and improves the system performance.

[0030] In some embodiments, the control chip 13 is further configured to, in the case of a power failure of the controller 2, read the cache data stored in the non-volatile memory 15 back to the first sub-interval corresponding to the controller 2.

[0031] Specifically, in the case of a power failure of the controller 2, the control chip 13 can read the cache data temporarily stored in the non-volatile memory 15 of the controller 2 that has failed back to the sub-interval corresponding to the controller 2 in the cache memory 14.

[0032] For example, assuming that the power supply of controller A fails, the control chip 13 can move the cache data in the first sub-interval A of the cache memory 14 to the non-volatile memory 15. When controller A is started again, the control chip 13 can read the cache data temporarily stored in the non-volatile memory 15 back to the first sub-interval A of the cache memory 14.

[0033] The application realizes an automatic cache data backup and recovery mechanism through the control chip, significantly improves the data security, system reliability and operation simplicity without increasing the additional hardware cost and space occupation, and optimizes the system performance and cost-effectiveness.

[0034] In some embodiments, the control chip 13 comprises a cache memory interface (not shown) and a non-volatile memory interface (not shown), the control chip 13 is connected with the cache memory 14 based on the cache memory interface and is connected with the non-volatile memory 15 based on the non-volatile memory interface, wherein the control chip 13 is further configured to, in the case of power failure of a controller, move the cache data of the first sub-interval corresponding to the failed controller to the non-volatile memory 15 through the cache memory interface and the non-volatile memory interface; and in the case of starting of the failed controller again, move the cache data of the failed controller stored in the non-volatile memory 15 to the first sub-interval corresponding to the failed controller through the non-volatile memory interface and the cache memory interface.

[0035] Specifically, the control chip 13 comprises a cache memory interface and a non-volatile memory interface, and the control chip 13 can realize the interactive data communication between the cache memory interface and the non-volatile memory interface. That is, the control chip 13 can move the cache data in the first sub-interval of the cache memory 14 to the non-volatile memory 15 through the cache memory interface and the non-volatile memory interface, and can also move the cache data in the non-volatile memory 15 back to the first sub-interval of the cache memory 14 through the cache memory interface and the non-volatile memory interface.

[0036] For example, assuming that the power supply of controller A fails, the control chip 13 can move the cache data in the first sub-interval A of the cache memory 14 to the non-volatile memory 15 through the cache memory interface and the non-volatile memory interface, to avoid the loss of cache data. When controller A is started again, the control chip 13 can move the cache data temporarily stored in the non-volatile memory 15 back to the first sub-interval A of the cache memory 14.

[0037] Therefore, the control chip can realize data interaction communication between the first non-volatile memory interface and the non-volatile memory interface, further enhance the flexibility and efficiency of data transmission, and significantly improve the data processing capability and system recovery speed in the case of power failure.

[0038] In some embodiments, the control chip 13 is further configured to, in the case that multiple controllers 2 have power failure, divide the non-volatile memory 15 into multiple second sub-intervals, the second sub-intervals corresponding to the first sub-intervals one by one; and in the case that the controller 2 with power failure is started again, read the cache data stored in the second sub-intervals back to the corresponding first sub-intervals.

[0039] Specifically, in the case that multiple controllers 2 have power failure, the control chip 13 will move the cache data in the sub-intervals corresponding to the multiple controllers 2 to the non-volatile memory 15, which will cause the cache data in the non-volatile memory 15 to be confused. Therefore, in the case that multiple controllers 2 have power failure, the control chip 13 needs to divide the non-volatile memory 15 into multiple second sub-intervals, the second sub-intervals corresponding to the first sub-intervals one by one, that is, the control chip 13 moves the cache data in the first sub-intervals to the corresponding second sub-intervals, thereby avoiding the confusion of the cache data in the non-volatile memory 15 to some extent.

[0040] For example, the non-volatile memory 15 can be divided according to the number of controllers 2 with power failure, so that in the case that the controller A and the controller B have power failure at the same time, the control chip 13 divides the non-volatile memory 15 into the second sub-interval A and the second sub-interval B, and the second sub-interval A corresponds to the first sub-interval A, and the second sub-interval B corresponds to the first sub-interval B; or the non-volatile memory 15 can be divided according to the size of the first sub-interval in the cache memory 14, so that the control chip 13 divides the non-volatile memory 15 into the second sub-interval A, the second sub-interval B, the second sub-interval C and the second sub-interval D, and the second sub-interval A corresponds to the first sub-interval A, the second sub-interval B corresponds to the first sub-interval B, the second sub-interval C corresponds to the first sub-interval C, and the second sub-interval D corresponds to the first sub-interval D.

[0041] Then, the control chip 13 moves the cache data in the first sub-interval A to the second sub-interval A, and moves the cache data in the first sub-interval B to the second sub-interval B. Further, in the case that the controller 2 with power failure is started again, the control chip 13 reads the cache data in the second sub-interval A back to the first sub-interval A, and reads the cache data in the second sub-interval B back to the first sub-interval B.

[0042] It should be noted that the order of moving and the order of reading back are not specifically limited here.

[0043] In this way, by dividing the non-volatile memory into intervals by the control chip, it is ensured that when power failures occur in multiple controllers at the same time, the cache data of each controller can be accurately stored and read back, thereby avoiding data confusion and loss to some extent, ensuring data consistency with the data after the last power-off shutdown, and improving the accuracy of data management and the reliability of the system.

[0044] In some embodiments, the control chip 13 is further configured to store the cache data of each controller 2 to the corresponding first sub-interval through the conversion chip 12 and the control chip 13; and in the case of data interaction among the multiple controllers 2, the control chip 13 is configured to control each controller 2 to read the cache data of other controllers 2.

[0045] Specifically, the controller 2 writes data into the corresponding first sub-interval through the switch chip 11 and the conversion chip 12. For example, the controller A can write data into the first sub-interval A through the switch chip 11 and the conversion chip 12, and only the controller A can read and write the memory data in the first sub-interval A, and other controllers, such as the controller B, cannot write cache data into the first sub-interval A, but the controller B can read the cache data of the first sub-interval A. The storage data in each first sub-interval in the cache memory 14 can be ensured not to be mistakenly written or deleted, and data interaction among multiple controllers can be achieved.

[0046] The present application can complete data interaction among multiple controllers without the need to equip each controller with a separate ROCE chip or CX6 chip. In this way, not only is the PCB (Printed Circuit Board) wiring work of the board card simplified, the design complexity is reduced, but also the hardware cost is significantly reduced, and the overall system cost performance and market competitiveness are improved.

[0047] In some embodiments, the control chip 13 is further configured to determine a master controller and a slave controller based on the multiple controllers 2; and in the case of a failure of the slave controller, the control chip 13 is configured to control the master controller to take over the task of the failed slave controller, and store the cache data generated by executing the task of the failed slave controller to the first sub-interval corresponding to the failed slave controller.

[0048] Specifically, a master controller in the plurality of controllers 2 can be assigned by the cache system, for example, controller A can be assigned as the master controller, and controller B, controller C and controller D are corresponding slave controllers. When a slave controller fails, the control chip 13 controls the master controller to take over the task of the failed slave controller, so that the master controller can perform write operation on the corresponding first sub-interval of the failed slave controller, that is, store the cache data generated by executing the task of the failed slave controller into the corresponding first sub-interval of the failed slave controller.

[0049] For example, when controller B fails, the control chip 13 can control controller A to take over the task of controller B, and controller A stores the cache data generated by executing the task of controller B into the first sub-interval B; when controller B and controller C fail, the control chip 13 can control controller A to take over the task of controller B and controller C, and controller A stores the cache data generated by executing the task of controller B and controller C into the first sub-interval B and the first sub-interval C respectively.

[0050] The application automatically takes over the task of the failed slave controller by the master controller, not only enhances the fault tolerance and task continuity of the system, ensures the uninterrupted execution of the key task, but also properly stores the cache data generated by the task of the failed controller in the corresponding first sub-interval, to a certain extent, avoids data confusion and loss, and enhances data security.

[0051] In some embodiments, the control chip 13 is further configured to, in the case that the master controller fails, determine one of the plurality of slave controllers as a new master controller, and control the new master controller to take over the task of the master controller and store the cache data generated by executing the task of the master controller into the corresponding first sub-interval of the master controller.

[0052] Specifically, the master controller can also fail, in which case, a new master controller needs to be assigned among the plurality of slave controllers, for example, the next adjacent slave controller of the original master controller is determined as the new master controller, if the next adjacent slave controller also fails, then the next next slave controller is determined as the new master controller, and so on. For example, assuming that the original master controller (controller A) fails, then the next adjacent controller of controller A, that is, controller B, is determined as the new master controller; if controller B also fails, then the next next adjacent controller of controller A, that is, controller C, is determined as the new master controller.

[0053] When the main controller fails, the control chip 13 controls the new main controller to take over the task of the failed main controller, so that the new main controller can perform a write operation on the first sub-interval corresponding to the failed main controller, that is, store the cache data generated by executing the task of the failed main controller into the first sub-interval corresponding to the failed main controller.

[0054] For example, when the main controller (controller A) fails, controller B is determined as the new main controller, and the control chip 13 can control controller B to take over the task of controller A, and controller B stores the cache data generated when executing the task of controller A into the first sub-interval A.

[0055] The application selects a new main controller from the slave controllers when the main controller fails, and realizes seamless takeover of the task, thereby ensuring continuous operation of the system and integrity of the data, which improves the fault tolerance of the system. In addition, the automatic master-slave controller switching mechanism simplifies the fault recovery process, reduces manual intervention, and reduces operation and maintenance costs. Furthermore, the new main controller can accurately store the cache data generated when executing the task of the original main controller into the corresponding first sub-interval, which to some extent avoids data confusion and loss, and enhances data security.

[0056] In some embodiments, the control chip 13 is configured to divide the cache memory 14 into intervals according to the number of controllers 2, including: determining the cache capacity of each controller 2 based on the number of tasks of the controller 2; and dividing the cache memory 14 into intervals based on the cache capacity of each controller 2.

[0057] Specifically, when dividing the cache memory 14 into intervals according to the number of controllers 2, the control chip 13 can determine the cache capacity of each controller 2 by looking up a two-dimensional relationship mapping table between the number of tasks of the controller 2 and the cache capacity, that is, determining the cache requirement of the controller 2, and dividing the cache memory 14 into intervals according to the cache capacity of the controller 2, wherein the two-dimensional relationship mapping table includes a plurality of task quantities and a cache capacity corresponding to each task quantity.

[0058] For example, assuming that there are four controllers, controller A, controller B, controller C and controller D, the control chip 13 can divide the cache memory 14 into four first sub-intervals. The control chip 13 looks up the above-mentioned two-dimensional relationship mapping table according to the number of tasks of controller A, controller B, controller C and controller D, respectively, to determine the cache capacity of controller A, controller B, controller C and controller D. Then, the control chip 13 divides the cache memory 14 into intervals according to the cache capacity of controller A, controller B, controller C and controller D, to form first sub-interval A, first sub-interval B, first sub-interval C and first sub-interval D.

[0059] It should be noted that the capacity of the cache memory 14 is limited, in order to avoid the cache capacity and value of the controller A, the controller B, the controller C and the controller D exceeding the capacity of the cache memory 14, the cache capacity ratio of the controller A, the controller B, the controller C and the controller D can be determined, and the cache memory 14 is divided into intervals according to the ratio.

[0060] The application optimizes the allocation and management of storage resources by controlling the chip to accurately divide the cache memory according to the number of tasks and cache requirements of the controller, which can ensure that the controller can obtain appropriate cache capacity to a certain extent to meet its specific task requirements, and improve the use efficiency and response speed of the memory.

[0061] In some embodiments, the control chip 13 is configured to divide the cache memory 14 into intervals according to the number of the plurality of controllers 2, including: dividing the cache memory 14 into a plurality of first subintervals of the same storage space according to the number of the plurality of controllers 2.

[0062] Specifically, when the control chip 13 divides the cache memory 14 into intervals according to the number of the plurality of controllers 2, the control chip 13 can also divide the cache memory 14 into intervals according to the number of the plurality of controllers 2.

[0063] For example, assuming that there are four controllers including the controller A, the controller B, the controller C and the controller D, the control chip 13 can divide the cache memory 14 into four first subintervals of the same storage space.

[0064] The application divides the cache memory into intervals by the control chip, and allocates the same size of storage space for the controller, so as to realize the fair allocation and efficient management of storage resources.

[0065] In some embodiments, the switch chip 11 and the conversion chip 12 support the computing high-speed interconnection technology, the control chip 13 includes a field programmable gate array chip, the cache memory 14 can be a DDR cache memory, and the nonvolatile memory 15 can be a nand flash nonvolatile memory.

[0066] For example, the switch chip 11 can be a switch chip 11 supporting CXL3.x, the conversion chip 12 can be a DDR Controller chip supporting CXL3.x, that is, the switch chip 11 and the conversion chip 12 support the computing high-speed interconnection technology, and the control chip 13 can be a FPGA chip.

[0067] In some embodiments, with reference to Figure 3The shared cache assembly 1 comprises an interchanger chip 11, a conversion chip 12, a control chip 13, a cache memory 14 and a non-volatile memory 15, wherein the interchanger chip 11 is connected with the plurality of controllers 2 respectively, the conversion chip 12 is connected with the interchanger chip 11 and the control chip 13 respectively, and is configured to realize conversion between a protocol supported by a computing high-speed interconnection technology and a protocol corresponding to the cache memory 14, and the control chip 13 is connected with the cache memory 14 and the non-volatile memory 15 respectively.

[0068] Figure 5 A flowchart of an implementation method of the shared cache assembly according to some embodiments of the present application is shown in FIG. 10. Referring to FIG. 10, Figure 5 the implementation method of the shared cache assembly according to some embodiments of the present application can comprise the following steps: S110, the cache memory 14 is divided into a plurality of first sub-intervals according to the number of the plurality of controllers 2, and each first sub-interval corresponds to one controller 2, and each first sub-interval is configured to store cache data of the corresponding controller 2.

[0069] Specifically, the cache memory 14 connected below the control chip 13 is shared by the plurality of controllers 2, and each controller 2 has its own storage space, i.e., the control chip 13 is configured to divide the cache memory 14 into a plurality of first sub-intervals according to the number of the plurality of controllers 2, each first sub-interval corresponds to one controller 2, and each first sub-interval is configured to store cache data of the corresponding controller 2. For example, assuming that there are four controllers 2, i.e., controller A, controller B, controller C and controller D, the control chip 13 can divide the cache memory 14 into four first sub-intervals, e.g., first sub-interval A, first sub-interval B, first sub-interval C and first sub-interval D, wherein the controller A corresponds to the first sub-interval A, the controller B corresponds to the first sub-interval B, the controller C corresponds to the first sub-interval C, and the controller D corresponds to the first sub-interval D, and the first sub-interval A is configured to store cache data of the controller A, the first sub-interval B is configured to store cache data of the controller B, the first sub-interval C is configured to store cache data of the controller C, and the first sub-interval D is configured to store cache data of the controller D.

[0070] For example, assuming that there are four controllers, controller A, controller B, controller C and controller D, the control chip 13 can divide the cache memory 14 into four first sub-intervals, and the control chip 13 can look up the above-mentioned two-dimensional relationship mapping table according to the number of tasks of the controller A, the controller B, the controller C and the controller D respectively, to determine the cache capacity of the controller A, the controller B, the controller C and the controller D, and then the control chip 13 can divide the cache memory 14 according to the cache capacity of the controller A, the controller B, the controller C and the controller D, to form the first sub-interval A, the first sub-interval B, the first sub-interval C and the first sub-interval D. It should be noted that the capacity of the cache memory 14 is limited, in order to avoid the cache capacity of the controller A, the controller B, the controller C and the controller D exceeding the capacity of the cache memory 14, the control chip 13 can determine the ratio of the cache capacity of the controller A, the controller B, the controller C and the controller D, and divide the cache memory 14 according to the ratio.

[0071] The cache memory 14 can also be divided according to the number of the plurality of controllers 2 to obtain a plurality of first sub-intervals of the same storage space. For example, assuming that there are four controllers, controller A, controller B, controller C and controller D, the control chip 13 can divide the cache memory 14 into four first sub-intervals of the same storage space.

[0072] S120, in the case of a power failure of the controller 2, the cache data corresponding to the controller 2 is moved to the non-volatile memory 15.

[0073] Specifically, the controller 2 has a corresponding power supply for power supply, in the case of normal power supply, the controller 2 writes data into the corresponding first sub-interval through the switch chip 11 and the conversion chip 12. For example, the controller A can write data into the first sub-interval A through the switch chip 11 and the conversion chip 12 when working normally, the controller B can write data into the first sub-interval B through the switch chip 11 and the conversion chip 12 when working normally, the controller C can write data into the first sub-interval C through the switch chip 11 and the conversion chip 12 when working normally, and the controller D can write data into the first sub-interval D through the switch chip 11 and the conversion chip 12 when working normally.

[0074] When the power supply corresponding to the controller 2 fails, the control chip 13 can move the cache data stored in the cache memory 14 of the failed controller 2 to the non-volatile memory 15 based on the cache memory interface and the non-volatile memory interface. For example, assuming that the power supply corresponding to the controller A fails, the control chip 13 can transmit the cache data in the first sub-interval A in the cache memory 14 to the non-volatile memory interface through the cache memory interface, and then move the cache data in the first sub-interval A to the non-volatile memory 15, so as to avoid the loss of cache data. When the power supply corresponding to the controller B, the controller C and the controller D fails, the cache data is also moved to the non-volatile memory 15 in the above-mentioned manner, which will not be described here.

[0075] In the case of emergency power failure of the controller, the application can automatically migrate the cache data of the affected controller to the non-volatile memory, thereby significantly reducing the risk of data loss caused by power failure. In addition, when using network performance measurement tools such as ib_send_lat, ib_read_lat and ib_write_lat for testing, the delay time of the cache data from the controller through the switch chip to the cache memory is 400ns-500ns for different data packet sizes, which is greatly improved compared with the original ROCE scheme of 5us-10us, significantly reducing the delay and improving the system performance.

[0076] In some embodiments, the above method further comprises: in the case that the controller 2 with power failure starts again, reading the cache data stored in the non-volatile memory 15 back to the sub-interval corresponding to the controller 2.

[0077] Specifically, when the controller 2 with power failure starts again, the control chip 13 can also read the cache data temporarily stored in the non-volatile memory 15 of the controller 2 with power failure back to the sub-interval corresponding to the controller 2 in the cache memory 14 based on the cache memory interface and the non-volatile memory interface.

[0078] For example, assuming that the power supply of controller A fails, the control chip 13 can transmit the cache data in the first sub-interval A in the cache memory 14 to the non-volatile memory interface through the cache memory interface, and then move the cache data in the first sub-interval A to the non-volatile memory 15. When controller A is started again, the control chip 13 can transmit the cache data temporarily stored in the non-volatile memory 15 to the cache memory interface through the non-volatile memory interface, and then read the cache data temporarily stored in the non-volatile memory 15 back to the first sub-interval A in the cache memory 14.

[0079] It should be noted that when the power supply of multiple controllers 2 fails, the control chip 13 will move the cache data in the sub-intervals corresponding to the multiple controllers 2 to the non-volatile memory 15, which will cause the cache data in the non-volatile memory 15 to be confused. Therefore, when the power supply of multiple controllers 2 fails, the control chip 13 needs to divide the non-volatile memory 15 into multiple second sub-intervals, and the second sub-intervals correspond one-to-one to the first sub-intervals, that is, the control chip 13 moves the cache data in the first sub-intervals to the corresponding second sub-intervals, thereby avoiding the confusion of the cache data in the non-volatile memory 15 to some extent. For example, assuming that the power supply of controller A and controller B fails at the same time, the control chip 13 divides the non-volatile memory 15 into multiple second sub-intervals. For example, the non-volatile memory 15 can be divided according to the number of power supply failures, so that when the power supply of controller A and controller B fails at the same time, the control chip 13 divides the non-volatile memory 15 into second sub-interval A and second sub-interval B evenly, and second sub-interval A corresponds to first sub-interval A, and second sub-interval B corresponds to first sub-interval B. For another example, the non-volatile memory 15 can be divided according to the size of the first sub-intervals in the cache memory 14, so that the control chip 13 divides the non-volatile memory 15 into second sub-interval A, second sub-interval B, second sub-interval C, and second sub-interval D, and second sub-interval A corresponds to first sub-interval A, second sub-interval B corresponds to first sub-interval B, second sub-interval C corresponds to first sub-interval C, and second sub-interval D corresponds to first sub-interval D. Then, the control chip 13 moves the cache data in the first sub-interval A to the second sub-interval A, and moves the cache data in the first sub-interval B to the second sub-interval B. Further, when the controller 2 whose power supply fails is started again, the control chip 13 reads the cache data in the second sub-interval A back to the first sub-interval A, and reads the cache data in the second sub-interval B back to the first sub-interval B. It should be noted that the order of moving and the order of reading back are not limited here.

[0080] The application realizes the automatic cache data backup and recovery mechanism through the control chip, significantly improves the data security, system reliability and operation simplicity without increasing the additional hardware cost and space occupation, optimizes the system performance and cost-effectiveness, and divides the non-volatile memory by the control chip, ensures that the cache data of each controller can be accurately stored and read when multiple controllers simultaneously occur power failure, avoids data confusion and loss to a certain extent, ensures the data consistency with the data after the last power-off shutdown, and improves the accuracy of data management and the reliability of the system.

[0081] In some embodiments, the above method further comprises: determining the master controller and the slave controller based on the plurality of controllers 2; in the case of failure of the slave controller, controlling the master controller to take over the task of the failed slave controller, and storing the cache data generated by executing the task of the failed slave controller to the first sub-interval corresponding to the failed slave controller; in the case of failure of the master controller, taking one of the plurality of slave controllers as a new master controller, and controlling the new master controller to take over the task of the master controller, and storing the cache data generated by executing the task of the master controller to the first sub-interval corresponding to the master controller.

[0082] Specifically, the master controller in the plurality of controllers 2 can be assigned by the cache system, for example, controller A can be assigned as the master controller, and controllers B, C and D are the slave controllers accordingly. When the slave controller fails, the control chip 13 controls the master controller to take over the task of the failed slave controller, so that the master controller can perform write operation on the first sub-interval corresponding to the failed slave controller, that is, store the cache data generated by executing the task of the failed slave controller to the first sub-interval corresponding to the failed slave controller. For example, in the case of failure of controller B, the control chip 13 can control controller A to take over the task of controller B, and controller A stores the cache data generated in executing the task of controller B into the first sub-interval B; in the case of failure of controller B and controller C, the control chip 13 can control controller A to take over the tasks of controller B and controller C, and controller A stores the cache data generated in executing the tasks of controller B and controller C into the first sub-interval B and the first sub-interval C respectively.

[0083] The main controller can also fail, in which case a new main controller needs to be assigned among the plurality of slave controllers, for example, the next adjacent slave controller of the original main controller is determined as the new main controller, if the next adjacent slave controller also fails, then the next next slave controller is determined as the new main controller, and so on. For example, assuming that the original main controller (controller A) fails, then the next adjacent controller 2 of controller A, i.e. controller B, is determined as the new main controller; if controller B also fails, then the next next adjacent controller 2 of controller A, i.e. controller C, is determined as the new main controller. When the main controller fails, the control chip 13 controls the new main controller to take over the task of the failed main controller, so that the new main controller can perform write operation on the first sub-interval corresponding to the failed main controller, i.e. store the cache data generated by executing the task of the failed main controller into the first sub-interval corresponding to the failed main controller. For example, in the case where the main controller (controller A) fails, controller B is determined as the new main controller, and the control chip 13 can control controller B to take over the task of controller A, and controller B stores the cache data generated by executing the task of controller A into the first sub-interval A.

[0084] The application automatically takes over the task of the slave controller by the main controller when the slave controller fails, not only enhances the fault tolerance and task continuity of the system, ensures the uninterrupted execution of critical tasks, but also properly stores the cache data generated by the task of the failed controller in the corresponding first sub-interval; when the main controller fails, a new main controller is selected among the slave controllers, and the task is seamlessly taken over, thereby ensuring the continuous operation of the system and the integrity of the data, so that the fault tolerance of the system is improved, and the automatic switching mechanism of the main and slave controllers simplifies the fault recovery process, reduces manual intervention, and reduces operation and maintenance costs; in addition, the new main controller can accurately store the cache data generated by executing the task of the original main controller into the corresponding first sub-interval, to a certain extent, avoiding data confusion and loss, and enhancing data security.

[0085] In summary, the shared cache assembly of the present application, by setting the switcher chip, the conversion chip and the control chip, realizes effective management of cache data of multiple controllers, the assembly can accurately store the cache data of each controller in the specified area of the cache memory, and in the emergency of controller power failure, the control chip can automatically migrate the cache data of the affected controller to the non-volatile memory, thereby significantly reducing the risk of data loss caused by power failure; the standby power supply of each controller is saved, not only reducing the space occupied by the device, but also greatly reducing the overall cost, showing its significant advantages in improving system reliability and economic benefits, and also significantly reducing the delay and improving the system performance; in addition, the present application can complete data interaction between multiple controllers without equipping each controller with a separate ROCE chip or CX6 chip, not only simplifying the PCB layout and wiring work of the board, reducing the design complexity, but also significantly reducing the hardware cost, improving the performance-price ratio and market competitiveness of the overall system.

[0086] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment.

[0087] The embodiment of the present application also provides an electronic device.

[0088] With reference to Figure 6 The electronic device 300 of the present application comprises a memory 310 for storing a computer program, and a processor 320 for executing the computer program to realize the steps of the implementation method of the aforementioned shared cache assembly.

[0089] The embodiment of the present application also provides a computer readable storage medium.

[0090] The computer readable storage medium of the present application stores a computer program, wherein the computer program is executed by the processor to realize the steps of the implementation method of the aforementioned shared cache assembly.

[0091] In one exemplary embodiment, the aforementioned computer readable storage medium can include but is not limited to: a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0092] The embodiment of the present application also provides a computer program product.

[0093] The computer program product of the present application comprises a computer program which, when executed by a processor, implements the steps of the implementation method of the aforementioned shared cache component.

[0094] Embodiments of the present application also provide another computer program product comprising a non-volatile computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of any of the implementation method embodiments of the aforementioned shared cache component.

[0095] Those skilled in the art will further appreciate that the steps of the example methods described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or both. The disclosure is not limited to any one form of implementation. The described examples are to be considered in a descriptive sense only and not for purposes of limitation. Therefore, the scope of the disclosure is not intended to be limited to any one form of implementation but is intended to cover any form of implementation consistent with the principles of the disclosure.

[0096] The above provides a kind of shared cache component and its implementation method, electronic equipment and storage medium provided by the present application in detail.The principle and implementation of the present application are described in this paper by applying specific examples, the above description of the example is only for helping to understand the method of the present application and its core idea.It should be pointed out that, for the ordinary skilled person in the art, without departing from the principle of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A shared cache component, characterized in that: include: A switch chip, a conversion chip, a control chip, a cache memory, and a non-volatile memory. The switch chip is connected to multiple controllers respectively. The conversion chip is connected to the switch chip and the control chip respectively, and is used to realize the conversion between the protocol supporting the computing high-speed interconnect technology and the protocol corresponding to the cache memory. The control chip is connected to the cache memory and the non-volatile memory respectively. The control chip is used to divide the cache memory into intervals according to the number of the multiple controllers to obtain multiple first sub-intervals, where the first sub-intervals correspond one-to-one to the controllers. The first sub-intervals are used to store cache data of the corresponding controllers, and in the event of a power failure of the controller, the cache data corresponding to the controller is moved to the non-volatile memory.

2. The shared cache component according to claim 1, wherein: The control chip is also used to: When the controller that has experienced a power failure is restarted, the cache data stored in the non-volatile memory is read back to the first sub-interval corresponding to the controller.

3. The shared cache component according to claim 2, wherein: The control chip includes a cache memory interface and a non-volatile memory interface. The control chip is connected to the cache memory based on the cache memory interface and is connected to the non-volatile memory based on the non-volatile memory interface. The control chip is further used to: In the event of a power failure of the controller, the cache data of the first subinterval corresponding to the failed controller is moved to the non-volatile memory through the cache memory interface and the non-volatile memory interface; When the faulty controller is restarted, the cache data of the faulty controller stored in the non-volatile memory is moved to the first sub-interval corresponding to the faulty controller through the non-volatile memory interface and the cache memory interface.

4. The shared cache component according to claim 1, wherein: The control chip is also used to: In the case where there are multiple controllers with power failure, the non-volatile memory is divided into intervals to obtain multiple second sub-intervals, and the second sub-intervals correspond to the first sub-intervals one by one; When the controller that has experienced a power failure is restarted, the cache data stored in the second sub-interval is read back to the corresponding first sub-interval.

5. The shared cache component according to claim 1, wherein: The control chip is also used to: storing the cache data of each controller into the corresponding first sub-interval through the conversion chip and the control chip; In the case where multiple controllers interact with each other, each controller is controlled to read cache data of other controllers.

6. The shared cache component according to claim 1, wherein: The control chip is also used to: determining a master controller and a slave controller based on the plurality of controllers; In the event that the slave controller fails, the master controller is controlled to take over tasks of the failed slave controller, and cache data generated by executing the tasks of the failed slave controller is stored in a first subinterval corresponding to the failed slave controller.

7. The shared cache component according to claim 6, wherein: The control chip is also used to: In the event that the master controller fails, one of the multiple slave controllers is used as a new master controller, and the new master controller is controlled to take over the tasks of the master controller, and the cache data generated by executing the tasks of the master controller is stored in the first sub-interval corresponding to the master controller.

8. The shared cache component according to claim 1, wherein: The control chip is used to divide the cache memory into sections according to the number of the multiple controllers, including: determining a cache capacity of the controller based on the number of tasks of the controller; The cache memory is divided into sections based on the cache capacity of each controller.

9. The shared cache component according to claim 1, wherein: The control chip is used to divide the cache memory into sections according to the number of the multiple controllers, including: The cache memory is evenly divided according to the number of the multiple controllers to obtain multiple first sub-intervals of the same storage space.

10. A method for implementing a shared cache component according to any one of claims 1 to 9, characterized in that: The method comprises: Dividing the cache memory into sections according to the number of the plurality of controllers to obtain a plurality of first subsections, wherein the first subsections correspond to the controllers one-to-one, and the first subsections are used to store cache data corresponding to the controllers; In the event of a power failure of the controller, cache data corresponding to the controller is moved to a non-volatile memory.

11. The method for implementing a shared cache component according to claim 10, wherein: The method further comprises: When the controller that has experienced a power failure is restarted, the cache data stored in the non-volatile memory is read back to the subinterval corresponding to the controller.

12. The method for implementing a shared cache component according to claim 10, wherein: The method further comprises: determining a master controller and a slave controller based on the plurality of controllers; In the event that the slave controller fails, controlling the master controller to take over tasks of the failed slave controller, and storing cache data generated by executing the tasks of the failed slave controller into a first subinterval corresponding to the failed slave controller; In the event that the master controller fails, one of the multiple slave controllers is used as a new master controller, and the new master controller is controlled to take over the tasks of the master controller, and the cache data generated by executing the tasks of the master controller is stored in the first sub-interval corresponding to the master controller.

13. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the method for implementing the shared cache component as claimed in any one of claims 10 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the method for implementing the shared cache component according to any one of claims 10 to 12 are implemented.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method for implementing the shared cache component according to any one of claims 10 to 12 are implemented.

Images