A network loop detection method, electronic device, and storage medium based on depth traversal

By constructing an adjacency list and combining it with a depth-first search algorithm, the problem of difficult identification of network loops in printed circuit boards in existing technologies is solved, enabling fast and accurate location of network loops and improving design efficiency and reliability.

CN120805830BActive Publication Date: 2025-11-14SHANGHAI UNIVISTA IND SOFTWARE GRP CO LTD +1
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Patent Information

Application Number
CN202511317050.7
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2025-09-16
Publication Date
2025-11-14
Estimated Expiration
2045-09-16

AI Technical Summary

Technical Problem

Existing electronic design automation tools struggle to quickly and accurately identify and locate network loops in printed circuit boards, limiting design iteration efficiency and reliability verification.

Method used

A network loop detection method based on depth traversal is adopted. By constructing an adjacency list and combining it with a depth-first search algorithm, a loop queue is obtained and standardized. Duplicate standard loop queues are removed, thereby achieving fast and accurate location of network loops.

Benefits of technology

This enables rapid and accurate location of network loops in printed circuit boards, improving design iteration efficiency and the accuracy of reliability verification.

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Abstract

This invention relates to the field of electronic design automation (EDA), and particularly to a network loop detection method, electronic device, and storage medium based on depth-first traversal. The method obtains the set of nodes and edges in the target network, constructs an adjacency list for each node, traverses it to obtain a loop queue, and performs standardization processing to remove duplicate loops, resulting in a standard queue of all unique loops. The standardization process includes: obtaining a unique identifier for each edge in the current loop queue; cyclically shifting the edge corresponding to the smallest unique identifier to the beginning of the current loop queue to obtain a candidate loop queue; if the second element in the candidate loop queue is less than the last element, then the candidate loop queue is the standard loop queue after standardization; otherwise, all elements in the candidate loop queue are re-stored in reverse order and then cyclically shifted again to obtain the standard loop queue, enabling rapid detection of all network loops.
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Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, and in particular to a network loop detection method, electronic device and storage medium based on depth traversal. Background Technology

[0002] In printed circuit board (PCB) design, a net is used to characterize a group of device pins, vias, and interconnects with the same electrical potential. Its topology directly determines signal integrity and electrical performance. With the increase in circuit integration and the widespread adoption of high-speed signal design, the complexity of PCB routing has increased significantly. Cross-layer traces and redundant connections are frequent in multilayer boards, which can lead to the formation of unintended closed conductive paths within the same net, i.e., net loops. Such loops are formed by repeated connections or redundant traces within the same net. Although they do not destroy the electrical connectivity of the network, they essentially introduce an additional ring-shaped conductor structure. Under conditions of high-frequency signal transmission or transient current changes, this structure is prone to parasitic inductance effects, which can induce problems such as enhanced electromagnetic interference and aggravated signal crosstalk, seriously affecting system stability and anti-interference capabilities.

[0003] Current electronic design automation (EDA) tools primarily rely on netlists for electrical rule checking (ERC) and routing connectivity verification. Their core logic focuses on the integrity of pin connections, but lacks effective criteria for determining the existence of redundant closed paths within the same net. Since network loops do not violate basic connection rules, conventional design rule checking (DRC) processes struggle to identify such structural defects. Current detection methods largely depend on manual visual inspection or preliminary screening based on simple geometric overlaps, resulting in low efficiency and a high risk of missed detections. This is especially true in high-density interconnect (HDI) or multilayer board designs, where cross-layer traces are complex and loop formations are diverse. The lack of automated and systematic detection mechanisms makes it impossible to quickly and accurately identify and locate the specific location and path of network loops, severely hindering design iteration efficiency and reliability verification processes. Therefore, a fast and accurate method for detecting network loops is urgently needed. Summary of the Invention

[0004] To address the aforementioned technical problems, the present invention adopts the following technical solution: a network loop detection method based on depth-first traversal, the method comprising the following steps:

[0005] S100, obtain the node set and edge set under the target network. The nodes in the node set are pins, vias or intersections, and the edges in the edge set are traces between two nodes.

[0006] S300, construct an adjacency table for each node based on the node set and edge set; wherein each entry in the adjacency table records all adjacent nodes of the current node, as well as the edges connecting the node to each adjacent node.

[0007] S500: Traverse the adjacency list to obtain the loop queues in the network, and perform standardization processing on each loop queue to obtain a standard loop queue. Remove duplicate standard loop queues to obtain all non-duplicate standard loop queues; wherein, the standardization processing steps include:

[0008] S510: Obtain the unique identifier of each edge in the current loop queue.

[0009] S530: Circularly shift the edge corresponding to the unique identifier with the smallest value to the first position of the current loop queue to obtain the candidate loop queue.

[0010] S550, if the second element in the candidate loop queue is less than the last element, then the candidate loop queue is a standard loop queue after standardization; otherwise, all elements in the candidate loop queue are restored in reverse order and then S530 is executed to obtain a standard loop queue.

[0011] Furthermore, the present invention also provides a non-transitory computer-readable storage medium storing at least one instruction or at least one program segment, wherein the at least one instruction or the at least one program segment is loaded and executed by a processor to implement the above-described method.

[0012] In addition, the present invention provides an electronic device including a processor and the aforementioned non-transitory computer-readable storage medium.

[0013] The present invention has at least the following beneficial effects:

[0014] This invention provides a network loop detection method based on depth-first traversal. It establishes an adjacency list and obtains a loop queue through traversal. Each loop queue is then standardized to obtain a standard loop queue. Duplicate standard loop queues are removed to obtain all unique standard loop queues. This method can quickly detect all network loops in a network, facilitating user problem localization. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 The flowchart illustrates a network loop detection method based on depth traversal, as provided in this embodiment of the invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Unless otherwise defined, all technical and scientific terms used in the embodiments of this invention have the same meaning as commonly understood by those skilled in the art.

[0019] Please see Figure 1 This invention provides a flowchart of a network loop detection method based on depth-first traversal, the method comprising the following steps:

[0020] S100, obtain the node set and edge set under the target network. The nodes in the node set are pins, vias or intersections, and the edges in the edge set are traces between two nodes.

[0021] In network design, a network is a collection of electrically interconnected circuit nodes used to implement signal or power connections between pins of specific devices.

[0022] In this context, a pin refers to the electrical connection point on the package of an integrated circuit device, discrete component, or connector, serving as the start or end point of a network. Each pin is uniquely identified in the schematic and corresponds to a metal pad or bump in the physical layout.

[0023] A via is a conductive structure in a multilayer printed circuit board (PCB) or integrated circuit interconnect layer used to achieve vertical electrical connections between different conductive layers. Vias are typically formed by drilling holes with copper plating or filling them with conductive material, and can connect traces of the same network on different layers.

[0024] An intersection point is a geometric connection point where three or more traces meet in the same conductive layer or multi-layer wiring, used to electrically merge multiple branch paths. An intersection point is not an independent physical structure, but rather a logical node in the wiring topology.

[0025] In this context, a trace refers to a continuous conductive path in a PCB or chip interconnect layer used to connect two or more electrical nodes, typically formed by photolithography. Electrical nodes can be pins, vias, or intersections.

[0026] A network loop is a closed current path formed within the same network by the connection of traces or components.

[0027] S300, construct an adjacency table for each node based on the node set and edge set; wherein each entry in the adjacency table records all adjacent nodes of the current node, as well as the edges connecting the node to each adjacent node.

[0028] It should be noted that there may be multiple edges between two nodes, so both edges and nodes are considered when designing the adjacency list. As an example, when there are two paths eid1 and eid2 between nodes NodeA and NodeB, the entry for nodeA in the adjacency list is {NodeA,{{NodeB,eid1},{NodeB,eid2}}}, and the entry for nodeB in the adjacency list is {NodeB,{{NodeA,eid1},{NodeA,eid2}}.

[0029] In one implementation, the adjacency list is constructed based on an undirected graph model and used to record bidirectional connections between nodes. This embodiment of the invention abstracts the electrical connections in the target network into an undirected graph model, where pins, vias, and intersections serve as nodes, and traces serve as edges connecting nodes. The graph model is represented by an adjacency list data structure, providing a foundation for subsequent depth-first traversal and loop detection.

[0030] S500: Traverse the adjacency list to obtain the loop queues in the network, and perform standardization processing on each loop queue to obtain a standard loop queue. Remove duplicate standard loop queues to obtain all non-duplicate standard loop queues.

[0031] In one implementation, the algorithm for traversing the adjacency list is depth-first search (DFS), breadth-first search (BFS), or Tarjan's algorithm. Other types of algorithms for traversing adjacency lists to find cycles fall within the scope of protection of this invention.

[0032] Among them, the loop queue refers to arranging the traces in the detected loop according to their adjacency relationship in the closed current path, in the traversal direction, to form a trace sequence that represents the loop topology.

[0033] The purpose of the standard loop queue is to deduplicate results. Since the same network loop may generate different routing sequences at different traversal starting points or directions, in order to avoid duplicate identification, the detected loop paths are standardized. This standardization process aligns different loop queues for the same loop into the same loop queue, which is then used for loop deduplication and storage.

[0034] Furthermore, the standardization process includes the following steps:

[0035] S510: Obtain the unique identifier of each edge in the current loop queue.

[0036] In one implementation, a unique identifier for each edge is pre-assigned when constructing the network topology model to uniquely identify the path between any two nodes; this identifier remains unchanged throughout the loop detection process to support subsequent path recording, standardization processing, etc.

[0037] S530: Circularly shift the edge corresponding to the unique identifier with the smallest value to the first position of the current loop queue to obtain the candidate loop queue.

[0038] Among them, cyclic shifting can ensure that the relative positional relationship between each edge in the loop queue remains unchanged.

[0039] As an example, when the original circular queue is {66,55,77,88}, after shifting the smallest number 55 to the left in a circular manner, the resulting candidate circular queue is {55,77,88,66}, and the relative positional relationship of each element in the circular queue remains unchanged.

[0040] S550, if the second element in the candidate loop queue is less than the last element, then the candidate loop queue is a standard loop queue after standardization; otherwise, all elements in the candidate loop queue are restored in reverse order and then S530 is executed to obtain a standard loop queue.

[0041] It should be noted that standardization is required after each loop is detected. If a queue of identical standard loops already exists, it will not be stored again. Specifically, S530 can solve the duplication problem caused by different starting points, and S550 can eliminate the two representations of the same loop caused by different traversal directions, such as clockwise or counterclockwise, thereby achieving true deduplication and ensuring that the same loop is recorded only once.

[0042] As an example, when the candidate loop queue is {55,77,88,66}, since the second element in the candidate loop queue is greater than the last element, it is re-stored in reverse order to get {66,88,77,55}. Based on {66,88,77,55}, S530 is executed to get {55,66,88,77}, which is the final standard loop queue.

[0043] In one implementation, in S500, the traversal step includes: traversing the adjacency list using a depth-first search algorithm, starting from any unvisited node, recursively visiting its adjacent nodes, and recording the node sequence and edge sequence in the traversal path; when the adjacent nodes of a certain node have been visited, it is determined that there is a loop in the network.

[0044] In one implementation, to further improve the efficiency and accuracy of loop detection, a fast criterion based on local topology is introduced during the traversal process. In S500, before the traversal, the following is also included:

[0045] S51, the network is divided into multiple connected components, each connected component representing a set of electrically connected nodes; independent loop detection is performed based on the topology of each connected component. It should be noted that a connected component is a set of interconnected nodes in the graph; nodes within the same connected component can reach each other through edge sequences, while nodes in different components are not connected by paths.

[0046] S52, count the number of nodes N and the number of edges M contained in each connected component.

[0047] S53. For each connected component, traverse and detect loops. If N>M, it is determined that there are no loops in the current connected component, and the component is skipped directly. Then, traverse the next connected component.

[0048] It should be noted that the above method can reduce the number of invalid traversals and improve detection accuracy and efficiency.

[0049] As an example, consider a cycle consisting of nodes NodeA, NodeB, NodeC, and NodeA again. The edge between NodeA and NodeB is eid1, the edge between NodeB and NodeC is eid2, and the edge between NodeC and NodeA is eid3. The adjacency list of NodeA is {NodeA, {NodeB, eid1}, {NodeC, eid3}}, the adjacency list of NodeB is {NodeB, {NodeA, eid1}, {NodeC, eid2}}, and the adjacency list of NodeC is {NodeC, {NodeB, eid2}, {NodeA, eid3}}. Assuming this cycle is a connected component, the node queue and edge queue are initialized to empty before the traversal begins. A Depth-First Search (DFS) traversal is performed on the current connected component to detect cycles. Since the number of nodes and edges is 3 (equal to each other), the traversal is performed. First, visit node A and add it to the node queue {NodeA}. Traverse NodeA's adjacency list, processing {NodeB, eid1} first. Visit NodeB. Since NodeB has not been visited, add it to the node queue to obtain a new node queue {NodeA, NodeB}, and add eid1 to the path queue to obtain a new path queue {eid1}. Traverse NodeB's adjacency list: {NodeA, eid1} and {NodeC, eid2}. Since NodeA is the parent node, skip it. Since NodeC has not been visited, proceed to the next step. Visit NodeC and add it to the node queue to obtain a new node queue {NodeA, NodeB, NodeC}. Add eid2 to the edge queue to obtain a new edge queue {eid1, eid2}. Traverse NodeC's adjacency list: {NodeB, eid2} and {NodeA, eid3}. Since NodeB is the parent node, skip it. Since NodeA is already in the node queue and is not the parent node, a cycle is found. If the current loop forms a closed path, then add eid3 to the edge queue to obtain a new edge queue {eid1, eid2, eid3}, which is the loop path.

[0050] In one implementation, in step S500, before traversal, nodes with a degree of 1 are excluded as the initial traversal starting point, and traversal is initiated only for nodes with a degree greater than 1. It should be noted that since each node in a loop must be connected to at least two different paths (i.e., a degree ≥ 2), nodes with a degree of 1 cannot participate in forming a closed path. Therefore, before traversal, the degree of all nodes is counted, and only nodes with a degree greater than 1 are used as the traversal starting point for potential loop regions. This avoids meaningless searches and significantly improves detection efficiency. It should also be noted that although nodes with a degree of 1 are not used as starting points, during the traversal of other nodes, if the path passes through such nodes, their connection relationships will still be accessed and recorded normally to ensure the integrity of the network topology.

[0051] In one implementation, the method further includes: S400, applying the Tarjan algorithm to identify cut vertices and bridges in the network, and decomposing the network into multiple biconnected components; for each biconnected component, performing S500 to detect loops. As an example, to better understand cut vertices, consider two loops: the node connection order of the first loop is NodeA, NodeB, NodeC, and NodeA; the node connection order of the second loop is NodeA, NodeD, NodeE, and NodeA; wherein the first and second loops share nodeA, which is a cut vertex. As another example, to better understand bridges, consider two loops: the node connection order of the first loop is NodeA, NodeB, NodeC, and NodeA; NodeA connects to NodeF; the node connection order of the second loop is NodeF, NodeD, NodeE, and NodeF; wherein the first and second loops share a bridge composed of nodes NodeA and NodeF.

[0052] In summary, this invention provides a network loop detection method based on depth-first traversal. It establishes an adjacency list and obtains a loop queue through traversal, standardizes each loop queue to obtain a standard loop queue, removes duplicate standard loop queues, and obtains all non-duplicate standard loop queues. This method can quickly detect all network loops in a network, facilitating user problem localization.

[0053] Embodiments of the present invention also provide a non-transitory computer-readable storage medium that can be disposed in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiments, wherein the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiments.

[0054] Embodiments of the present invention also provide an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0055] Embodiments of the present invention also provide a computer program product including program code, which, when the program product is run on an electronic device, causes the electronic device to perform the steps of the methods described above in various exemplary embodiments of the present invention.

[0056] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0057] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A network loop detection method based on depth-first traversal, characterized in that, The method includes the following steps: S100, obtain the node set and edge set under the target network, wherein the nodes in the node set are pins, vias or intersections, and the edges in the edge set are traces between two nodes; S300, construct an adjacency table for each node based on the node set and edge set; wherein, each entry in the adjacency table records all adjacent nodes of the current node, as well as the edges connecting the node to each adjacent node; S500: Traverse the adjacency list to obtain the loop queues in the network, and perform standardization processing on each loop queue to obtain a standard loop queue. Remove duplicate standard loop queues to obtain all non-duplicate standard loop queues; wherein, the standardization processing steps include: S510, obtain the unique identifier of each edge in the current loop queue; S530: Circularly shift the edge corresponding to the unique identifier with the smallest value to the first position of the current loop queue to obtain the candidate loop queue; S550, if the second element in the candidate loop queue is less than the last element, then the candidate loop queue is a standard loop queue after standardization; otherwise, all elements in the candidate loop queue are restored in reverse order and then S530 is executed to obtain a standard loop queue.

2. The method according to claim 1, characterized in that, In S500, the traversal steps include: traversing the adjacency list using a depth-first search algorithm, starting from any unvisited node, recursively visiting its adjacent nodes, and recording the node sequence and edge sequence in the traversal path; when the adjacent nodes of a certain node have been visited, it is determined that there is a loop in the network.

3. The method according to claim 1, characterized in that, In S500, the process before traversal includes: S51, the network is divided into multiple connected components, each connected component representing a set of electrically interconnected nodes; independent loop detection is performed based on the topology of each connected component; S52, count the number of nodes N and the number of edges M contained in each connected component; S53. For each connected component, traverse and detect loops. If N>M, it is determined that there are no loops in the current connected component, and the component is skipped directly. Then, traverse the next connected component.

4. The method according to claim 1, characterized in that, In S500, before traversal, nodes with a degree of 1 are excluded as the initial traversal starting point, and traversal is only started for nodes with a degree greater than 1.

5. The method according to claim 1, characterized in that, The method further includes: S400, applying the Tarjan algorithm to identify cut points and bridges in the network, and decomposing the network into multiple biconnected components; for each biconnected component, S500 is performed to perform loop detection.

6. The method according to claim 1, characterized in that, Each edge's unique identifier is pre-assigned when the network topology model is built, and is used to uniquely identify the path between any two nodes; this identifier remains unchanged throughout the entire loop detection process.

7. The method according to claim 1, characterized in that, The adjacency list in S300 is constructed based on an undirected graph model and is used to record bidirectional connection relationships between nodes.

8. A non-transitory computer-readable storage medium, wherein the storage medium stores at least one instruction or at least one program segment, characterized in that, The at least one instruction or the at least one program segment is loaded and executed by the processor to implement the method as described in any one of claims 1-7.

9. An electronic device, characterized in that, Includes a processor and the non-transitory computer-readable storage medium as described in claim 8.

Citation Information

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