Processing unit in systolic array, systolic array, data processing method and electronic equipment

Abstract

The invention discloses a processing unit in a systolic array, the systolic array, a data processing method and electronic equipment. The processing unit is provided with a first group of data transmission paths for transmitting data in a first dimension, a second group of data transmission paths for transmitting data in a second dimension and a third group of data transmission paths for transmitting data in the first dimension; wherein the first group of data transmission paths comprises a first data transmission path for transmitting data along a first direction and a second data transmission path for transmitting data along a second direction; the second group of data transmission paths comprises a third data transmission path for transmitting data along a third direction and a fourth data transmission path for transmitting data along a fourth direction; and the third group of data transmission paths comprises a first data output path for transmitting data along the first direction and a second data output path for transmitting data along the second direction.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, and in particular to a processing unit in systolic array, systolic array, data processing method and electronic equipment. BACKGROUND

[0002] The systolic array is a parallel computing architecture, which can be implemented by hardware circuit. Specifically, the systolic array is composed of a plurality of same processing units (PEs) according to certain interconnection rules. Each processing unit can communicate with adjacent processing units and perform certain computing tasks to efficiently perform matrix operations and other linear algebra operations.

[0003] The core idea of the systolic array is to make data flow in the array of processing units to reduce the number of memory accesses and thus improve the computing frequency. Therefore, how to improve the running speed and pipeline running efficiency in the systolic array has become a research direction of those skilled in the art. SUMMARY

[0004] In view of the above problems, the present application provides the following technical solutions:

[0005] A processing unit in a systolic array, the processing unit has a first group of data transmission paths for transmitting data in a first dimension, a second group of data transmission paths for transmitting data in a second dimension, and a third group of data transmission paths for transmitting data in the first dimension; wherein,

[0006] The first group of data transmission paths includes a first data transmission path for transmitting data in a first direction and a second data transmission path for transmitting data in a second direction;

[0007] The second group of data transmission paths includes a third data transmission path for transmitting data in a third direction and a fourth data transmission path for transmitting data in a fourth direction;

[0008] The third group of data transmission paths includes a first data output path for transmitting data in a first direction and a second data output path for transmitting data in a second direction.

[0009] Optionally, the first group of data transmission paths includes a first selection module, and the first selection module is configured to select the first data transmission path or the second data transmission path to transmit the first data based on a first selection signal;

[0010] The second group of data transmission paths includes a second selection module, and the second selection module selects the third data transmission path or the fourth data transmission path to transmit the second data based on the second selection signal;

[0011] The processing unit further comprises a data processing module, the data processing module comprises a calculation unit, the calculation unit is located on the data transmission paths of the first group of data transmission paths and the second group of data transmission paths, and is configured to process the first data and the second data to generate third data, store the third data, and output the third data through the first data output path or the second data output path based on the first selection signal.

[0012] Optionally, the first group of data transmission paths further comprises a first group of output ports located on the first dimension, the second group of data transmission paths further comprises a second group of output ports located on the second dimension, and the third group of data transmission paths further comprises a third group of output ports located on the first dimension.

[0013] The first group of output ports comprises a first output port and a second output port, the first output port and the second output port are configured to output the first data; the second group of output ports comprises a third output port and a fourth output port, the third output port and the fourth output port are configured to output the second data; and the third group of output ports comprises a fifth output port and a sixth output port, the fifth output port and the sixth output port are configured to output the third data.

[0014] The first data output end of the calculation unit is connected to the first group of output ports.

[0015] The second data output end of the calculation unit is connected to the second group of output ports.

[0016] The third data output end of the calculation unit is connected to the third group of output ports.

[0017] Optionally, the first group of data transmission paths further comprises a first group of input ports located on the first dimension, the second group of data transmission paths further comprises a second group of input ports located on the second dimension, and the third group of data transmission paths further comprises a third group of input ports located on the first dimension; the first group of input ports comprises a first input port and a second input port, the first input port and the second input port are configured to input the first data; the second group of input ports comprises a third input port and a fourth input port, the third input port and the fourth input port are configured to input the second data; and the third group of input ports comprises a fifth input port and a sixth input port, the fifth input port and the sixth input port are configured to input the third data.

[0018] The two input ends of the first selection module are connected to the first input port and the second input port respectively, and the output end is connected to the first data input end of the calculation unit;

[0019] The two input ends of the second selection module are connected to the third input port and the fourth input port respectively, and the output end is connected to the second data input end of the calculation unit;

[0020] The control end of the first selection module is used for inputting the first selection signal, and the control end of the second selection module is used for inputting the second selection signal;

[0021] The third group of input ports are connected to the third data input end of the calculation unit.

[0022] Optionally, the calculation unit comprises:

[0023] The first processing unit is used for processing the first data input from the first data input end and the second data input from the second data input end to generate the third data;

[0024] The second processing unit is used for selecting the third data output from the third data input end based on the first selection signal;

[0025] The third processing unit is used for selecting the third data output from the first processing unit or selecting the third data output from the second processing unit based on the third selection signal;

[0026] The fourth processing unit is used for selecting the third data output from the first processing unit and outputting to the first processing unit or selecting the third data output from the second processing unit and outputting to the processing unit based on the third selection signal.

[0027] Optionally, the calculation unit further comprises:

[0028] The output signal generation module is used for generating the third selection signal based on the end signal transmitted by the first data transmission path and / or the second data transmission path, the output end of the output signal generation module is connected to the selection signal input end of the third processing unit, and the third processing unit outputs the third data input from the third group of input ports based on the third selection signal;

[0029] The end signal represents that the data processing task of the processing unit in the systolic array has ended.

[0030] Optionally, the processing unit further comprises:

[0031] a first selection signal generation module configured to generate a corresponding first selection signal based on signal input states of two input ends of the first selection module; a selection signal output end of the first selection signal generation module is connected to a control end of the first selection module and a first selection signal input end of the calculation unit;

[0032] a second selection signal generation module configured to generate a corresponding second selection signal based on signal input states of two input ends of the second selection module; a selection signal output end of the second selection signal generation module is connected to a control end of the second selection module;

[0033] The first selection signal generation module is configured to generate a first sub-selection signal when the first input port first receives the first data, so that the first selection module selects the first data transmission path to transmit the first data, and the third data input end of the calculation unit selects to input third data output by the second data output path, and generate the first sub-selection signal or a second sub-selection signal based on signal input states of two input ends of the first selection module of other processing units when the second input port first receives the first data, and the first selection module selects the second data transmission path to transmit the first data when the first selection signal generation module outputs the second sub-selection signal, and the third data input end of the calculation unit selects to input third data output by the first data output path.

[0034] The second selection signal generation module is configured to generate a third sub-selection signal when the third input port first receives the second data, so that the second selection module selects the third data transmission path to transmit the second data, and generate the third sub-selection signal or a fourth sub-selection signal based on signal input states of two input ends of the second selection module of other processing units when the fourth input port first receives the second data, and the second selection module selects the fourth data transmission path to transmit the second data when the second selection signal generation module outputs the fourth sub-selection signal.

[0035] Optionally, the system further comprises:

[0036] a first delay module, two input ends of the first delay module are connected to the first input port and the second input port respectively, and two output ends are connected to two input ends of the first selection module, configured to output the first data to the first selection module after one cycle;

[0037] A second delay module, two input ends of the second delay module are connected to the third input port and the fourth input port respectively, two output ends are connected to two input ends of the second selection module respectively, and the second data is output to the second selection module after one period;

[0038] Two input ends of the first selection signal generation module are connected with two input ends of the first delay module respectively, and two input ends of the second selection signal generation module are connected with two input ends of the second delay module respectively.

[0039] A systolic array comprising 2n x 2n processing units, n being greater than 1, the processing units having a first set of data transmission paths for transmitting data in a first dimension, a second set of data transmission paths for transmitting data in a second dimension, and a third set of data transmission paths for transmitting data in the first dimension; wherein,

[0040] The first set of data transmission paths comprises a first data transmission path for transmitting data in a first direction and a second data transmission path for transmitting data in a second direction;

[0041] The second set of data transmission paths comprises a third data transmission path for transmitting data in a third direction and a fourth data transmission path for transmitting data in a fourth direction;

[0042] The third set of data transmission paths comprises a first data output path for transmitting data in the first direction and a second data output path for transmitting data in the second direction.

[0043] Optionally, the systolic array comprises four systolic arrays arranged in a matrix, a first systolic array comprising processing units located in 1-n rows and 1-n columns, a second systolic array comprising processing units located in 1-n rows and (n+1)-2n columns, a third systolic array comprising processing units located in (n+1)-2n rows and 1-n columns, and a fourth systolic array comprising processing units located in (n+1)-2n rows and (n+1)-2n columns;

[0044] The processing unit located in the first row and the first column is the first processing unit in the first systolic array, the processing unit located in the first row and the (n+1)th column and the processing unit located in the first row and the 2nth column are the first processing units in the second systolic array, the processing unit located in the (n+1)th row and the first column and the processing unit located in the 2nth row and the first column are the first processing units in the third systolic array, and the processing unit located in the (n+1)th row and the (n+1)th column and the processing unit located in the 2nth row and the 2nth column are the first processing units in the fourth systolic array;

[0045] The first processing unit generates a first selection signal based on the input state of the data input port of the first group of data transmission paths thereof and the input state of the data input port of the first group of data transmission paths of other first processing units located in the same systolic matrix, and selects the first data transmitted in the first group of data transmission paths as input based on the first selection signal and outputs the first data to downstream processing units through the first group of data transmission paths, and selects the third data transmitted in the third group of data transmission paths as input and transmits the third data to downstream processing units through the third group of data transmission paths;

[0046] The first processing unit also generates a second selection signal based on the input state of the data input port of the second group of data transmission paths thereof and the input state of the data input port of the second group of data transmission paths of other first processing units located in the same systolic matrix, and selects the second data transmitted in the second group of data transmission paths as input based on the second selection signal and outputs the second data to downstream processing units through the second group of data transmission paths;

[0047] The second processing unit selects the first data transmitted in the first group of data transmission paths and the second data transmitted in the second group of data transmission paths as input based on the first selection signal and the second selection signal output by the first processing unit located in the same systolic matrix, and outputs the first data and the second data to downstream processing units through the first group of data transmission paths and the second group of data transmission paths, and selects the third data transmitted in the third group of data transmission paths as input and transmits the third data to downstream processing units through the third group of data transmission paths.

[0048] Optionally, the systolic array includes four systolic matrices arranged in a matrix, the first systolic matrix includes processing units located in 1-n rows and 1-n columns, the second systolic matrix includes processing units located in 1-n rows and (n+1)-2n columns, the third systolic matrix includes processing units located in (n+1)-2n rows and 1-n columns, and the fourth systolic matrix includes processing units located in (n+1)-2n rows and (n+1)-2n columns;

[0049] The processing unit located in the first row and the first column is the first processing unit in the first systolic matrix, the processing unit located in the first row and the second n column is the first processing unit in the second systolic matrix, the processing unit located in the second n row and the first column is the first processing unit in the third systolic matrix, and the processing unit located in the second n row and the second n column is the first processing unit in the fourth systolic matrix;

[0050] The first processing unit generates a first selection signal based on the input state of the data input port of the first set of data transmission paths thereof, and selects to input first data transmitted in the first set of data transmission paths and output to a downstream processing unit through the first set of data transmission paths, and selects to input third data transmitted in the third set of data transmission paths and transmit to a downstream processing unit through the third set of data transmission paths based on the first selection signal;

[0051] The first processing unit generates a second selection signal based on the input state of the data input port of the second set of data transmission paths thereof, and selects to input second data transmitted in the second set of data transmission paths and output to a downstream processing unit through the second set of data transmission paths based on the second selection signal;

[0052] The second processing unit selects to input first data transmitted in the first set of data transmission paths and second data transmitted in the second set of data transmission paths and output to a downstream processing unit through the first set of data transmission paths and the second set of data transmission paths, and selects to input third data transmitted in the third set of data transmission paths and transmit to a downstream processing unit through the third set of data transmission paths based on the first selection signal and the second selection signal output by the first processing unit located in the same systolic matrix as the second processing unit.

[0053] Optionally, the systolic array comprises a first processing unit and a second processing unit adjacent in the first dimension, the first output port of the first processing unit is connected to the first input port of the second processing unit, the second input port of the first processing unit is connected to the second output port of the second processing unit, the fifth output port of the first processing unit is connected to the fifth input port of the second processing unit, and the sixth input port of the first processing unit is connected to the sixth output port of the second processing unit.

[0054] The systolic array comprises a first processing unit and a second processing unit adjacent in the second dimension, the third output port of the first processing unit is connected to the third input port of the second processing unit, and the fourth input port of the first processing unit is connected to the fourth output port of the second processing unit.

[0055] An electronic device comprising the systolic array of any one of the preceding items or a systolic array composed of the processing units in the systolic array of any one of the preceding items.

[0056] A data processing method applied to a systolic array, the systolic array comprising 2n*2n processing units, the processing units having a first group of data transmission paths for transmitting data in a row direction, a second group of data transmission paths for transmitting data in a column direction, and a third group of data transmission paths for transmitting data in the row direction, the first group of data transmission paths transmitting first data, the second group of data transmission paths transmitting second data, and the third group of data transmission paths transmitting third data; each group comprising 2 data transmission directions;

[0057] The systolic array comprises four systolic matrices arranged in a matrix, each systolic matrix comprising n*n processing units, the processing unit located at the first row and the first column being the first processing unit in the first systolic matrix, the processing unit located at the first row and the 2nth column being the first processing unit in the second systolic matrix, the processing unit located at the 2nth row and the first column being the first processing unit in the third systolic matrix, and the processing unit located at the 2nth row and the 2nth column being the first processing unit in the fourth systolic matrix;

[0058] The data processing method comprises:

[0059] At a first time, the processing units in the first systolic matrix are controlled to transmit the first data through the first data transmission paths and the second data through the third data transmission paths, the processing units in the second systolic matrix are controlled to transmit the first data through the second data transmission paths and the second data through the third data transmission paths, the processing units in the third systolic matrix are controlled to transmit the first data through the first data transmission paths and the second data through the fourth data transmission paths, and the processing units in the fourth systolic matrix are controlled to transmit the first data through the second data transmission paths and the second data through the fourth data transmission paths.

[0060] Optionally, the processing unit located at the first row and the n+1th column is also the first processing unit in the second systolic matrix, the processing unit located at the n+1th row and the first column is also the first processing unit in the third systolic matrix, and the processing unit located at the n+1th row and the n+1th column is also the first processing unit in the fourth systolic matrix.

[0061] Optionally, in the first systolic matrix, along the row direction, the first column of processing units are inputted with the second data in the second data matrix from the first column, and each second data in the second data matrix is transmitted to the processing units in the next row according to the data transmission period; meanwhile, along the column direction, the first row of processing units are inputted with the first data in the first data matrix from the first row, and each first data in the first data matrix is transmitted to the processing units in the next column according to the data transmission period.

[0062] In the second pulsation matrix, along the row direction, the first data in the first data matrix from the last column is inputted to the first row processing units of the previous columns in turn with a delay of one cycle, and each first data in the array of the first data in each column is transmitted to the processing units of the next row in the data transmission cycle; meanwhile, along the column direction, the same second data is inputted to the last row processing units of each column in the second pulsation matrix synchronously and symmetrically with the first pulsation matrix, and each second data in the array of the second data in each column is transmitted to the processing units of the next column in the data transmission cycle.

[0063] In the third pulsation matrix, along the row direction, the same second data is inputted to the last row processing units of each column in the third pulsation matrix synchronously and symmetrically with the first pulsation matrix, and each second data in the array of the second data in each column is transmitted to the processing units of the next row in the data transmission cycle; meanwhile, along the column direction, the first data in the first data matrix from the last row is inputted to the first column processing units of the previous rows in turn with a delay of one cycle, and each first data in the array of the first data in each row is transmitted to the processing units of the next column in the data transmission cycle.

[0064] In the fourth pulsation matrix, along the row direction, the same second data is inputted to the last row processing units of each column in the second pulsation matrix synchronously and symmetrically with the second pulsation matrix, and each second data in the array of the second data in each column is transmitted to the processing units of the next row in the data transmission cycle; meanwhile, along the column direction, the same first data is inputted to the last column processing units of each row in the third pulsation matrix synchronously and symmetrically with the third pulsation matrix, and each first data in the array of the first data in each row is transmitted to the processing units of the next column in the data transmission cycle.

[0065] Optionally, according to the data input state of the first processing unit in each of the pulsation matrices, a data transmission path in the corresponding direction of the pulsation matrix is selected, so that the same data transmission direction is selected for each processing unit in the same pulsation matrix.

[0066] Optionally, the data processing device further comprises:

[0067] After the processing unit in the kth row and the kth column outputs a third signal, the third data stored in the processing unit in the kth row and the kth column is outputted, wherein the third signal represents that the data processing process in the processing unit in the kth row and the kth column is completed, and k is an integer not less than 1 and not greater than 2n.

[0068] An electronic device, comprising: a systolic array, a processor and a memory, wherein the systolic array is any of the above-mentioned systolic arrays; the memory is used to store a computer program; and the processor is used to execute the computer program, so that the electronic device can implement the data processing method of any of the above-mentioned data processing methods. BRIEF DESCRIPTION OF DRAWINGS

[0069] The above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent with regard to the following detailed description, appended claims, and accompanying drawings. Throughout the drawings, the same or similar reference numerals can represent the same or similar elements. It should be understood that the drawings are schematic and elements in the drawings are not necessarily to scale.

[0070] Figure 1 A schematic diagram of a processing unit according to the present disclosure;

[0071] Figure 2 A schematic diagram of another processing unit according to the present disclosure;

[0072] Figure 3 A schematic diagram of yet another processing unit according to the present disclosure;

[0073] Figure 4 A schematic diagram of a data processing procedure of a computing unit in a processing unit according to the present disclosure;

[0074] Figure 5 A schematic diagram of yet another processing unit according to the present disclosure;

[0075] Figure 6 A schematic diagram of yet another processing unit according to the present disclosure;

[0076] Figure 7 A schematic diagram of a data transmission path of a first delay module in a processing unit according to the present disclosure;

[0077] Figure 8 A schematic diagram of another data transmission path of a first delay module in a processing unit according to the present disclosure;

[0078] Figure 9 A schematic diagram of a systolic array according to the present disclosure;

[0079] Figure 10 A schematic diagram of another systolic array according to the present disclosure;

[0080] Figure 11 A schematic diagram of yet another systolic array according to the present disclosure;

[0081] Figure 12 A schematic diagram of a partial structure of a systolic array according to the present disclosure;

[0082] Figure 13 A schematic diagram of yet another systolic array according to the present disclosure;

[0083] Figure 14 A schematic diagram of yet another systolic array according to the present disclosure;

[0084] Figures 15-21A schematic diagram of the data input process when a systolic array uses a bidirectional input data matrix of the same dimension in another data processing method provided by the present application;

[0085] Figure 22 is a schematic diagram of simultaneously outputting third data stored in each processing unit in the same row of processing units from the left and right sides of the systolic matrix;

[0086] Figure 23 is a schematic diagram of outputting third data stored in each processing unit in the same row of processing units from one side of a systolic matrix;

[0087] Figure 24 A schematic diagram of the structure of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0088] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0089] It will be apparent to those skilled in the art that various modifications and variations can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the examples of this application can be combined with each other without contradiction.

[0090] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0091] As described in the background technology section, how to improve the operating speed and pipeline operating efficiency in a systolic array has become a research direction for those skilled in the art.

[0092] In view of this, an embodiment of the present application provides a processing unit in a systolic array, such as Figure 1As shown, the processing element PE has a first group of data transmission paths a for transmitting data in a first dimension X, a second group of data transmission paths b for transmitting data in a second dimension Y, and a third group of data transmission paths c for transmitting data in the first dimension X, the first group of data transmission paths a being used for transmitting first data, the second group of data transmission paths b being used for transmitting second data, thereby realizing input of data in a data array, and the third group of data transmission paths c being used for transmitting third data, thereby realizing output of a calculation result in a systolic array. The first dimension X and the second dimension Y are different.

[0093] In the embodiment, the first group of data transmission paths a includes a first data transmission path a1 for transmitting data in a first direction and a second data transmission path a2 for transmitting data in a second direction, and the second group of data transmission paths b includes a third data transmission path b1 for transmitting data in a third direction and a fourth data transmission path b2 for transmitting data in a fourth direction, the first direction being different from the second direction and the third direction being different from the fourth direction, so that the processing element PE can transmit data in two directions in the same dimension, and thus the processing element PE can receive data matrices in two directions in the same dimension at the same time when applied to a systolic array, thereby improving the data input speed of the systolic array and the running speed and pipeline running efficiency of the systolic array. Figure 1

[0094] In the embodiment, the third group of data transmission paths c includes a first data output path c1 for transmitting data in a first direction and a second data output path c2 for transmitting data in a second direction, so that the processing element PE can output calculation results in two directions in the same dimension, thereby improving the data processing result output speed of the systolic array and the running speed and pipeline running efficiency of the systolic array.

[0095] Optionally, in an embodiment of the present application, the first direction and the second direction are opposite, and the third direction and the fourth direction are opposite.

[0096] As shown in FIG. 1, the processing element PE includes a first group of data transmission paths a for transmitting data in a first dimension X, a second group of data transmission paths b for transmitting data in a second dimension Y, and a third group of data transmission paths c for transmitting data in the first dimension X, the first group of data transmission paths a being used for transmitting first data, the second group of data transmission paths b being used for transmitting second data, thereby realizing input of data in a data array, and the third group of data transmission paths c being used for transmitting third data, thereby realizing output of a calculation result in a systolic array. The first dimension X and the second dimension Y are different. Figure 2 and Figure 3 ​As shown in the figure, in one embodiment of the present application, the first group of data transmission paths of the processing unit includes a first selection module 10, which is configured to select the first data transmission path a1 to transmit first data or select the second data transmission path a2 to transmit the first data based on a first selection signal select1, so that the processing unit PE selects only one data transmission path to transmit the first data at the same time in the first dimension, avoiding the disorder of the data processing process of the processing unit PE; the second group of data transmission paths includes a second selection module 20, which is configured to select the third data transmission path b1 to transmit second data or select the fourth data transmission path b2 to transmit the second data based on a second selection signal select2, so that the processing unit PE selects only one data transmission path to transmit the second data at the same time in the second dimension, avoiding the disorder of the data processing process of the processing unit PE.

[0097] Optionally, in one embodiment of the present application, as shown in the figure, Figure 3 The first selection module 10 and the second selection module 20 can be implemented by a MUX selector, when the first selection signal select1 is 1, the first selection module 10 selects the first data transmission path a1 to transmit the first data, when the first selection signal select1 is 0, the first selection module 10 selects the second data transmission path a2 to transmit the first data; when the second selection signal select2 is 1, the second selection module 20 selects the third data transmission path b1 to transmit the second data, when the second selection signal select2 is 0, the second selection module 20 selects the fourth data transmission path b2 to transmit the second data.

[0098] In this embodiment, as shown in the figure, Figure 3 The processing unit PE further includes a data processing module, which includes a calculation unit 30 located on the data transmission paths of the first group of data transmission paths a and the second group of data transmission paths b, configured to process the first data and the second data to generate third data and store the third data.

[0099] In addition, as shown in the figures, Figure 1 And Figure 2 The processing unit 30 is further configured to select the first data output path c1 to output the third data based on the first selection signal select1 or select the second data output path c2 to output the third data based on the first selection signal select1, so as to realize the transmission of the third data.

[0100] Optionally, in one embodiment of the present application, as shown in the figure, Figure 4As shown, when the first selection signal select1 is 0, the processing unit 30 selects the first data output channel c1 to transmit the third data psm; when the first selection signal select1 is 1, the processing unit 30 selects the second data output channel c2 to transmit the third data psm, but the present application is not limited thereto, and the specific selection can be determined according to the actual situation.

[0101] On the basis of the above-mentioned embodiments, in an embodiment of the present application, the processing unit PE continues to select the first data output channel c1 to transmit the third data psm when the first selection signal select1 is 0, and the processing unit PE continues to select the second data output channel c2 to transmit the third data psm when the first selection signal select1 is 1. Figures 1-3 As shown, the first group of data transmission channels a of the processing unit PE includes a first group of input ports located on the first dimension X, the second group of data transmission channels b includes a second group of input ports located on the second dimension Y, and the third group of data transmission channels c includes a third group of input ports located on the first dimension X; wherein the first group of input ports includes a first input port a1i and a second input port a2i, and the first input port a1i and the second input port a2i are used to input the first data; the second group of input ports includes a third input port b1i and a fourth input port b2i, and the third input port b1i and the fourth input port b2i are used to input the second data; and the third group of input ports includes a fifth input port c1i and a sixth input port c2i, and the fifth input port c1i and the sixth input port c2i are used to input the third data.

[0102] Optionally, in an embodiment of the present application, the first group of data transmission channels of the processing unit PE further includes a first group of output ports located on the first dimension, the second group of data transmission channels further includes a second group of output ports located on the second dimension, and the third group of data transmission channels further includes a third group of output ports located on the first dimension; and the processing unit PE continues to select the first group of output ports to output the first data when the first selection signal select1 is 0, and the processing unit PE continues to select the second group of output ports to output the first data when the first selection signal select1 is 1. Figures 2-4As shown, the first group of output ports of the processing unit PE includes a first output port a1o and a second output port a2o, the first output port a1o outputs the first data transmitted in the first data transmission path a1 when the first data is transmitted in the first data transmission path a1, and the second output port a2o outputs the first data transmitted in the second data transmission path a2 when the first data is transmitted in the second data transmission path a2; the second group of output ports includes a third output port b1o and a fourth output port b2o, the third output port b1o outputs the second data transmitted in the third data transmission path b1 when the second data is transmitted in the third data transmission path b1, and the fourth output port b2o outputs the second data transmitted in the fourth data transmission path b2 when the second data is transmitted in the fourth data transmission path b2; the third group of output ports includes a fifth output port c1o and a sixth output port c2o, the fifth output port c1o outputs the third data a1_pusm transmitted in the first data output path c1 when the third data pusm is transmitted in the first data output path c1, and the sixth output port c2o outputs the third data a2_pusm transmitted in the second data output path c2 when the third data pusm is transmitted in the second data output path c2.

[0103] As shown in FIG. 1, the processing unit PE includes a first input port a1i, a second input port a2i, a third input port b1i, a fourth input port b2i, a first output port a1o, a second output port a2o, a third output port b1o, a fourth output port b2o, a fifth output port c1o, and a sixth output port c2o. Figure 3 As shown in FIG. 1, the processing unit PE includes a first input port a1i, a second input port a2i, a third input port b1i, a fourth input port b2i, a first output port a1o, a second output port a2o, a third output port b1o, a fourth output port b2o, a fifth output port c1o, and a sixth output port c2o. Figure 4 As shown in FIG. 1, the processing unit PE includes a first input port a1i, a second input port a2i, a third input port b1i, a fourth input port b2i, a first output port a1o, a second output port a2o, a third output port b1o, a fourth output port b2o, a fifth output port c1o, and a sixth output port c2o.

[0104] In the embodiment, the signal transmission path between the first input port a1i and the first output port a1o is the signal transmission path of the first data transmission path a1, that is, when the first data is transmitted in the first data transmission path a1, the first data is input from the first input port a1i and transmitted along the first data transmission path a1 to be output from the first output port a1o.

[0105] The signal transmission path between the second input port a2i and the second output port a2o is the signal transmission path of the second data transmission path a2, that is, when the second data transmission path a2 transmits the first data, the first data is input from the second input port a2i and transmitted along the second data transmission path a2 to the second output port a2o for output;

[0106] The signal transmission path between the third input port b1i and the third output port b1o is the signal transmission path of the third data transmission path b1, that is, when the third data transmission path b1 transmits the second data, the second data is input from the third input port b1i and transmitted along the third data transmission path b1 to the third output port b1o for output;

[0107] The signal transmission path between the fourth input port b2i and the fourth output port b2o is the signal transmission path of the fourth data transmission path b2, that is, when the fourth data transmission path b2 transmits the second data, the second data is input from the fourth input port b2i and transmitted along the fourth data transmission path b2 to the fourth output port b2o for output;

[0108] The signal transmission path between the fifth input port c1i and the fifth output port c1o is the signal transmission path of the first data output path c1, that is, when the first data output path c1 transmits the third data pusb, the third data a1_pusb is input from the fifth input port c1i and transmitted along the first data output path c1 to the fifth output port c1o for output, and at this time, pusb is a1_pusb;

[0109] The signal transmission path between the sixth input port c2i and the sixth output port c2o is the signal transmission path of the second data output path c2, that is, when the second data output path c2 transmits the third data pusb, the third data a2_pusb is input from the sixth input port c2i and transmitted along the second data output path c2 to the sixth output port c2o for output, and at this time, pusb is a2_pusb.

[0110] On the basis of the above embodiment, in an embodiment of the present application, as shown in Figure 3 The first selection module 10 has two input ends connected to the first input port a1i and the second input port a2i respectively, an output end connected to the first data input end of the calculation unit 30, and a control end for inputting a first selection signal select1. Based on the first selection signal select1, the data input from the first input port a1i or the data input from the second input port a2i is selected. When the first selection signal is 1, the data input from the first input port a1i is input to the first data input end of the calculation unit 30; when the first selection signal is 0, the data input from the second input port a2i is input to the first data input end of the calculation unit 30.

[0111] The two input ends of the second selection module 20 are connected to the third input port b1i and the fourth input port b2i respectively, the output end is connected to the second data input end of the calculation unit 30, and the control end is used for inputting a second selection signal select2; based on the second selection signal select2, whether the data output by the third input port b1i or the data output by the fourth input port b2i is selected, when the second selection signal is 1, the data output by the third input port b1i is input to the second data input end of the calculation unit 30, and when the second selection signal is 0, the data output by the fourth input port b2i is input to the second data input end of the calculation unit 30;

[0112] As shown in the continuation of Figure 4 The third group of input ports is connected to the third data input end of the calculation unit 30, and the first selection signal input end of the processing unit 30 inputs a first selection signal select1, that is, the fifth input port c1i and the sixth input port c2i are connected to the third data input end of the calculation unit 30, so that the processing unit selects the third data a1_pusm input by the fifth input port c1i or the third data a2_pusm input by the sixth input port c2i based on the first selection signal select1.

[0113] Optionally, in an embodiment of the present application, as shown in Figure 5 The processing unit further comprises:

[0114] A first selection signal generation module 40 is configured to generate a corresponding first selection signal select1 based on at least the signal input states of the two input ends of the first selection module 10; the selection signal output end of the first selection signal generation module 40 is connected to the control end of the first selection module 10 and the first selection signal input end of the calculation unit 30, so as to generate a corresponding first selection signal select1 based on the signal input states of the two input ends of the first selection module 10 and output the first selection signal select1 to the control end of the first selection module and the first selection signal input end of the calculation unit 30;

[0115] A second selection signal generation module 44 is configured to generate a corresponding second selection signal select2 based on at least the signal input states of the two input ends of the second selection module 20; the selection signal output end of the second selection signal generation module 40 is connected to the control end of the second selection module 20, so as to generate a corresponding second selection signal select2 based on the signal input states of the two input ends of the second selection module 20 and output the second selection signal select2 to the control end of the second selection module.

[0116] Specifically, in the embodiment, the first selection signal generation module 40 is configured to generate a first sub-selection signal, such as select1 being 1, when the first input port a1i first receives the first data, so that the first selection module 10 selects the first data transmission path a1 to transmit the first data, and the third data input end of the calculation unit 30 selects to input the third data a2_psum transmitted by the second data output path c2.

[0117] The first selection signal generation module 40 is further configured to generate the first sub-selection signal or a second sub-selection signal based on the signal input states of the two input ends of the first selection module of other processing units when the second input port a2i first receives the first data, and the first selection signal generation module outputs the second sub-selection signal, such as select1 being 0, so that the first selection module 10 selects the second data transmission path a2 to transmit the first data, and the third data input end of the calculation unit 30 selects to input the third data a1_psum transmitted by the first data output path c1.

[0118] The second selection signal generation module 44 is configured to generate a third sub-selection signal, such as select2 being 1, when the third input port b1i first receives the second data, so that the second selection module 20 selects the third data transmission path b1 to transmit the second data.

[0119] The second selection signal generation module 44 is further configured to generate the third sub-selection signal or a fourth sub-selection signal based on the signal input states of the two input ends of the second selection module of other processing units when the fourth input port b2i first receives the second data, and the second selection signal generation module outputs the fourth sub-selection signal, such as select2 being 0, so that the second selection module 20 selects the fourth data transmission path b2 to transmit the second data.

[0120] As can be seen from the above description, in the embodiment, the processing unit includes two data transmission channels in different directions in the same dimension. When the first data and the second data are input, the first data transmitted by the first data transmission path and the second data transmitted by the third data transmission path can be selected, the first data transmitted by the second data transmission path and the second data transmitted by the fourth data transmission path can be selected, the first data transmitted by the first data transmission path and the second data transmitted by the fourth data transmission path can be selected, and the first data transmitted by the second data transmission path and the second data transmitted by the third data transmission path can be selected. Specifically, the first input port a1i and the third input port b1i receive valid data first, or the second input port a2i and the fourth input port b2i receive valid data first. If the first input port a1i and the second input port a2i receive valid data at the same time, the processing unit can select the first data input by the first input port a1i or the first data input by the second input port a2i at will. Similarly, if the third input port b1i and the fourth input port b2i receive valid data at the same time, the processing unit can select the second data input by the third input port b1i or the second data input by the fourth input port b2i at will or based on a default configuration.

[0121] In addition, the processing unit also includes two data output channels in different directions in the same dimension. When the third data is output, the third data transmitted by the first data output path or the third data transmitted by the second data output path can be selected. Specifically, the fifth input port c1i receives valid data first, or the sixth input port c2i receives valid data first. If the fifth input port c1i and the sixth input port c2i receive valid data at the same time, the processing unit can select the third data input by the fifth input port c1i or the third data input by the sixth input port c2i at will or based on a default configuration.

[0122] Optionally, in an embodiment of the present application, as shown in Figure 5 The first selection signal generation module 40 includes:

[0123] A first logic element 41, the first logic element 41 has a seventh input port, an eighth input port and a seventh output port, the seventh input port inputs a first signal a1_pre, and the eighth input port inputs a second signal a2_pre.

[0124] The first flip-flop module 42 comprises a ninth input port D1, a tenth input port D2 and an eighth output port Q2, the ninth input port D1 is connected with the seventh output port of the first logic element 41, the tenth input port D2 is connected with the seventh input port of the first logic element 41;

[0125] The second logic element 43 has an eleventh input port, a twelfth input port and a ninth output port, wherein the eleventh input port is connected with the eighth output port of the first flip-flop module of the processing unit, the twelfth input port is connected with the eighth output port of the first flip-flop module in other processing units, and the ninth output port is an output port of the first selection signal generation module, outputting a first selection signal.

[0126] On the basis of the above embodiment, in one embodiment of the present application, when the first signal a1_pre inputted by the seventh input port of the first logic element 41 is a valid signal, the eighth output port Q2 outputs a fourth selection signal, for example, the fourth selection signal select01 is 1, and the first selection signal select1 outputted by the second logic element 43 is 1; when the second signal a2_pre inputted by the eighth input port of the first logic element 41 is a valid signal, the eighth output port Q2 outputs the fourth selection signal, for example, the fourth selection signal select01 is 0, and the second logic element 43 outputs the first selection signal based on the fourth selection signal outputted by the eighth output port of the first flip-flop module in other processing units, at this time, if the fourth selection signal outputted by the eighth output port of the first flip-flop module in other processing units is 1, the first selection signal outputted by the first selection signal generation module is 1, and if the fourth selection signal outputted by the eighth output port of the first flip-flop module in other processing units is also 0, the first selection signal outputted by the first selection signal generation module is 0. Wherein, the first signal a1_pre represents that the first input port a1i of the first data transmission path a1 inputs the first data, and the second signal a2_pre represents that the second input port a2i of the second data transmission path a2 inputs the first data.

[0127] Specifically, in one embodiment of the present application, the first trigger module 42 comprises a first trigger unit 421 and a second trigger unit 422, wherein the first trigger unit 421 comprises a D1 input end, an E1 input end, a Q1 output end and a Qn1 output end, and the second trigger unit 422 comprises a D2 input end, an E2 input end, a Q2 output end and a Qn2 output end; wherein the D1 input end of the first trigger unit 421 is the ninth input port of the first trigger module, the E1 input end is connected with the Qn1 output end, the Qn1 output end is connected with the E2 input end of the second trigger unit 422, the D2 input end of the second trigger unit 422 is connected with the seventh input port of the first logic element 41, and the Q2 output end is the eighth output port of the first trigger module for outputting a fourth selection signal select01.

[0128] It should be noted that in the above embodiment, the first trigger unit 421 further has a first reset end RST1 for inputting a reset signal, and the second trigger unit 422 has a second reset end RST2 for inputting a reset signal, and before the start of the operation of the systolic array, the first reset end and the second reset end input the reset signal, so that E1 is 1 and E2 is 1. It should be noted that if E1 is 1, the signal inputted by the D1 input end can be delayed for one period from the Q1 output, and similarly, if E2 is 1, the signal inputted by the D2 input end can be delayed for one period from the Q2 output; if E1 is 0, the signal inputted by the D1 input end is not transmitted to Q1, and similarly, if E2 is 0, the signal inputted by the D2 input end is not transmitted to Q2; when Q1 is 1, Qn1 is 0, and when Q1 is 0, Qn1 is 1, and similarly, when Q2 is 1, Qn2 is 0, and when Q2 is 0, Qn2 is 1.

[0129] Optionally, in one embodiment of the present application, the first logic element is an OR gate, and the second logic element is an OR gate. In this embodiment, the working process of the first selection generation module comprises:

[0130] In the initial state, E1 is 1 and E2 is 1. If a1_pre is 1 and a2_pre is 0, the first logic element 41 outputs 1, D1 is 1, and D2 is 1. In the next period, Q1 is 1, Q2 is 1, Qn1 is 0, and E2 is 0. Q2 keeps outputting 1, the second logic element 43 keeps outputting 1, and the first selection module 10 selects the signal inputted by the first input port a1i. At the same time, the second trigger unit 422 saves the value of a1_pre (i.e. the output signal of the logic element) until the next reset signal arrives.

[0131] In the initial state, E1 is 1, E2 is 1, if a1_pre is 0 and a2_pre is 1, the first logic element 41 outputs 1, D1 is 1, D2 is 0, in the next cycle, Q1 is 1, Q2 is 0, Qn1 is 0, E2 is 0, Q2 keeps outputting 0, at this time, if the fourth selection signal select_o1 from other processing units is also 0, the second logic element 43 outputs 0, the first selection module 10 selects the signal input into the second input port a2i, at the same time, the second flip-flop unit 422 will save the value of a1_pre (i.e. the output signal of the first logic element) until the next reset signal arrives, if the fourth selection signal select_o1 from other processing units is 1, the second logic element 43 outputs 1, the first selection module 10 selects the signal input into the first input port a1i, at the same time, the second flip-flop unit 422 will save the value of a1_pre (i.e. the output signal of the first logic element) until the next reset signal arrives.

[0132] If a1_pre is 1 and a2_pre is 1, the first logic element 41 outputs 1, D1 is 1, D2 is 1, in the next cycle, Q1 is 1, Q2 is 1, Qn1 is 0, E2 is 0, Q2 keeps outputting 1, the second logic element 43 keeps outputting 1, the first selection module 10 selects the signal input into the first input port a1i, at the same time, the second flip-flop unit 422 will save the value of a1_pre (i.e. the output signal of the first logic element) until the next reset signal arrives.

[0133] It should be noted that in the above embodiment, the output signal a_pre of the first logic element can also be output to the downstream processing unit of the processing unit, to inform the downstream processing unit that the data in the processing unit is valid data.

[0134] Continuing as shown in Figure 5 The second selection signal generation module 44 includes:

[0135] A third logic element 45, the third logic element 45 has a thirteenth input port, a fourteenth input port and a tenth output port, the thirteenth input port inputs a third signal b1_pre, the fourteenth input port inputs a fourth signal b2_pre;

[0136] A second flip-flop module 46, the second flip-flop module 46 includes a fifteenth input port D5, a sixteenth input port D6 and an eleventh output port Q6, the fifteenth input port D5 is connected with the tenth output port of the third logic element 45, the sixteenth input port D6 is connected with the thirteenth input port of the third logic element 45;

[0137] The fourth logic element 47 has a seventeenth input port, an eighteenth input port and a twelfth output port, wherein the seventeenth input port is connected with the eleventh output port of the second trigger module of the processing unit, the eighteenth input port is connected with the eleventh output port of the second trigger module of the other processing unit, and the twelfth output port is an output port of the second selection signal generation module and outputs the second selection signal.

[0138] In one embodiment of the present application, based on the above-mentioned embodiments, when the third signal b1_pre inputted into the thirteenth input port of the third logic element 45 is a valid signal, the eleventh output port Q6 outputs the fifth selection signal, for example, the fifth selection signal select02 is 1, and the second selection signal select2 outputted by the fourth logic element 47 is 1; when the fourth signal b2_pre inputted into the fourteenth input port of the third logic element 45 is a valid signal, the eleventh output port Q6 outputs the fifth selection signal, for example, the fifth selection signal select02 is 0, and the second selection signal outputted by the fourth logic element 47 is based on the fifth selection signal outputted by the eleventh output port of the second trigger module of the other processing unit; at this time, if the fifth selection signal outputted by the eleventh output port of the second trigger module of the other processing unit is 1, the second selection signal outputted by the second selection signal generation module is 1, and if the fifth selection signal outputted by the eleventh output port of the second trigger module of the other processing unit is also 0, the second selection signal outputted by the second selection signal generation module is 0. Wherein, the third signal b1_pre represents that the third input port b1i of the third data transmission path b1 inputs the second data, and the fourth signal b2_pre represents that the fourth input port b2i of the fourth data transmission path b2 inputs the second data.

[0139] Specifically, in one embodiment of the present application, the second trigger module 46 includes a fifth trigger unit 461 and a sixth trigger unit 462, wherein the fifth trigger unit 461 includes a D5 input port, an E5 input port, a Q5 output port and a Qn5 output port, and the sixth trigger unit 462 includes a D6 input port, an E6 input port, a Q6 output port and a Qn6 output port; wherein the D5 input port of the fifth trigger unit 461 is the fifteenth input port of the second trigger module, the E5 input port is connected with the Qn5 output port, the Qn5 output port is connected with the E6 input port of the sixth trigger unit 462, the D6 input port of the sixth trigger unit 462 is connected with the thirteenth input port of the third logic element 45, and the Q6 output port is the eleventh output port of the second trigger module and is used for outputting the fifth selection signal select02.

[0140] It should be noted that in the above embodiment, the fifth flip-flop unit 461 further has a fifth reset end RST5 for inputting a reset signal, and the sixth flip-flop unit 462 has a sixth reset end RST6 for inputting a reset signal. Before the systolic array starts to work, the fifth reset end and the sixth reset end input the reset signal, so that E5 is 1 and E6 is 1. It should be noted that if E5 is 1, the signal inputted by the D5 input end can be delayed for one cycle to be outputted from Q5, and similarly, if E6 is 1, the signal inputted by the D6 input end can be delayed for one cycle to be outputted from Q6. If E5 is 0, the signal inputted by the D5 input end is not transmitted to Q5, and similarly, if E6 is 0, the signal inputted by the D6 input end is not transmitted to Q6. When Q5 is 1, Qn5 is 0, and when Q5 is 0, Qn5 is 1. Similarly, when Q6 is 1, Qn6 is 0, and when Q6 is 0, Qn6 is 1.

[0141] Optionally, in an embodiment of the present application, the third logic element is an OR gate, and the fourth logic element is an OR gate. In this embodiment, the working process of the second selection generation module includes:

[0142] In the initial state, E5 is 1 and E6 is 1. If b1_pre is 1 and b2_pre is 0, the third logic element 45 outputs 1, D5 is 1, and D6 is 1. In the next cycle, Q5 is 1, Q6 is 1, Qn5 is 0, and E6 is 0. Q6 keeps outputting 1, and the fourth logic element 47 keeps outputting 1. The second selection module 20 selects the signal inputted by the third input port b1i until the next reset signal arrives.

[0143] In the initial state, E5 is 1 and E6 is 1. If b1_pre is 0 and b2_pre is 1, the third logic element 45 outputs 1, D5 is 1, and D6 is 0. In the next cycle, Q5 is 1, Q6 is 0, Qn5 is 0, and E6 is 0. Q6 keeps outputting 0. At this time, if the fifth selection signal select_o2 from other processing units is also 0, the fourth logic element 47 outputs 0, the second selection module 20 selects the signal inputted by the fourth input port b2i. Meanwhile, the sixth flip-flop unit 462 saves the value of b1_pre (i.e. the output signal of the third logic element) until the next reset signal arrives. If the selection signal select_o2 from other processing units is 1, the fourth logic element 47 outputs 1, the second selection module 20 selects the signal inputted by the third input port b1i. Meanwhile, the sixth flip-flop unit 462 saves the value of b1_pre (i.e. the output signal of the third logic element) until the next reset signal arrives.

[0144] If b1_pre is 1 and b2_pre is 1, the third logic element 45 outputs 1, D5 is 1, D6 is 1, in the next cycle, Q5 is 1, Q6 is 1, Qn5 is 0, E6 is 0, Q6 keeps outputting 1, the fourth logic element 47 keeps outputting 1, the second selection module 20 selects the signal inputted into the third input port b1i, at the same time, the sixth flip-flop unit 462 will save the value of b1_pre (i.e. the output signal of the third logic element) until the next reset signal arrives.

[0145] In another embodiment of the present application, the processing unit can also not include the first selection signal generating module and the second selection signal generating module, but in addition to the first selection module 10, the second selection module 20 and the calculation unit 30, it also includes a fifth logic element 50 and a sixth logic element 60, as shown in Figure 2 and Figure 3 The processing unit does not generate the first selection signal and the second selection signal, but receives the first selection signal and the second selection signal outputted by the processing unit upstream; as shown in Figure 3 In the data input stage, the processing unit will select the first data inputted into the first input port a1i or the first data inputted into the second input port a2i according to the inputted first selection signal select1 signal, and select the second data inputted into the third input port b1i or the second data inputted into the fourth input port b2i according to the inputted second selection signal select2 signal, at the same time, the corresponding first signal a1_pre and the second signal a2_pre are ORed and outputted as the new a_pre value, which is transmitted to the processing unit downstream, and the corresponding third signal b1_pre and the fourth signal b2_pre are ORed and outputted as the new b_pre value, which is transmitted to the processing unit downstream; at the same time, in the data output stage, the processing unit will select the third data inputted into the fifth input port c1i or the third data inputted into the sixth input port c2i according to the inputted first selection signal select1 signal.

[0146] Optionally, in an embodiment of the present application, as shown in Figure 6As shown, the first data transmission path a1 includes three signal transmission paths, respectively transmitting the first data a1_data, the first valid signal a1_valid representing the validity of the first data, and the first end signal a1_last representing whether the first data a1_data is the last data in the first data matrix; the second data transmission path a2 includes three signal transmission paths, respectively transmitting the first data a2_data, the second valid signal a2_valid representing the validity of the second data, and the second end signal a2_last representing whether the first data is the last data in the first data matrix. For example, a1_valid is 1 and a2_valid is 0, representing that the first data a1_data transmitted by the first data transmission path is valid data and the first end signal a1_last is a valid signal; a1_valid is 0 and a2_valid is 1, representing that the first data a2_data transmitted by the second data transmission path is valid data and the second end signal a2_last is a valid signal.

[0147] Similarly, continue as Figure 6 As shown, the third data transmission path b1 includes three signal transmission paths, respectively transmitting the third data b1_data, the third valid signal b1_valid representing the validity of the third data, and the third end signal b1_last representing whether the third data b1_data is the last data in the third data matrix; the fourth data transmission path b2 includes three signal transmission paths, respectively transmitting the third data b2_data, the fourth valid signal b2_valid representing the validity of the fourth data, and the fourth end signal b2_last representing whether the third data is the last data in the third data matrix. For example, b1_valid is 1 and b2_valid is 0, representing that the third data b1_data transmitted by the third data transmission path is valid data and the third end signal b1_last is a valid signal; b1_valid is 0 and b2_valid is 1, representing that the third data b2_data transmitted by the fourth data transmission path is valid data and the fourth end signal b2_last is a valid signal.

[0148] As can be seen from the foregoing, since the Q2 output terminal of the second flip-flop unit outputs the fourth selection signal select01 one period later than the time when the signal is input to the D2 input terminal, the first selection signal generation module outputs the first selection signal one period later than the time when the signal is input to the input terminal of the first logic element. If the two input terminals of the first logic element directly input a1_valid and a2_valid, the control terminal of the first selection module will input the first selection signal one period later than the time when the signal is input to the two input terminals of the first selection module.

[0149] Since the time when the Q6 output terminal of the sixth flip-flop unit outputs the fifth selection signal select02 is one period later than the time when the D6 input terminal inputs the signal, the time when the second selection signal generation module outputs the second selection signal is one period later than the time when the input terminal of the third logic element inputs the signal. If the two input terminals of the third logic element directly input b1_valid and b2_valid, the time when the control terminal of the second selection module inputs the second selection signal is one period later than the time when the two input terminals of the second selection module input the signals.

[0150] Therefore, on the basis of the above embodiment, in an embodiment of the present application, the processing unit further comprises:

[0151] a first delay module, two input terminals of the first delay module are connected to the first input port and the second input port respectively, and two output terminals are connected to two input terminals of the first selection module respectively, for outputting the first data to the first selection module after one period, so that the signals inputted by the two input terminals of the first selection module and the first selection signal inputted by the control terminal of the first selection module are inputted into the first selection module at the same time; two input terminals of the first selection generation module are connected to two input terminals of the first delay module respectively;

[0152] a second delay module, two input terminals of the second delay module are connected to the third input port and the fourth input port respectively, and two output terminals are connected to two input terminals of the second selection module respectively, for outputting the second data to the second selection module after one period, so that the signals inputted by the two input terminals of the second selection module and the second selection signal inputted by the control terminal of the second selection module are inputted into the second selection module at the same time. It should be noted that in the above embodiment, two input terminals of the second selection generation module are connected to two input terminals of the second delay module respectively.

[0153] Optionally, in an embodiment of the present application, the first delay module and the second delay module can be realized by registers, but the present application does not make any limitation thereto, and the specific implementation is determined according to the situation.

[0154] Next, the working principle of the first delay module is described by taking an example that two input terminals of the first selection generation module are connected to two input terminals of the first delay module.

[0155] Specifically, as Figure 7As shown, the first valid signal a1_valid0 indicating whether the first data a1_data0 is valid is directly input as the first signal a1_pre to the seventh input port of the first logic element 41, i.e., an input port of the first selection generation module 40; the first valid signal a1_valid0 indicating whether the first data a1_data0 is valid, the first data a1_data0, and the first end signal a1_last indicating whether the first data is the last data in the first data matrix are input to the input port of the first delay module REG1, and after being delayed by one cycle by the first delay module REG1, are output to the first input port a1i of the first selection module 10, so that the first data a1_data, the first valid signal a1_valid, the first end signal a1_last, and the first selection signal input to the control port of the first selection module 10 are simultaneously input to the first selection module 10;

[0156] Similarly, if Figure 8 As shown, the second valid signal a2_valid0 indicating whether the first data a2_data0 is valid is directly input as the second signal a2_pre to the eighth input port of the first logic element 41, i.e., another input terminal of the first selection generation module 40; the second valid signal a2_valid0 indicating whether the first data a2_data0 is valid, the first data a2_data0, and the second end signal a2_last indicating whether the first data is the last data in the first data matrix are input to the input terminal of the first delay module REG1, and after being delayed for one cycle by the first delay module REG1, are output to the second input port a2i of the first selection module 10, so that the first data a2_data in the second input port a2i of the first selection module 10, the first valid signal a2_valid indicating that the first data a2_data is valid, the first end signal a1_last, and the first selection signal input to its control terminal are simultaneously input to the first selection module 10.

[0157] Since the working principle of the second delay module is the same as that of the first delay module, this application will not elaborate on it.

[0158] Optionally, in the above embodiments, the first delay module can realize the delay of the data input by the first input port and the delay of the data input by the second input port through different delay units (such as registers), or realize the delay of the data input by the first input port and the delay of the data input by the second input port through the same delay unit (such as a register); similarly, the second delay module can realize the delay of the data input by the third input port and the delay of the data input by the fourth input port through different delay units (such as registers), or realize the delay of the data input by the third input port and the delay of the data input by the fourth input port through the same delay unit (such as a register), which is not limited in the present application, and is determined according to the specific situation.

[0159] In the above embodiment, taking the calculation unit for realizing convolution operation as an example, as shown in Figure 4 , the calculation unit 30 includes:

[0160] The first processing unit 31 is configured to process the first data a input by the first data input end and the second data b input by the second data input end to generate third data;

[0161] The second processing unit 32 is configured to select and output the first data output path transmission, the third data input by the third data input end, or select and output the second data output path transmission, the third data input by the third data input end based on the first selection signal select1.

[0162] The third processing unit 33 is configured to select and output the third data output by the first processing unit, or select and output the third data output by the second processing unit based on the third selection signal select3.

[0163] The fourth processing unit 34 is configured to select and store the third data output by the first processing unit and output to the first processing unit, or select and output the third data output by the second processing unit based on the third selection signal select3.

[0164] Specifically, in an embodiment of the present application, when the third selection signal is 0, the calculation unit 30 performs convolution operation (corresponding to mul in Figure 4 ) on the first data a output by the first selection module 10 and the second data b output by the second selection module 20, and performs accumulation calculation (corresponding to acc in Figure 4 ) on the third data stored in the last period to obtain the third data at the current time, stores (corresponding to psum reg in Figure 4 ) the third data at the current time and outputs (corresponding to out in Figure 4The first data a outputted by the first selection module 10 is outputted through the first output port a1o and the second output port a2o in the next cycle after passing through a delay unit reg (such as the third delay unit 36), so as to realize the processing of the first data and the second data. Optionally, the third delay unit and the fourth delay unit can be realized by registers, which are not limited in the present application and can be determined according to actual conditions.

[0165] When the third selection signal is 1, the second processing unit 32 selects and outputs the third data a1_psum inputted by the fifth input port c1i based on the first selection signal select1, or selects and outputs the third data a2_psum inputted by the sixth input port c2i, the third processing unit 33 selects and outputs the third data outputted by the second processing unit 32, and the fourth processing unit 34 stores and outputs the third data outputted by the third processing unit 33 through the fifth output port c1o and the sixth output port c2o, so as to realize the output of the third data.

[0166] It should be noted that, in the embodiment, the fifth input port of the processing unit is connected with the fifth output port of the processing unit upstream, and the sixth input port is connected with the sixth output port upstream; the fifth output port of the processing unit is connected with the fifth input port of the processing unit downstream, and the sixth output port is connected with the sixth input port downstream.

[0167] On the basis of any of the above embodiments, in an embodiment of the present application, the first data a outputted by the first selection module 10 is outputted through the first output port a1o and the second output port a2o in the next cycle after passing through a delay unit reg (such as the third delay unit 36), so as to realize the processing of the first data and the second data. Optionally, the third delay unit and the fourth delay unit can be realized by registers, which are not limited in the present application and can be determined according to actual conditions. Figure 4 The calculation unit further comprises:

[0168] The output signal generation module 35 is configured to generate a third selection signal based on an end signal a-last transmitted by the first data transmission path and / or the second data transmission path, and an output end of the output signal generation module is connected to a selection signal input end of the third processing unit, and the third processing unit outputs the third data inputted by the third group of input ports based on the third selection signal.

[0169] The end signal represents that the data processing task of the processing unit in the systolic array has ended.

[0170] Optionally, in an embodiment of the present application, the output signal generating module 35 comprises a third flip-flop unit 351 and a fourth flip-flop unit 352, wherein the third flip-flop unit 351 comprises a D3 input end, an E3 input end, a Q3 output end and a Qn3 output end, and the fourth flip-flop unit 352 comprises a D4 input end, an E4 input end, a Q4 output end and a Qn4 output end; wherein the D3 input end of the third flip-flop unit 351 and the D4 input end of the fourth flip-flop unit 352 are input ends of the output signal generating module 35, the Q4 output end of the fourth flip-flop unit 352 is an output end of the output signal generating module 35, the E3 input end of the third flip-flop unit 351 is connected with the Qn3 output end thereof, and the Qn3 output end of the third flip-flop unit 351 is further connected with the E4 input end of the fourth flip-flop unit 352.

[0171] In the initial state, when E3 is 1, E4 is 1, and the end signal a_last is 1, D3 is 1 and D4 is 1 in the next cycle, Q3 is 1, Q4 is 1, Qn3 is 0, Qn4 is 0, E3 becomes 0, E4 becomes 0, and Q4 keeps outputting 1, i.e., the Q4 output end of the fourth flip-flop unit keeps outputting 1, at the same time, the fourth flip-flop unit 352 keeps the value of a_last until the next reset signal arrives.

[0172] In the initial state, when E3 is 1, E4 is 1, and the end signal a_last is 0, in the next cycle, Q3 is 0, Q4 is 0, Qn3 is 1, Qn4 is 1, E4 is 1, and Q4 keeps outputting the input signal of D4, at this time, the Q4 output end of the fourth flip-flop unit keeps outputting 0 until the end signal a_last becomes 1.

[0173] In the embodiment, when the end signal a_last is pulled high, i.e., a_last becomes 1, it indicates that the matrix operation is completed, and data output can be performed.

[0174] It should be noted that, in the embodiment, the third flip-flop unit and the fourth flip-flop unit constitute a flip-flop module, and since the working principle of the first flip-flop module composed of the first flip-flop unit and the second flip-flop unit is the same, the present application will not be described again.

[0175] Correspondingly, the present application further provides a systolic array, as shown in Figure 9As shown, the systolic array includes 2n×2n processing units PE (including a first processing unit PE_1 and a second processing unit PE_2), n is greater than 1, the processing unit PE has a first group of data transmission paths a for transmitting data in a first dimension X, a second group of data transmission paths b for transmitting data in a second dimension Y, and a third group of data transmission paths c for transmitting data in the first dimension X, the first group of data transmission paths a is used for transmitting first data, the second group of data transmission paths b is used for transmitting second data, thereby realizing the input of data in the data array, and the third group of data transmission paths c is used for transmitting third data, thereby realizing the output of the calculation result in the systolic array. Wherein, the first dimension X and the second dimension Y are different.

[0176] In this embodiment, continue as Figure 9 As shown, the first group of data transmission paths a includes a first data transmission path a1 for transmitting data in a first direction and a second data transmission path a2 for transmitting data in a second direction; the second group of data transmission paths includes a third data transmission path b1 for transmitting data in a third direction and a fourth data transmission path b2 for transmitting data in a fourth direction, wherein the first direction and the second direction are different, and the third direction and the fourth direction are different, so that the processing unit PE can transmit data in two directions in the same dimension, and further so that the systolic array can receive data matrices in two directions in the same dimension at the same time, thereby improving the data input speed of the systolic array, and thereby improving the running speed and pipeline running efficiency of the systolic array.

[0177] Moreover, in this embodiment, the third group of data transmission paths c includes a first data output path c1 for transmitting data in a first direction and a second data output path c2 for transmitting data in a second direction, so that the processing unit PE can output calculation results in two directions in the same dimension, thereby improving the data processing result output speed of the systolic array, and improving the running speed and pipeline running efficiency of the systolic array.

[0178] Optionally, in an embodiment of the present application, the first direction and the second direction are opposite, and the third direction and the fourth direction are opposite.

[0179] Optionally, in an embodiment of the present application, continue as Figure 9 As shown, the systolic array includes four systolic matrices M arranged in a matrix, the first systolic matrix M1 includes processing units located in 1~n rows and 1~n columns, the second systolic matrix M2 includes processing units located in 1~n rows and (n+1)~2n columns, the third systolic matrix M3 includes processing units located in (n+1)~2n rows and 1~n columns, and the fourth systolic matrix M4 includes processing units located in (n+1)~2n rows and (n+1)~2n columns; specifically,

[0180] The processing unit located at the first row and the first column is the first processing unit PE_1 in the first systolic matrix M1, the processing unit located at the first row and the (n+1)th column and the processing unit located at the first row and the 2nth column are the first processing units PE_1 in the second systolic matrix M2, the processing unit located at the (n+1)th row and the first column and the processing unit located at the 2nth row and the first column are the first processing units PE_1 in the third systolic matrix M3, the processing unit located at the (n+1)th row and the (n+1)th column and the processing unit located at the 2nth row and the 2nth column are the first processing units PE_1 in the fourth systolic matrix M4, and the remaining processing units are the second processing units PE_2.

[0181] In the embodiment, the first processing unit generates a first selection signal based on the input state of the data input port of the first group of data transmission paths thereof and the input state of the data input port of the first group of data transmission paths of other first processing units located in the same systolic matrix, and selects the first data transmitted in the first group of data transmission paths to be input based on the first selection signal and outputs the first data to the downstream processing unit through the first group of data transmission paths, and selects the third data transmitted in the third group of data transmission paths to be input and transmits the third data to the downstream processing unit through the third group of data transmission paths;

[0182] The first processing unit also generates a second selection signal based on the input state of the data input port of the second group of data transmission paths thereof and the input state of the data input port of the second group of data transmission paths of other first processing units located in the same systolic matrix, and selects the second data transmitted in the second group of data transmission paths to be input based on the second selection signal and outputs the second data to the downstream processing unit through the second group of data transmission paths.

[0183] The second processing unit selects the first data transmitted in the first group of data transmission paths to be input based on the first selection signal output by the first processing unit located in the same systolic matrix, and outputs the first data to the downstream processing unit through the first group of data transmission paths, and selects the third data transmitted in the third group of data transmission paths to be input and transmits the third data to the downstream processing unit through the third group of data transmission paths; the second processing unit also selects the second data transmitted in the second group of data transmission paths to be input based on the second selection signal output by the first processing unit located in the same systolic matrix, and outputs the second data to the downstream processing unit through the second group of data transmission paths.

[0184] Specifically, the first processing element PE_1 in the first systolic matrix M1 generates a first selection signal select1 based on the input state of the data input port of its first group of data transmission paths a, and generates a second selection signal select2 based on the input state of the data input port of its second group of data transmission paths b, such as the first selection signal is a first sub-selection signal, and the second selection signal is a third sub-selection signal, and selects the first data input from the first data transmission path a1 and the second data input from the third data transmission path b1 based on the first selection signal select1 and the second selection signal select2, and outputs to the downstream processing element through the first group of data transmission paths a and the second group of data transmission paths b; the second processing element PE_2 receives the data output from the processing element at the upstream node of the first systolic matrix M1, and selects the first data input from the first data transmission path a1 and the second data input from the third data transmission path b1 based on the first selection signal select1 and the second selection signal select2 output from the upstream processing element, and outputs to the downstream processing element through the first group of data transmission paths a and the second group of data transmission paths b;

[0185] Or,

[0186] The first processing element PE_1 in the first systolic matrix M1 generates a first selection signal select1 based on the input state of the data input port of its first group of data transmission paths a, and generates a second selection signal select2 based on the input state of the data input port of its second group of data transmission paths b, such as the first selection signal is a second sub-selection signal, and the second selection signal is a fourth sub-selection signal, and selects the first data input from the second data transmission path a2 and the second data input from the fourth data transmission path b2 based on the first selection signal select1 and the second selection signal, and outputs to the downstream processing element through the first group of data transmission paths a and the second group of data transmission paths b; the second processing element PE_2 receives the data output from the processing element at the upstream node of the first systolic matrix, and selects the first data input from the second data transmission path a2 and the second data input from the fourth data transmission path b2 based on the first selection signal select1 and the second selection signal select2 output from the upstream processing element, and outputs to the downstream processing element through the first group of data transmission paths a and the second group of data transmission paths b;

[0187] Or,

[0188] The first processing element PE_1 in the first systolic matrix M1 generates a first selection signal select1 based on the input state of the data input port of its first set of data transmission paths a, and a second selection signal select2 based on the input state of the data input port of its second set of data transmission paths b, like the first selection signal is the first sub-selection signal, and the second selection signal is the fourth sub-selection signal, and selects the first data transmitted by the first data transmission path a1 based on the first selection signal select1 and the second data transmitted by the fourth data transmission path b2 based on the second selection signal, and outputs to the downstream processing element through the first set of data transmission paths a and the second set of data transmission paths b; the second processing element PE_2 is configured to receive the data output by the processing element in the first systolic matrix located at its upstream node, and select the first data transmitted by the first data transmission path a2 based on the first selection signal select1 and the second selection signal select2 accepted from the upstream processing element output, and the second data transmitted by the fourth data transmission path b2, and output to the downstream processing element through the first set of data transmission paths a and the second set of data transmission paths b.

[0189] Or,

[0190] The first processing element PE_1 in the first systolic matrix M1 generates a first selection signal select1 based on the input state of the data input port of its first set of data transmission paths a, and a second selection signal select2 based on the input state of the data input port of its second set of data transmission paths b, like the first selection signal is the second sub-selection signal, and the second selection signal is the third sub-selection signal, and selects the first data transmitted by the second data transmission path a2 based on the first selection signal select1 and the second data transmitted by the third data transmission path b1 based on the second selection signal, and outputs to the downstream processing element through the first set of data transmission paths a and the second set of data transmission paths b; the second processing element PE_2 is configured to receive the data output by the processing element in the first systolic matrix located at its upstream node, and select the first data transmitted by the second data transmission path a2 based on the first selection signal select1 and the second selection signal select2 accepted from the upstream processing element output, and the second data transmitted by the third data transmission path b2, and output to the downstream processing element through the first set of data transmission paths a and the second set of data transmission paths b.

[0191] The first processing unit PE_1 generates a first selection signal select1 based on the input state of the data input port of the first group data transmission path a thereof and the input state of the data input port of the first group data transmission path a of other first processing units PE_1 located in the same systolic matrix, and generates a second selection signal select2 based on the input state of the data input port of the second group data transmission path b thereof and the input state of the data input port of the second group data transmission path b of other first processing units PE_1 located in the same systolic matrix, wherein the first selection signal is a first sub-selection signal and the second selection signal is a third sub-selection signal, and selects the first data transmitted by the first data transmission path a1 and the second data transmitted by the third data transmission path b1 to be input based on the first selection signal select1 and the second selection signal select2, and outputs the selected first data and second data to the downstream processing unit through the first group data transmission path a and the second group data transmission path b; the second processing unit PE_2 receives the data output by the processing unit located at the upstream node thereof in the same systolic matrix, and selects the first data transmitted by the first data transmission path a1 and the second data transmitted by the third data transmission path b1 to be input based on the first selection signal select1 and the second selection signal select2 accepted from the upstream processing unit, and outputs the selected first data and second data to the downstream processing unit through the first group data transmission path a and the second group data transmission path b;

[0192] Or, among the second systolic matrix M2, the third systolic matrix M3 and the fourth systolic matrix M4, the first processing unit PE_1 generates a first selection signal select1 based on the input state of the data input port of the first group data transmission path a of the first processing unit PE_1 and the input state of the data input port of the first group data transmission path a of other first processing units PE_1 located in the same systolic matrix, and generates a second selection signal select2 based on the input state of the data input port of the second group data transmission path b and the input state of the data input port of the second group data transmission path b of other first processing units PE_1 located in the same systolic matrix, wherein the first selection signal is the second sub-selection signal, the second selection signal is the fourth sub-selection signal, and the first data input by the second data transmission path a2 and the second data input by the fourth data transmission path b2 are selected based on the first selection signal select1 and the second selection signal select2, and output to the downstream processing unit through the first group data transmission path a and the second group data transmission path b; the second processing unit PE_2 is configured to receive the data output by the processing unit located at the upstream node of the same systolic matrix, and select the first data input by the second data transmission path a2 and the second data input by the fourth data transmission path b2 based on the first selection signal select1 and the second selection signal select2 accepted from the upstream processing unit, and output to the downstream processing unit through the first group data transmission path a and the second group data transmission path b;

[0193] Or, among the second systolic matrix M2, the third systolic matrix M3 and the fourth systolic matrix M4, the first processing unit PE_1 generates a first selection signal select1 based on the input state of the data input port of the first group data transmission path a of the first processing unit PE_1 and the input state of the data input port of the first group data transmission path a of other first processing units PE_1 located in the same systolic matrix, and generates a second selection signal select2 based on the input state of the data input port of the second group data transmission path b and the input state of the data input port of the second group data transmission path b of other first processing units PE_1 located in the same systolic matrix, wherein the first selection signal is the second sub-selection signal, the second selection signal is the third sub-selection signal, and the first data transmitted by the second data transmission path a2 and the second data transmitted by the third data transmission path b1 are selected based on the first selection signal select1 and the second selection signal select2 respectively, and output to the downstream processing unit through the first group data transmission path a and the second group data transmission path b; the second processing unit PE_2 is configured to receive the data output by the processing unit located at the upstream node of the same systolic matrix, and select the first data transmitted by the second data transmission path a2 and the second data transmitted by the third data transmission path b2 based on the first selection signal select1 and the second selection signal select2 accepted from the upstream processing unit, and output to the downstream processing unit through the first group data transmission path a and the second group data transmission path b;

[0194] Or, among the second systolic matrix M2, the third systolic matrix M3 and the fourth systolic matrix M4, the first processing unit PE_1 generates a first selection signal select1 based on the input state of the data input port of the first group data transmission path a of the first processing unit PE_1 and the input state of the data input port of the first group data transmission path a of other first processing units PE_1 located in the same systolic matrix, and generates a second selection signal select2 based on the input state of the data input port of the second group data transmission path b and the input state of the data input port of the second group data transmission path b of other first processing units PE_1 located in the same systolic matrix, such as the first selection signal is a first sub-selection signal and the second selection signal is a fourth sub-selection signal, and selects the first data transmitted by the first data transmission path a1 and the second data transmitted by the fourth data transmission path b2 based on the first selection signal select1 and the second selection signal select2, and outputs to the downstream processing unit through the first group data transmission path a and the second group data transmission path b; the second processing unit PE_2 is used to receive the data output by the processing unit located at the upstream node of the same systolic matrix, and select the first data transmitted by the first data transmission path a1 and the second data transmitted by the fourth data transmission path b2 based on the first selection signal select1 and the second selection signal select2 accepted from the upstream processing unit, and output to the downstream processing unit through the first group data transmission path a and the second group data transmission path b.

[0195] On the basis of the above-mentioned embodiments, in an embodiment of the present application, in the data output stage, the first processing unit PE_1 in the first systolic matrix M1 generates a first selection signal select1 based on the input state of the data input port of the first group data transmission path a, and selects the third data transmitted by the first data output path c1 or the third data transmitted by the second data output path c2 based on the first selection signal select1, and transmits to the downstream processing unit in the first systolic matrix through the third group data transmission path; the second processing unit PE_2 selects the third data transmitted by the first data output path c1 or the third data transmitted by the second data output path c2 based on the data output by the processing unit located at the upstream node of the first systolic matrix M1 and the first selection signal select1 accepted from the upstream processing unit, and transmits to the downstream processing unit in the first systolic matrix through the third group data transmission path.

[0196] In the data output stage, among the second systolic matrix M2, the third systolic matrix M3 and the fourth systolic matrix M4, the first processing element PE_1 generates a first selection signal select1 based on the input state of the data input port of the first group of data transmission paths a of the first processing element PE_1 and the input state of the data input port of the first group of data transmission paths a of other first processing elements PE_1 in the same systolic matrix, and selects the third data transmitted by the first data output path c1 or the third data transmitted by the second data output path c2 based on the first selection signal select1, and transmits the selected third data to the processing element downstream in the same systolic matrix through the third group of data transmission paths; the second processing element PE_2 selects the third data transmitted by the first data output path c1 or the third data transmitted by the second data output path c2 based on the data output by the processing element at the upstream node in the same systolic matrix and the first selection signal select1 accepted from the upstream processing element, and transmits the selected third data to the processing element downstream in the same systolic matrix through the third group of data transmission paths.

[0197] In other embodiments of the present application, in the data output stage, the first processing element and the second processing element in the first systolic matrix M1, the second systolic matrix M2, the third systolic matrix M3 and the fourth systolic matrix M4 can also select the third data transmitted by the first data output path c1 or the third data transmitted by the second data output path c2 based on a second selection signal, which is not limited in the present application and is determined according to the specific situation.

[0198] In another embodiment of the present application, as shown in Figure 10 The systolic array includes four systolic matrices M arranged in a matrix, the first systolic matrix M1 includes processing elements located in 1~n rows and 1~n columns, the second systolic matrix M2 includes processing elements located in 1~n rows and (n+1)~2n columns, the third systolic matrix M3 includes processing elements located in (n+1)~2n rows and 1~n columns, and the fourth systolic matrix M4 includes processing elements located in (n+1)~2n rows and (n+1)~2n columns; specifically,

[0199] The processing element located in the first row and the first column is the first processing element PE_1 in the first systolic matrix M1, the processing element located in the first row and the second n column is the first processing element PE_1 in the second systolic matrix, the processing element located in the second n row and the first column is the first processing element PE_1 in the third systolic matrix, and the processing element located in the second n row and the second n column is the first processing element PE_1 in the fourth systolic matrix, and the remaining processing elements are the second processing elements PE_2;

[0200] In the embodiment, in the first systolic array M1, the second systolic array M2, the third systolic array M3 and the fourth systolic array M4, the first processing element PE_1 generates a first selection signal select1 based on the input state of the data input port of the first group of data transmission paths a thereof and a second selection signal select2 based on the input state of the data input port of the second group of data transmission paths b thereof, selects the first data transmitted in the first group of data transmission paths a and the second data transmitted in the second group of data transmission paths b based on the first selection signal select1 and the second selection signal select2, and outputs the first data and the second data to the processing element downstream thereof in the same systolic array through the first group of data transmission paths a and the second group of data transmission paths b, and selects the third data transmitted in the third group of data transmission paths c and transmits the third data to the processing element downstream thereof in the same systolic array through the third group of data transmission paths c;

[0201] The second processing element PE_2 selects the first data transmitted in the first group of data transmission paths a and the second data transmitted in the second group of data transmission paths b based on the first selection signal select1 and the second selection signal select2 output by the first processing element PE_1 in the same systolic array, and outputs the first data and the second data to the processing element downstream thereof in the same systolic array through the first group of data transmission paths a and the second group of data transmission paths b, and selects the third data transmitted in the third group of data transmission paths c and transmits the third data to the processing element downstream thereof through the third group of data transmission paths c.

[0202] As can be seen from the above description, the first processing element needs to generate selection signals, and the second processing element does not need to generate selection signals, but only needs to receive selection signals, so the first processing element can be a processing element provided in any of the above embodiments, such as shown in Figure 1 and Figure 5 , and can include a first selection module, a second selection module, a data processing module, a first selection signal generation module, a second selection signal generation module, a first delay module or a second delay module, etc. Compared with the first processing element, the second processing element does not need to include the first selection signal generation module and the second selection signal generation module, and can include a first selection module, a second selection module, a data processing module, etc. as shown in Figure 2 and Figure 3 . It should be noted that in the embodiment, the second processing element can include the first delay module or the second delay module, or can not include the first delay module and the second delay module, which is determined according to the situation.

[0203] Since the structures and working principles of the first selection module, the second selection module, the data processing module, the first selection signal generating module, the second selection signal generating module, the first delay module and the second delay module have been described in the various embodiments of the processing unit, they will not be repeated here.

[0204] Optionally, in one embodiment of the present application, Figure 11 As shown, the first column and last column of the processing units in each row of the 2n×2n processing units PE are provided with a first delay module Input REG1, and the first row and last row of the processing units PE in each column of the processing units PE are provided with a second delay module Input REG2. However, this application does not impose any limitation on this, and the specific use case may vary.

[0205] Based on the above embodiments, in one embodiment of the present application, Figure 12 As shown, Figure 12 for Figure 11 The partially enlarged view shows a systolic array including a first processing unit 101 and a second processing unit 102 adjacent to each other in a first dimension X. The first output port a1o of the first processing unit 101 is connected to the first input port a1i of the second processing unit 102, the second input port a2i of the first processing unit 101 is connected to the second output port a2o of the second processing unit 102, the fifth output port c1o of the first processing unit 101 is connected to the fifth input port c1i of the second processing unit 102, and the sixth input port c2i of the first processing unit 101 is connected to the sixth output port c2o of the second processing unit 102. It should be noted that the first processing unit 101 and the second processing unit 102 can be any two adjacent processing units in the systolic array in the first dimension X.

[0206] The systolic array includes a first processing unit 103 and a second processing unit 104 that are adjacent to each other in the second dimension Y. The third output port b1o of the first processing unit 103 is connected to the third input port b1i of the second processing unit 104. The fourth input port b2i of the first processing unit 103 is connected to the fourth output port b2o of the second processing unit 104. It should be noted that the first processing unit 103 and the second processing unit 104 can be any two adjacent processing units in the second dimension Y in the systolic array.

[0207] For the convenience of description, the i-th row and j-th column is represented by PE(i, j), such as the processing unit of the first row and the first column is represented by PE(1, 1), the processing unit of the first row and the second column is represented by PE(1, 2), the processing unit of the second row and the first column is represented by PE(2, 1), the processing unit of the second row and the second column is represented by PE(2, 2), and so on, as shown in the following table. Figure 13 Figure 13 The coordinates of each processing unit when the systolic array includes 4x4 processing units are shown.

[0208] In an embodiment of the present application, PE(1, 1) is the first processing unit in the first systolic matrix, and generates the first selection signal and the second selection signal as the first selection signal and the second selection signal of itself, respectively;

[0209] PE(1, 2) is the second processing unit in the first systolic matrix, and the first selection signal input end thereof is connected to the first selection signal output end of PE(1, 1) to input the first selection signal output by PE(1, 1), and the second selection signal input end thereof is connected to the second selection signal output end of PE(1, 1) to input the second selection signal output by PE(1, 1);

[0210] PE(2, 1) is the second processing unit in the first systolic matrix, and the first selection signal input end thereof is connected to the first selection signal output end of PE(1, 1) to input the first selection signal output by PE(1, 1), and the second selection signal input end thereof is connected to the second selection signal output end of PE(1, 1) to input the second selection signal output by PE(1, 1);

[0211] PE(2, 2) is the second processing unit in the first systolic matrix, and the first selection signal input end thereof is connected to the first selection signal output end of PE(1, 1) to input the first selection signal output by PE(1, 1), and the second selection signal input end thereof is connected to the second selection signal output end of PE(1, 1) to input the second selection signal output by PE(1, 1);

[0212] PE(1, 3) and PE(1, 4) are the first processing units in the second systolic matrix, and generate the first selection signal and the second selection signal as the first selection signal and the second selection signal of themselves, respectively;

[0213] PE(2, 3) and PE(2, 4) are the second processing units in the second systolic matrix, and the first selection signal input end thereof is connected to the first selection signal output end of PE(1, 3) and PE(1, 4) to input the first selection signal output by PE(1, 3) and PE(1, 4), and the second selection signal input end thereof is connected to the second selection signal output end of PE(1, 3) and PE(1, 4) to input the second selection signal output by PE(1, 3) and PE(1, 4).​

[0214] PE(3, 1) and PE(4, 1) are first processing units in the third systolic array, generating the first selection signal and the second selection signal as their own first selection signal and second selection signal;

[0215] PE(3, 2) and PE(4, 2) are second processing units in the third systolic array, the first selection signal input end of which is connected to the first selection signal output end of PE(3, 1) and PE(4, 1), inputting the first selection signal output by PE(3, 1) and PE(4, 1), and the second selection signal input end of which is connected to the second selection signal output end of PE(3, 1) and PE(4, 1), inputting the second selection signal output by PE(3, 1) and PE(4, 1);

[0216] PE(3, 3) and PE(4, 4) are first processing units in the fourth systolic array, generating the first selection signal and the second selection signal as their own first selection signal and second selection signal;

[0217] PE(3, 4) and PE(4, 3) are second processing units in the third systolic array, the first selection signal input end of which is connected to the first selection signal output end of PE(3, 3) and PE(4, 4), inputting the first selection signal output by PE(3, 3) and PE(4, 4), and the second selection signal input end of which is connected to the second selection signal output end of PE(3, 3) and PE(4, 4), inputting the second selection signal output by PE(3, 3) and PE(4, 4).

[0218] In another embodiment of the present application, as shown in FIG. 1B, PE(1, 1) is a first processing unit in the first systolic array, generating the first selection signal and the second selection signal as its own first selection signal and second selection signal; Figure 14

[0219] PE(1, 2), PE(2, 1), and PE(2, 2) are second processing units in the first systolic array, the first selection signal input end of which is connected to the first selection signal output end of PE(1, 1), inputting the first selection signal output by PE(1, 1), and the second selection signal input end of which is connected to the second selection signal output end of PE(1, 1), inputting the second selection signal output by PE(1, 1);

[0220] PE(1, 4) is a first processing unit in the second systolic array, generating the first selection signal and the second selection signal as its own first selection signal and second selection signal;

[0221] ​PE(1,3), PE(2,3) and PE(2,4) are second processing units in the second systolic array, the first selection signal input ends of which are connected to the first selection signal output end of PE(1,4) to input the first selection signal output by PE(1,4), and the second selection signal input ends of which are connected to the second selection signal output end of PE(1,4) to input the second selection signal output by PE(1,4);

[0222] PE(4,1) is a first processing unit in the third systolic array, which generates the first selection signal and the second selection signal as the first selection signal and the second selection signal of itself;

[0223] PE(3,1), PE(3,2) and PE(4,2) are second processing units in the third systolic array, the first selection signal input ends of which are connected to the first selection signal output end of PE(4,1) to input the first selection signal output by PE(4,1), and the second selection signal input ends of which are connected to the second selection signal output end of PE(4,1) to input the second selection signal output by PE(4,1);

[0224] PE(4,4) is a first processing unit in the fourth systolic array, which generates the first selection signal and the second selection signal as the first selection signal and the second selection signal of itself;

[0225] PE(3,3), PE(3,4) and PE(4,3) are second processing units in the third systolic array, the first selection signal input ends of which are connected to the first selection signal output end of PE(4,4) to input the first selection signal output by PE(4,4), and the second selection signal input ends of which are connected to the second selection signal output end of PE(4,4) to input the second selection signal output by PE(4,4).

[0226] It should be noted that, unlike the corresponding systolic array, Figure 14 as shown in the systolic array, Figure 13 The systolic array shown can not only be applied to the scene of bidirectional transmission of data and bidirectional output of calculation results, but also can be applied to the scene of unidirectional transmission of data and unidirectional output of calculation results. Figure 14 The systolic array shown can only be applied to the scene of bidirectional transmission of data and bidirectional output of calculation results.

[0227] Correspondingly, the application also provides an electronic device, which can include the systolic array provided by any of the above embodiments, or can include the systolic array composed of the processing units in the systolic array provided by any of the above embodiments, which is not limited by the application, and is determined according to the specific situation. It should be noted that, since the related content of the systolic array and the related content of the processing units in the systolic array have been described in the above embodiments, they will not be described here.

[0228] Further, the application also provides a data processing method applied to a systolic array, the systolic array comprising 2n*2n processing units, the processing units having a first group of data transmission paths for transmitting data in a row direction, a second group of data transmission paths for transmitting data in a column direction, and a third group of data transmission paths for transmitting data in the row direction, the first group of data transmission paths transmitting first data, the second group of data transmission paths transmitting second data, and the third group of data transmission paths transmitting third data; each group comprising 2 data transmission directions. Since the related description of the systolic array has been described in the above embodiments, the application will not be described here again.

[0229] On the basis of the above embodiments, in one embodiment of the application, the systolic array comprises four systolic matrices arranged in a matrix, each systolic matrix comprising n*n processing units, the first systolic matrix M1 comprising processing units located in 1~n rows and 1~n columns, the second systolic matrix M2 comprising processing units located in 1~n rows and (n+1)~2n columns, the third systolic matrix M3 comprising processing units located in (n+1)~2n rows and 1~n columns, and the fourth systolic matrix M4 comprising processing units located in (n+1)~2n rows and (n+1)~2n columns; specifically, the processing unit located in the first row and the first column is the first processing unit in the first systolic matrix, the processing unit located in the first row and the 2n column is the first processing unit in the second systolic matrix, the processing unit located in the 2n row and the first column is the first processing unit in the third systolic matrix, and the processing unit located in the 2n row and the 2n column is the first processing unit in the fourth systolic matrix; in this embodiment, the data processing method comprises:

[0230] In the first time, the processing units in the first systolic matrix are controlled to transmit first data through the first data transmission path and second data through the third data transmission path, the processing units in the second systolic matrix are controlled to transmit first data through the second data transmission path and second data through the third data transmission path, the processing units in the third systolic matrix are controlled to transmit first data through the first data transmission path and second data through the fourth data transmission path, and the processing units in the fourth systolic matrix are controlled to transmit first data through the second data transmission path and second data through the fourth data transmission path.

[0231] Taking the systolic array comprising 4*4 processing units as an example, the data matrix input process in the systolic array is described. As shown in FIG. 1, the systolic array comprises four systolic matrices M1, M2, M3 and M4, each systolic matrix comprising 4*4 processing units. Figure 14As shown, PE (1,1) transmits first data through the first data transmission path al and second data through the third data transmission path bl at the same time as PE (1,4) transmits first data through the second data transmission path a2 and second data through the third data transmission path bl, PE (4,1) transmits first data through the first data transmission path al and second data through the fourth data transmission path b2, and PE (4,4) transmits first data through the second data transmission path a2 and second data through the fourth data transmission path b2, i.e. PE (1,1), PE (1,4), PE (4,1) and PE (4,4) transmit data at the same time;

[0232] As shown, PE (1,1) transmits first data through the first data transmission path al and second data through the third data transmission path bl at the same time as PE (1,4) transmits first data through the second data transmission path a2 and second data through the third data transmission path bl, PE (4,1) transmits first data through the first data transmission path al and second data through the fourth data transmission path b2, and PE (4,4) transmits first data through the second data transmission path a2 and second data through the fourth data transmission path b2, i.e. PE (1,1), PE (1,4), PE (4,1) and PE (4,4) transmit data at the same time;

[0233] PE(2,2) receives and transmits the first data transmitted by PE(2,1) or PE(1,2) through the first data transmission path al and receives and transmits the second data transmitted by PE(2,1) or PE(1,2) through the third data transmission path bl, PE(2,3) receives and transmits the first data transmitted by PE(1,3) or PE(4,2) through the second data transmission path a2 and receives and transmits the second data transmitted by PE(1,3) or PE(2,4) through the third data transmission path bl, PE(3,2) receives and transmits the first data transmitted by PE(3,1) or PE(4,2) through the first data transmission path al and receives and transmits the second data transmitted by PE(3,1) or PE(4,2) through the fourth data transmission path b2, and PE(3,3) receives and transmits the first data transmitted by PE(4,3) or PE(3,4) through the second data transmission path a2 and receives and transmits the second data transmitted by PE(4,3) or PE(3,4) through the fourth data transmission path b2, that is, PE(2,2), PE(2,3), PE(3,2) and PE(3,3) transmit data at the same time.

[0234] Therefore, the systolic array provided in the embodiments of the present application can improve the running speed and the pipeline running efficiency of the systolic array by inputting the data matrix in the manner of simultaneously inputting data from different directions by multiple processing units at the same time.

[0235] Optionally, in an embodiment of the present application, in order to enable the systolic array to also be applied to the application scenario of unidirectional data transmission, the systolic array is arranged as shown in FIG. 4. Figure 13 As shown in FIG. 4, the processing unit located at the first row and the n+1th column is also the first processing unit in the second systolic matrix, the processing unit located at the n+1th row and the first column is also the first processing unit in the third systolic matrix, and the processing unit located at the n+1th row and the n+1th column is also the first processing unit in the fourth systolic matrix. However, the present application does not make any limitation in this regard, and the specific arrangement is determined according to the situation. Since the data processing method of the systolic array applied to the scenario of unidirectional data transmission is the same as the data processing method of the existing systolic array, the present application does not make any further description in this regard.

[0236] On the basis of any of the above embodiments, in an embodiment of the present application, in the first pulsating matrix, along the row direction, the first row processing units of each column after the first column are inputted with the second data of each column in the second data matrix starting from the first column, and each second data in the second data array of each column is transmitted to the processing units of the next row in the data transmission period; at the same time, along the column direction, the first column processing units of each row after the first row are inputted with the first data of each row in the first data matrix starting from the first row, and each first data in the first data array of each row is transmitted to the processing units of the next column in the data transmission period.

[0237] In the second pulsating matrix, along the row direction, the first row processing units of each column after the 2nth column are inputted with the second data of each column in the second data matrix starting from the last column, and each second data in the second data array of each column is transmitted to the processing units of the next row in the data transmission period; at the same time, along the column direction, the last column processing units of each row are inputted with the same first data synchronously and symmetrically in the first pulsating matrix and transmitted to the processing units of the next column in the data transmission period.

[0238] In the third pulsating matrix, along the row direction, the last row processing units of each column are inputted with the same second data synchronously and symmetrically in the first pulsating matrix and transmitted to the processing units of the next row in the data transmission period; at the same time, along the column direction, the first column processing units of each row after the 2nth row are inputted with the first data of each row in the first data matrix starting from the last row, and each first data in the first data array of each row is transmitted to the processing units of the next column in the data transmission period.

[0239] In the fourth pulsating matrix, along the row direction, the last row processing units of each column are inputted with the same second data synchronously and symmetrically in the second pulsating matrix and transmitted to the processing units of the next row in the data transmission period; at the same time, along the column direction, the last column processing units of each row are inputted with the same first data synchronously and symmetrically in the third pulsating matrix and transmitted to the processing units of the next column in the data transmission period.

[0240] It should be noted that the first data matrix is a data matrix composed of a plurality of first data, and the second data matrix is a data matrix composed of a plurality of second data.

[0241] Taking the pulsating array including 4x4 processing units as an example, the data matrix input process in the pulsating array is described. Optionally, in the embodiment, when the pulsating array includes 4x4 processing units, the first data matrix is: a0,0a0,1a0,2a0,3 b0,0b0,1b0,2b0,3

[0242] a1,0a1,1a1,2a1,3 b1,0b1,1b1,2b1,3

[0243] a2,0a2,1a2,2a2,3 b2,0b2,1b2,2b2,3

[0244] a3,0a3,1a3,2a3,3; the second data matrix is: b3,0b3,1b3,2b3,3.

[0245] In this embodiment, if Figures 15-21 As shown, when the first data matrix and the second data matrix are input into the systolic array including 4×4 processing units, the data matrix input process of the systolic array includes:

[0246] In the first data transmission cycle T1, PE(1,1) inputs data a0,0 and b0,0 through the first data transmission path a1 and the third data transmission path b1, generates the third data a0,0*b0,0, and transmits a0,0 and b0,0 to the two downstream processing units PE(1,2) and PE(2,1) according to the transmission direction;

[0247] PE (1, 4) inputs data a0, 0 and b0, 3 through the second data transmission path a2 and the third data transmission path b1, generates third data a0, 0*b0, 3, and transmits a0, 0 and b0, 3 to the two downstream processing units PE (1, 3) and PE (2, 4) according to the transmission direction;

[0248] PE (4, 1) inputs data a3, 0 and b0, 0 through the first data transmission path a1 and the fourth data transmission path b2, generates third data a3, 0*b0, 0, and transmits a3, 0 and b0, 0 to the two downstream processing units PE (3, 1) and PE (4, 2) according to the transmission direction;

[0249] PE(4,4) inputs data a3,0 and b0,3 through the second data transmission path a2 and the fourth data transmission path b2, generates the third data a3,0*b0,3, and transmits a3,0 and b0,3 to the two downstream processing units PE(4,3) and PE(3,4) according to the transmission direction, so that the systolic matrix is ​​changed from Figure 15 Transformed into Figure 16 It should be noted that, in addition to processing data, the processing unit also needs to transmit the received first data and second data to the downstream processing unit PE according to the input transmission direction, which will not be described in detail below.

[0250] In the second data transmission cycle T2, if Figure 17As shown, PE (1,1) inputs data a0,1 and b1,0 through the first data transmission path al and the third data transmission path bl, generates the third data as a0,0*b0,0+a0,1*b1,0, and transmits a0,1 and b1,0 to the two processing elements PE (1,2) and PE (2,1) downstream according to the transmission direction;

[0251] PE (1,2) inputs data a0,0 and b0,1 through the first data transmission path al and the third data transmission path bl, generates the third data as a0,0*b0,1, and transmits a0,0 and b0,1 to the processing element PE (2,2) downstream according to the transmission direction;

[0252] PE (2,1) inputs data a1,0 and b0,0 through the first data transmission path al and the third data transmission path bl, generates the third data as a1,0*b0,0, and transmits a1,0 and b0,0 to the processing element PE (2,2) downstream according to the transmission direction;

[0253] PE (1,4) inputs data a0,1 and b1,3 through the second data transmission path a2 and the third data transmission path bl, generates the third data as a0,0*b0,3+a0,1*b1,3, and transmits a0,1 and b1,3 to the processing elements PE (1,3) and PE (2,4) downstream according to the transmission direction;

[0254] PE (1,3) inputs data a0,0 and b0,2 through the second data transmission path a2 and the third data transmission path bl, generates the third data as a0,0*b0,2, and transmits a0,0 and b0,2 to the two processing elements PE (2,3) downstream according to the transmission direction;

[0255] PE (2,4) inputs data a1,0 and b0,3 through the second data transmission path a2 and the third data transmission path bl, generates the third data as a1,0*b0,3, and transmits a1,0 and b0,3 to the two processing elements PE (2,3) downstream according to the transmission direction;

[0256] PE (4,1) inputs data a3,1 and b1,0 through the first data transmission path al and the fourth data transmission path b2, generates the third data as a3,0*b0,0+a3,1*b1,0, and transmits a3,1 and b1,0 to the two processing elements PE (3,1) and PE (4,2) downstream according to the transmission direction;

[0257] PE(3,1) inputs data a2,0 and b0,0 through the first data transmission path al and the fourth data transmission path b2, generates the third data as a2,0*b0,0, and transmits a2,0 and b0,0 to the processing element PE(3,2) downstream according to the transmission direction;

[0258] PE(4,2) inputs data a3,0 and b0,1 through the first data transmission path al and the fourth data transmission path b2, generates the third data as a3,0*b0,1, and transmits a3,0 and b0,1 to the processing element PE(3,2) downstream according to the transmission direction;

[0259] PE(4,4) inputs data a3,1 and b1,3 through the second data transmission path a2 and the fourth data transmission path b2, generates the third data as a3,0*b0,3+a3,1*b1,3, and transmits a3,1 and b1,3 to the two processing elements PE(4,3) and PE(3,4) downstream according to the transmission direction;

[0260] PE(4,3) inputs data a3,0 and b0,2 through the second data transmission path a2 and the fourth data transmission path b2, generates the third data as a3,0*b0,2, and transmits a3,0 and b0,2 to the processing element PE(3,3) downstream according to the transmission direction;

[0261] PE(3,4) inputs data a2,0 and b0,3 through the second data transmission path a2 and the fourth data transmission path b2, generates the third data as a2,0*b0,3, and transmits a2,0 and b0,3 to the processing element PE(3,3) downstream according to the transmission direction.

[0262] In the third data transmission period T3, as shown in Fig. 3, the processing element PE(1,1) inputs data a0,2 and b2,0 through the first data transmission path al and the third data transmission path bl, generates the third data as a0,0*b0,0+a0,1*b1,0+a0,2*b2,0, and transmits a0,2 and b2,0 to the processing element PE(1,2) downstream according to the transmission direction; Figure 18

[0263] The processing element PE(1,2) inputs data a0,1 and b1,1 through the first data transmission path al and the third data transmission path bl, generates the third data as a0,0*b0,1+a0,1*b1,1, and transmits a0,1 and b1,1 to the processing element PE(2,1) downstream according to the transmission direction;

[0264] The processing element PE(2,1) inputs data a1,1 and b1,0 through the first data transmission path al and the third data transmission path bl, generates the third data as a1,0*b0,0+a1,1*b1,0, and transmits a1,1 and b1,0 to the processing element PE(2,2) downstream according to the transmission direction;

[0265] ​PE(2, 2) inputs data a1,0 and b0,1 through the first data transmission path al and the third data transmission path bl, and the third data generated is a1,0*b0,1;

[0266] PE(1, 4) inputs data a0,2 and b2,3 through the second data transmission path a2 and the third data transmission path bl, and the third data generated is a0,0*b0,3+a0,1*b1,3+a0,2*b2,3;

[0267] PE(1, 3) inputs data a0,1 and b1,2 through the second data transmission path a2 and the third data transmission path bl, and the third data generated is a0,0*b0,2+a0,1*b1,2;

[0268] PE(2, 4) inputs data a1,1 and b1,3 through the second data transmission path a2 and the third data transmission path bl, and the third data generated is a1,0*b0,3+a1,1*b1,3;

[0269] PE(2, 3) inputs data a1,0 and b0,2 through the second data transmission path a2 and the third data transmission path bl, and the third data generated is a1,0*b0,2;

[0270] PE(4, 1) inputs data a3,2 and b2,0 through the first data transmission path al and the fourth data transmission path b2, and the third data generated is a3,0*b0,0+a3,1*b1,0+a3,2*b2,0;

[0271] PE(3, 1) inputs data a2,1 and b1,0 through the first data transmission path al and the fourth data transmission path b2, and the third data generated is a2,0*b0,0+a2,1*b1,0;

[0272] PE(4, 2) inputs data a3,1 and b1,1 through the first data transmission path al and the fourth data transmission path b2, and the third data generated is a3,0*b0,1+a3,1*b1,1;

[0273] PE(3, 2) inputs data a2,0 and b0,1 through the first data transmission path al and the fourth data transmission path b2, and the third data generated is a2,0*b0,1;

[0274] PE(4, 4) inputs data a3,2 and b2,3 through the second data transmission path a2 and the fourth data transmission path b2, and the third data generated is a3,0*b0,3+a3,1*b1,3+a3,2*b2,3;

[0275] PE(4,3) inputs data a3,1 and b1,2 through the second data transmission path a2 and the fourth data transmission path b2, and the third data generated is a3,0*b0,2+a3,1*b1,2;

[0276] PE(3,4) inputs data a2,1 and b1,3 through the second data transmission path a2 and the fourth data transmission path b2, and the third data generated is a2,0*b0,3+a2,1*b1,3;

[0277] PE(3,3) inputs data a2,0 and b0,2 through the second data transmission path a2 and the fourth data transmission path b2, and the third data generated is a2,0*b0,2;

[0278] In the fourth data transmission period T4, as shown in Fig. 4, PE(1,1) inputs data a0,3 and b3,0 through the first data transmission path a1 and the third data transmission path b1, and the third data generated is a0,0*b0,0+a0,1*b1,0+a0,2*b2,0+a0,3*b3,0; Figure 19

[0279] PE(1,2) inputs data a0,2 and b2,1 through the first data transmission path a1 and the third data transmission path b1, and the third data generated is a0,0*b0,1+a0,1*b1,1+a0,2*b2,1;

[0280] PE(2,1) inputs data a1,2 and b2,0 through the first data transmission path a1 and the third data transmission path b1, and the third data generated is a1,0*b0,0+a1,1*b1,0+a1,2*b2,0;

[0281] PE(2,2) inputs data a1,1 and b1,1 through the first data transmission path a1 and the third data transmission path b1, and the third data generated is a1,0*b0,1+a1,1*b1,1;

[0282] PE(1,4) inputs data a0,3 and b3,3 through the second data transmission path a2 and the third data transmission path b1, and the third data generated is a0,0*b0,3+a0,1*b1,3+a0,2*b2,3+a0,3*b3,3;

[0283] PE(1,3) inputs data a0,2 and b2,2 through the second data transmission path a2 and the third data transmission path b1, and the third data generated is a0,0*b0,2+a0,1*b1,2+a0,2*b2,2;

[0284] ​PE(2,4) inputs data a1,2 and b2,3 through the second data transmission path a2 and the third data transmission path b1, and the third data generated is a1,0*b0,3+a1,1*b1,3+a1,2*b2,3;

[0285] PE(2,3) inputs data a1,1 and b1,2 through the second data transmission path a2 and the third data transmission path b1, and the third data generated is a1,0*b0,2+a1,1*b1,2;

[0286] PE(4,1) inputs data a3,3 and b3,0 through the first data transmission path a1 and the fourth data transmission path b2, and the third data generated is a3,0*b0,0+a3,1*b1,0+a3,2*b2,0+a3,3*b3,0;

[0287] PE(3,1) inputs data a2,2 and b2,0 through the first data transmission path a1 and the fourth data transmission path b2, and the third data generated is a2,0*b0,0+a2,1*b1,0+a2,2*b2,0;

[0288] PE(4,2) inputs data a3,2 and b2,1 through the first data transmission path a1 and the fourth data transmission path b2, and the third data generated is a3,0*b0,1+a3,1*b1,1+a3,2*b2,1;

[0289] PE(3,2) inputs data a2,1 and b1,1 through the first data transmission path a1 and the fourth data transmission path b2, and the third data generated is a2,0*b0,1+a2,1*b1,1;

[0290] PE(4,4) inputs data a3,3 and b3,3 through the second data transmission path a2 and the fourth data transmission path b2, and the third data generated is a3,0*b0,3+a3,1*b1,3+a3,2*b2,3+a3,3*b3,3;

[0291] PE(4,3) inputs data a3,2 and b2,2 through the second data transmission path a2 and the fourth data transmission path b2, and the third data generated is a3,0*b0,2+a3,1*b1,2+a3,2*b2,2;

[0292] PE(3,4) inputs data a2,2 and b2,3 through the second data transmission path a2 and the fourth data transmission path b2, and the third data generated is a2,0*b0,3+a2,1*b1,3+a2,2*b2,3;

[0293] PE(3,3) inputs data a2,1 and b1,2 through the second data transmission path a2 and the fourth data transmission path b2, and generates the third data as a2,0*b0,2+a2,1*b1,2;

[0294] In the fifth data transmission period T5, as shown in FIG. 5, the PE (1,1) no longer inputs data, and keeps the third data as a0,0*b0,0+a0,1*b1,0+a0,2*b2,0+a0,3*b3,0; Figure 20

[0295] PE(1,2) inputs data a0,3 and b3,1 through the first data transmission path a1 and the third data transmission path b1, and generates the third data as a0,0*b0,1+a0,1*b1,1+a0,2*b2,1+a0,3*b3,1;

[0296] PE(2,1) inputs data a1,3 and b3,0 through the first data transmission path a1 and the third data transmission path b1, and generates the third data as a1,0*b0,0+a1,1*b1,0+a1,2*b2,0+a1,3*b3,0;

[0297] PE(2,2) inputs data a1,2 and b2,1 through the first data transmission path a1 and the third data transmission path b1, and generates the third data as a1,0*b0,1+a1,1*b1,1+a1,2*b2,1;

[0298] PE(1,4) no longer inputs data, and keeps the third data as a0,0*b0,3+a0,1*b1,3+a0,2*b2,3+a0,3*b3,3;

[0299] PE(1,3) inputs data a0,3 and b3,2 through the second data transmission path a2 and the third data transmission path b1, and generates the third data as a0,0*b0,2+a0,1*b1,2+a0,2*b2,2+a0,3*b3,2;

[0300] PE(2,4) inputs data a1,3 and b3,3 through the second data transmission path a2 and the third data transmission path b1, and generates the third data as a1,0*b0,3+a1,1*b1,3+a1,2*b2,3+a1,3*b3,3;

[0301] PE(2,3) inputs data a1,2 and b2,2 through the second data transmission path a2 and the third data transmission path b1, and generates the third data as a1,0*b0,2+a1,1*b1,2+a1,2*b2,2;

[0302] ​PE(4,1) no longer inputs data and keeps the third data a3,0*b0,0+a3,1*b1,0+a3,2*b2,0+a3,3*b3,0;

[0303] PE(3,1) inputs data a2,3 and b3,0 through the first data transmission path a1 and the fourth data transmission path b2, and generates third data a2,0*b0,0+a2,1*b1,0+a2,2*b2,0+a2,3*b3,0;

[0304] PE(4,2) inputs data a3,3 and b3,1 through the first data transmission path a1 and the fourth data transmission path b2, and generates third data a3,0*b0,1+a3,1*b1,1+a3,2*b2,1+a3,3*b3,1;

[0305] PE(3,2) inputs data a2,2 and b2,1 through the first data transmission path a1 and the fourth data transmission path b2, and generates third data a2,0*b0,1+a2,1*b1,1+a2,2*b2,1;

[0306] PE(4,4) no longer inputs data and keeps the third data a3,0*b0,3+a3,1*b1,3+a3,2*b2,3+a3,3*b3,3;

[0307] PE(4,3) inputs data a3,3 and b3,2 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a3,0*b0,2+a3,1*b1,2+a3,2*b2,2+a3,3*b3,2;

[0308] PE (3, 4) inputs data a2,3 and b3,3 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a2,0*b0,3+a2,1*b1,3+a2,2*b2,3+a2,3*b3,3;

[0309] PE(3,3) inputs data a2,2 and b2,2 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a2,0*b0,2+a2,1*b1,2+a2,2*b2,2;

[0310] In the sixth data transmission cycle T6, as shown in FIG. Figure 21 As shown, PE (1, 1) no longer inputs data and keeps the third data a0,0*b0,0+a0,1*b1,0+a0,2*b2,0+a0,3*b3,0;

[0311] PE(1,2) no longer inputs data, keeps the third data as a0,0*b0,1 + a0,1*b1,1 + a0,2*b2,1 + a0,3*b3,1;

[0312] PE(2,1) no longer inputs data, keeps the third data as: a1,0*b0,0 + a1,1*b1,0 + a1,2*b2,0 + a1,3*b3,0;

[0313] PE(2,2) inputs data a1,3 and b3,1 through the first data transmission path a1 and the third data transmission path b1, generates the third data as: a1,0*b0,1 + a1,1*b1,1 + a1,2*b2,1 + a1,3*b3,1;

[0314] PE(1,4) no longer inputs data, keeps the third data as a0,0*b0,3 + a0,1*b1,3 + a0,2*b2,3 + a0,3*b3,3;

[0315] PE(1,3) no longer inputs data, keeps the third data as a0,0*b0,2 + a0,1*b1,2 + a0,2*b2,2 + a0,3*b3,2;

[0316] PE(2,4) no longer inputs data, keeps the third data as a1,0*b0,3 + a1,1*b1,3 + a1,2*b2,3 + a1,3*b3,3;

[0317] PE(2,3) inputs data a1,3 and b3,2 through the second data transmission path a2 and the third data transmission path b1, generates the third data as a1,0*b0,2 + a1,1*b1,2 + a1,2*b2,2 + a1,3*b3,2;

[0318] PE(4,1) no longer inputs data, keeps the third data as a3,0*b0,0 + a3,1*b1,0 + a3,2*b2,0 + a3,3*b3,0;

[0319] PE(3,1) no longer inputs data, keeps the third data as a2,0*b0,0 + a2,1*b1,0 + a2,2*b2,0 + a2,3*b3,0;

[0320] PE(4,2) no longer inputs data, keeps the third data as a3,0*b0,1 + a3,1*b1,1 + a3,2*b2,1 + a3,3*b3,1;

[0321] PE(3,2) inputs data a2,3 and b3,1 through the first data transmission path al and the fourth data transmission path b2, and generates the third data as a2,0*b0,1 +a2,1*b1,1 +a2,2*b2,1 +a2,3*b3,1;

[0322] PE(4,4) no longer inputs data, and keeps the third data as a3,0*b0,3 +a3,1*b1,3 +a3,2*b2,3 +a3,3*b3,3;

[0323] PE(4,3) no longer inputs data, and keeps the third data as a3,0*b0,2 +a3,1*b1,2 +a3,2*b2,2 +a3,3*b3,2;

[0324] PE(3,4) no longer inputs data, and keeps the third data as a2,0*b0,3 +a2,1*b1,3 +a2,2*b2,3 +a2,3*b3,3;

[0325] PE(3,3) inputs data a2,3 and b3,2 through the second data transmission path a2 and the fourth data transmission path b2, and generates the third data as a2,0*b0,2 +a2,1*b1,2 +a2,2*b2,2 +a2,3*b3,2;

[0326] After the above six cycles, the input and calculation of the data matrix in the systolic array are completed.

[0327] Optionally, in an embodiment of the present application, according to the data input state of the first processing element in each systolic array, the data transmission path in the corresponding direction of the systolic array is selected, so that the same data transmission direction is selected for each processing element in the same systolic array.

[0328] On the basis of any of the above embodiments, in an embodiment of the present application, as Figure 22As shown, the data processing method further comprises: after the processing unit at the kth row and the kth column outputs a third signal, outputting the third data stored in the processing unit at the kth row and the kth column, the third signal representing that the data processing process in the processing unit at the kth row and the kth column is completed, k is an integer not less than 1 and not greater than 2n, so that the calculation result of each processing unit is outputted immediately after the data processing in the processing unit is completed, without waiting for the data processing in all processing units to be completed before outputting the calculation result of each processing unit, thereby further improving the data processing efficiency of the data processing method. Specifically, when the third data in the systolic array is started to be outputted, the second processing unit selects the third data outputted by the upstream processing unit and transmits the third data to the fourth processing unit through the third processing unit for storage and output, thereby forming an output data path and gradually outputting the third data outputted by each processing unit to the buffer, and after the third data outputted by each processing unit in the systolic array is buffered in the buffer, the buffer uniformly outputs the third data outputted by each processing unit.

[0329] It should be noted that the output signal generation module of the processing unit includes the flip-flop group composed of the third flip-flop unit and the fourth flip-flop unit, because the systolic array applied by the processing unit needs to keep the a_last signal high when outputting the third data, so as to keep the output path unblocked, for example, the data of the second processing unit is first transmitted to the previous processing unit and then transmitted to the buffer, so the a_last signal needs to be maintained high for two beats to ensure that the data of the second processing unit is normally transmitted to the buffer.

[0330] Optionally, in one embodiment of the present application based on the above-mentioned embodiments, the data processing method comprises: synchronously outputting the third data outputted by each processing unit in the systolic array along the first direction and the second direction, as shown in Figure 22 so as to improve the output speed of the calculation result of the systolic array, but the present application is not limited thereto, and in other embodiments of the present application, the data processing method can also comprise: synchronously outputting the third data outputted by each processing unit in the systolic array along the first direction or the second direction, as shown in Figure 23 as the case may be.

[0331] It should be noted that each of the above-mentioned embodiments is described by taking the systolic array as an example which adopts the bidirectional input mode in the same dimension when inputting the data matrix, but the present application is not limited thereto, and in other embodiments of the present application, the systolic array can also adopt the unidirectional input mode in the same dimension to process data.

[0332] Optionally, in one embodiment of the present application, if the systolic array adopts the manner of inputting the data matrix in one direction in the same dimension, the data processing method comprises:

[0333] In the row direction, the first data in each column of the first data matrix is input into the first row of the processing unit of each column in turn with a delay of one period, and each first data in the first data matrix is transmitted to the processing unit of the next row in the row direction according to the data transmission period.

[0334] In the column direction, the second data in each row of the second data matrix is input into the first column of the processing unit of each row in turn with a delay of one period, and each second data in the second data matrix is transmitted to the processing unit of the next column in the column direction according to the data transmission period.

[0335] Since the data transmission is only in one direction, in this embodiment, the first selection module of each processing unit PE in the systolic array selects the data transmission channel in the same direction for transmission in the row direction, and the second selection module of each processing unit PE in the systolic array selects the data transmission channel in the same direction for transmission in the column direction.

[0336] Since the data processing process of the systolic array adopting the manner of inputting the data matrix in one direction is well known to those skilled in the art, the present application will not be described in detail.

[0337] It should be noted that when the data processing method adopts the manner of inputting the data matrix in one direction in the same dimension, the parameters of the first data matrix and the second data matrix are loaded in turn from the horizontal direction (i.e. the first dimension) and the vertical direction (i.e. the second dimension) respectively, and using this calculation method, there will be a large number of idle PE units at the beginning and the end of the calculation, and the entire data processing requires (3m-2) data transmission periods, the calculation time is relatively long, and the design difficulty is relatively high. When the data matrix in two directions in the same dimension is adopted in the embodiment of the present application, the entire data processing requires (2m-2) data transmission periods, compared with the manner of inputting the data matrix in one direction in the same dimension, the number of data transmission periods in the entire data processing process is reduced from (3m-2) to (2m-2), which greatly improves the data processing running speed and the pipeline running efficiency of the systolic array.

[0338] Optionally, on the basis of any of the above embodiments, in one embodiment of the present application, the data processing method can be realized by hardware circuit, which is used for data processing of regular algorithms such as matrix operation, convolution and the like, but the present application does not limit this, which is determined according to the specific situation.

[0339] It should be noted that in the embodiment, as shown in the figure, since the way of inputting the first data in the first direction and the way of inputting the first data in the second direction are the same, the same set of hardware input devices can be shared when the first data is input in the first direction and the second direction; similarly, since the way of inputting the second data in the third direction and the way of inputting the second data in the fourth direction are the same, the same set of hardware input devices can be shared when the second data is input in the third direction and the fourth direction, so that the data processing method provided by the embodiment simplifies the hardware circuit structure for implementing the data processing method on the basis of providing the data processing speed. However, the present application does not make any limitation in this regard, and the specific implementation is subject to the actual situation. Figures 15-19

[0340] Optionally, in an embodiment of the present application, the data processing method can be applied to the calculation of a neural network unit, such as the calculation of an AI model, and the present application does not make any limitation in this regard, and the specific implementation is subject to the actual situation.

[0341] In addition, the embodiment of the present application further provides an electronic device, as shown in the figure, which comprises a systolic array 100, a processor 200 and a memory 300, wherein the systolic array 100 can be the systolic array provided by any of the above embodiments; the memory 300 is used to store a computer program; the processor 200 is used to execute the computer program, so that the electronic device can implement the data processing method provided by any of the above embodiments. Since the related content of the systolic array and the related content of the data processing method have been described in the above embodiments, they will not be described again. Figure 24

[0342] In summary, the electronic device, the systolic array and the data processing method thereof provided by the embodiment of the present application can input the data matrix into the systolic array in the way of inputting the data matrix in four positions in the same dimension in a bidirectional manner, thereby improving the data processing running speed and the pipeline running efficiency of the systolic array.

[0343] In the present specification, each embodiment is described in a progressive, or parallel, or progressive and parallel manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts of each embodiment can be referred to. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the method part.

[0344] ​​It is to be understood that the figures and descriptions of the embodiments described herein are illustrative of the various aspects of the present application. Although every aspect of the present application has been described and

[0345] The foregoing description of the disclosed embodiments enables a person skilled in the art to make or use the application. Modifications of these embodiments will occur to persons of skill in the art, and are within the scope of the application. The description is not intended to limit the application to the described embodiments, but to describe the general principles of the application. The scope of the application is limited only by the claims.

Claims

1. A processing unit in a systolic array, the processing unit having a first set of data transmission paths for transmitting data in a first dimension, a second set of data transmission paths for transmitting data in a second dimension, and a third set of data transmission paths for transmitting data in the first dimension; wherein The first group of data transmission paths includes a first data transmission path for transmitting data in a first direction and a second data transmission path for transmitting data in a second direction; The second group of data transmission paths includes a third data transmission path that transmits data along a third direction and a fourth data transmission path that transmits data along a fourth direction; The third set of data transmission paths includes a first data output path that transmits data along a first direction and a second data output path that transmits data along a second direction.

2. The processing unit in the systolic array according to claim 1, The first group of data transmission paths includes a first selection module, the first selection module being configured to select the first data transmission path or the second data transmission path to transmit first data based on a first selection signal; The second group of data transmission paths includes a second selection module, and the second selection module selects the third data transmission path or the fourth data transmission path to transmit the second data based on a second selection signal; The processing unit further includes: A data processing module, the data processing module includes a computing unit, the computing unit is located on the data transmission path of the first group of data transmission paths and the second group of data transmission paths, and is used to process the first data and the second data to generate third data, store the third data, and select the first data output path or the second data output path to output the third data based on the first selection signal.

3. The processing unit in the systolic array of claim 2 , wherein the first set of data transmission paths further comprises a first set of output ports located in the first dimension, the second set of data transmission paths further comprises a second set of output ports located in the second dimension, and the third set of data transmission paths further comprises a third set of output ports located in the first dimension; in, The first group of output ports includes a first output port and a second output port, the first output port and the second output port are used to output the first data; the second group of output ports includes a third output port and a fourth output port, the third output port and the fourth output port are used to output the second data; the third group of output ports includes a fifth output port and a sixth output port, the fifth output port and the sixth output port are used to output the third data; A first data output terminal of the computing unit is connected to the first group of output ports; The second data output terminal of the computing unit is connected to the second group of output ports; The third data output terminal of the computing unit is connected to the third group of output ports.

4. The processing unit in the systolic array of claim 2 , wherein the first set of data transmission paths further comprises a first set of input ports located in the first dimension, the second set of data transmission paths further comprises a second set of input ports located in the second dimension, and the third set of data transmission paths further comprises a third set of input ports located in the first dimension; The first group of input ports includes a first input port and a second input port, and the first input port and the second input port are used to input the first data; the second group of input ports includes a third input port and a fourth input port, and the third input port and the fourth input port are used to input the second data; The third group of input ports includes a fifth input port and a sixth input port, and the fifth input port and the sixth input port are used to input the third data; The two input terminals of the first selection module are connected to the first input port and the second input port respectively, and the output terminal is connected to the first data input terminal of the calculation unit; The two input terminals of the second selection module are connected to the third input port and the fourth input port respectively, and the output terminal is connected to the second data input terminal of the calculation unit; The control end of the first selection module is used to input the first selection signal, and the control end of the second selection module is used to input the second selection signal; The third group of input ports is connected to a third data input terminal of the calculation unit.

5. The processing unit in the systolic array of claim 4 , wherein the computing unit comprises: a first processing unit, configured to process the first data inputted from the first data input terminal and the second data inputted from the second data input terminal to generate the third data; a second processing unit, configured to select and output third data transmitted to the third data input terminal based on the first selection signal; a third processing unit, configured to select and output the third data output by the first processing unit or the third data output by the second processing unit based on a third selection signal; The fourth processing unit is used to select, based on the third selection signal, to store the third data output by the first processing unit and output it to the first processing unit, or to store the third data output by the second processing unit and output it to the processing unit.

6. The processing unit in the systolic array of claim 5 , wherein the computing unit further comprises: an output signal generating module, configured to generate the third selection signal based on an end signal transmitted by the first data transmission path and / or the second data transmission path, wherein an output end of the output signal generating module is connected to a selection signal input end of the third processing unit, and the third processing unit outputs the third data input from the third group of input ports based on the third selection signal; The end signal indicates that the data processing task of the processing unit in the systolic array has been completed.

7. The processing unit in the systolic array of claim 4 , further comprising: a first selection signal generating module, configured to generate a corresponding first selection signal based at least on signal input states of two input terminals of the first selection module; The selection signal output terminal of the first selection signal generating module is connected to the control terminal of the first selection module and the first selection signal input terminal of the calculation unit; a second selection signal generating module, configured to generate a corresponding second selection signal based at least on the signal input states of the two input terminals of the second selection module; a selection signal output terminal of the second selection signal generating module being connected to a control terminal of the second selection module; wherein the first selection signal generating module is configured to generate a first sub-selection signal when the first input port first receives the first data, so that the first selection module selects the first data transmission path to transmit the first data, and the third data input terminal of the computing unit selects to input the third data output by the second data output path; and is configured to generate the first sub-selection signal or the second sub-selection signal based on the signal input states of the two input terminals of the first selection modules of other processing units when the second input port first receives the first data, and when the first selection signal generating module outputs the second sub-selection signal, the first selection module selects the second data transmission path to transmit the first data, and the third data input terminal of the computing unit selects to input the third data output by the first data output path; The second selection signal generating module is used to generate a third sub-selection signal when the third input port first receives the second data, so that the second selection module selects the third data transmission path to transmit the second data, and when the fourth input port first receives the second data, based on the signal input status of the two input ends of the second selection module of other processing units, generate the third sub-selection signal or the fourth sub-selection signal, and when the second selection signal generating module outputs the fourth sub-selection signal, the second selection module selects the fourth data transmission path to transmit the second data.

8. The processing unit according to claim 7, further comprising: a first delay module, wherein two input terminals of the first delay module are respectively connected to the first input port and the second input port, and two output terminals are respectively connected to the two input terminals of the first selection module, and are used to delay the first data by one cycle and output it to the first selection module; a second delay module, wherein the two input terminals of the second delay module are respectively connected to the third input port and the fourth input port, and the two output terminals are respectively connected to the two input terminals of the second selection module, and are used to delay the second data by one cycle and output it to the second selection module; The two input ends of the first selection signal generating module are respectively connected to the two input ends of the first delay module, and the two input ends of the second selection signal generating module are respectively connected to the two input ends of the second delay module.

9. A systolic array comprising 2n×2n processing units, where n is greater than 1, the processing units having a first set of data transmission paths for transmitting data in a first dimension, a second set of data transmission paths for transmitting data in a second dimension, and a third set of data transmission paths for transmitting data in the first dimension; wherein The first group of data transmission paths includes a first data transmission path for transmitting data in a first direction and a second data transmission path for transmitting data in a second direction; The second group of data transmission paths includes a third data transmission path that transmits data along a third direction and a fourth data transmission path that transmits data along a fourth direction; The third set of data transmission paths includes a first data output path that transmits data along a first direction and a second data output path that transmits data along a second direction.

10. The systolic array of claim 9, wherein the systolic array comprises four systolic matrices arranged in a matrix, wherein a first systolic matrix comprises processing units located in rows 1 to n and columns 1 to n, a second systolic matrix comprises processing units located in rows 1 to n and columns (n+1) to 2n, a third systolic matrix comprises processing units located in rows (n+1) to 2n and columns 1 to n, and a fourth systolic matrix comprises processing units located in rows (n+1) to 2n and columns (n+1) to 2n. The processing unit at row 1, column 1 is the first processing unit in the first systolic matrix; the processing unit at row 1, column n+1 and the processing unit at row 1, column 2n are the first processing units in the second systolic matrix; the processing unit at row n+1, column 1 and the processing unit at row 2n, column 1 are the first processing units in the third systolic matrix; the processing unit at row n+1, column n+1 and the processing unit at row 2n, column 2n are the first processing units in the fourth systolic matrix; and the remaining processing units are second processing units. The first processing unit generates a first selection signal based on input states of data input ports of its first group of data transmission paths and input states of data input ports of first groups of data transmission paths of other first processing units in the same systolic matrix, and selects, based on the first selection signal, first data transmitted in the first group of data transmission paths to be input and output to a downstream processing unit through the first group of data transmission paths, and third data transmitted in the third group of data transmission paths to be input and transmitted to a downstream processing unit through the third group of data transmission paths; The first processing unit further generates a second selection signal based on input states of data input ports of its second group of data transmission paths and input states of data input ports of the second group of data transmission paths of other first processing units in the same systolic matrix, and selects second data to be input into the second group of data transmission paths based on the second selection signal, and outputs the second data to a downstream processing unit through the second group of data transmission paths. The second processing unit selects, based on the first selection signal and the second selection signal output by the first processing unit in the same systolic matrix, the first data transmitted in the first group of data transmission paths and the second data transmitted in the second group of data transmission paths as input, and outputs the data to the downstream processing unit through the first group of data transmission paths and the second group of data transmission paths, and selects the third data transmitted in the third group of data transmission paths as input, and transmits the third data to the downstream processing unit through the third group of data transmission paths.

11. The systolic array of claim 9, wherein the systolic array comprises four systolic matrices arranged in a matrix, wherein a first systolic matrix comprises processing units located in rows 1 to n and columns 1 to n, a second systolic matrix comprises processing units located in rows 1 to n and columns (n+1) to 2n, a third systolic matrix comprises processing units located in rows (n+1) to 2n and columns 1 to n, and a fourth systolic matrix comprises processing units located in rows (n+1) to 2n and columns (n+1) to 2n. The processing unit at row 1, column 1 is the first processing unit in the first systolic matrix, the processing unit at row 1, column 2n is the first processing unit in the second systolic matrix, the processing unit at row 2n, column 1 is the first processing unit in the third systolic matrix, the processing unit at row 2n, column 2n is the first processing unit in the fourth systolic matrix, and the remaining processing units are second processing units. The first processing unit generates a first selection signal based on an input state of a data input port of a first group of data transmission paths, and selects, based on the first selection signal, first data transmitted in the first group of data transmission paths to be input and output to a downstream processing unit via the first group of data transmission paths, and selects third data transmitted in the third group of data transmission paths to be input and transmitted to a downstream processing unit via the third group of data transmission paths; The first processing unit generates a second selection signal based on an input state of a data input port of its second group of data transmission paths, and selects second data to be input into the second group of data transmission paths based on the second selection signal, and outputs the second data to a downstream processing unit via the second group of data transmission paths; The second processing unit selects, based on the first selection signal and the second selection signal output by the first processing unit in the same systolic matrix, the first data transmitted in the first group of data transmission paths and the second data transmitted in the second group of data transmission paths as input, and outputs the first data to the downstream processing unit through the first group of data transmission paths and the second group of data transmission paths, and selects, based on the first selection signal and the second selection signal output by the first processing unit in the same systolic matrix as the second processing unit, the third data transmitted in the third group of data transmission paths as input, and transmits the third data to the downstream processing unit through the third group of data transmission paths.

12. The systolic array of claim 10 or 11, comprising a first processing unit and a second processing unit adjacent to each other in a first dimension, wherein a first output port of the first processing unit is connected to a first input port of the second processing unit, a second input port of the first processing unit is connected to a second output port of the second processing unit, a fifth output port of the first processing unit is connected to a fifth input port of the second processing unit, and a sixth input port of the first processing unit is connected to a sixth output port of the second processing unit; The systolic array includes a first processing unit and a second processing unit adjacent to each other in a second dimension, the third output port of the first processing unit is connected to the third input port of the second processing unit, and the fourth input port of the first processing unit is connected to the fourth output port of the second processing unit.

13. An electronic device comprising a systolic array according to any one of claims 9 to 12 or a systolic array composed of processing units in the systolic array according to any one of claims 1 to 8.

14. A data processing method, applied to a systolic array, the systolic array comprising 2n×2n processing units, the processing units having a first group of data transmission paths for transmitting data in a row direction, a second group of data transmission paths for transmitting data in a column direction, and a third group of data transmission paths for transmitting data in a row direction, the first group of data transmission paths transmitting first data, the second group of data transmission paths transmitting second data, and the third group of data transmission paths transmitting third data; each group comprising two data transmission directions; The systolic array includes four systolic matrices arranged in a matrix, each systolic matrix includes n*n processing units, the processing unit located in the 1st row and the 1st column is the first processing unit in the first systolic matrix, the processing unit located in the 1st row and the 2nth column is the first processing unit in the second systolic matrix, the processing unit located in the 2nth row and the 1st column is the first processing unit in the third systolic matrix, and the processing unit located in the 2nth row and the 2nth column is the first processing unit in the fourth systolic matrix; The data processing method includes: At a first moment, the processing units in the first systolic matrix are controlled to transmit first data through the first data transmission path and simultaneously transmit second data through the third data transmission path. The processing units in the second systolic matrix are controlled to transmit first data through the second data transmission path and simultaneously transmit second data through the third data transmission path. The processing units in the third systolic matrix are controlled to transmit first data through the first data transmission path and simultaneously transmit second data through the fourth data transmission path. The processing units in the fourth systolic matrix are controlled to transmit first data through the second data transmission path and simultaneously transmit second data through the fourth data transmission path.

15. The data processing method according to claim 14, wherein the processing unit located at the 1st row and the n+1th column is also the first processing unit in the second systolic matrix, the processing unit located at the n+1th row and the 1st column is also the first processing unit in the third systolic matrix, and the processing unit located at the n+1th row and the n+1th column is also the first processing unit in the fourth systolic matrix.

16. The data processing method according to claim 14 or 15, wherein in a first systolic matrix, along the row direction, second data of each column starting from the first column in the second data matrix are input to the first-row processing units of each subsequent column one cycle later, and each second data in the second data array of each column is transferred row by row to the processing units of the subsequent row according to the data transmission cycle; simultaneously, along the column direction, first data of each row starting from the first row in the first data matrix are input to the first-row processing units of each subsequent row one cycle later, and each first data in the first data array of each row is transferred column by column to the processing units of the subsequent column according to the data transmission cycle; In the second systolic matrix, along the row direction, starting from the 2nth column, the second data of each column of the second data matrix starting from the last column is input to the first row processing units of the previous columns one cycle later, and each second data in each column of the second data array is transferred row by row to the processing units of the next row according to the data transfer cycle. Simultaneously, along the column direction, the same first data is synchronously input to the last column processing units of each row, synchronously and symmetrically with the first systolic matrix, and transferred forward column by column according to the data transfer cycle. In the third systolic matrix, along the row direction, the same second data is synchronously and symmetrically input to the last-row processing units of each column, and is transferred forward row by row according to the data transmission cycle, synchronously and symmetrically with the first systolic matrix. Simultaneously, along the column direction, starting from the 2nth row, the first data of each row of the first data matrix, starting from the last row, is input to the first-column processing units of each preceding row one cycle later, and each first data in the first data array of each row is transferred column by column to the processing units of the succeeding column according to the data transmission cycle. In the fourth systolic matrix, along the row direction, the same second data is synchronously input to the last-row processing unit of each column in a manner that is synchronous and symmetrical with that in the second systolic matrix, and is forwarded row by row according to the data transmission cycle. Simultaneously, along the column direction, the same first data is synchronously input to the last-column processing unit of each row in a manner that is synchronous and symmetrical with that in the third systolic matrix, and is forwarded column by column according to the data transmission cycle.

17. The data processing method according to claim 16, further comprising selecting a data transmission path in a corresponding direction of the systolic matrix according to a data input state of the first processing unit in each systolic matrix, so that each processing unit in the same systolic matrix selects the same data transmission direction.

18. The data processing method according to claim 16, further comprising: After the processing unit in the kth row and kth column outputs the third signal, the third data stored in the processing unit in the kth row and kth column is output, and the third signal indicates that the data processing process in the processing unit in the kth row and kth column is completed, where k is an integer not less than 1 and not greater than 2n.

19. An electronic device comprising: A systolic array, a processor, and a memory, wherein the systolic array is the systolic array according to any one of claims 9 to 12; the memory is used to store a computer program; and the processor is used to execute the computer program so that the electronic device can implement the data processing method according to any one of claims 14 to 18.

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