All-organic LIF neuron circuit

Abstract

The invention relates to an LIF neuron circuit based on an organic semiconductor device, which comprises an OECT device, an organic resistor and a hysteresis comparator based on an organic field effect transistor (OFET), and the OECT device performs behavioral modeling based on an ion accumulation / relaxation model, a compact model of a thin film transistor and a Steamn capacitance model; the drain electrode of the OECT device is used for receiving an excitation signal; the two ends of the resistor element are connected with the source electrode of the OECT element and the ground, the hysteresis comparator is composed of an OFET, the input end of the hysteresis comparator is connected with the source electrode of the OECT element to receive signals output by the OECT element, output signals of the comparator are output signals of the neuron circuit, and the output end of the hysteresis comparator is connected with the grid electrode of the OECT to form a feedback path. According to the invention, integration, leakage and distribution functions of the LIF neuron model are realized, the structure is simple, and the method has the advantages of high biological similarity, full organic realization and the like.

Description

TECHNICAL FIELD

[0001] The present application belongs to the cross field of semiconductor microelectronic devices and artificial intelligence, and particularly relates to a full-organic LIF neuron circuit. BACKGROUND

[0002] In recent years, brain-inspired computing has attracted extensive attention in the fields of artificial intelligence, neuromorphic chips, and flexible electronic systems. Spiking Neural Network (SNN) is a model that simulates the behavior of biological neurons and synapses, and has advantages such as high parallelism, low power consumption, and strong robustness. LIF (Leaky Integrate-and-Fire) model is one of the most commonly used neuron models, and its key behaviors include the integration of membrane potential, leakage, and firing and resetting after reaching the threshold.

[0003] The hardware implementation of traditional LIF neurons usually uses memristor devices or CMOS circuits. However, the memristor has uncontrollability in the transition of conductive state, making it difficult to achieve precise time coding. The CMOS circuit structure is complex and has high power consumption, which is not suitable for flexible or implantable systems.

[0004] Organic electronic materials have many advantages such as low manufacturing cost, good mechanical flexibility, and good biocompatibility. Among them, organic electrochemical transistors stand out due to their potential in various biological applications, and are therefore suitable for building new neuron circuits. Existing organic device neurons rely on ideal capacitors or still need to be mixed with CMOS to build, resulting in increased system complexity and process incompatibility. SUMMARY

[0005] To achieve the above purpose, the technical scheme of the present application is as follows: a full-organic LIF neuron circuit, comprising an OECT device module, the input end of the OECT device module receiving an excitation signal, and the output end outputting a membrane potential signal; a resistance element connected in series with the source of the OECT device module; a hysteresis comparator, the input end of the hysteresis comparator connected to the source of the OECT device module and receiving the membrane potential signal input, and the output end connected to the gate of the OECT device module, the output signal being the output signal of the neuron circuit; wherein the comparator and the OECT device module form a closed-loop feedback path.

[0006] Preferably, the OECT device module includes a double-layer capacitor model for simulating proton accumulation and depletion behavior, and has a double-layer effect.

[0007] Preferably, the gate of the OECT device module can receive different pulse frequencies or amplitudes to realize short-term synaptic plasticity simulation.

[0008] Preferably, the resistive element is used to convert the source current of the OECT device module into a membrane potential voltage signal.

[0009] Preferably, the hysteresis comparator module is composed of 6 organic field effect transistors.

[0010] Preferably, the hysteresis comparator has two threshold voltages, respectively, an up threshold and a down threshold.

[0011] Preferably, the output pulse width of the hysteresis comparator is determined by the voltage interval between the up threshold and the down threshold.

[0012] Preferably, the hysteresis comparator output enables the OECT gate to obtain a reset voltage to complete the reset operation.

[0013] Preferably, all elements in the circuit are made of organic materials.

[0014] Preferably, the OECT model is implemented by Verilog-A language and is compatible with SPICE simulation tools.

[0015] The beneficial effects of the present application relative to the prior art are: (1) In the modeled organic electrochemical transistor, under the action of a negative gate voltage, due to the design of a real capacitor model, the capacitor of the entire device can be regarded as the series connection of two double-layer capacitors; by using different pulse voltage excitations, the bionic function of the neural synapse is simulated, and the organic electrochemical transistor can realize several important functions of the neural synapse, such as double-pulse facilitation (PPF), short-term enhancement or inhibition (STP / STD), and can successfully simulate the learning and memory functions of the neural synapse; (2) A hysteresis comparator based on OFET is proposed to replace the traditional CMOS circuit and the memristor, while maintaining the discharge decision and reset control functions of the neuron, the LIF neuron circuit is fully organic. It is helpful to deploy in wearable application scenarios.

[0016] (3) The designed LIF neuron circuit can accurately respond to external pulse input, and the response speed can match the mammalian cerebral cortex neurons, and has wide application prospects in time coding neural networks, wearable neural electronic devices, and high-density neuron chips. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 The neuron circuit structure schematic diagram provided for the embodiments of the present application; Figure 2 The hysteresis comparator structure schematic diagram provided by the present application; Figure 3A schematic diagram of transient response characteristics of the OECT device model provided by the application under single pulse excitation is shown in the figure; Figure 4 A graph of output potential response curves of each node of the neuron circuit provided by the application under continuous voltage pulse input is shown in the figure. DETAILED DESCRIPTION

[0018] The application will be further clarified by the following embodiments and specific examples, which should not be construed as limiting the scope of the application.

[0019] Embodiment: As shown in the figure, the neuron circuit provided by the application comprises an OECT device model M1, a series resistor R1, and a hysteresis comparator module C1 based on an OFET device. Figure 1

[0020] Further, the drain of the OECT device M1 is connected to the input end IN, and the source is grounded through the resistor R1 to realize current-to-voltage conversion, and then the source serves as the output end to output the membrane potential VMEM.

[0021] Further, the gate of the OECT is connected to the output end of the hysteresis comparator C1, forming a feedback path, and the feedback signal is used for resetting the membrane potential of the OECT.

[0022] During the working process of the circuit, when the input end accepts a negative pulse signal, the accumulation behavior of simulated protons at the electrolyte / channel interface in the OECT model causes the source potential VMEM to gradually rise, realizing time integration and simulating the integral behavior of the membrane potential of the LIF model.

[0023] During the input pulse interval, protons diffuse or interface potential relaxes, causing the source potential VMEM to gradually decrease, simulating the leakage behavior of the membrane potential in the LIF model.

[0024] Because the pulse interval is very short, the protons caused by the first pulse have not returned to their initial state before the second pulse arrives, so the overall VMEN voltage gradually rises.

[0025] In the initial initial state, VMEM is lower than the rising threshold set by the hysteresis comparator module C1, at which time the comparator C1 outputs a low level (such as VSS), and this signal is applied to the gate of the OECT, and the resulting channel-to-gate electric field will accumulate the interface protons, thereby causing the VMEM amplitude to gradually rise.

[0026] ​When VMEM rises to the rising threshold set by the hysteresis comparator module C1, the comparator C1 outputs a high level (such as VDD), and the signal is applied to the OECT gate. The resulting electric field from the channel to the gate depletes the protons accumulated at the interface, causing VMEM to quickly drop to a low voltage state.

[0027] Subsequently, when VMEM drops below the set falling threshold, the comparator output returns to a low level, completing the reset process, and the circuit prepares for the next round of integration.

[0028] Furthermore, if Figure 2 As shown, the input end of the hysteresis comparator module is connected to VMEM, and the output end is connected to the gate end of the OECT. It is composed of 6 OFETs, including: PMOS tube M0, PMOS tube M1, NMOS tube M2, NMOS tube M3, PMOS tube M4 and NMOS tube M5, wherein the gates of M0, M1, M2 and M3 are all connected to the input end; the source of the PMOS tube M0 is connected to the power supply VDD, and its drain is respectively connected to the source of M1 and the gate of M5; the gate of the PMOS tube M1 is connected to the input end Vin, its source is connected to the drain of M0, and its drain is respectively connected to the gate of M2 The drain of NMOS transistor M2 is connected to the drain of M1, and its source is connected to the drain of M3; the drain of NMOS transistor M3 is connected to the source of M2, and its source is connected to VSS; the drain of PMOS transistor M4 is connected to the power supply VDD, its source is connected to the node formed by the source of M2 and the drain of M3, and its gate is connected to the node formed by the drain of M1 and the drain of M2, which is also the output of the comparator; the gate of NMOS transistor M5 is connected to the output of the comparator, its source is connected to the node formed by the drain of M0 and the source of M1, and its drain is connected to VSS. The operating voltage of the hysteresis comparator is the power supply voltage VDD and VSS respectively. It has two threshold voltages, corresponding to rising trigger and falling trigger respectively. The pulse width of the comparator output is determined by the threshold difference. Setting two different thresholds can ensure that the width of the reset pulse is sufficient, VMEM is fully reset, and false triggering is avoided.

[0029] It should be noted that the above content merely illustrates the technical idea of ​​the present invention and cannot be used to limit the scope of protection of the present invention. For ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications all fall within the scope of protection of the claims of the present invention.

Claims

1. An all-organic LIF neuron circuit, characterized by: It includes an OECT device module, the input end of the OECT device module receives an excitation signal, and the output end outputs a membrane potential signal; a resistor element, the resistor element is connected in series with the source of the OECT device module; a hysteresis comparator, the input end of the hysteresis comparator is connected to the source of the OECT device module, receives the membrane potential signal input, the output signal is the output signal of the neuron circuit, and the output end is connected to the gate of the OECT device module; wherein the comparator and the OECT device module constitute a closed-loop feedback path.

2. The all-organic LIF neuron circuit according to claim 1, characterized in that: The OECT device module includes a double-layer capacitance model for simulating proton accumulation and depletion behavior.

3. The all-organic LIF neuron circuit according to claim 1, characterized in that: The gate of the OECT device module can receive different pulse frequencies or amplitudes to achieve short-term synaptic plasticity simulation.

4. The all-organic LIF neuron circuit according to claim 1, characterized in that: The resistor element is used to convert the source current of the OECT device module into a membrane potential voltage signal.

5. The all-organic LIF neuron circuit according to claim 1, characterized in that: The hysteresis comparator module is composed of 6 organic field effect transistors.

6. The all-organic LIF neuron circuit according to claim 1, characterized in that: The hysteresis comparator has two threshold voltages, namely a rising threshold and a falling threshold.

7. The all-organic LIF neuron circuit according to claim 1, characterized in that: The output pulse width of the hysteresis comparator is determined by the voltage interval between the rising threshold and the falling threshold.

8. The all-organic LIF neuron circuit according to claim 1, characterized in that: The hysteresis comparator outputs a signal so that the OECT gate obtains a reset voltage to complete a reset operation.

9. The all-organic LIF neuron circuit according to any one of claims 1 to 8, characterized in that: All components in the circuit are made of organic materials.

10. The all-organic LIF neuron circuit according to claim 1, characterized in that: The OECT device module is implemented using Verilog-A language and is compatible with SPICE simulation tools.

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