Etching simulation method, and etching simulation model training method and device

Abstract

The embodiment of the invention provides an etching simulation method and an etching simulation model training method and device, and the method comprises the steps: carrying out the photoetching simulation of a target wafer through a photoresist model through a joint model, and determining a photoetching simulation image. And carrying out etching simulation on the photoetching simulation image and the etching material distribution data through an etching simulation model obtained by training through an etching simulation model training method, and simulating an etching simulation image of the target wafer. According to the technical scheme of the invention, the method can achieve the high-efficiency and real-condition-fitting etching simulation for the target wafer, and greatly improves the production efficiency and precision of a chip through the integrated simulation process of photoetching and etching. According to the method, the etching material distribution data is introduced in the etching simulation process, the influence of different etching materials on the etching process in the real etching process is accurately restored, the accuracy and practicability of the etching simulation process are improved, and the chip yield and the performance strength of the chip in the actual production process are further improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor process, and particularly relates to an etching simulation method, an etching simulation model training method and device. BACKGROUND

[0002] In the field of chip production and manufacturing, etching is a process closer to the final chip output, and the processing precision and efficiency of the etching process have important influence on the overall chip production process.

[0003] Through pre-etching simulation, various parameters and data in the etching process can be effectively deployed to ensure the efficiency and accuracy of the actual etching process. At present, the mainstream method for etching simulation is mostly to construct an etching transfer function, and to simulate the wafer etching process based on the transfer function. This method needs to collect a large amount of etching data for function fitting, which consumes a large amount of time cost and resources, and the processing efficiency of actual etching simulation is also low. Moreover, the etching simulation based on the transfer function has poor practicability and accuracy, and cannot accurately simulate the real etching result of the wafer, resulting in errors in the size of the wafer after actual etching, and further affecting the chip yield and performance of the chip production process.

[0004] Therefore, how to realize efficient and accurate etching simulation is an important problem to be solved. SUMMARY

[0005] The embodiments of the present application provide an etching simulation method, an etching simulation model training method and device, which can perform efficient and accurate etching simulation on wafers.

[0006] In a first aspect, the embodiments of the present application provide an etching simulation method, which is applied to a joint model composed of a photoresist model and an etching simulation model, the output of the photoresist model is connected to the input of the etching simulation model, and the method comprises the following steps.

[0007] Obtaining a mask plate image and etching material distribution data of a target wafer;

[0008] Performing photoetching simulation on the mask plate image based on the photoresist model to obtain a photoetching simulation image of the target wafer;

[0009] Performing etching simulation on the photoetching simulation image and the etching material distribution data based on the etching simulation model to obtain an etching simulation image of the target wafer.

[0010] In a second aspect, the embodiments of the present application provide an etching simulation device, which comprises:

[0011] An obtaining unit, configured to obtain a mask plate image and etching material distribution data of a target wafer;

[0012] A photoetching simulation unit is configured to perform photoetching simulation on the mask pattern based on a photoresist model to obtain a photoetching simulation image of the target wafer;

[0013] An etching simulation unit is configured to perform etching simulation on the photoetching simulation image and the etching material distribution data based on an etching simulation model to obtain an etching simulation image of the target wafer.

[0014] In a third aspect, an embodiment of the present application provides an etching simulation model training method, including:

[0015] obtaining sample mask pattern and etching material distribution sample data of a sample wafer, and determining standard size data of the sample wafer;

[0016] performing photoetching simulation on the sample mask pattern based on a pre-trained photoresist model in a joint model to determine a photoetching simulation sample image of the sample wafer, the joint model being composed of the photoresist model and an etching simulation model to be trained, and an output of the photoresist model being connected to an input of the etching simulation model to be trained;

[0017] performing etching simulation on the photoetching simulation sample image and the etching material distribution sample data based on the etching simulation model to be trained to determine an etching simulation sample image of the sample wafer;

[0018] determining simulation size data of the sample wafer according to the etching simulation sample image;

[0019] determining etching loss according to the simulation size data and the standard size data;

[0020] training the etching simulation model to be trained according to the etching loss.

[0021] In a fourth aspect, an embodiment of the present application provides an etching simulation model training device, including:

[0022] a sample obtaining unit configured to obtain sample mask pattern and etching material distribution sample data of a sample wafer, and determine standard size data of the sample wafer;

[0023] a photoetching training unit configured to perform photoetching simulation on the sample mask pattern based on a pre-trained photoresist model in a joint model to determine a photoetching simulation sample image of the sample wafer, the joint model being composed of the photoresist model and an etching simulation model to be trained, and an output of the photoresist model being connected to an input of the etching simulation model to be trained;

[0024] an etching training unit configured to perform etching simulation on the photoetching simulation sample image and the etching material distribution sample data based on the etching simulation model to be trained to determine an etching simulation sample image of the sample wafer;

[0025] A size determination unit is configured to determine simulation size data of the sample wafer according to the etching simulation sample image.

[0026] A loss determination unit is configured to determine etching loss according to the simulation size data and the standard size data.

[0027] A model training unit is configured to perform model training on the etching simulation model to be trained according to the etching loss.

[0028] In a fifth aspect, an electronic device is provided, which includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, and the program or instructions are executed by the processor to implement the steps of the etching simulation method or the etching simulation model training method according to any of the embodiments of the present application.

[0029] In a sixth aspect, a readable storage medium is provided, and the readable storage medium stores a program or instructions, and the program or instructions are executed by a processor to implement the steps of the etching simulation method or the etching simulation model training method according to any of the embodiments of the present application.

[0030] In a seventh aspect, a computer program product is provided, and instructions in the computer program product are executed by a processor of an electronic device to enable the electronic device to perform the steps of the etching simulation method or the etching simulation model training method according to any of the embodiments of the present application.

[0031] The technical solutions provided by the embodiments of the present application at least bring the following beneficial effects:

[0032] The etching simulation method and the etching simulation model training method provided by the embodiments of the present application include: the etching simulation model training process can be used to train an etching simulation model with precise etching simulation capability, and the trained etching simulation model and the pre-trained photolithography simulation model can be combined to obtain a joint model for photolithography and etching integration in the actual etching simulation process. Specifically, the photolithography simulation of the target wafer can be performed through the photoresist model, so as to determine the photolithography simulation image of the target wafer. Then, the etching simulation model can be used to perform etching simulation on the photolithography simulation image generated by the photoresist model and the etching material distribution data corresponding to the target wafer, so as to accurately simulate the etching simulation image of the target wafer.

[0033] The technical scheme provided by the embodiment of the present application can realize efficient and real situation fitting etching simulation for a target wafer, and the simulation process of lithography and etching integration can greatly improve the chip production efficiency and precision. In addition, the etching material distribution data is introduced in the etching simulation process in the present application, which accurately restores the influence of different etching materials on the etching process in the real etching process, improves the accuracy and practicality of the etching simulation process, and further improves the chip yield and performance strength in the actual chip production process.

[0034] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical scheme of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly introduced below. Those skilled in the art can also obtain other drawings according to these drawings without creating creative labor.

[0036] Figure 1 A flowchart of an etching simulation method provided by an embodiment of the present application;

[0037] Figure 2 A structural diagram of a module for determining a base feature map in an etching simulation model provided by an embodiment of the present application;

[0038] Figure 3 A structural diagram of a module for determining a receptive field enhanced feature map in an etching simulation model provided by an embodiment of the present application;

[0039] Figure 4 A flowchart of an etching simulation model training method provided by an embodiment of the present application;

[0040] Figure 5 A flowchart of a photoresist model training process provided by an embodiment of the present application;

[0041] Figure 6 A structural diagram of an etching simulation device provided by another embodiment of the present application;

[0042] Figure 7 A structural diagram of an etching simulation model training device provided by another embodiment of the present application;

[0043] Figure 8 A hardware structural diagram of a terminal device provided by still another embodiment of the present application. DETAILED DESCRIPTION

[0044] The features and exemplary embodiments of the various aspects of the present application will be described in detail below with reference to the drawings. For the purpose of clarity, the description is divided into the following sections: technical field, brief description of the drawings, detailed description of the embodiments, and conclusion. It should be noted that the specific embodiments described herein are intended to be illustrative only and are not to be limiting of the present application. The present application can be implemented in ways not described herein without departing from the spirit and scope of the present application. The following description is presented to enable any person skilled in the art to make and use the present application.

[0045] It should be noted that the terms such as first and second, etc., are merely used to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between such entities or operations. Also, the terms "comprises", "comprising", or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by an "includes" statement does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0046] Etching is one of the most important steps in the production and manufacturing process of chips, and the processing efficiency and precision of the etching process have a significant impact on the performance and yield of the final produced chips. Etching simulation can predict and adjust the etching parameters and data in the real etching process in advance, thereby improving the processing efficiency and etching precision of the wafer etching process.

[0047] Today's traditional etching method for wafers mostly fits and constructs an etching transfer function according to the collected etching parameters and data, and realizes the wafer etching simulation process through the transfer function. This method needs to collect a large amount of etching data through a pre-set sensor device, and a series of processing and calculation are needed for the data to determine the etching transfer function which is not necessarily accurate.

[0048] The simulation of the wafer etching process by the above method consumes a lot of time and resource cost, resulting in a decrease in the processing efficiency of the etching simulation process, and the constructed etching transfer function does not necessarily conform to the real etching process, the etching precision cannot be guaranteed, and the etching error is serious, which will seriously affect the chip quality and production yield of the chips produced subsequently.

[0049] To solve the above technical problems, the embodiments of the present application provide an etching simulation method, an etching simulation model training method and device. The etching simulation method specifically includes: first, the joint model can perform photoetching simulation on the mask plate graph of the target wafer through the photoresist model, and accurately simulate the photoetching simulation image of the target wafer.

[0050] Then, the joint model can perform etching simulation on the target wafer according to the photoetching simulation image and the etching material distribution data corresponding to the target wafer through the etching simulation model, and determine the etching simulation image of the target wafer. The etching simulation image can be used to adjust the etching parameters and other data in the real etching process, so that the etching pattern that accurately meets the etching requirements can be etched on the wafer surface in the subsequent real etching process. The etching simulation model can be trained by the etching simulation model training method.

[0051] The technical scheme provided by the embodiments of the present application can realize efficient and real etching simulation for the target wafer. The integrated simulation process of photoetching and etching can greatly improve the chip production efficiency and precision, and provide important help for the optimization of wafer mask and the improvement of etching precision.

[0052] In addition, in the etching simulation process in the present application, the etching material distribution data on the wafer surface is ingeniously introduced, so that the potential influence of different etching materials on the wafer etching process in the real etching process can be accurately restored, the accuracy and practicability of the etching simulation process are significantly improved, practical data are provided for the subsequent actual etching process, and the chip yield and performance strength in the actual chip production process are improved.

[0053] Among them, regarding the execution subject of the technical scheme in the embodiments of the present application, the execution subject of the etching simulation method can be a joint model composed of the etching simulation model and the photoetching simulation model after model training. The etching simulation model training method can be a terminal device, such as a desktop computer, a notebook computer, etc., or a remote device, such as a server, etc.

[0054] In addition, the execution subject of the etching simulation model training method can also be an execution subject in the form of software, such as a client, a software program, etc. installed in a terminal device. The specific type of the execution subject applying the etching simulation model training method provided by the embodiments of the present application is not strictly limited, and can be flexibly selected and applied according to the application scene and actual demand.

[0055] In addition, the actual application scene of the etching simulation method and device provided by the embodiments of the present application is not strictly limited, and can be flexibly selected and applied according to the actual demand.

[0056] For example, in a scenario where parameters are pre-set for the actual etching process of a wafer, the technical solution provided by the embodiments of the present application can determine a photolithography simulation image of the wafer using a photoresist model based on the wafer's mask layout. Then, based on the photolithography simulation image and the corresponding etched material distribution data of the wafer, the etching simulation model of the embodiments of the present application can be used to perform an etching simulation on the wafer for which etching parameters need to be set, thereby determining the wafer's etching simulation image.

[0057] The simulated etching images accurately predict the actual etching process results for wafers requiring etching parameter settings. Based on these images, parameters in the actual etching process can be adjusted effectively and promptly. They can also be used to optimize the etching simulation model, significantly improving the etching efficiency and accuracy of the wafer during the actual etching process. This improvement in etching accuracy and speed will also enhance the efficiency, quality, and yield of the overall chip production process.

[0058] It should be noted that the application scenarios described in the above embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that, with the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems. The etching simulation method provided in the embodiments of the present application can be applied to various application scenarios requiring efficient and accurate etching simulation of wafers.

[0059] The following is a detailed introduction to the etching simulation method provided by this application:

[0060] Figure 1 A schematic flow chart of an etching simulation method provided in one embodiment of the present application.

[0061] like Figure 1 As shown in , the etching simulation method provided in the embodiment of the present application includes steps S101 to S103.

[0062] S101: Obtaining the mask layout and etching material distribution data of the target wafer.

[0063] S102: Based on the photoresist model, perform photolithography simulation on the mask layout to obtain a photolithography simulation image of the target wafer.

[0064] S103: Based on the etching simulation model, perform etching simulation on the photolithography simulation image and the etching material distribution data to obtain an etching simulation image of the target wafer.

[0065] The etching simulation method provided in the embodiments of the present application can be applied to a joint model combined by an etching simulation model trained by a model and a lithography simulation model. The output of the lithography simulation model is connected to the input of the etching simulation model, so that the joint model combined can realize the function of integrated simulation of lithography and etching.

[0066] In step S101, the joint model applying the technical solution provided in the embodiments of the present application can first obtain the mask plate graph and the etching material distribution data corresponding to the target wafer, and input the mask plate graph and the etching material distribution data into the joint model composed of the photoresist model and the etching simulation model. The joint model can input the received mask plate graph into the photoresist model to perform lithography simulation on the target wafer, and the etching material distribution data can be input into the etching simulation model for subsequent etching simulation on the target wafer.

[0067] The mask plate graph corresponding to the target wafer contains the mask pattern that needs to be lithographed on the photoresist layer of the target wafer in the lithography simulation process. The etching material distribution data contains the distribution of the etching material on the surface of the target wafer in the etching simulation process of the target wafer, and the specific data form can be an etching material distribution graph.

[0068] Each target chip on the target wafer can be stacked by multiple layers of structures, and the material of each layer of chip is used to realize different functions, such as conduction, insulation, heat insulation, etc. Therefore, the etching material required in the etching stage also needs to be corresponding to the function and wafer area, so as to ensure that each target chip on the target wafer after etching can have normal performance.

[0069] It should be noted that the specific content of the etching material distribution data is not strictly limited in the embodiments of the present application, and can be set according to the wafer type corresponding to the target wafer and the actual process parameters.

[0070] For example, in some embodiments, when performing Fin Field-Effect Transistor (FinFET) gate etching simulation on the target wafer, the etching material distribution data can specifically contain the etching material stack structure corresponding to the silicon / silicon germanium heterostructure (Si / SiGe).

[0071] The etching material stack structure can be composed of, from top to bottom, a 100-nm photoresist layer, a 50-nm organic bottom anti-reflective coating (BARC), a 60-nm polycrystalline silicon (Poly-Si) gate layer, a 2-nm gate dielectric layer (for example, silicon oxynitride SiON or hafnium oxide HfO2), a 50-nm silicon fin (SiFin) layer, and a 300-nm shallow trench isolation (for example, silicon dioxide SiO2).

[0072] Based on the detailed material data of each stack layer contained in the etching material distribution data, the etching simulation can be performed on the target wafer to simulate a nanoscale gate structure on the target wafer in this embodiment.

[0073] In addition, the mask pattern and the etching material distribution data can be obtained by the joint model when obtaining the mask pattern of the target wafer. This input method can enable the lithography and etching simulation processes to be completed together by only inputting the mask pattern and the etching material distribution data, thereby significantly improving the processing efficiency of the overall etching simulation.

[0074] Alternatively, the etching material distribution data of the target wafer can be obtained after the joint model determines the lithography simulation image corresponding to the target wafer based on the mask pattern by the photoresist model, and before the lithography simulation image is input to the etching simulation model. This input method can increase the inspection operation after the lithography simulation, thereby determining whether the lithography simulation image meets the expected standard, significantly improving the accuracy and practicality of the lithography process, and also enhancing the accuracy of the etching simulation process. The input process and timing of the etching material distribution data are not strictly limited in this application, and can be flexibly limited according to actual needs and application scenarios.

[0075] The etching material distribution data introduced in the subsequent etching simulation process of the embodiment of the present application can make the etching simulation process more consistent with the real etching process of the target wafer, significantly improving the authenticity and practicality of the subsequent etching simulation image. Moreover, the joint model with lithography simulation and etching simulation capabilities can effectively improve the chip production efficiency. Only the mask pattern and the etching material distribution data need to be input to directly complete the lithography and etching simulation processes, thereby accelerating the simulation rate and improving the simulation accuracy, providing practical reference for the actual processing process.

[0076] In step S102, the joint model can implement photolithography simulation on the target wafer based on the mask pattern of the target wafer input to the joint model through the photoresist model, and further simulate a photolithography simulation image of the target wafer.

[0077] Specifically, in an embodiment provided in the present application, the spatial image corresponding to the target wafer can be accurately determined according to the mask pattern of the target wafer and the preset photolithography simulation parameters.

[0078] The photolithography simulation parameters are used to represent the corresponding photolithography process parameters of the target wafer in the photolithography simulation process, and specifically can include but are not limited to illumination conditions (such as traditional illumination, off-axis illumination, etc.), polarization modes (such as transverse electric polarization (TE), transverse magnetic polarization (TM), etc.), numerical aperture (such as can be set to 1.35), spatial image acquisition length, sampling interval of light intensity distribution, etc.

[0079] The spatial image is used to represent the light intensity distribution image projected onto the photoresist layer on the surface of the target wafer when the mask pattern is subjected to photolithography based on the photolithography simulation parameters. It should be noted that the specific manner of determining the spatial image is not strictly limited in the embodiments of the present application, and in some embodiments, the spatial image corresponding to the target wafer can be determined based on the photolithography simulation parameters and the mask pattern by, for example, the Hopkins Imaging method. In other embodiments, other feasible spatial image determination methods can be used, which can be flexibly selected and set according to application scenarios and actual needs.

[0080] Further, based on the determined spatial image corresponding to the target wafer, the photoresist model can be used to perform photolithography simulation on the target wafer. Specifically, according to the distribution of light intensity on the photoresist layer reflected by the spatial image, the photoresist model can accurately simulate the photolithography simulation image corresponding to the target wafer, and the simulated photolithography simulation image can be used for subsequent etching simulation process of the target wafer.

[0081] The above photolithography simulation process can provide a high-precision photolithography simulation image for the subsequent etching simulation process, providing a practical basis for the etching simulation process, and also significantly improving the precision and authenticity of the etching simulation image of the target wafer. The efficient and accurate photolithography simulation image also provides a practical reference basis for subsequent adjustment of the mask pattern of the target wafer, further improving the chip quality and yield of the chip production process.

[0082] The lithography simulation image corresponding to the target wafer and the etching material distribution data can be accurately obtained through steps S101 and S102, and the determined data can be used for subsequent etching simulation process of the target wafer. The introduction and use of the etching material distribution data will also significantly enhance the simulation authenticity of the etching simulation process, and effectively improve the accuracy of the etching simulation image obtained by simulation.

[0083] In step S103, the joint model can perform etching simulation on the target wafer according to the lithography simulation image and the etching material distribution data corresponding to the target wafer determined in the above steps, through the pre-trained etching simulation model, to determine the etching simulation model corresponding to the target wafer.

[0084] Specifically, in an embodiment provided by the present application, after inputting the lithography simulation image generated by the lithography simulation model and the etching material distribution data corresponding to the target wafer into the etching simulation model, the etching simulation model can perform feature extraction on the lithography simulation image and the etching material distribution data respectively, to determine a lithography feature map of the lithography simulation image, and a material distribution feature image presented in an etching material distribution map corresponding to the etching material distribution data on the target wafer. The etching material distribution map can be a material space distribution map corresponding to the etching material distribution data on the target wafer, to display the distribution of various etching materials and different stacked layers on the wafer surface.

[0085] Then, the etching simulation model can simulate and determine the etching simulation image corresponding to the target wafer according to the lithography feature map and the material distribution feature map based on the preset etching simulation rule. The lithography feature map can be used to represent the image features of the lithography simulation image, and the material distribution feature map can be used to represent the etching material distribution features corresponding to the etching material distribution data.

[0086] It should be noted that the etching simulation rule used in the etching simulation process is not strictly limited in the embodiment of the present application. In an embodiment provided by the present application, the etching simulation rule can specifically be a weighted fusion of the lithography feature map and the material distribution feature map of the target wafer with preset weights, so as to make the etching material distribution data into the lithography simulation image of the target wafer, realize the etching simulation process, and finally determine the etching simulation image of the target wafer according to the fused features.

[0087] In other embodiments, other feasible etching simulation rules or methods can also be used, for example, according to a preset feature fusion function, substituting the lithography feature map and the material distribution feature map into the feature fusion function to obtain the etching simulation image features, etc. The specific application scenarios and actual requirements can be flexibly limited.

[0088] The above embodiments can realize determination of the etching simulation image. The determined etching simulation image can provide a practical reference basis for the real etching process of the target wafer. Based on the etching simulation image, potential problems and errors that may occur in the real etching process of the target wafer can be predicted in advance, so that the etching parameters, processing technology and the like in the real etching process can be adjusted and optimized. The chip production efficiency is effectively enhanced, and the accuracy of the actual etching machine of the target wafer is also significantly improved, and the chip quality and yield of the produced chip can also be fully guaranteed.

[0089] Regarding the specific determination process of the above lithography feature map and material distribution feature map, specifically, in an embodiment provided by the present application, the lithography simulation image and the etching material distribution data of the target wafer can determine the respective corresponding base feature maps by the etching simulation model. Meanwhile, the present application embodiment also considers avoiding the loss or weakening of global features in the lithography simulation image and the etching material distribution data, and can also determine the corresponding receptive field enhancement feature maps of the lithography simulation image and the etching material distribution data by the etching simulation model.

[0090] Among them, the base feature map can be obtained by performing image convolution on the etching material distribution map corresponding to the lithography simulation image and the etching material distribution data by the convolution module in the etching simulation model. The receptive field enhancement feature map can be obtained by performing feature extraction on the etching material distribution map corresponding to the lithography simulation image and the etching material distribution data by the module (such as a hollow convolution) having a receptive field expansion function in the etching simulation model.

[0091] Then, the base feature map and the receptive field enhancement feature map of the lithography simulation image can be fused by the etching simulation model, and the fused feature map can be used as the lithography feature map corresponding to the lithography simulation image. Meanwhile, the base feature map and the receptive field enhancement feature map of the etching material distribution data can also be fused by the etching simulation model, and the fused feature map can be used as the material distribution feature map corresponding to the etching material distribution data.

[0092] The determined lithography feature map and material distribution feature map contain the base features and the scale magnification features of the receptive field enhancement of the corresponding image or data, which not only fully reflect the detailed features but also take into account the global features, significantly improve the accuracy and practicality of the subsequently determined etching simulation image, and are more close to the real etching process of the target wafer.

[0093] It should be noted that the above etching simulation model and the specific model structure of the module for determining the base feature map and the receptive field enhanced feature map in the etching simulation model are not strictly limited in the embodiments of the present application. In some embodiments, the module for determining the lithography simulation image and the etching material distribution data corresponding to the base feature map in the etching simulation model can be, for example, a standard convolution module, and the specific model structure can be referred to as shown in Figure 2 The module for determining the receptive field enhanced feature map can be, for example, a hollow convolution module, and the specific model structure can be referred to as shown in Figure 3 .

[0094] Figure 2 A structure diagram of a module for determining a base feature map in an etching simulation model provided by an embodiment of the present application.

[0095] Wherein, 210 and 220 are two module units for determining the base feature map in the etching simulation model, 211 is a convolution layer with a convolution kernel of a*a in the module unit 210, 212 is a convolution layer with a convolution kernel of 1*1, 213 is a batch normalization layer, and 204 is a linear rectification layer.

[0096] As shown in Figure 2 , the module for determining the base feature map in the etching simulation model can be a standard convolution module, and each module unit corresponding to the module can be divided into two branches. Taking the module unit 210 in Figure 2 as an example, one branch can be composed of the convolution layer 211 with the convolution kernel of a*a, the batch normalization layer 213, and the linear rectification layer 214, which extracts the local spatial features of the input image or feature map. The other branch can be composed of the convolution layer 212 with the convolution kernel of 1*1, the batch normalization layer 213, and the linear rectification layer 214, which adjusts the channel number to deepen the module structure, and can introduce an additional linear rectification layer 214 to enhance the nonlinearity of the feature map. The module unit 220 is similar, and will not be repeated.

[0097] The module for determining the base feature map in the etching simulation model in the embodiments of the present application can be composed of at least two module units connected as shown in Figure 2 , and the feature data output by the two branches of each module unit can be processed by a linear rectification layer and output to the next module unit or the output model. The linear rectification layer can specifically use a rectified linear unit (ReLU) as an activation function.

[0098] In addition, the convolution layer 211 with the convolution kernel of a*a can be used to optimize the slight etching deviation that may be caused by the micro-loading effect in the etching simulation process in addition to extracting image features. Figure 2The module unit shown can accurately and efficiently extract the basic feature map corresponding to the lithography simulation image and the etching material distribution data, and improve the accuracy and practicability of the etching simulation image.

[0099] Figure 3 The structure diagram of a module for determining a receptive field enhanced feature map in an etching simulation model is provided for an embodiment of the present application.

[0100] Among them, 310 and 320 are two module units for determining a receptive field enhanced feature map in an etching simulation model, 311 is a dilated convolution layer with a convolution kernel of a*a and an expansion rate of a, 312 is a convolution layer with a convolution kernel of 1*1, 313 is a batch normalization layer, and 314 is a linear rectification layer.

[0101] As shown in Figure 3 , the module for determining a receptive field enhanced feature map in an etching simulation model can be a dilated convolution module, and the module unit corresponding to the module can also be divided into two branches. Taking Figure 3 the module unit 310 in the embodiment as an example, one branch can be composed of a dilated convolution layer 311 with a convolution kernel of a*a and an expansion rate of a, a batch normalization layer 313, and a linear rectification layer 314, which realizes the expansion of the feature extraction receptive field, thereby extracting the context features with a larger receptive field of the input image or feature map. The other branch is the same as shown in Figure 2 , which can be composed of a convolution layer 312 with a convolution kernel of 1*1, a batch normalization layer 313, and a linear rectification layer 314, which adjusts the number of channels and deepens the module structure, and can introduce an additional linear rectification layer 314 to enhance the nonlinearity of the feature map. The module unit 320 is similar, and will not be repeated.

[0102] Similarly, the module for determining a receptive field enhanced feature map in an etching simulation model in the embodiment of the present application can be composed of at least two module units as shown in Figure 3 , and the feature data output by the two branches of each module unit can be processed by a linear rectification layer and input to the next module unit or output model. Figure 3 The linear rectification layer shown in Figure 2 , can use a linear rectification function as an activation function.

[0103] Through the module unit shown in Figure 3 , the receptive field enhanced feature map corresponding to the lithography simulation image and the etching material distribution data can be accurately and efficiently extracted, and after feature fusion with the corresponding basic feature map, a feature map that fully represents the feature details of the lithography simulation image and the etching material distribution data can be determined.

[0104] In addition, when the hollow convolution is selected as the receptive field enhancement feature map in the etching simulation model, a convolution module containing a filter can be additionally added to eliminate the grid artifact problem caused by the hollow convolution, reduce feature errors and interference, and improve the accuracy and authenticity of the etching simulation process.

[0105] The above is a specific implementation of the etching simulation method provided by the embodiments of the present application. The etching simulation method provided by the embodiments of the present application can realize efficient and close-to-real integrated simulation of photolithography and etching of a target wafer through a joint model composed of a photolithography simulation model and an etching simulation model. The integrated simulation process can greatly improve the production efficiency and chip quality of the overall chip production process, and also provides important help for optimization of the target wafer mask pattern and improvement of the accuracy of the real etching process.

[0106] In addition to the etching simulation method in the actual application process described above, the embodiments of the present application also provide an etching simulation model training method that can provide a trained etching simulation model for the etching simulation method described above. The etching simulation model training method provided by the embodiments of the present application is described in detail as follows:

[0107] Figure 4 A flowchart of an etching simulation model training method provided by an embodiment of the present application includes steps S401 to S406.

[0108] S401: Obtain sample mask pattern and etching material distribution sample data of a sample wafer, and determine standard size data of the sample wafer.

[0109] S402: Perform photolithography simulation on the sample mask pattern based on the pre-trained photoresist model in the joint model to determine a photolithography simulation sample image of the sample wafer.

[0110] S403: Perform etching simulation on the photolithography simulation sample image and the etching material distribution sample data based on the etching simulation model to be trained to determine an etching simulation sample image of the sample wafer.

[0111] S404: Determine simulation size data of the sample wafer according to the etching simulation sample image.

[0112] S405: Determine etching loss according to the simulation size data and the standard size data.

[0113] S406: Model training of the etching simulation model to be trained is performed according to the etching loss.

[0114] In steps S401 and S402, the etching simulation model training method provided in the present application can input the sample mask pattern of the sample wafer obtained into the photoresist model pre-trained, so as to determine the photoetching simulation sample image corresponding to the sample wafer through the photoresist model.

[0115] In addition, the standard size data of the sample wafer can represent the critical dimension (CD) data on the sample wafer, such as the line width, the trench depth, the critical dimension, and the like of the sample wafer after standard etching, which can be used for subsequent determination of etching loss.

[0116] Regarding the photoetching simulation process in step S402, the photoetching simulation process in step S102 of the etching simulation method is similar, that is, the sample space image of the sample wafer is determined first, and then the photoetching simulation of the sample space image is performed based on the photoresist model to determine the photoetching simulation sample image corresponding to the sample wafer. Here, the photoetching simulation process in the etching simulation model training method will not be described in detail, and the above content can be referred to.

[0117] In step S403, the photoetching simulation sample image determined in step S402 and the etching material distribution sample data corresponding to the sample wafer are input into the etching simulation model to be trained, so that the etching simulation model to be trained can determine the etching simulation sample image corresponding to the sample wafer through the etching simulation process in step S103.

[0118] The specific etching simulation process is similar to that in step S103, that is, the photoetching feature map of the photoetching simulation sample image and the material distribution feature map corresponding to the etching material distribution sample data are determined first, and then the etching simulation sample image is determined based on the preset etching simulation rule. For details, please refer to the corresponding content in step S103, which will not be described in detail here.

[0119] In step S404, the simulation size data of the sample wafer can be determined according to the etching simulation sample image determined in step S403. The specific data content of the simulation size data corresponds to the standard size data of the sample experience, which is used to represent the critical dimension data in the etching simulation sample image, such as the line width, the trench depth, the critical dimension, and the like of the target wafer after etching simulation in the etching simulation sample image.

[0120] Specifically, in an embodiment provided in the present application, all etching simulation parameter data contained in the etching simulation sample image of the sample wafer can be determined according to the etching simulation sample image of the sample wafer. Then, the simulation size data corresponding to the sample wafer can be selected from the etching simulation parameter data according to the preset etching parameter standard.

[0121] The etching simulation parameter data is used to represent each image parameter data in the etching simulation sample image. The etching parameter criterion represents a parameter screening criterion corresponding to the standard size data of the sample experience, and is used to determine the simulation size data corresponding to the standard size data from the etching simulation parameter data of the entire sample wafer.

[0122] The determination of the critical dimension data in the etching simulation sample image can provide a practical reference basis for the subsequent determination of the etching loss, and enhance the model capability. At the same time, the data processing amount in the etching simulation model training process is reduced, and the training rate of the training process is improved.

[0123] Further, through steps S405 and S406, the etching loss corresponding to the etching simulation model to be trained can be determined according to the simulation size data and the standard size data of the sample wafer. Then, the model parameters of the etching simulation model to be trained can be adjusted and optimized according to the etching loss, and finally the etching simulation model with precise etching simulation capability after training can be obtained.

[0124] The specific calculation process and calculation method of the etching loss are not strictly limited in the embodiments of the present application. In some embodiments, for example, the mean square error (MSE) can be used as the loss function of the etching simulation model, and the specific calculation process can refer to the formula (1) as shown below:

[0125]

[0126] The MSE is the mean square error corresponding to the etching simulation model in the embodiments of the present application, which can be used as the etching loss of the etching simulation process. rec The simulation size data corresponding to the etching simulation sample image is determined for the etching simulation model to be trained, p def The standard size data corresponding to the sample wafer, and k is the training data amount of the etching simulation model in the model training process.

[0127] In addition to the mean square error shown in formula (1) as the etching loss of the etching simulation model, other feasible loss determination methods can also be used in other embodiments, which can be flexibly set and selected according to actual needs and application scenarios.

[0128] After the training process of the above steps S401 to S406, the etching simulation model with precise etching simulation capability can be obtained, which can be used to execute the actual etching simulation process of the target wafer in step S103 above, and the etching simulation image corresponding to the target wafer can be accurately simulated and determined. The production efficiency and chip quality of the whole chip production process are further enhanced while the etching simulation image precision is effectively improved.

[0129] As to the training process of the photolithography simulation model in the above-mentioned etching simulation method and etching simulation model training method. In an embodiment provided by the present application, the photoresist model to be trained can be trained before the photolithography simulation is performed by the photoresist model in step S101 and step 402, so as to optimize the model parameters and make the photoresist model perform more accurate and efficient photolithography simulation. The specific training process of the photoresist model can refer to the process shown in Figure 5

[0130] Figure 5 A flowchart of a photoresist model training process provided by an embodiment of the present application, comprising steps S501 to S505.

[0131] S501: Obtain a sample photolithography image corresponding to a sample chip on a sample wafer, and position information of a key pattern region on the sample chip.

[0132] S502: Determine a sample spatial image of the sample wafer.

[0133] To improve the training efficiency of the photoresist model, in the embodiments provided by the present application, the photoresist model can be trained for a specific region of a single chip on the wafer.

[0134] The specific region can be a part of chip pattern on the wafer which is prone to photolithography simulation error determined according to historical photolithography data statistics. By training the photoresist model for the specific region, the photolithography simulation capability of the photoresist model can be effectively improved, and the data volume is greatly reduced compared to training the photoresist model for the entire wafer, thereby significantly improving the training efficiency of the photoresist model.

[0135] Based on this, in step S501, the technical solution provided by the embodiments of the present application can obtain a sample photolithography image corresponding to a sample chip in a sample wafer, and determine the position information of the key pattern region on the sample chip.

[0136] In step S502, the corresponding sample spatial image can be determined according to the mask plate pattern corresponding to the sample wafer. The key pattern region is the specific region in the above-mentioned single chip, and the corresponding position information can be used to represent the position information of the key image region on the sample wafer.

[0137] ​According to the position of the at least one key point of the key pattern region in the key pattern region, the position information of the key pattern region can further include: when the key point is located inside the key pattern region, it can be understood that the key pattern region is constructed based on multiple key points or a center point of the key pattern region. At this time, the position information corresponding to the key pattern region can further include region size information (such as length, width, etc.) for indicating the size of the key pattern region.

[0138] When the key point is at the edge of the key pattern region, the position information of the key point itself is sufficient to represent the coverage range of the key pattern region, and the corresponding position information can not need to include region size information. According to the position information of the key point, the position information corresponding to the key image region can be accurately determined.

[0139] The specific implementation method of determining the sample space image in step S502 is not strictly limited in the embodiments of the present application. In some embodiments, the space image of the target wafer can be determined based on the preset lithography simulation parameters as in step S102 described above. For details, reference can be made to the corresponding content described above, and excessive details will not be described here. In other embodiments, other feasible methods for determining the space image can be used, which can be flexibly selected and set according to application scenarios and actual needs.

[0140] S503: Based on the photoresist model to be trained, performing lithography simulation on the sample space image and the position information to determine the simulated lithography image of the key pattern region.

[0141] In step S503, the sample space image and the position information corresponding to the key pattern region determined through steps S501 and S502 can be input into the photoresist model to be trained, so that the photoresist model to be trained can perform targeted lithography simulation on the key pattern region in the sample chip to obtain the simulated lithography image of the key pattern region.

[0142] S504: According to the sample lithography image and the simulated lithography image, determining the lithography simulation loss of the photoresist model to be trained.

[0143] S505: According to the lithography simulation loss, performing model training on the photoresist model to be trained.

[0144] Through the steps S504 and S505, the photoetching simulation loss of the photoresist model to be trained in the training process can be calculated according to the sample photoetching image corresponding to the sample chip and the simulation photoetching image determined by the photoresist model to be trained. According to the photoetching simulation loss, the model parameter adjustment and optimization of the photoresist model to be trained can be performed, and the photoresist model trained can be used for the photoetching simulation of the target wafer in the step S102 and the photoetching simulation of the sample wafer in the step S402 to determine the photoetching simulation image corresponding to the target wafer or the sample wafer.

[0145] Through the processing procedures of the steps S501 to S505, the photoresist model capable of performing the photoetching simulation of the target wafer can be efficiently trained. Through the trained photoresist model, the photoetching simulation image of the target wafer or the sample wafer close to the real photoetching process can be accurately determined in the photoetching simulation process of the steps S102 or S402, and a practical basis can be provided for the subsequent etching simulation process and the training process of the etching simulation model. In addition, the training of the photoresist model for the key pattern area can greatly reduce the training data amount, and the model training efficiency can be significantly improved.

[0146] In addition to the above, in another embodiment provided by the present application, when the model training of the etching simulation model is performed through the steps S401 to S406, whether the trained etching simulation model meets the preset etching model standard can be determined according to the training of the etching simulation model.

[0147] When it is determined that the etching simulation model after multiple parameter adjustments and optimizations in the training process still cannot meet the etching model standard (for example, the etching loss cannot be reduced to the standard threshold), the technical solution provided by the present application can perform parameter adjustment on the photoresist model responsible for the photoetching simulation process according to the etching loss in the training process to determine the photoresist model after the parameter adjustment.

[0148] Then, the model training process of the steps S401 to S406 can be performed again based on the adjusted photoresist model to re-perform the model training of the etching simulation model to be trained, and the etching simulation model meeting the etching model standard can be trained. The etching simulation model meeting the etching model standard and the adjusted photoresist model are combined, and finally the joint model having both the photoetching simulation capability and the etching simulation capability can be obtained.

[0149] Based on the above return adjustment photoresist model parameter processing process, the training rate and model precision of the etching simulation model can be effectively improved, and a joint model with precise lithography simulation capability and etching simulation capability can be constructed. In addition to determining the etching simulation image corresponding to the target wafer, the joint model can also provide reference for mask pattern optimization of the target wafer through the integrated model structure of lithography and etching.

[0150] When the etching simulation image determined based on the technical solutions provided in the embodiments of the present application is used for mask pattern adjustment and optimization of the target wafer, the possible problems in the mask pattern during the lithography and etching process can be solved or compensated. The optimization rate and effect of the mask pattern are significantly improved, and the production rate and chip quality of the overall chip production process are significantly enhanced.

[0151] The above is a specific implementation of the etching simulation model training method provided in the embodiments of the present application. Through the etching simulation model training method and the training process of the photoresist model, a photoresist model with precise lithography simulation capability and an etching simulation model with precise etching simulation capability can be efficiently trained. Therefore, when the above etching simulation method is applied, the precision of lithography simulation and etching simulation can be significantly improved, and the accuracy of the etching simulation image of the target wafer can be improved.

[0152] The technical solutions provided in the embodiments of the present application can realize efficient and real lithography and etching integrated simulation for the target wafer through the etching simulation model trained by the model. The integrated simulation process can greatly improve the production efficiency and chip quality of the overall chip production process, and also provides important help for optimization of the target wafer mask pattern and improvement of the real etching process precision.

[0153] In the etching simulation process in the present application, the etching material distribution data of the wafer surface is ingeniously introduced, so that the potential influence of different etching materials in the wafer etching process in the real etching process can be accurately restored, the etching simulation process precision and practicability are significantly improved, practical data for the subsequent actual etching process are provided, and the chip yield and performance strength of the actual chip production process are improved.

[0154] Based on the etching simulation method and the etching simulation model training method provided in the above embodiments, the present application also provides specific implementation modes of the etching simulation device and the etching simulation model training device. Please refer to the following embodiments.

[0155] Figure 6 The structure schematic diagram of the etching simulation device provided in another embodiment of the present application is shown. The etching simulation device 600 comprises:

[0156] The acquisition unit 601 is configured to acquire a mask plate graph and etching material distribution data of a target wafer.

[0157] The photolithography simulation unit 602 is configured to perform photolithography simulation on the mask plate graph based on a photoresist model to obtain a photolithography simulation image of the target wafer.

[0158] The etching simulation unit 603 is configured to perform etching simulation on the photolithography simulation image and the etching material distribution data based on an etching simulation model to obtain an etching simulation image of the target wafer.

[0159] In some embodiments, the photolithography simulation unit 602 is configured to determine a spatial image of the target wafer according to the mask plate graph and preset photolithography simulation parameters.

[0160] The photolithography simulation unit 602 is configured to perform photolithography simulation on the spatial image based on the photoresist model to determine the photolithography simulation image.

[0161] In some embodiments, the etching simulation unit 603 is configured to determine a photolithography feature map of the photolithography simulation image and a material distribution feature map of a material distribution image corresponding to the etching material distribution data based on the etching simulation model.

[0162] The etching simulation unit 603 is configured to determine the etching simulation image according to the photolithography feature map and the material distribution feature map based on preset etching simulation rules in the etching simulation model.

[0163] In some embodiments, the etching simulation unit 603 is configured to determine a basic feature map and a receptive field enhancement feature map of the photolithography simulation image and a basic feature map and a receptive field enhancement feature map of the material distribution image based on the etching simulation model.

[0164] The etching simulation unit 603 is configured to perform photolithography feature fusion on the basic feature map and the receptive field enhancement feature map of the photolithography simulation image, take the photolithography fused feature map as the photolithography feature map, and perform material distribution feature fusion on the basic feature map and the receptive field enhancement feature map of the material distribution image, and take the material distribution fused feature map as the material distribution feature map.

[0165] Figure 7 The etching simulation model training device provided by another embodiment of the present application is shown in a structural schematic diagram. The etching simulation model training device 700 comprises:

[0166] The sample acquisition unit 701 is configured to acquire a sample mask plate graph and etching material distribution sample data of a sample wafer, and determine standard size data of the sample wafer.

[0167] The photolithography training unit 702 is configured to perform photolithography simulation on the sample mask plate image based on a pre-trained photoresist model in a joint model, to determine a photolithography simulation sample image of the sample wafer, the joint model comprising the photoresist model and a to-be-trained etching simulation model, and an output of the photoresist model being connected to an input of the to-be-trained etching simulation model.

[0168] The etching training unit 703 is configured to perform etching simulation on the photolithography simulation sample image and etching material distribution sample data based on the to-be-trained etching simulation model, to determine an etching simulation sample image of the sample wafer.

[0169] The size determination unit 704 is configured to determine simulation size data of the sample wafer according to the etching simulation sample image.

[0170] The loss determination unit 705 is configured to determine an etching loss according to the simulation size data and standard size data.

[0171] The model training unit 706 is configured to perform model training on the to-be-trained etching simulation model according to the etching loss.

[0172] In some embodiments, the photolithography training unit 702 is configured to determine a sample aerial image of the sample wafer according to the sample mask plate image and preset photolithography simulation parameters.

[0173] The photolithography training unit 702 is configured to perform photolithography simulation on the sample space image based on the photoresist model, to determine the photolithography simulation sample image.

[0174] In some embodiments, the photolithography training unit 702 is configured to obtain a sample photolithography image corresponding to a sample chip on the sample wafer, and position information of a key pattern region on the sample chip.

[0175] The photolithography training unit 702 is configured to determine a sample aerial image of the sample wafer.

[0176] The photolithography training unit 702 is configured to perform photolithography simulation on the sample aerial image and the position information based on the to-be-trained photoresist model, to determine a simulation photolithography image of the key pattern region.

[0177] The photolithography training unit 702 is configured to determine a photolithography simulation loss of the to-be-trained photoresist model according to the sample photolithography image and the simulation photolithography image.

[0178] The photolithography training unit 702 is configured to perform model training on the to-be-trained photoresist model according to the photolithography simulation loss.

[0179] In some embodiments, the etching training unit 703 is configured to determine a photolithography feature map of the photolithography simulation sample image based on the to-be-trained etching simulation model, and determine a material distribution feature map of a material distribution sample image corresponding to the etching material distribution sample data.

[0180] According to the photolithography feature map and the material distribution feature map, the etching simulation sample image is determined based on preset etching simulation rules in the etching simulation model to be trained.

[0181] In some embodiments, the size determination unit 704 is configured to determine etching simulation parameter data of the sample wafer according to the etching simulation sample image.

[0182] According to the preset etching parameter standard, the simulation size data is determined from the etching simulation parameter data.

[0183] In some embodiments, the model training unit 706 is configured to, in a case where the trained etching simulation model does not meet the preset etching model standard, perform parameter adjustment on the photoresist model according to the etching loss to obtain an adjusted photoresist model.

[0184] Based on the adjusted photoresist model, the model training of the etching simulation model to be trained is performed again, the trained etching simulation model and the adjusted photoresist model are combined to obtain a joint model.

[0185] Figure 8 A hardware structure schematic diagram of a terminal device is provided for another embodiment of the present application.

[0186] The terminal device can include a processor 801 and a memory 802 storing computer program instructions.

[0187] Specifically, the processor 801 can include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement one or more embodiments of the present application.

[0188] The memory 802 can include a mass storage for data or instructions. By way of example and not limitation, the memory 802 can include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. Where appropriate, the memory 802 can include removable or non-removable (or fixed) media. Where appropriate, the memory 802 can be internal or external to the integrated gateway disaster recovery device. In some embodiments, the memory 802 is a non-volatile solid-state memory.

[0189] In particular embodiments, the memory 802 includes read-only memory (ROM). Where appropriate, this ROM can be mask programmed ROM, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), electrically alterable ROM (EAROM), or flash memory or a combination of two or more of these. Optionally, the ROM is further combination with one or more of a volatile memory and / or a non-volatile memory.

[0190] The processor 801 implements any of the above-described etching simulation methods or etching simulation model training methods by reading and executing computer program instructions stored in the memory 802.

[0191] In one example, the terminal device further includes a communication interface 803 and a bus 800. Wherein, as shown in the figure, the processor 801, the memory 802, the communication interface 803 are connected through the bus 800 and complete the communication between each other. Figure 8

[0192] The communication interface 803 is mainly used to realize the communication between each module, device, unit and / or equipment in the embodiments of the application.

[0193] The bus 800 includes hardware, software or both to couple components of the online data traffic billing device to each other in a known manner. By way of example and not limitation, the bus can include an accelerated graphics port (AGP) or other graphics bus, an enhanced industry standard architecture (EISA) bus, a front-side bus (FSB), a hypertransport (HT) interconnect, an industry standard architecture (ISA) bus, an infiniband interconnect, a low pin count (LPC) bus, a memory bus, a microchannel architecture (MCA) bus, a peripheral component interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a serial advanced technology attachment (SATA) bus, a video electronics standards association local (VLB) bus, or another suitable bus or interconnect, or a combination of two or more of these. Where appropriate, the bus 800 can include one or more buses. Although particular buses have been described and illustrated, the present application contemplates any suitable bus or interconnect.

[0194] In addition, in combination with the etching simulation method or etching simulation model training method in the above-described embodiments, the embodiments of the present application can provide a computer storage medium to realize. The computer storage medium has computer program instructions stored thereon; the computer program instructions are executed by the processor to realize any of the above-described etching simulation methods or etching simulation model training methods.

[0195] The embodiments of the present application also provide a computer program product, including a computer program, the computer program is executed by the processor to realize any of the above-described etching simulation methods or etching simulation model training methods. ​

[0196] It is to be understood that the present application is not limited to the particular examples described and illustrated herein, and that the application includes a variety of modifications and changes that can be made thereto without departing from the spirit and scope of the application. For simplicity, detailed descriptions of well-known methods and apparatuses are omitted so as not to obscure the disclosure. In the above embodiments, several specific steps are described and illustrated as examples. However, the methods process of the present application is not limited to the specific steps described and illustrated, and one of ordinary skill in the art can make various changes, modifications, and additions, or can change the order of steps, after having the benefit of this description.

[0197] The functional blocks shown in the above described block diagrams of the structure can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application specific integrated circuits (ASICs), appropriate firmware, plug-ins, functional cards, and the like. When implemented in software, the elements of the present application are program or code segments that are used to perform the required tasks. The program or code segments can be stored in a machine-readable medium or transmitted through a data signal carried in a carrier wave over a transmission medium or communication link. The "machine-readable medium" can include any medium that can store or transfer information. Examples of the machine-readable medium include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, and the like. The code segments can be downloaded via a computer network such as the Internet, an intranet, and the like.

[0198] It is also to be understood that the example embodiments described in this application are based on a series of steps or apparatuses to describe some methods or systems. However, the present application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiments, or in an order different from the embodiments, or several steps can be performed simultaneously.

[0199] The computer program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other processing devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other processing devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0200] The above is only a specific implementation of the present application, and those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, module and unit described above can refer to the corresponding process in the foregoing method embodiments, which will not be described here. It should be understood that the protection scope of the present application is not limited to this, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical range disclosed in the present application, and these modifications or replacements should be covered within the protection scope of the present application.

Claims

1. An etching simulation method, characterized in that: The etching simulation method is applied to a joint model, the joint model consisting of a photoresist model and an etching simulation model, the output of the photoresist model being connected to the input of the etching simulation model, and is characterized by comprising: Obtain the mask layout and etching material distribution data of the target wafer; Based on the photoresist model, performing photolithography simulation on the mask pattern to obtain a photolithography simulation image of the target wafer; Based on the etching simulation model, etching simulation is performed on the photolithography simulation image and the etching material distribution data to obtain an etching simulation image of the target wafer.

2. The method according to claim 1, characterized in that The step of performing photolithography simulation on the mask pattern based on the photoresist model to obtain a photolithography simulation image of the target wafer includes: Determining an aerial image of the target wafer according to the mask pattern and preset lithography simulation parameters; Based on the photoresist model, photolithography simulation is performed on the aerial image to determine the photolithography simulation image.

3. The method according to claim 1, characterized in that The step of performing etching simulation on the photolithography simulation image and the etching material distribution data based on the etching simulation model to obtain the etching simulation image of the target wafer includes: Determining a lithography feature map of the lithography simulation image and a material distribution feature map of the material distribution image corresponding to the etched material distribution data based on the lithography simulation model; The etching simulation image is determined according to the photolithography feature map and the material distribution feature map and based on etching simulation rules preset in the etching simulation model.

4. The method according to claim 3, characterized in that The determining of the lithography feature map of the lithography simulation image and the determining of the material distribution feature map of the material distribution image corresponding to the etching material distribution data include: Based on the etching simulation model, determining a basic feature map and a receptive field enhancement feature map of the lithography simulation image, and determining a basic feature map and a receptive field enhancement feature map of the distribution image; The basic feature map and the receptive field enhancement feature map of the lithography simulation image are subjected to lithography feature fusion, and the feature map after lithography fusion is used as the lithography feature map; the basic feature map and the receptive field enhancement feature map of the distribution image are subjected to material distribution feature fusion, and the feature map after material distribution feature fusion is used as the material distribution feature map.

5. A method for training an etching simulation model, characterized in that: include: Obtaining sample mask layout and etching material distribution sample data of a sample wafer, and determining standard size data of the sample wafer; Based on a pre-trained photoresist model in a joint model, performing a photolithography simulation on the sample mask layout to determine a photolithography simulation sample image of the sample wafer, wherein the joint model is composed of the photoresist model and an etching simulation model to be trained, and the output of the photoresist model is connected to the input of the etching simulation model to be trained; Based on the etching simulation model to be trained, performing etching simulation on the photolithography simulation sample image and the etching material distribution sample data to determine the etching simulation sample image of the sample wafer; Determining simulated size data of the sample wafer according to the etching simulation sample image; determining etching loss according to the simulated size data and the standard size data; Model training is performed on the etching simulation model to be trained according to the etching loss.

6. The method according to claim 5, characterized in that The step of performing photolithography simulation on the sample mask layout based on the etching simulation model to be trained to determine a photolithography simulation sample image of the sample wafer includes: Determining a sample spatial image of the sample wafer according to the sample mask pattern and preset lithography simulation parameters; Based on the photoresist model, photolithography simulation is performed on the sample spatial image to determine the photolithography simulation sample image.

7. The method according to claim 5, characterized in that The training process of the photoresist model includes: Obtaining a sample photolithography image corresponding to a sample chip on the sample wafer, and position information of a key pattern area on the sample chip; determining a sample spatial image of the sample wafer; Based on the photoresist model to be trained, performing photolithography simulation on the sample space image and the position information to determine a simulated photolithography image of the key pattern area; determining a photolithography simulation loss of the to-be-trained photoresist model according to the sample photolithography image and the simulated photolithography image; Model training is performed on the photoresist model to be trained according to the photolithography simulation loss.

8. The method according to claim 5, characterized in that The etching simulation is performed on the photolithography simulation sample image and the etching material distribution sample data based on the etching simulation model to be trained to determine the etching simulation sample image of the sample wafer, including: Determining a photolithography feature map of the photolithography simulation sample image and a material distribution feature map of the material distribution sample image corresponding to the etching material distribution sample data based on the etching simulation model to be trained; The etching simulation sample image is determined according to the photolithography feature map and the material distribution feature map and based on etching simulation rules preset in the etching simulation model to be trained.

9. The method according to claim 5, characterized in that Determining the simulated size data of the sample wafer according to the etching simulation sample image includes: Determining etching simulation parameter data of the sample wafer according to the etching simulation sample image; The simulated dimension data is determined from the etching simulation parameter data according to a preset etching parameter standard.

10. The method according to claim 5, characterized in that After the etching simulation model to be trained is trained according to the etching loss, the method includes: When it is determined that the trained etching simulation model does not meet the preset etching model standard, adjusting the parameters of the photoresist model according to the etching loss to obtain an adjusted photoresist model; Based on the adjusted photoresist model, the etching simulation model to be trained is retrained, and the trained etching simulation model and the adjusted photoresist model are combined to obtain the joint model.

Images