Pixel circuit and display panel

Abstract

The invention discloses a pixel circuit and a display panel, and the pixel circuit is characterized in that a reset transistor, a second light-emitting control transistor and a driving transistor are all in an on state in a period of time, and a first light-emitting control transistor, a write-in transistor and a compensation transistor are all in an off state; according to the technical scheme, the driving transistor can be reset through the reset transistor and the second light-emitting control transistor, flicker can be improved, charging time is not occupied due to the fact that the driving transistor is not reset through the write-in transistor, and display with a higher refresh rate can be achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel circuit and a display panel. BACKGROUND

[0002] With the development of display technology, the refresh rate is also getting higher and higher, and when switching from high refresh rate to low refresh rate, flickering phenomenon is prone to occur.

[0003] However, in order to overcome the flickering phenomenon, the data signal needs to reset the driving transistor through the write transistor, which will occupy the charging time, thereby being not conducive to realizing higher refresh frequency display. SUMMARY

[0004] The present application provides a pixel circuit and a display panel to alleviate the technical problem that the charging time is occupied too much when the data signal resets the driving transistor through the write transistor.

[0005] In a first aspect, the present application provides a pixel circuit, comprising: a first light-emitting control transistor, a driving transistor, a second light-emitting control transistor and a light-emitting device connected in sequence between a first power supply end and a second power supply end; a storage capacitor connected between a gate of the driving transistor and an anode of the light-emitting device; a compensation transistor connected between the gate of the driving transistor and a first pole of the driving transistor; a write transistor connected between a second pole of the driving transistor and a data line; and a reset transistor connected between a reset line and the anode of the light-emitting device; wherein, in a time period, the reset transistor, the second light-emitting control transistor and the driving transistor are all in a conductive state, and the first light-emitting control transistor, the write transistor and the compensation transistor are all in a non-conductive state.

[0006] Optionally, a gate of the write transistor is connected to a scan signal, a gate of the first light-emitting control transistor is connected to a first light-emitting control signal, a gate of the second light-emitting control transistor is connected to a second light-emitting control signal, a gate of the reset transistor is connected to the first light-emitting control signal, and a gate of the compensation transistor is connected to the second light-emitting control signal.

[0007] Optionally, a gate of the write transistor is connected to a scan signal, a gate of the first light-emitting control transistor is connected to a first light-emitting control signal, a gate of the second light-emitting control transistor is connected to a second light-emitting control signal, a gate of the reset transistor is connected to a third light-emitting control signal, and a gate of the compensation transistor is connected to the second light-emitting control signal; the first light-emitting control signal is the same as the second light-emitting control signal in amplitude, frequency and duty cycle, and the phase of the first light-emitting control signal is different from the phase of the second light-emitting control signal.

[0008] Optionally, the third light emitting control signal has the same amplitude, frequency and duty cycle as the first light emitting control signal and the second light emitting control signal, and the phase of the third light emitting control signal is different from any one of the phase of the first light emitting control signal and the phase of the second light emitting control signal.

[0009] Optionally, the first light emitting control signal is an (n+2)th light emitting control signal, the second light emitting control signal is an nth light emitting control signal, and the third light emitting control signal is an (n+1)th light emitting control signal.

[0010] Optionally, the third light emitting control signal has different amplitude, frequency and duty cycle from the first light emitting control signal and the second light emitting control signal, and the phase of the third light emitting control signal is different from any one of the phase of the first light emitting control signal and the phase of the second light emitting control signal.

[0011] Optionally, the first light emitting control signal is an (n+2)th light emitting control signal, the second light emitting control signal is an nth light emitting control signal, and the pulse start time of the third light emitting control signal is the same as the pulse start time of the second light emitting control signal, and the pulse end time of the third light emitting control signal is the same as the pulse end time of the first light emitting control signal in a frame.

[0012] Optionally, the working stage of the pixel circuit in a frame includes an initialization stage, a write stage, a bias stress elimination stage and a light emitting stage in sequence; wherein, in the bias stress elimination stage, the reset transistor and the second light emitting control transistor are in a conductive state, and the write transistor, the first light emitting control transistor and the compensation transistor are in a disconnected state.

[0013] Optionally, in the initialization stage, the first light emitting control transistor and the compensation transistor are synchronously turned on first, the reset transistor is turned on later, and the write transistor and the second light emitting control transistor are in a disconnected state.

[0014] Optionally, the pulse start time of the third light emitting control signal is the same as the pulse start time of the second light emitting control signal, and the pulse end time of the third light emitting control signal is the same as the pulse end time of the first light emitting control signal, so as to increase the duration of the initialization stage and the duration of the bias stress elimination stage.

[0015] Optionally, the channel type of the first light emitting control transistor is the same as the channel type of the second light emitting control transistor, the channel type of the compensation transistor is the same as the channel type of the reset transistor, and the channel type of the first light emitting control transistor is different from the channel type of the compensation transistor.

[0016] In a second aspect, the present application provides a display panel, comprising: the pixel circuit, the pixel circuit being located in a display area; two light-emitting drive circuits for outputting first, second and third light-emitting control signals, the two light-emitting drive circuits being located at opposite sides of the display area respectively; and two gate drive circuits for outputting scanning signals, the two gate drive circuits being located at opposite sides of the display area respectively.

[0017] The pixel circuit and the display panel provided by the present application can reset the driving transistor through the reset transistor and the second light-emitting control transistor, which can improve flicker and does not occupy charging time because the driving transistor is not reset through the write transistor, and is conducive to realizing a higher refresh rate of display. BRIEF DESCRIPTION OF DRAWINGS

[0018] The technical solutions and other beneficial effects of the present application will become apparent through the following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings.

[0019] Figure 1 FIG. 1 is a structural schematic diagram of a pixel circuit in the related art.

[0020] Figure 2 FIG. 2 is a timing schematic diagram of the pixel circuit shown in FIG. 1. Figure 1

[0021] Figure 3 FIG. 3 is a first structural schematic diagram of a pixel circuit provided by an embodiment of the present application.

[0022] Figure 4 FIG. 4 is a timing schematic diagram of the pixel circuit shown in FIG. 3. Figure 3

[0023] Figure 5 FIG. 5 is a timing schematic diagram of the pixel circuit shown in FIG. 3 in an initialization stage. Figure 3

[0024] Figure 6 FIG. 6 is a timing schematic diagram of the pixel circuit shown in FIG. 3 in a write stage. Figure 3

[0025] Figure 7 FIG. 7 is a timing schematic diagram of the pixel circuit shown in FIG. 3 in a bias stress elimination stage. Figure 3

[0026] Figure 8 FIG. 8 is a timing schematic diagram of the pixel circuit shown in FIG. 3 in a light-emitting stage. Figure 3

[0027] FIG. 8 is a timing schematic diagram of the pixel circuit shown in FIG. 3 in a light-emitting stage.​​​​​Figure 9 for Figure 3 The timing diagram of the pixel circuit shown is when operating in a write frame.

[0028] Figure 10 for Figure 3 The diagram shows a timing comparison of the pixel circuit operating in a write frame and a hold frame.

[0029] Figure 11 This is a second structural diagram of the pixel circuit provided in an embodiment of the present application.

[0030] Figure 12 for Figure 11 Timing diagram of the pixel circuit shown.

[0031] Figure 13 This is a third structural schematic diagram of the pixel circuit provided in an embodiment of the present application.

[0032] Figure 14 for Figure 13 Timing diagram of the pixel circuit shown.

[0033] Figure 15 for Figure 11 A schematic structural diagram of a display panel provided in an embodiment of the application is shown.

[0034] Figure 16 for Figure 11 The diagram shows a timing comparison of the pixel circuit operating in a write frame and a hold frame. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0036] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features. The features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0037] Figure 1A structure diagram of a pixel circuit 10 in the related art is shown in FIG. 1. The pixel circuit 10 includes a driving transistor T1, a writing transistor T2, a compensation transistor T3, a reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a storage capacitor Cst, and a light-emitting device D1.

[0038] A first electrode of the first light-emitting control transistor T5 is connected to a first power supply terminal VDD, a gate electrode of the first light-emitting control transistor T5 is connected to a first light-emitting driving signal (EM1), and a second electrode of the first light-emitting control transistor T5 is connected to a first electrode of the compensation transistor T3 and a first electrode of the driving transistor T1 to form a first node A.

[0039] A first electrode of the writing transistor T2 is connected to a data line transmitting a data signal DS, a second electrode of the writing transistor T2 is connected to a second electrode of the driving transistor T1 and a first electrode of the second light-emitting control transistor T6 to form a second node B, and a gate electrode of the writing transistor T2 is connected to a scanning signal SCAN1.

[0040] A control electrode of the second light-emitting control transistor T6 is connected to a second light-emitting driving signal (EM2), a second electrode of the second light-emitting control transistor T6 is connected to an anode of the light-emitting device D1, a first electrode of the reset transistor T4, and a first terminal of the storage capacitor Cst to form a third node C, and a cathode of the light-emitting device D1 is connected to a second power supply terminal VSS.

[0041] A second electrode of the compensation transistor T3 is connected to a gate electrode of the driving transistor T1 and a second terminal of the storage capacitor Cst to form a fourth node Q, and a gate electrode of the compensation transistor T3 is connected to a gate driving signal (SCAN2).

[0042] A second electrode of the reset transistor T4 is connected to a reset line transmitting a reset signal VI, and a gate electrode of the reset transistor T4 is connected to the second light-emitting driving signal (EM2).

[0043] The first light-emitting control transistor T5, the second light-emitting control transistor T6, and the writing transistor T2 are P-channel thin film transistors, and the driving transistor T1, the compensation transistor T3, and the reset transistor T4 are N-channel thin film transistors.

[0044] As shown in FIG. 2, a working stage of the pixel circuit 10 in one frame includes: Figure 2 Figure 1 As shown in FIG. 2, a working stage of the pixel circuit 10 in one frame includes:

[0045] ​The first stage (P1): EM2 is high, the reset transistor T4 is turned on, and the second light-emitting control transistor T6 is turned off; EM1 is low, the first light-emitting control transistor T5 is turned on; the scanning signal SCAN1 is high, the write transistor T2 is turned off; SCAN2 is high, the compensation transistor T3 is turned on. The reset signal VI resets the anode of the light-emitting device D1 through the reset transistor T4, and the signal of the first power supply end VDD resets the gate of the driving transistor T1 through the first light-emitting control transistor T5 and the compensation transistor T3.

[0046] The second stage (P2): EM2 is high, the reset transistor T4 is turned on, and the second light-emitting control transistor T6 is turned off; EM1 is high, the first light-emitting control transistor T5 is turned off; the scanning signal SCAN1 is low, the write transistor T2 is turned on; SCAN2 is low, the compensation transistor T3 is turned off. The data signal DS resets the second node B and the first node A through the write transistor T2, so as to relieve or eliminate the open-state bias stress (OBS) of the driving transistor T1. The reset signal VI resets the anode of the light-emitting device D1 through the reset transistor T4.

[0047] The third stage (P3): EM2 is high, the reset transistor T4 is turned on, and the second light-emitting control transistor T6 is turned off; EM1 is high, the first light-emitting control transistor T5 is turned off; the scanning signal SCAN1 is low, the write transistor T2 is turned on; SCAN2 is high, the compensation transistor T3 is turned on. The data signal DS charges the fourth node Q through the write transistor T2, the driving transistor T1 and the compensation transistor T3, until the potential of the fourth node Q reaches the sum of VDS and Vth. The anode potential of the light-emitting device D1 remains at the potential of the reset signal VI.

[0048] The fourth stage (P4): EM2 is low, the reset transistor T4 is turned off, and the second light-emitting control transistor T6 is turned on; EM1 is low, the first light-emitting control transistor T5 is turned on; the scanning signal SCAN1 is high, the write transistor T2 is turned off; SCAN2 is low, the compensation transistor T3 is turned off. The light-emitting device D1 emits light, and the current flowing through the light-emitting device D1 is proportional to the square of (VDS-VVI).

[0049] Wherein, VDS represents the voltage of the data signal DS. VVI represents the voltage of the reset signal VI. Vth is the threshold voltage of the driving transistor T1. From the description process of the above working stages, it can be known that, Figure 1 The pixel circuit 10 shown has the following two shortcomings:

[0050] 1. The waveforms of EM1, EM2, SCAN1, and SCAN2 are different, and each requires a set of driving circuits to generate them. A total of four sets of driving circuits are required, which will take up too much frame space and is not conducive to achieving a narrower frame.

[0051] 2. In order to alleviate or eliminate the on-state bias stress (OBS) of the driving transistor T1, it is necessary to implement this through the writing transistor T2 in the second phase (P2). This reduces the writing time of the data signal DS, which makes it difficult for the pixel circuit 10 to operate at a higher refresh rate.

[0052] Based on this, this embodiment provides a pixel circuit 10, such as Figure 3 As shown, the pixel circuit 10 includes a driving transistor T1, a writing transistor T2, a compensation transistor T3, a reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a storage capacitor Cst and a light-emitting device D1. The first light-emitting control transistor T5, the driving transistor T1, the second light-emitting control transistor T6 and the light-emitting device D1 are sequentially connected between the first power supply terminal VDD and the second power supply terminal VSS; the storage capacitor Cst is connected between the gate of the driving transistor T1 and the anode of the light-emitting device D1; the compensation transistor T3 is connected between the gate of the driving transistor T1 and the first electrode of the driving transistor T1; the writing transistor T2 is connected between the second electrode of the driving transistor T1 and the data line; the reset transistor T4 is connected between the reset line and the anode of the light-emitting device D1; wherein, in a period of time, the reset transistor T4, the second light-emitting control transistor T6 and the driving transistor T1 are all in the on state, and the first light-emitting control transistor T5, the writing transistor T2 and the compensation transistor T3 are all in the off state.

[0053] It can be understood that the pixel circuit 10 provided in this embodiment is in a state where the reset transistor T4, the second light-emitting control transistor T6 and the driving transistor T1 are all in an on state during a period of time, and the first light-emitting control transistor T5, the write transistor T2 and the compensation transistor T3 are all in an off state. The driving transistor T1 can be reset by the reset transistor T4 and the second light-emitting control transistor T6, which not only improves the flicker, but also does not take up the charging time because the driving transistor T1 is not reset by the write transistor T2, which is conducive to achieving a display with a higher refresh rate.

[0054] It should be noted that for the same transistor, the first electrode can be one of the source and the drain, and the second electrode can be the other of the source and the drain. For example, if the first electrode is the drain, the second electrode is the source; or if the first electrode is the source, the second electrode is the drain.

[0055] The light emitting device D1 may be, but is not limited to, an organic light emitting diode (OLED), and may also be a mini light emitting diode, a micro light emitting diode, or a quantum dot light emitting diode.

[0056] In some embodiments, as Figure 4 As shown, the gate of the write transistor T2 is connected to the scan signal SCAN1, the gate of the first light-emitting control transistor T5 is connected to the first light-emitting control signal, the gate of the second light-emitting control transistor T6 is connected to the second light-emitting control signal, the gate of the reset transistor T4 is connected to the first light-emitting control signal, and the gate of the compensation transistor T3 is connected to the second light-emitting control signal.

[0057] It should be noted that since the gate of the first light-emitting control transistor T5 and the gate of the reset transistor T4 share the first light-emitting control signal, such as EM2, and the gate of the second light-emitting control transistor T6 and the gate of the compensation transistor T3 share the second light-emitting control signal, such as EM1, this means that the scanning signals SCAN1, EM1 and EM2 each require only one set of driving circuits. Compared with the related art, the same 6T pixel circuit requires four sets of driving circuits, thereby reducing the number of driving circuits, thereby reducing the space occupied by the frame, and facilitating the realization of a narrower frame.

[0058] Figure 3 One frame of the pixel circuit shown includes the following working stages:

[0059] Initialization phase (M1): Figure 4 and Figure 5 As shown, EM1 is at a high level, the compensation transistor T3 is turned on, and the second light-emission control transistor T6 is turned off. EM2 switches from a low level to a high level, the first light-emission control transistor T5 is first turned on and then turned off, and the reset transistor T4 switches from off to on. The scan signal SCAN1 is at a high level, and the write transistor T2 is turned off. After the signal from the first power supply terminal VDD resets the gate of the drive transistor T1 through the first light-emission control transistor T5 and the compensation transistor T3, the reset signal VI resets the anode of the light-emitting device D1 through the reset transistor T4.

[0060] Writing phase (M2): Figure 4 and Figure 6 As shown, EM1 is at a high level, the compensation transistor T3 is turned on, and the second emission control transistor T6 is turned off. EM2 is at a high level, the first emission control transistor T5 is turned off, and the reset transistor T4 is turned on. The scan signal SCAN1 is at a low level, and the write transistor T2 is turned on. The data signal DS charges the fourth node Q through the write transistor T2, the drive transistor T1, and the compensation transistor T3 until the potential of the fourth node Q reaches the sum of VDS and Vth. The anode potential of the light-emitting device D1 is maintained at the potential of the reset signal V1.

[0061] Bias stress relief stage (M3): as shown in Figure 4 and Figure 7 , EM1 is low, compensation transistor T3 is off, and the second light-emitting control transistor T6 is turned on; EM2 is high, the first light-emitting control transistor T5 is off, and the reset transistor T4 is turned on; the scan signal SCAN1 is high, and the write transistor T2 is off. The reset signal VI is reset to the second node B and the first node A through the reset transistor T4 and the second light-emitting control transistor T6, respectively, to relieve or eliminate the on-state bias stress (OBS) of the driving transistor T1.

[0062] Light-emitting stage (M4): as shown in Figure 4 and Figure 8 , EM1 is low, compensation transistor T3 is off, and the second light-emitting control transistor T6 is turned on; EM2 is low, the first light-emitting control transistor T5 is turned on, and the reset transistor T4 is off; the scan signal SCAN1 is high, and the write transistor T2 is off. The light-emitting device D1 emits light, and the current flowing through the light-emitting device D1 is proportional to the square of (VDS-VVI).

[0063] In some embodiments, as shown in Figure 11 , Figure 13 , the gate of the write transistor T2 is connected to the scan signal, the gate of the first light-emitting control transistor T5 is connected to the first light-emitting control signal, the gate of the second light-emitting control transistor T6 is connected to the second light-emitting control signal, the gate of the reset transistor T4 is connected to the third light-emitting control signal, and the gate of the compensation transistor T3 is connected to the second light-emitting control signal; the first light-emitting control signal has the same amplitude, frequency and duty cycle as the second light-emitting control signal, and the phase of the first light-emitting control signal is different from that of the second light-emitting control signal.

[0064] It should be noted that the first light-emitting control signal has the same amplitude, frequency and duty cycle as the second light-emitting control signal, and the phase of the first light-emitting control signal is different from that of the second light-emitting control signal, so that the first light-emitting control signal and the second light-emitting control signal can be generated by the same set of driving circuits, so that the first light-emitting control transistor T5, the second light-emitting control transistor T6 and the compensation transistor T3 can share the same set of driving circuits. Thus, the entire pixel circuit 10 only needs a maximum of three sets of driving circuits, which is less than the four sets of driving circuits required by the same pixel circuit 10, thereby reducing the number of driving circuits and the occupied space of the frame, which is conducive to achieving a narrower frame.

[0065] Figure 9 The timing diagram of the pixel circuit 10 shown in Figure 3 operating in the write frame. Figure 10 The timing diagram of the pixel circuit 10 shown in Figure 3The pixel circuit 10 is shown in a timing diagram of a write frame and a hold frame. It should be noted that in a variable refresh rate display, a frame of the pixel circuit 10 can be either a write frame or a hold frame. The write frame includes Figure 4 M1-M4, and the hold frame includes Figure 4 M3 and M4.

[0066] In either the write frame or the hold frame, a high level of EM2 controls the reset transistor T4 to be turned on, and a low level of EM1 controls the second light emitting control transistor T6 to be turned on, so as to reset the second node B and the first node A, respectively. In a frame, the number of pulses of EM2 can be one or more, so as to control the number of times of resetting the second node B and the first node A.

[0067] In Figure 10 , the highest refresh rate is exemplarily 120 Hz, and the refresh rate of one write frame or one hold frame is 120 Hz, and 10 Hz display needs 12 continuous frames to be implemented. The first frame of the 12 continuous frames is a write frame of 10 Hz display, and the following 11 frames are hold frames of 10 Hz display.

[0068] In some embodiments, the channel type of the first light emitting control transistor T5 is the same as the channel type of the second light emitting control transistor T6, the channel type of the compensation transistor T3 is the same as the channel type of the reset transistor T4, and the channel type of the first light emitting control transistor T5 is different from the channel type of the compensation transistor T3.

[0069] Exemplarily, at least one of the first light emitting control transistor T5, the second light emitting control transistor T6 and the write transistor T2 is a P-channel thin film transistor, and at least one of the drive transistor T1, the compensation transistor T3 and the reset transistor T4 is an N-channel thin film transistor. Alternatively, at least one of the first light emitting control transistor T5, the second light emitting control transistor T6 and the write transistor T2 is an N-channel thin film transistor, and at least one of the drive transistor T1, the compensation transistor T3 and the reset transistor T4 is a P-channel thin film transistor.

[0070] It should be noted that the first light emitting control transistor T5 and the second light emitting control transistor T6 can each be a single P-channel thin film transistor, or can be two P-channel thin film transistors, so as to prevent leakage current from causing the light emitting device D1 to be turned on.

[0071] As Figure 12As shown, the first light emitting control signal is the n+2th light emitting control signal EM(n+2), the second light emitting control signal is the nth light emitting control signal EM(n), and the third light emitting control signal is the n+1th light emitting control signal EM(n+1). Figure 11 The working stages of the pixel circuit 10 in a frame include:

[0072] The initialization stage (M1): EM(n) is high, the compensation transistor T3 is turned on, and the second light emitting control transistor T6 is turned off; EM(n+2) is low, the first light emitting control transistor T5 is turned on; the scanning signal SCAN1 is high, the write transistor T2 is turned off; EM(n+1) is switched from low to high, and the reset transistor T4 is switched from off to on. The signal of the first power supply end VDD resets the gate of the driving transistor T1 through the first light emitting control transistor T5 and the compensation transistor T3. The reset signal VI resets the anode of the light emitting device D1 through the reset transistor T4.

[0073] The write stage (M2): EM(n) is high, the compensation transistor T3 is turned on, and the second light emitting control transistor T6 is turned off; EM(n+2) is high, the first light emitting control transistor T5 is turned off; the scanning signal SCAN1 is low, the write transistor T2 is turned on; EM(n+1) is high, and the reset transistor T4 is turned on. The data signal DS charges the fourth node Q through the write transistor T2, the driving transistor T1, and the compensation transistor T3, until the potential of the fourth node Q reaches the sum of VDS and Vth. The anode potential of the light emitting device D1 remains at the potential of the reset signal VI.

[0074] The bias stress elimination stage (M3): EM(n) is low, the compensation transistor T3 is turned off, and the second light emitting control transistor T6 is turned on; EM(n+2) is high, the first light emitting control transistor T5 is turned off; the scanning signal SCAN1 is high, the write transistor T2 is turned off; EM(n+1) is high, and the reset transistor T4 is turned on. The reset signal VI resets the second node B and the first node A through the reset transistor T4 and the second light emitting control transistor T6, respectively, to alleviate or eliminate the on-state bias stress (OBS) of the driving transistor T1.

[0075] The light emitting stage (M4): EM(n) is low, the compensation transistor T3 is turned off, and the second light emitting control transistor T6 is turned on; EM(n+2) is low, the first light emitting control transistor T5 is turned on; the scanning signal SCAN1 is high, the write transistor T2 is turned off; EM(n+1) is low, and the reset transistor T4 is turned off. The light emitting device D1 emits light, and the current flowing through the light emitting device D1 is proportional to the square of (VDS-VVI).

[0076] It needs to be explained that in the embodiment, the third light-emitting control signal is the same as the first light-emitting control signal, the second light-emitting control signal in amplitude, frequency and duty cycle, and the phase of the third light-emitting control signal is different from any one of the phase of the first light-emitting control signal and the phase of the second light-emitting control signal. Therefore, this makes the first light-emitting control signal, the second light-emitting control signal and the third light-emitting control signal can be generated by the same group of driving circuits, so that the number of groups of driving circuits required by the whole pixel circuit 10 is two groups, which further reduces the occupied space of the frame, and is beneficial to realize narrower frame.

[0077] Moreover, the bias stress elimination stage (M3) is located after the writing stage (M2), and the bias stress elimination stage (M3) does not occupy the duration of the writing stage (M2), compared with Figure 1 The pixel circuit 10 shown in the figure can make the duration of the writing data signal DS longer, which is beneficial to realize higher display frequency.

[0078] Compared with Figure 11 , Figure 13 The pixel circuit 10 shown in the figure configures the third light-emitting control signal as a separate light-emitting control signal. As Figure 14 shown, this makes the third light-emitting control signal EM2 different from the first light-emitting control signal EM(n+2) and the second light-emitting control signal EM(n) in amplitude, frequency and duty cycle, and the phase of the third light-emitting control signal is different from any one of the phase of the first light-emitting control signal and the phase of the second light-emitting control signal. In this way, one group of driving circuits is needed to generate the first light-emitting control signal and the second light-emitting control signal, another group of driving circuits generates the third light-emitting control signal, and still another group of driving circuits generates the scanning signal SCAN1.

[0079] As Figure 14 shown, Figure 13 The working stage of the pixel circuit 10 shown in the figure in a frame includes:

[0080] Initialization stage (M1): EM(n) is high, compensation transistor T3 is turned on, and second light-emitting control transistor T6 is turned off; EM(n+2) is low, first light-emitting control transistor T5 is turned on; the scanning signal SCAN1 is high, the writing transistor T2 is turned off; EM2 is high, the reset transistor T4 is turned on. The signal of the first power supply end VDD resets the gate of the driving transistor T1 through the first light-emitting control transistor T5 and the compensation transistor T3. The reset signal VI resets the anode of the light-emitting device D1 through the reset transistor T4.

[0081] Write stage (M2): EM(n) is high, the compensation transistor T3 is turned on, and the second light-emitting control transistor T6 is turned off; EM(n+2) is high, the first light-emitting control transistor T5 is turned off; the scanning signal SCAN1 is low, the write transistor T2 is turned on; EM2 is high, the reset transistor T4 is turned on. The data signal DS charges the fourth node Q through the write transistor T2, the driving transistor T1 and the compensation transistor T3, until the potential of the fourth node Q reaches the sum of VDS and Vth. The anode potential of the light-emitting device D1 remains at the potential of the reset signal VI.

[0082] Bias stress elimination stage (M3): EM(n) is low, the compensation transistor T3 is turned off, and the second light-emitting control transistor T6 is turned on; EM(n+2) is high, the first light-emitting control transistor T5 is turned off; the scanning signal SCAN1 is high, the write transistor T2 is turned off; EM2 is high, the reset transistor T4 is turned on. The reset signal VI resets the second node B and the first node A through the reset transistor T4 and the second light-emitting control transistor T6, respectively, to alleviate or eliminate the on-state bias stress (OBS) of the driving transistor T1, thereby alleviating or eliminating the hysteresis effect of the driving transistor T1 and improving flicker.

[0083] Light-emitting stage (M4): EM(n) is low, the compensation transistor T3 is turned off, and the second light-emitting control transistor T6 is turned on; EM(n+2) is low, the first light-emitting control transistor T5 is turned on; the scanning signal SCAN1 is high, the write transistor T2 is turned off; EM2 is low, the reset transistor T4 is turned off. The light-emitting device D1 emits light, and the current flowing through the light-emitting device D1 is proportional to the square of (VDS-VVI).

[0084] Similarly, the bias stress elimination stage (M3) is located after the write stage (M2), and the bias stress elimination stage (M3) does not occupy the duration of the write stage (M2). Compared with Figure 1 The pixel circuit 10 shown in FIG. 8 can make the duration of writing the data signal DS longer, which is beneficial to realize a higher display frequency.

[0085] In addition, from Figure 14 It can be seen that the pulse start time of the third light-emitting control signal EM2 is the same as the pulse start time of the second light-emitting control signal, and the pulse end time of the third light-emitting control signal is the same as the pulse end time of the first light-emitting control signal.

[0086] It should be noted that, compared with Figure 12 , the present embodiment can be used to increase the duration of the initialization stage and the duration of the bias stress elimination stage.

[0087] In some embodiments, the present embodiments provide a display panel 100 as shown in Figure 15 The display panel 100 includes the pixel circuit 10 described above.

[0088] It can be understood that, since the display panel 100 provided by the present embodiments includes the pixel circuit 10 described above, by resetting the transistors T4, the second light-emitting control transistor T6 and the driving transistor T1 to be in the conductive state and the first light-emitting control transistor T5, the write transistor T2 and the compensation transistor T3 to be in the non-conductive state in a time period, the driving transistor T1 can be reset by the reset transistor T4 and the second light-emitting control transistor T6, which not only improves flicker, but also does not occupy the charging time since the driving transistor T1 is not reset by the write transistor T2, which is conducive to realizing higher refresh rate display.

[0089] In some embodiments, as shown in Figure 15 The display panel 100 further includes a display area AA, two light-emitting driving circuits 20 and two gate driving circuits 30, and the pixel circuit 10 is located in the display area AA. Each light-emitting driving circuit 20 is configured to output a first light-emitting control signal EM(n+2), a second light-emitting control signal EM(n) and a third light-emitting control signal EM(n+1), and the two light-emitting driving circuits 20 are located on opposite sides of the display area AA. Each gate driving circuit 30 is configured to output a scanning signal SCAN1, and the two gate driving circuits 30 are located on opposite sides of the display area AA.

[0090] It should be noted that the pixel circuit 10 in the present embodiments corresponds to the pixel circuit 10 as shown in Figure 11 The pixel circuit 10 is driven by two sides, so that the pixel circuit 10 only needs two groups of driving circuits (GOA), which is conducive to realizing narrower frame and higher refresh rate, and also reduces power consumption since the number of groups of driving circuits is reduced.

[0091] Wherein, EM(n+1) and EM(n+2) can be replaced by EM(n+x) and EM(n+y) in turn, where x < y, i.e. n < n+x < n+y, the time of the initialization stage and the time of the bias stress elimination are adjusted by the size of x and y.

[0092] Figure 16 For the timing comparison schematic diagram of the pixel circuit 10 working in the write frame and the holding frame as shown in Figure 11 It should be noted that in variable refresh rate display, one frame of the pixel circuit 10 can be a write frame or a holding frame. Wherein, the write frame includes Figure 12M1-M4 are shown, while the EM(n), EM(n+1), EM(n+2) in the frame are kept at low level, and the scanning signal SCAN1 is kept at high level. This case also applies to Figure 13 The pixel circuit 10 is shown.

[0093] wherein, in the case of Figure 16 Hz, then the refresh rate of one write frame or one holding frame is 120 Hz, and the display of 10 Hz refresh rate needs 12 continuous frames to realize. The first frame in the 12 continuous frames is the write frame of 10 Hz display, and the following 11 frames are the holding frames of 10 Hz display.

[0094] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0095] The pixel circuit 10 and the display panel 100 provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples in this paper. The above description of the embodiments is only used to help understand the technical solutions of the present application and the core idea thereof; those skilled in the art should understand that the technical solutions recorded in the above embodiments can still be modified, or some technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A pixel circuit, characterized in that: The pixel circuit comprises: A first light-emitting control transistor, a driving transistor, a second light-emitting control transistor, and a light-emitting device connected sequentially between the first power supply terminal and the second power supply terminal; a storage capacitor connected between the gate of the driving transistor and the anode of the light emitting device; a compensation transistor connected between the gate of the driving transistor and the first electrode of the driving transistor; a write transistor connected between the second electrode of the drive transistor and the data line; a reset transistor connected between a reset line and an anode of the light emitting device; In one time period, the reset transistor, the second light emission control transistor and the driving transistor are all in an on state, and the first light emission control transistor, the write transistor and the compensation transistor are all in an off state.

2. The pixel circuit according to claim 1, wherein: The gate of the write transistor is connected to a scan signal, the gate of the first light-emitting control transistor is connected to a first light-emitting control signal, the gate of the second light-emitting control transistor is connected to a second light-emitting control signal, the gate of the reset transistor is connected to the first light-emitting control signal, and the gate of the compensation transistor is connected to the second light-emitting control signal.

3. The pixel circuit according to claim 1, wherein: The gate of the write transistor is connected to a scan signal, the gate of the first light-emitting control transistor is connected to a first light-emitting control signal, the gate of the second light-emitting control transistor is connected to a second light-emitting control signal, the gate of the reset transistor is connected to a third light-emitting control signal, and the gate of the compensation transistor is connected to the second light-emitting control signal; The first light emitting control signal is identical to the second light emitting control signal in amplitude, frequency, and duty cycle, and a phase of the first light emitting control signal is different from a phase of the second light emitting control signal.

4. The pixel circuit according to claim 3, wherein: The third light-emitting control signal is the same as the first light-emitting control signal and the second light-emitting control signal in amplitude, frequency and duty cycle, and the phase of the third light-emitting control signal is different from the phase of the first light-emitting control signal and the phase of the second light-emitting control signal.

5. The pixel circuit according to claim 4, wherein: The first light-emitting control signal is an n+2th level light-emitting control signal, the second light-emitting control signal is an nth level light-emitting control signal, and the third light-emitting control signal is an n+1th level light-emitting control signal.

6. The pixel circuit according to claim 3, wherein: The third light-emitting control signal is different from the first light-emitting control signal and is the same as the second light-emitting control signal in amplitude, frequency and duty cycle, and the phase of the third light-emitting control signal is different from either the phase of the first light-emitting control signal or the phase of the second light-emitting control signal.

7. The pixel circuit according to claim 6, wherein: The first light-emitting control signal is the n+2th level light-emitting control signal, and the second light-emitting control signal is the nth level light-emitting control signal; in one frame, the pulse start time of the third light-emitting control signal is the same as the pulse start time of the second light-emitting control signal, and the pulse end time of the third light-emitting control signal is the same as the pulse end time of the first light-emitting control signal.

8. The pixel circuit according to any one of claims 1 to 7, wherein: The working phases of the pixel circuit in one frame include an initialization phase, a writing phase, a bias stress relief phase and a light emitting phase in sequence; In the bias stress elimination phase, the reset transistor and the second light emission control transistor are both in an on state, and the write transistor, the first light emission control transistor and the compensation transistor are all in an off state.

9. The pixel circuit according to claim 8, wherein: In the initialization phase, the first light emission control transistor and the compensation transistor are synchronously turned on first, and the reset transistor is turned on later. The write transistor and the second light emission control transistor are both in an off state.

10. The pixel circuit according to any one of claims 3 to 7, wherein: The pulse start time of the third light-emitting control signal is the same as the pulse start time of the second light-emitting control signal, and the pulse end time of the third light-emitting control signal is the same as the pulse end time of the first light-emitting control signal, so as to increase the duration of the initialization phase and the duration of the bias stress elimination phase.

11. The pixel circuit according to any one of claims 1 to 7, wherein: The communication type of the first light emission control transistor is the same as the channel type of the second light emission control transistor, the channel type of the compensation transistor is the same as the channel type of the reset transistor, and the communication type of the first light emission control transistor is different from the channel type of the compensation transistor.

12. A display panel, characterized in that: The display panel includes: The pixel circuit according to any one of claims 1 to 11, wherein the pixel circuit is located in a display area; two light-emitting driving circuits for outputting the first light-emitting control signal, the second light-emitting control signal, and the third light-emitting control signal, the two light-emitting driving circuits being located on opposite sides of the display area; Two gate driving circuits are used to output the scanning signal, and the two gate driving circuits are respectively located at opposite sides of the display area.

Images