Use method of novel nonvolatile memory based on RRAM + FCM structure

Abstract

The invention provides a use method of a novel nonvolatile memory based on an RRAM + FCM structure, and relates to the technical field of novel nonvolatile memorizes.The use method comprises the steps that an FCM device and an RRAM device are connected in series, and a memory device is obtained; the high and low resistance states of the RRAM device and the high and low capacitance states of the FCM device are regulated and controlled by adjusting the applied voltage; by adjusting the voltage applied to the two electrodes of the memory, the working delay of the memory is adjusted, a working delay adjusting result is obtained, and the defects that the switching ratio of a memory device designed by a traditional ferroelectric capacitor is not enough, misjudgment is easily caused by external signal interference and the like are overcome. Meanwhile, the multi-valued storage can be realized, more environment conditions can be applied, and the method has the advantages of high speed, low power consumption, long retention time and the like.

Description

TECHNICAL FIELD

[0001] The application provides a use method of a new nonvolatile memory based on an RRAM+FCM structure, and relates to the technical field of the new nonvolatile memory, in particular to the technical field of the new nonvolatile memory based on the RRAM+FCM structure. BACKGROUND

[0002] A traditional memory use method utilizes a memristor (RRAM) and a ferroelectric capacitor memory (FCM) in series to form an RC memory, wherein the RRAM shows two resistance states, i.e., a high resistance state (HRS) and a low resistance state (LRS), under different write voltages, for example, 100KΩ and 1KΩ. The RRAM structure is very simple, is compatible with a standard CMOS process, has the characteristics of low working voltage, fast read-write speed and low power consumption, and the storage information unit is a variable resistance realized by one or more metal oxides, which has been widely studied in the application of nonvolatile memories; the ferroelectric capacitor shows a capacitance switch between a high capacitance state (HCS) and a low capacitance state (LCS) by applying a proper voltage, and has the advantages of fast read-write speed and low power consumption, but the highest high-to-low capacitance ratio can only reach about 100, and the state misjudgment is caused by the interference of external noise signals; the traditional ferroelectric memory is affected by defects and electrode interface effects, and thus the device durability is reduced. SUMMARY

[0003] The application provides a use method of a new nonvolatile memory based on an RRAM+FCM structure, so as to solve the problems that the high-to-low capacitance ratio of a traditional ferroelectric capacitor is not large enough, the state misjudgment is caused by the interference of external noise signals, the device durability is reduced due to the defects of ferroelectric materials and electrode interface effects, the number of read-write cycles of the device is small, the number of cycles is not enough, and the device is difficult to be mass-produced in industrialization and the like. The application provides a use method of a new nonvolatile memory based on an RRAM+FCM structure, and the method comprises the following steps: The FCM device and the RRAM device are connected in series to obtain a memory device. The high-to-low resistance states of the RRAM device and the high-to-low capacitance states of the FCM device are regulated by adjusting the applied voltage. The working delay of the memory is adjusted by adjusting the voltage applied to the two poles of the memory, and a working delay adjustment result is obtained.

[0004] Further, the RRAM device comprises an RRAM bottom electrode material 100, a metal oxide 101 and a top electrode material 102.

[0005] Further, the method of regulating high and low resistance states of the RRAM device and high and low capacitance states of the FCM device by adjusting the applied voltage comprises: applying a bias voltage to both poles of the RRAM device, and converting the set and reset states to each other to obtain high and low resistance states, and setting an upper limit of the current.

[0006] Further, the method of applying a bias voltage to both poles of the RRAM device and converting the set and reset states to each other to obtain high and low resistance states comprises: applying a forward bias voltage to both poles of the RRAM device to obtain an oxygen vacancy conduction channel formed inside the metal oxide; When the voltage increases, the oxygen vacancy conduction channel thickens, the current increases, the resistance decreases, and a low resistance state is obtained.

[0007] Further, the method of applying a bias voltage to both poles of the RRAM device and converting the set and reset states to each other to obtain high and low resistance states further comprises: applying a negative bias voltage to both poles of the RRAM device to obtain oxygen ions through the active electrode of the RRAM device, and controlling the oxygen vacancy conduction channel to be disconnected by the recombination of the oxygen ions and the oxygen vacancies in the conduction channel, thereby reducing the current and increasing the resistance to obtain a high resistance state. The device can also be in an intermediate state of different resistances by controlling the voltage size.

[0008] Further, the FCM device comprises a pn junction region 001, a ferroelectric material 002, a FCM bottom electrode material 003, a gate electrode material 004, and an oxide layer material 005.

[0009] Further, the method of regulating high and low resistance states of the RRAM device and high and low capacitance states of the FCM device by adjusting the applied voltage comprises: applying a bias voltage to both poles of the FCM device, and adjusting the size of the bias voltage to control the capacitance state of the device.

[0010] Further, the method of applying a bias voltage to both poles of the FCM device and adjusting the size of the bias voltage to control the capacitance state of the device comprises: applying a forward bias voltage to both poles of the FCM device to control the polarization of the ferroelectric material to be downward, so that electrons are attracted at the interface, and the width of the np depletion layer is increased to obtain a low capacitance state; applying a negative bias voltage to both poles of the FCM device to control the polarization of the ferroelectric material to be upward, so that holes are attracted at the interface, and the width of the np depletion layer is reduced to obtain a high capacitance state.

[0011] Further, the method of regulating high and low resistance states of the RRAM device and high and low capacitance states of the FCM device by adjusting the applied voltage comprises: sharing the RRAM bottom electrode material 100 and the gate electrode material 004 to become the gate electrode of the memory; The high and low resistance states of the RRAM device are controlled by adjusting the voltage applied between the top electrode material 102 and the bottom electrode material 100; The high and low capacitance states of the FCM device can be adjusted by adjusting the voltage applied between the gate electrode material 004 and the FCM bottom electrode material 003.

[0012] Furthermore, the working delay of the memory is adjusted by adjusting the voltage applied to the two electrodes of the memory to obtain the working delay adjustment result, including: Connect the RRAM and FCM devices in series and provide a static operating point through a voltage source; Adjust the working delay of the memory by adjusting the voltage; The calculation formula for delay is: tdelay=-R*C*ln((EV) / E) Where tdelay is the delay of the memory, E is the voltage between the resistor and the capacitor, V is the voltage to be reached between the capacitors, R is the resistor, and C is the capacitor.

[0013] Beneficial effects of the present invention: The present invention connects a ferroelectric capacitor memory and a memristor in series to produce a new type of memory. The memory has a delay characteristic due to its own capacitance and resistance, and its delay characteristic can be used to display a delay switch. When different capacitance states and resistance states are connected in series, the device has different RC delay values. These values ​​are used as storage windows for information, and the values ​​are read by adjusting the pulse width to achieve read and write functions. At the same time, the nonlinear resistance characteristics of RRAM and the high retention characteristics of the ferroelectric capacitor memory can be used to adjust the pulse width to achieve more stable multi-value storage; therefore, the present invention can effectively improve the shortcomings of ordinary ferroelectric capacitors that are easily interfered with and cause state misjudgment, amplify and distinguish different storage states, and improve the durability of the device. It solves the shortcomings of traditional ferroelectric capacitors used in designing memories that are easily interfered with by external signals and cause misjudgment. At the same time, the present invention can achieve multi-value storage, is applicable to more environmental conditions, has the advantages of high speed, low power consumption, long retention time, etc., and has obvious advantages compared to previous technologies.

[0014] Therefore, the present invention uses the working delay value of the device as the information storage window, adjusts the voltage to achieve the effect of changing the delay, and adjusts the read signal pulse width to achieve the reading of different signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Schematic diagram of the 2D structure of the RRAM device; Figure 2 Schematic diagram of the state transition I-V curve of the unipolar RRAM device; Figure 3 Schematic diagram of the 2D structure of the FCM device; Figure 4 C-V diagram for FCM device capacitance state conversion; Figure 5 2D structure diagram of RRAM-FCM device; Figure 6 schematic diagram of device working model; Figure 7 schematic diagram of V-T waveform in different working states of the device.

[0016] Reference numerals: 100, RRAM bottom electrode material; 101, metal oxide; 102, top electrode material; 001, pn junction region; 002, ferroelectric material; 003, FCM bottom electrode material; 004, gate electrode material, and 005, oxide layer material. DETAILED DESCRIPTION

[0017] The preferred embodiments of the present application will be described below in conjunction with the accompanying drawings, and it should be understood that the preferred embodiments described herein are only used to explain and illustrate the present application, and are not used to limit the present application.

[0018] In one embodiment of the present application, the present application provides a use method of a new nonvolatile memory based on RRAM+FCM structure, and the method comprises the following steps: connecting the FCM device and the RRAM device in series to obtain a memory device, as shown in Figure 5 . adjusting the high and low resistance states of the RRAM device and the high and low capacitance states of the FCM device by adjusting the applied voltage; adjusting the working delay of the memory by adjusting the voltage applied to the two poles of the memory, and obtaining the working delay adjustment result.

[0019] The RRAM device comprises an RRAM bottom electrode material 100, a metal oxide 101, and a top electrode material 102, as shown in Figure 1 .

[0020] The step of adjusting the high and low resistance states of the RRAM device and the high and low capacitance states of the FCM device by adjusting the applied voltage comprises the following steps: Figure 2 applying a bias voltage to the two poles of the RRAM device, as shown in , to convert the set and reset states into each other, obtain the high and low resistance states, and set the upper limit of the current.

[0021] The step of applying a bias voltage to the two poles of the RRAM device to convert the set and reset states into each other to obtain the high and low resistance states comprises the following steps: applying a forward bias voltage to the two poles of the RRAM device to obtain an oxygen vacancy conduction channel formed inside the metal oxide; When the voltage increases, the oxygen vacancy conduction channel becomes thicker, the current increases, the resistance decreases, and the low resistance state is obtained.

[0022] The two poles of the RRAM device are connected to the bias voltage, and the set and reset are converted to each other to obtain the high and low resistance states. The two poles of the RRAM device are connected to the bias voltage, and the set and reset are converted to each other to obtain the high and low resistance states.

[0023] The FCM device includes a pn junction region 001, a ferroelectric material 002, an FCM bottom electrode material 003, a gate electrode material 004, and an oxide layer material 005, as shown in Figure 3 The FCM device includes a pn junction region 001, a ferroelectric material 002, an FCM bottom electrode material 003, a gate electrode material 004, and an oxide layer material 005, as shown in The high and low resistance states of the RRAM device and the high and low capacitance states of the FCM device are adjusted by adjusting the applied voltage, including connecting the two poles of the FCM device to the bias voltage, and adjusting the bias voltage to control the capacitance state of the device, as shown in Figure 4 The high and low resistance states of the RRAM device and the high and low capacitance states of the FCM device are adjusted by adjusting the applied voltage, including connecting the two poles of the FCM device to the bias voltage, and adjusting the bias voltage to control the capacitance state of the device, as shown in The high and low resistance states of the RRAM device and the high and low capacitance states of the FCM device are adjusted by adjusting the applied voltage, including connecting the two poles of the FCM device to the bias voltage, and adjusting the bias voltage to control the capacitance state of the device, as shown in The two poles of the FCM device are connected to the bias voltage, and the set and reset are converted to each other to obtain the high and low resistance states. The two poles of the FCM device are connected to the bias voltage, and the set and reset are converted to each other to obtain the high and low resistance states.

[0024] The high and low resistance states of the RRAM device and the high and low capacitance states of the FCM device are adjusted by adjusting the applied voltage, including: The RRAM bottom electrode material 100 and the gate electrode material 004 are shared to become the gate electrode of the memory. The meaning of sharing is that the electrode materials of the two regions are the same, and the two parts can be combined into one part.

[0025] The high and low resistance states of the RRAM device are adjusted by adjusting the voltage applied between the top electrode material 102 and the bottom electrode material 100. The high and low capacitance states of the FCM device are adjusted by adjusting the voltage applied between the gate electrode material 004 and the FCM bottom electrode material 003.

[0026] The working principle and technical effects of the above technical solution are as follows: metal oxide is the region where the RRAM conductive channel is formed. Figure 2As shown, the electrodes of the RRAM device are connected to a bias voltage, and the SET and RESET processes can be converted into each other, corresponding to the high and low resistance states, wherein Icc is the upper limit of the current set to prevent the device from being broken down during the SET process. For unipolar RRAM, a positive bias voltage is applied to the electrodes of the device, and a thin oxygen vacancy conduction channel is formed inside the metal oxide. As the voltage increases, the conduction channel gradually thickens, the current increases, and the resistance decreases, showing a low resistance state. Conversely, as the bias voltage gradually decreases, the active electrode of the device releases oxygen ions, the oxygen ions combine with the channel oxygen vacancies, the channel gradually breaks, the current decreases, and the resistance increases, and the device shows a high resistance state. Therefore, the device can be controlled to be in different intermediate states of different resistances by adjusting the voltage.

[0027] The C-V diagram of the FCM device capacitance state conversion is shown. When a positive bias voltage is applied, the ferroelectric polarization is downward, a large number of electrons are attracted at the interface, the np depletion layer width increases, the depletion layer capacitance is generated, and the device shows a low capacitance state, realizing fast programming. When a negative bias voltage is applied, the ferroelectric polarization is upward, and holes are attracted at the interface. The holes come from the interband tunneling at the pn junction of the channel layer. At this time, the width of the depletion layer decreases, the depletion layer capacitance disappears, and the device shows a high capacitance state, realizing fast erasing. Therefore, the device can be controlled to be in different capacitance states by adjusting the bias voltage. The structure diagram of the memory device is shown. The device is formed by connecting the FCM structure and the RRAM structure in series, and the device materials and physical properties are described above. The gate electrode of the device is shared by 100 and 004. The high and low resistance states of the RRAM part of the device are adjusted by adjusting the voltage applied between the top electrode and the gate electrode. The high and low capacitance states of the FCM part of the device are adjusted by adjusting the voltage applied between the gate electrode and the bottom electrode. The determination of the working states of the two parts does not interfere with each other. The present application connects the ferroelectric capacitor memory and the memristor to make a new type of memory. The memory has a delay characteristic due to its capacitance and resistance. The delay characteristic can be used to display a delay switch. When different capacitance states and resistance states are connected in series, the device has different RC delay values. These values are used as information storage windows. The values are read by adjusting the pulse width, realizing the read and write functions. At the same time, the nonlinear resistance characteristic of the RRAM and the high retention characteristic of the ferroelectric capacitor memory are used. By adjusting the pulse width, more stable multi-value storage is realized. The high and low capacitance ratio of the traditional ferroelectric capacitor is not large enough, and it is easy to be disturbed by external noise signals, causing state misjudgment. The ferroelectric material is affected by defects, electrode interface effects, etc. The present application solves the problems of the traditional ferroelectric capacitor used in the design of the memory device, such as insufficient switching ratio, easy to be disturbed by external signals, and misjudgment.

[0028] Meanwhile, the application can realize multi-value storage, is suitable for more environmental conditions, has the advantages of high speed, low power consumption, long retention time and the like, and has obvious advantages compared with the prior art.

[0029] On the infrastructure, the RRAM device is composed of a bottom electrode material, a metal oxide and a top electrode material, and the resistance state is adjusted by the formation and rupture of an oxygen vacancy conduction channel; the FCM device contains a pn junction region, a ferroelectric material, a bottom electrode, a gate electrode and an oxide layer material, and the capacitance state is regulated by changing the width of the depletion layer using the ferroelectric polarization characteristics. When the two are connected in series, the integrated gate structure is formed through the shared design of the bottom electrode and the gate electrode.

[0030] The device realizes core performance control through a double-path independent adjustment mechanism. For the RRAM device, a positive bias can promote the formation of an oxygen vacancy conduction channel in the metal oxide, and the channel becomes thicker as the voltage increases, and the device enters a low resistance state; when a negative bias is applied, the oxygen ions provided by the active electrode combine with the channel oxygen vacancies to break the channel, and the device turns to a high resistance state, and the multi-grade intermediate resistance state can be stably realized through voltage amplitude control. For the FCM device, a positive bias makes the ferroelectric material polarize downward, the interface attracts electrons to make the np depletion layer wider, forming a low capacitance state; a negative bias makes the polarization upward, the interface attracts holes to make the depletion layer narrower, turning to a high capacitance state, and the continuous or stepwise change of the capacitance can be realized by adjusting the bias. In addition, by connecting the RRAM and FCM in series, the precise control of the working delay is realized by voltage regulation.

[0031] Through the independent adjustability of the resistance state and the capacitance state, the device has multi-dimensional storage capacity, and compared with the single parameter regulated memory, the information density is significantly improved; the combination of the intermediate resistance state and the wide range of capacitance adjustment simplifies the circuit design and reduces the power consumption; the shared electrode structure reduces the connection loss between devices, improves the regulation efficiency, and the adjustable characteristics of the working delay enhance the adaptability of the device in different circuit environments.

[0032] In an embodiment of the application, the RRAM device and the FCM device are connected in series, the working delay of the memory is adjusted by adjusting the voltage applied to the two poles of the memory, and the working delay adjustment result is obtained, including: The RRAM and FCM devices are connected in series, and a static operating point is provided by a voltage source, as shown in Figure 6 ; The working delay of the memory is adjusted by adjusting the voltage; The calculation formula of the delay is: tdelay=-R*C*ln((E-V) / E) Wherein, tdelay is the delay of the memory, E is the voltage between the resistance and the capacitor, V is the voltage to be reached between the capacitors, R is the resistance, and C is the capacitor. Figure 7 As shown in the voltage-time waveform diagram of the device in operation, t1 and t3 are the time instants of the low level "0" state, and t2 and t4 are the time instants of the high level "1" state, and different states of the device will obtain different delay values, such as "t2-t1" and "t4-t3".

[0033] The unit of the formula is second after reduction, and a recognized formula conversion method in the art is used.

[0034] The working principle and technical effects of the above technical solution are as follows: the RRAM and the FCM are connected in series during operation, and a voltage source provides a static operating point. The working mechanism of the memory is to adjust the operating delay of the device by adjusting the voltage, so the delay of the operating circuit can be calculated.

[0035] The working delay value of the device is used as an information storage window, the delay is changed by adjusting the voltage, and different signals are read by adjusting the pulse width of the read signal: the delay value is 1 ns, the pulse width is less than 1 ns, such as 0.1 ns, the read signal of 0.1 ns width reads "0", and the pulse width is greater than 1 ns, such as 2 ns, the read signal of 2 ns reads "1". By connecting the RRAM device and the FCM device in series, a delay-adjustable memory unit is constructed. The circuit provides a static operating point by a voltage source, which lays a foundation for delay adjustment. The core control mechanism is to dynamically adjust the resistance (R) of the RRAM and the capacitance value (C) of the FCM by changing the applied voltage, and then to accurately calculate the operating delay of the memory according to the formula tdelay=-RCln ((E-V) / E) (wherein E is the voltage between the resistance and the capacitor, and V is the voltage to be reached between the capacitors).

[0036] As shown in Figure 7 t1 and t3 correspond to the low level "0" state, t2 and t4 correspond to the high level "1" state, and the delay values (such as t2-t1 and t4-t3) under different states are different, which is due to the change of R and C parameters with the voltage during the conversion of high and low levels, resulting in dynamic change of the delay result.

[0037] The dynamic delay adjustment is realized by voltage control, which solves the limitation of fixed delay of the traditional memory and improves the flexibility of circuit timing adaptation; quantitative adjustment is realized based on a clear mathematical formula to ensure the accuracy of delay control and meet the timing requirements in different scenarios; in combination with the characteristics of RRAM and FCM, multiple delay levels are generated by using the difference between high and low level states, which effectively reduces the system power consumption and improves the operation efficiency, and is especially suitable for intelligent storage and computing scenarios that require flexible timing configuration.

[0038] Obviously, a person skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application belong to the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims

1. A method for using a novel non-volatile memory based on an RRAM+FCM structure, characterized in that: The method comprises: Connecting the FCM device and the RRAM device in series to obtain a memory device; By adjusting the applied voltage, the high and low resistance states of the RRAM device and the high and low capacitance states of the FCM device can be controlled; The working delay of the memory is adjusted by adjusting the voltage applied to the two electrodes of the memory to obtain the working delay adjustment result.

2. The method for using the novel non-volatile memory based on the RRAM+FCM structure according to claim 1, characterized in that: The RRAM device comprises an RRAM bottom electrode material (100), a metal oxide (101) and a top electrode material (102).

3. The method for using the novel non-volatile memory based on the RRAM+FCM structure according to claim 1, characterized in that: The method of regulating the high and low resistance states of the RRAM device and the high and low capacitance states of the FCM device by adjusting the applied voltage includes: A bias voltage is applied to the two poles of the RRAM device to convert between set and reset states, obtain high and low resistance states, and set the current upper limit.

4. The method for using the novel non-volatile memory based on the RRAM+FCM structure according to claim 3, characterized in that: The method of applying a bias voltage to the two electrodes of the RRAM device to perform set and reset conversion to obtain a high resistance state and a low resistance state includes: Applying a forward bias to the two electrodes of the RRAM device to obtain the oxygen vacancy conductive channel formed inside the metal oxide; When the voltage increases, the oxygen vacancy conductive channel becomes thicker, the current increases, the resistance decreases, and a low-resistance state is obtained.

5. The method for using the novel non-volatile memory based on the RRAM+FCM structure according to claim 3, characterized in that: The step of applying a bias voltage to the two electrodes of the RRAM device to perform set and reset conversions to obtain high and low resistance states further includes: A negative bias is applied to the two poles of the RRAM device, and oxygen ions are obtained through the active electrode of the RRAM device. The oxygen ions recombine with the oxygen vacancies in the conductive channel, controlling the oxygen vacancy conductive channel to disconnect, reduce the current, increase the resistance, and obtain a high-resistance state.

6. The method for using the novel non-volatile memory based on the RRAM+FCM structure according to claim 1, characterized in that: The FCM device comprises a pn junction region (001), a ferroelectric material (002), an FCM bottom electrode material (003), a gate electrode material (004), and an oxide layer material (005).

7. The method for using the novel non-volatile memory based on the RRAM+FCM structure according to claim 1, characterized in that: The high and low resistance states of the RRAM device and the high and low capacitance states of the FCM device are regulated by adjusting the applied voltage, including connecting a bias voltage to the two poles of the FCM device and controlling the capacitance state of the device by adjusting the bias voltage.

8. The method for using the novel non-volatile memory based on the RRAM+FCM structure according to claim 7, characterized in that: The method of applying a bias voltage to the two electrodes of the FCM device and controlling the capacitance state of the device by adjusting the bias voltage includes: Applying a forward bias to the two electrodes of the FCM device controls the polarization of the ferroelectric material downward, so that electrons are attracted at the interface, the width of the np depletion layer is controlled to increase, the depletion layer capacitance is generated, and a low capacitance state is obtained; Applying a negative bias to the two poles of the FCM device controls the polarization of the ferroelectric material to be upward, so that holes are attracted at the interface, the width of the np depletion layer is controlled to decrease, the depletion layer capacitance disappears, and a high capacitance state is obtained.

9. The method for using the novel non-volatile memory based on the RRAM+FCM structure according to claim 1, characterized in that: The method of regulating the high and low resistance states of the RRAM device and the high and low capacitance states of the FCM device by adjusting the applied voltage includes: The RRAM bottom electrode material (100) and the gate electrode material (004) are shared to form a gate electrode of the memory; The high and low resistance states of the RRAM device are controlled by adjusting the voltage applied between the top electrode material (102) and the bottom electrode material (100); The high and low capacitance states of the FCM device are adjusted by adjusting the voltage applied between the gate electrode material (004) and the FCM bottom electrode material (003).

10. The method for using the novel non-volatile memory based on the RRAM+FCM structure according to claim 1, characterized in that: The working delay of the memory is adjusted by adjusting the voltage applied to the two electrodes of the memory to obtain the working delay adjustment result, including: Providing a static operating point through a voltage source; By adjusting the voltage applied to the two poles of the memory, the working delay of the memory is adjusted; The calculation formula for delay is: tdelay=-R*C*ln((EV) / E) Where tdelay is the delay of the memory, E is the voltage between the resistor and the capacitor, V is the voltage to be reached between the capacitors, R is the resistor, and C is the capacitor.

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