Heat dissipation chip packaging structure, heat dissipation packaging device and electronic equipment

Abstract

The invention relates to the technical field of chip packaging, in particular to a heat dissipation chip packaging structure, a heat dissipation packaging device and electronic equipment.The heat dissipation chip packaging structure comprises a heat dissipation part, a chip, a packaging substrate and a heat conduction material layer, a containing groove used for fixing the chip is formed in the lower surface of the heat dissipation part, the first surface of the containing groove is connected with the heat conduction material layer, and the second surface of the containing groove abuts against the packaging substrate to form a containing space; and the chip is welded and fixed on the packaging substrate. According to the invention, the integrally formed heat dissipation part is multiplexed as a chip packaging structure and a heat dissipation structure, and the heat resistance of heat spread between the packaging structure and the heat dissipation structure is reduced, so that the heat is quickly spread to the outside, and the heat dissipation function and the working efficiency of the chip packaging structure are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip packaging, in particular to a heat dissipation chip packaging structure, a heat dissipation packaging device and an electronic device. BACKGROUND

[0002] With the development of chip research and development process, the heat brought by the computing power is also increasing, and the chip packaging structure process is also developing. The chip packaging structure process is a process of isolating the semiconductor chip from the external environment, providing electrical connection, mechanical protection and heat dissipation function, which plays an important role in improving the performance and reliability of the chip.

[0003] In the existing packaging process, the chip is fixed on the substrate by welding, wire bonding and other methods, and then the chip and the substrate are covered with plastic packaging material to protect the chip from the external environment, and the heat dissipation part is fixed on the packaging shell of the chip. In the actual packaging process, the thermal conductivity of the fixing glue used to fix the heat dissipation part is much lower than that of the heat dissipation part and the chip shell. Due to the existence of additional contact thermal resistance between different materials, the overall thermal resistance of the chip packaging structure hinders the heat conduction between materials and materials, making it difficult for heat to conduct and dissipate outward, which affects the heat dissipation function of the chip packaging structure.

[0004] Therefore, the prior art still needs to be improved and developed. SUMMARY

[0005] In view of the above problems of the prior art, the purpose of the present application is to provide a heat dissipation chip packaging structure, a heat dissipation packaging device and an electronic device, so as to solve the problems of high thermal resistance of heat transfer to the heat dissipation part in the existing chip packaging structure, low heat dissipation efficiency and affect the working efficiency of the chip.

[0006] The technical scheme of the present application is as follows: In a first aspect, the present application provides a heat dissipation chip packaging structure, which comprises: a heat dissipation part, a chip, a packaging substrate and a heat conductive material layer, wherein, The heat dissipation part is an integral structure, the lower surface of the heat dissipation part is provided with a containing groove for fixing the chip, the first surface of the containing groove is connected with the heat conductive material layer, the second surface of the containing groove is in abutment with the packaging substrate and forms a containing space with the packaging substrate; the heat dissipation part comprises upper heat dissipation fins, a heat dissipation substrate and lower heat dissipation fins; a plurality of upper heat dissipation fins are vertically arranged on the upper surface of the heat dissipation substrate, and a plurality of lower heat dissipation fins are vertically arranged on the lower surface of the heat dissipation substrate; The chip is welded and fixed on the upper surface of the packaging substrate and arranged in the containing space; The heat-conducting material layer is arranged at the upper surface of the chip, and is used for being in heat-conducting contact with the chip and the heat-dissipating part respectively, and conducting the heat generated inside the chip to the heat-dissipating part.

[0007] Further, the heat-dissipating part further comprises a supporting fin; wherein, The accommodating groove is arranged in the middle of the lower surface of the heat-dissipating substrate; the supporting fin is arranged at the edge of the accommodating groove, and is used for being fixedly connected with the upper surface of the packaging substrate; the lower heat-dissipating fin is located outside the accommodating groove; and the length of the upper heat-dissipating fin is greater than that of the lower heat-dissipating fin.

[0008] Further, at least one avoiding space is arranged on the lower heat-dissipating fin; a plurality of avoiding fins are vertically arranged in the avoiding space, or no fin structure is arranged in the avoiding space; when the plurality of avoiding fins are vertically arranged in the avoiding space, the avoiding fins are arranged on the lower surface of the heat-dissipating substrate, and the length of the avoiding fin is less than that of the lower heat-dissipating fin.

[0009] Further, the upper heat-dissipating fin is a plate-fin type fin or a needle-shaped fin, and the lower heat-dissipating fin is a plate-fin type fin or a needle-shaped fin.

[0010] Further, the heat-conducting material layer is one of a heat-conducting silicone grease layer, a heat-conducting silica gel layer, a heat-dissipating gasket layer, a phase change material layer, a phase change metal layer or a heat-conducting glue layer.

[0011] Further, a plurality of conductive bumps are arranged between the lower surface of the chip and the upper surface of the packaging substrate; the conductive bumps are arranged at the upper surface of the packaging substrate; the conductive bumps are used for being electrically connected with the chip and the packaging substrate respectively, and are used for conducting the heat generated inside the chip to the packaging substrate.

[0012] Further, a plurality of ball grid structures are arranged at the lower surface of the packaging substrate; the ball grid structures are arranged on the lower surface of the packaging substrate in an array form, and are used for conducting the heat of the packaging substrate to a printed circuit board.

[0013] Further, the material of the heat-dissipating part is one of aluminum, copper, aluminum alloy, iron and graphite.

[0014] In the second aspect, the application further provides a heat-dissipating packaging device, which comprises the heat-dissipating chip packaging structure and a printed circuit board; the heat-dissipating chip packaging structure is arranged on the printed circuit board; and the circuit on the printed circuit board is electrically connected with the packaging substrate of the heat-dissipating chip packaging structure.

[0015] In a third aspect, the present application further provides an electronic device comprising the chip heat dissipation packaging device as described above.

[0016] The present application provides a heat dissipation chip packaging structure, a heat dissipation packaging device and an electronic device. The heat dissipation chip packaging structure comprises a heat dissipation part, a chip, a packaging substrate and a heat conductive material layer. The heat dissipation part is an integral molding structure. A receiving groove for fixing the chip is arranged on the lower surface of the heat dissipation part. The first surface of the receiving groove is connected with the heat conductive material layer. The second surface of the receiving groove is in abutment with the packaging substrate and forms a receiving space with the packaging substrate. The chip is welded and fixed on the upper surface of the packaging substrate and arranged in the receiving space. The heat conductive material layer is arranged at the upper surface of the chip. The heat conductive material layer is used for being in heat conductive contact with the chip and the heat dissipation part respectively and conducting the heat generated inside the chip to the heat dissipation part. In the present application, the integral molding heat dissipation part can be used as the chip packaging structure and dissipate heat at the same time. The overall thermal resistance of the heat conductive channel is reduced to two layers. The overall thermal resistance of the chip packaging structure is significantly reduced. The heat is quickly dissipated to the outside. The heat dissipation function and working efficiency of the chip packaging structure are improved. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application. Those skilled in the art can also obtain other drawings according to the structures shown in these drawings without any creative effort.

[0018] Figure 1 is an embodiment of a chip packaging structure in the prior art.

[0019] Figure 2 is another embodiment of a chip packaging structure in the prior art.

[0020] Figure 3 is a schematic diagram of a chip packaging structure in the present application.

[0021] Figure 4 is a schematic diagram of a chip packaging structure in some preferred embodiments of the present application.

[0022] Figure 5 is a structural schematic diagram of a heat dissipation part in some preferred embodiments of the present application.

[0023] Figure 6 is a schematic diagram of the relative positions between the heat dissipation part and the chip in some preferred embodiments of the present application.

[0024] Figure 7is a schematic view of a chip packaging structure in another preferred embodiment of the present application.

[0025] In the drawings: 11, solder ball; 12, heat dissipation cover; 13, heat conductive adhesive; 14, wafer; 15, solder ball; 16, adhesive layer; 17, substrate; 18, heat dissipation packaging device; 100, heat dissipation part; 110, upper heat dissipation fin; 110a, upper plate fin type fin; 110b, upper needle-shaped fin; 120, heat dissipation substrate; 121, accommodating groove; 1211, first surface; 1212, second surface; 130, lower heat dissipation fin; 130a, lower plate fin type fin; 130b, lower needle-shaped fin; 140, support fin; 150, avoiding space; 200, chip; 300, packaging substrate; 400, heat conductive material layer; 500, conductive bump; 600, ball grid structure. DETAILED DESCRIPTION

[0026] The present application provides a heat dissipation chip packaging structure, a heat dissipation packaging device and an electronic device. In order to make the purpose, technical scheme and effect of the present application more clear and explicit, the present application will be further described in detail below with reference to the drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0027] In the embodiments and the patent application scope, unless the article has a specific limitation in the text, "a", "an", "said" and "the" can also include plural forms. If there is a description of "first", "second" and the like in the embodiments of the present application, the description of "first", "second" and the like is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features.

[0028] It should be further understood that the phrase "comprising" used in the specification of the present application means that the features, integers, steps, operations, elements and / or components exist, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their combinations. It should be understood that when we say that an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. In addition, "connected" or "coupled" used herein can include wireless connection or wireless coupling. The phrase "and / or" used herein includes all or any unit and all combinations of the associated listed items.

[0029] Those of skill in the art will understand that, in this application, terms such as "engaging", "coupling", "connecting", and "securing" are intended to refer to an interaction between components, devices, or structures, wherein the components, devices, or structures are joined or operate to together in one capacity or as one whole entity. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise, or clear from context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then "X employs A or B" is satisfied. In addition, the articles "a" and "an" as used in this application are intended to mean one or more unless otherwise indicated.

[0030] In addition, the technical solutions among various embodiments can be combined with each other, but it must be based on the fact that a person skilled in the art can realize the combination, and when the combination of technical solutions appears contradictory or cannot be realized, it should be considered that the combination of technical solutions does not exist, and is not within the protection scope required by the present application.

[0031] The inventor has found that the semiconductor packaging technology is a key process for protecting, connecting and supporting the manufactured integrated circuit chip, specifically involving packaging the exposed chip in a protective shell, and electrically connecting the chip with the external circuit through the conductive material on the chip packaging structure, and conducting the heat generated in the working process from the chip packaging structure to the external environment. It can be seen that the chip packaging provides necessary support for the electrical connection and heat dissipation of the chip, and plays a crucial role in the performance and stability of electronic products. In the existing packaging process, the chip is fixed on the substrate by welding, wire bonding and other methods, and then the chip and the substrate are covered with plastic packaging material to protect the chip from the external environment. During normal operation of the chip, the integrated circuit inside the chip will bear the computing task load, and the energy required for its work is input from the power pin of the chip, but not all energy can be converted into work, and part of the energy will be converted into heat. During use, if there is no proper heat conduction method, the chip may overheat, resulting in reduced performance and shortened service life of the chip, and even possible damage to the components.

[0032] The commonly used chip packaging structure in the prior art is as follows Figure 1As shown in the figure, the wafer 14 is flip-chip mounted and electrically connected to the substrate 17 through solder balls 15; the center part of the heat dissipation cover 12 is raised to form a raised part, the raised part of the heat dissipation cover 12 is connected to the upper surface of the wafer 14 through the heat conductive adhesive 13, the periphery of the heat dissipation cover 12 is fixedly connected to the substrate 17 through the adhesive layer 16, and a sealed space for accommodating the wafer 14 is formed below the raised part, the solder balls 11 are located on the lower surface of the substrate 17, and the substrate 17 is electrically connected to the external circuit through the solder balls 11. At this time, the wafer 14 has two heat conduction channels, one of which is from the upper surface of the heat dissipation cover 12 to the air, and the other of which is from the wafer 14 to the substrate 17 through the solder balls 15. Then, part of the heat is conducted by the substrate 17 to the solder balls 11, and further conducted by the solder balls 11 to the external material; the other part of the heat is conducted by the substrate 17 to the air. When the chip packaging structure conducts heat in a natural convection manner, the part of the heat conducted upward is small, most of the heat is conducted downward to the substrate 17 through the solder balls 15, resulting in limited heat dissipation effect of the chip packaging structure, and the existing chip packaging structure itself has limited heat dissipation efficiency, and additional heat dissipation packaging devices are needed to improve heat dissipation.

[0033] In order to improve the heat dissipation problem of the chip packaging structure, another existing chip packaging structure further provides a heat dissipation part on the basis of the heat dissipation cover scheme to improve the heat dissipation effect, and a structure diagram thereof is as follows Figure 2As shown. Wherein, on the basis of the above-mentioned existing chip packaging structure, by coating a layer of heat-conducting adhesive 13 at the upper surface of the heat dissipation cover 12, the heat dissipation packaging device 18 is pressed and fixed at the upper surface of the heat dissipation cover 12 through the heat-conducting adhesive 13. The heat dissipation packaging device 18 is used to play a heat-conducting role, which can be selected as any fin structure or other heat dissipation structure that increases the heat exchange area with air. When the chip packaging with the heat dissipation packaging device 18 works, a part of the generated heat is conducted from the upper surface of the wafer 14 to the heat dissipation cover 12 through the first layer of heat-conducting adhesive 13, and then conducted to the heat dissipation packaging device 18 through the second layer of heat-conducting adhesive 13 on the upper surface of the heat dissipation cover 12. Since the heat dissipation cover 12 and the heat dissipation packaging device 18 are two devices in the conventional scheme, a layer of heat-conducting adhesive 13 needs to be added for their connection and fixation in the processing process, and the heat-conducting adhesive 13 is generally selected as glue, whose thermal conductivity is much smaller than that of copper or aluminum and other metal materials used by the heat dissipation cover 12 and the heat dissipation packaging device 18. In addition, the heat-conducting adhesive 13 is arranged on the upper surface of the heat dissipation cover 12, and the heat dissipation packaging device 18 is fixedly connected above the heat-conducting adhesive 13, so that the heat propagation between the interface between the heat dissipation cover 12 and the heat-conducting adhesive 13 and the interface between the heat-conducting adhesive 13 and the heat dissipation packaging device 18 needs to cross materials with different thermal conductivities, volumes, densities and structures, which produces additional multi-layer contact thermal resistance between the materials. Specifically, the use of the conventional scheme will additionally increase a layer of heat-conducting adhesive, and correspondingly introduce two layers of contact thermal resistance, which inevitably leads to the reduction of the heat transfer rate and efficiency in the chip packaging structure.

[0034] To solve the above technical problems, in a first aspect, the present application provides a heat dissipation chip packaging structure, as shown in Figure 3As shown, it comprises: a heat dissipation part 100, a chip 200, a packaging substrate 300 and a heat conductive material layer 400, wherein the heat dissipation part 100 is an integrated structure, the lower surface of the heat dissipation part 100 is provided with a receiving groove 121 for fixing the chip 200, the first surface 1211 of the receiving groove 121 is connected with the heat conductive material layer 400; the second surface 1212 of the receiving groove 121 abuts against the packaging substrate 300 and forms a receiving space with the packaging substrate 300; the heat dissipation part 100 comprises upper heat dissipation fins 110, a heat dissipation substrate 120 and lower heat dissipation fins 130, a plurality of upper heat dissipation fins 110 are vertically arranged on the upper surface of the heat dissipation substrate 120, and a plurality of lower heat dissipation fins 130 are vertically arranged on the lower surface of the heat dissipation substrate 120; the chip 200 is welded and fixed on the upper surface of the packaging substrate 300 and arranged in the receiving space; the heat conductive material layer 400 is arranged at the upper surface of the chip 200, and the heat conductive material layer 400 is used for being in thermal contact with the chip 200 and the heat dissipation part 100 respectively, and conducting the heat generated inside the chip 200 to the heat dissipation part 100.

[0035] Specifically, the material of the heat dissipation part 100 is selected from one of aluminum, copper, aluminum alloy, iron and graphite, or other materials with good thermal conductivity, and an integrated structure is obtained by cutting, extruding, stamping, die casting and other processing methods. In the present application, the integrated heat dissipation part 100 can play a role in heat conduction as a heat dissipation structure. The receiving groove 121 comprises the first surface 1211 formed by inwardly recessing and the second surface 1212 formed at the surrounding position thereof, specifically, the heat dissipation part 100 is inverted and buckled on the packaging substrate 300, when the second surface 1212 of the receiving groove 121 abuts against the packaging substrate 300, a sealed receiving space for receiving the chip 200 is formed between the first surface 1211 of the receiving groove 121 and the upper surface of the packaging substrate 300, thereby realizing the integration of heat dissipation and packaging, and realizing the reuse of the chip packaging structure while achieving heat dissipation, and playing the role of placing, fixing, sealing and protecting the chip 200. When the chip 200 works, part of the heat generated inside is conducted upward to the heat dissipation part 100 through the heat conductive material layer 400, which can be equivalent to having two layers of contact thermal resistance. Since the heat dissipation part 100 is made of high thermal conductivity material, the heat in the heat dissipation part 100 is quickly conducted in the horizontal direction and to the end of the heat dissipation part 100 close to the air, realizing the rapid transfer of heat. At the same time, another part of the heat generated inside the chip 200 is conducted downward to the packaging substrate 300 from the second surface 1212 of the receiving groove 121, and is dissipated to the outside through the packaging substrate 300, and at the same time, since the heat dissipation part 100 is connected with the packaging substrate 300, the packaging substrate 300 can also conduct part of the heat to the heat dissipation part 100.

[0036] The heat dissipation part 100 can also be provided with a heat conductive material layer 400 made of a heat conductive interface material on the contact surface of the packaging substrate 300 to fill the gap at the contact position and further reduce the overall thermal resistance. The chip 200 is a semiconductor chip wafer, which can be made of a silicon wafer or other non-silicon-based materials that can be used as a wafer. The packaging substrate 300 is usually made of ceramic, BT resin, glass laminate or polyimide, and can also be made of other organic materials or flexible materials, which serves the function of electrical interconnection and mechanical support. Accordingly, the heat dissipation part 100 can be used to provide natural convection or forced convection. When the heat dissipation part 100 dissipates heat by natural convection, the heat dissipation surface area can be maximized and the heat can be conducted without adding active components. If the heat dissipation part 100 dissipates heat by forced convection, a fan device corresponding to the heat dissipation part 100 can be added externally, which is an active device for providing air flow through the heat dissipation part 100. Thus, the fan assembly forces cooler air to pass through the heat dissipation part 100 and generates turbulence inside the heat dissipation part 100 structure, improving the cooling performance of the heat dissipation part 100. The upper heat dissipation fins 110 are plate-fin type fins or needle-shaped fins, and the lower heat dissipation fins 130 are plate-fin type fins or needle-shaped fins.

[0037] Further provided by the present application, the heat dissipation part 100 further comprises a support fin 140; wherein the lower surface of the heat dissipation substrate 120 is provided with the accommodation groove 121 in the middle, and the support fin 140 is arranged at the edge of the accommodation groove 121 and fixedly connected to the upper surface of the packaging substrate 300; at this time, the second surface 1212 of the accommodation groove 121 is located on the lower surface of the support fin 140, that is, the support fin 140 is formed by the second surface 1212 of the accommodation groove 121 extending downward, so that the support fin 140 is reused to dissipate heat and fix the packaging substrate 300. The lower heat dissipation fin 130 is located outside the accommodation groove 121; the length of the upper heat dissipation fin 110 is greater than that of the lower heat dissipation fin 130.

[0038] It should be noted that, in order to intuitively display and illustrate the internal structure of the chip packaging structure, the Figures 4 to 7The structure diagram of the heat dissipation chip package structure after vertical cutting at both ends. In actual use, the chip 200 is located in the sealed space, specifically, the accommodating groove 121 is located on the vertical center line of the heat dissipation substrate 120, and the support fins 140 in four directions form a vertical facade structure, and when the support fins 140 are fixedly connected with the package substrate 300, a sealed accommodating space for accommodating the chip 200 is formed in the accommodating groove 121, so that the chip package structure can simultaneously play the functions of mechanically protecting the chip, electrically connecting and integrally dissipating heat.

[0039] In some preferred embodiments of the present application, the upper heat dissipation fins 110 and the lower heat dissipation fins 130 are plate-fin type fins, as shown in Figures 4 to 6 As shown, the upper heat dissipation fins 110 are upper plate-fin type fins 110a, the lower heat dissipation fins 130 are lower plate-fin type fins 130a, and the upper plate-fin type fins 110a are vertically arranged in an array structure on the upper surface of the heat dissipation substrate 120, and the lower plate-fin type fins 130a are vertically arranged in an array structure on the lower surface of the heat dissipation substrate 120. In another preferred embodiment of the present application, the upper heat dissipation fins 110 are upper needle-shaped fins 110b, the lower heat dissipation fins 130 are lower needle-shaped fins 130b, and similarly, the upper needle-shaped fins 110b are vertically arranged in an array structure on the upper surface of the heat dissipation substrate 120, and the lower needle-shaped fins 130b are vertically arranged in an array structure on the lower surface of the heat dissipation substrate 120, as shown in Figure 7 The needle-shaped fins can be at least one of rectangular fins, circular fins and elliptical fins, having the advantages of being light and small in volume, while having high volume efficiency and isotropicity, which means that the needle-shaped fins have the same characteristics in the face of airflow in each direction, facilitating the forced convection process.

[0040] It should be noted that in some other preferred embodiments, the upper heat dissipation fins 110 of the heat dissipation part 100 can be plate-fin type fins, and the lower heat dissipation fins 130 can be needle-shaped fins; or the upper heat dissipation fins 110 of the heat dissipation part 100 can be needle-shaped fins, and the lower heat dissipation fins 130 can be plate-fin type fins. The specific structures of the upper heat dissipation fins 110 and the lower heat dissipation fins 130 can be set according to the heat dissipation requirements, convection methods and chip models, which will not be described here.

[0041] Specifically, the heat dissipation part 100 is in contact with the upper surface of the chip 200 as a heat source through the heat conductive material layer 400, and spreads the heat in the chip 200 from the hot spot to the plane of the upper heat dissipation fins 110, the lower heat dissipation fins 130 and the support fins 140. The upper heat dissipation fins 110, the lower heat dissipation fins 130 and the support fins 140 can be cut or forged into any number of heat dissipation structures of any geometric shape, which are generally perpendicular to the base to disperse heat. Preferably, the upper heat dissipation fins 110, the lower heat dissipation fins 130 and the support fins 140 in the present application can be rectangular fins, so as to increase the overall surface area of the heat dissipation part 100, thereby increasing the total heat transferred and dissipated, and optimizing the heat dissipation effect.

[0042] Further, the lower heat dissipation fins 130 are further provided with at least one avoiding space 150, and a plurality of avoiding fins are vertically arranged in the avoiding space 150, or no fin structure is arranged. When the plurality of avoiding fins are vertically arranged in the avoiding space 150, the avoiding fins are arranged on the lower surface of the heat dissipation substrate, and the length of the avoiding fins is less than the length of the lower heat dissipation fins 130. Specifically, when there are other electrical elements such as inductors and capacitors on the external circuit to be assembled in the chip packaging structure, a certain space is needed, which results in that the lower heat dissipation fins 130 cannot be completely and regularly arrayed on the heat dissipation substrate 120. Therefore, the present application can refer to the relative position of the corresponding electronic components in space, and correspondingly arrange the avoiding space 150 at the occupied position. Further, according to the height of the corresponding electronic components, the avoiding fins of corresponding length can be arranged at the corresponding position of the avoiding space 150, and the minimum distance between the avoiding fins and the plane where the electronic components are located is greater than the maximum height of the electronic components, so as to leave the avoiding space 150 for the electronic components in the chip packaging structure while achieving a certain heat dissipation effect. The avoiding space 150 on the heat dissipation substrate 120 can also not be provided with additional avoiding fins, further reducing the influence of the heat conducted by the chip packaging structure on the working efficiency of the electronic components.

[0043] Further, the heat conductive material layer 400 adopts one of a heat conductive silicone grease layer, a heat conductive silicone rubber layer, a heat dissipation gasket layer, a phase change material layer, a phase change metal layer or a heat conductive glue layer. The heat conductive material layer 400 can adopt any organic material and / or inorganic material with high thermal conductivity and high flexibility, which can fully fill the pores of the contact surface and ensure that the thermal interface material has small contact thermal resistance with the contact surface.

[0044] In further implementation of the preferred embodiments of the present application, a first conductive structure layer is further included between the lower surface of the chip 200 and the upper surface of the packaging substrate 300, which is electrically connected with the chip 200 and the packaging substrate 300 respectively and used for conducting the heat generated inside the chip 200 to the packaging substrate 300; the first conductive structure layer includes a plurality of conductive bumps 500, which are located at the upper surface of the packaging substrate 300; the conductive bumps 500 are electrically connected with the chip 200 and the packaging substrate 300 respectively and used for conducting the heat generated inside the chip 200 to the packaging substrate 300. Flip-chip is to connect the chip 200 with the substrate directly through the conductive bumps on the surface of the chip 200 with the active surface facing down, which omits the long metal bonding wires and further shortens the signal transmission path; the conductive bumps 500 are used as the connecting bridge between the chip 200 and the printed circuit board (PCB), which are preferably made of tin and can also be made of other metals with excellent thermal conductivity.

[0045] Further, a second conductive structure is further provided at the lower surface of the packaging substrate 300, which is electrically connected with the packaging substrate 300 and used for conducting the heat of the packaging substrate 300 to the outside; the second conductive structure layer includes a plurality of ball grid arrays 600, which are installed on the lower surface of the packaging substrate 300 in an array form and used for conducting the heat of the packaging substrate 300 to the printed circuit board.

[0046] The several ball grid structures 600 constitute a ball grid array (BGA). The BGA packaging technology, i.e. the BGA packaging, is a surface mount technology applied to integrated circuits, and is often used to permanently mount devices such as microprocessors. Compared with other packaging methods such as the dual in-line package (DIP) or the quad flat package (QFP), the BGA packaging can accommodate more pins and achieve more complex computing tasks. On the other hand, compared with the periphery defined packaging type, the ball grids on the bottom surface of the chip 200 using the ball grid array can all be used as pins, and have a shorter average wire length to have better high-speed performance. The ball grid structure 600 is made of a conductive and heat-conductive material such as tin, lead or a metal alloy, thereby forming an electrical connection with the packaging substrate 300. Meanwhile, the ball grid structure 600 also provides a heat dissipation path for the BGA packaging, which is beneficial to improve the power density of the chip. Specifically, the connection points between the ball grid structure 600 and the packaging substrate 300 of the BGA packaging are two-dimensionally distributed, and the connection surface is wider, which can be equivalent to increasing the heat transfer area, reducing the junction plate thermal resistance of the chip 200, and providing good heat dissipation conditions for the chip 200.

[0047] Specifically, the chip packaging structure used in the prior art as shown in Figure 2 is tested for heat dissipation effect, and the heat dissipation effect of the heat dissipation chip packaging structure as shown in Figure 4 of the present application is tested. The test results are shown in Table 1.

[0048] Table 1

[0049] Wherein, Tj represents the chip junction temperature, Rj_hs represents the thermal resistance from the chip 200 to the heat dissipation part 100, and Rja represents the thermal resistance from the chip 200 to the environment. When the chip 200 is working, the main heat source of the microcircuit on the chip 200 is the temperature of the semiconductor junction, that is, the chip junction temperature. The chip junction temperature is the highest temperature in the chip packaging structure, which is usually higher than the shell temperature and the device surface temperature. The chip junction temperature can measure the time required for heat dissipation from the semiconductor wafer to the packaging device shell and the overall thermal resistance. The environment refers to the air environment around the chip packaging structure, that is, the thermal resistance from the chip 200 to the environment is the overall thermal resistance of the heat conduction channel from the chip 200 to the air. According to Table 1, the chip junction temperature in the present application is 96.529℃, the thermal resistance from the chip 200 to the heat dissipation part 100 is 4.61℃ / W, and the thermal resistance from the chip 200 to the environment is 15.31℃ / W. The junction temperature of the chip packaging structure in the prior art is 99.39℃, the thermal resistance from the chip 200 to the heat dissipation part 100 is 5.95℃ / W, and the thermal resistance from the chip 200 to the environment is 15.88℃ / W. According to Table 1, the chip junction temperature in the chip packaging structure of the present application is reduced by 3% compared with the conventional scheme, the thermal resistance from the chip 200 to the heat dissipation part 100 is reduced by 29%, and the thermal resistance from the chip 200 to the environment is reduced by 4%. It can be seen that the overall thermal resistance and the chip junction temperature during work of the chip packaging structure in the present application are lower than those of the conventional scheme, and the heat dissipation effect is better, and then according to the Arrhenius equation, the service life of the chip 200 in the chip packaging structure in the present application can be significantly improved.

[0050] In a second aspect, the present application also provides a heat dissipation packaging device, which comprises the heat dissipation chip packaging structure and the printed circuit board, the heat dissipation chip packaging structure is arranged on the printed circuit board, and the circuit on the printed circuit board is electrically connected with the packaging substrate of the heat dissipation chip packaging structure. As described in the specific embodiment of the heat dissipation chip packaging structure, the present application will not be repeated here.

[0051] In a third aspect, the present application also provides an electronic device, which comprises the chip heat dissipation packaging device, and as described in the specific embodiment of the heat dissipation chip packaging structure, the present application will not be repeated here.

[0052] The application provides a heat dissipation chip packaging structure, a heat dissipation packaging device and an electronic equipment. The heat dissipation chip packaging structure has the following beneficial effects:

[0053] The heat in the chip can be conducted to the heat dissipation part in the vertical direction or conducted to the packaging substrate in the downward direction, so that the double heat conduction channel heat dissipation is realized.

[0054] The heat dissipation of the heat dissipation part is mainly realized through the convection heat exchange, and the effect of the convection heat exchange is mainly positively correlated with the heat dissipation area.

[0055] The packaging structure with the lower heat dissipation fins can be provided with the arrayed lower heat dissipation fins, so that the lower space of the chip packaging structure is effectively utilized, the heat exchange area is increased on the basis of the same size of the chip area, the heat dissipation effect of the chip packaging structure under the limited chip space condition is significantly improved, and the heat dissipation packaging integration is realized.

[0056] It should be understood that the application of the application is not limited to the above examples, and those skilled in the art can make improvements or changes according to the above description, and all these improvements and changes shall belong to the protection scope of the appended claims of the application.

Claims

1. A heat dissipation chip packaging structure, characterized in that: include: heat dissipation part, chip, packaging substrate and thermal conductive material layer, wherein, The heat dissipation portion is an integrally formed structure, and a receiving groove for fixing the chip is provided on the lower surface of the heat dissipation portion. The first surface of the receiving groove is connected to the thermal conductive material layer, and the second surface of the receiving groove abuts against the packaging substrate and forms an accommodating space with the packaging substrate. The heat dissipation portion includes an upper heat dissipation fin, a heat dissipation substrate, and a lower heat dissipation fin; a plurality of the upper heat dissipation fins are vertically arranged on the upper surface of the heat dissipation substrate, and a plurality of the lower heat dissipation fins are vertically arranged on the lower surface of the heat dissipation substrate; The chip is soldered and fixed on the upper surface of the packaging substrate and is arranged in the accommodating space; The heat-conducting material layer is arranged on the upper surface of the chip, and is used for being in heat-conducting contact with the chip and the heat dissipation portion respectively, and conducting the heat generated inside the chip to the heat dissipation portion.

2. The heat dissipation chip packaging structure according to claim 1, characterized in that: The heat dissipation portion further includes supporting fins; wherein, The accommodating groove is opened in the middle of the lower surface of the heat dissipation substrate, and the supporting fin is arranged at the edge of the accommodating groove for being fixedly connected to the upper surface of the packaging substrate; The lower heat dissipation fin is located outside the accommodating groove; the length of the upper heat dissipation fin is greater than that of the lower heat dissipation fin.

3. The heat dissipation chip packaging structure according to claim 2, characterized in that: At least one avoidance space is also provided on the lower heat dissipation fin, and a plurality of avoidance fins are vertically arranged in the avoidance space, or no fin structure is provided; when a plurality of avoidance fins are vertically arranged in the avoidance space, the avoidance fins are arranged on the lower surface of the heat dissipation substrate, and the length of the avoidance fins is less than the length of the lower heat dissipation fin.

4. The heat dissipation chip packaging structure according to claim 2, characterized in that: The upper heat dissipation fins are plate-fin type fins or pin-shaped fins, and the lower heat dissipation fins are plate-fin type fins or pin-shaped fins.

5. The heat dissipation chip packaging structure according to claim 1, characterized in that: The thermally conductive material layer is one of a thermally conductive silicone grease layer, a thermally conductive silica gel layer, a heat dissipation gasket layer, a phase change material layer, a phase change metal layer or a thermally conductive glue layer.

6. The heat dissipation chip packaging structure according to claim 1, characterized in that: A plurality of conductive bumps are arranged between the lower surface of the chip and the upper surface of the packaging substrate, and the conductive bumps are located on the upper surface of the packaging substrate; the conductive bumps are respectively used to electrically connect to the chip and the packaging substrate, and to conduct the heat generated inside the chip to the packaging substrate.

7. The heat dissipation chip packaging structure according to claim 1, characterized in that: A plurality of ball grid structures are further provided on the lower surface of the packaging substrate. The ball grid structures are mounted on the lower surface of the packaging substrate in an array form and are used to conduct heat from the packaging substrate to the printed circuit board.

8. The heat dissipation chip packaging structure according to claim 1, characterized in that: The heat dissipation part is made of one of aluminum, copper, iron and graphite.

9. A heat dissipation packaging device, characterized in that: It comprises the heat dissipation chip packaging structure and a printed circuit board according to any one of claims 1 to 8, wherein the heat dissipation chip packaging structure is arranged on the printed circuit board, and the on-board circuit of the printed circuit board is electrically connected to the packaging substrate of the heat dissipation chip packaging structure.

10. An electronic device, characterized in that: The heat dissipation package device comprises the heat dissipation package device as claimed in claim 9.

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