A source-on-board power supply

Abstract

The application discloses a source-load integrated power supply which comprises an AC-DC conversion module, a DC-DC conversion module and a controllable load module. When the source-load integrated power supply works in a load mode, electric energy is consumed by the controllable load module and does not need to be input to a power grid, so that the source-load integrated power supply is not affected by the power grid, thereby outputting high-precision voltage and current. The electric energy is not fed back to the power grid, and the ripple can be reduced. The electric energy is not fed back to the power grid, so that harmonic current is not injected into the power grid, thereby the electromagnetic interference problem caused by other devices under the same power grid can be reduced. The electric energy is not fed back to the power grid, so that the source-load integrated power supply cannot work normally due to power grid abnormalities, and the influence on the stability of the power grid can be reduced, and the stability of the source-load integrated power supply is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power supply, in particular to a source-load integrated power supply. BACKGROUND

[0002] With the rapid development of science and technology, there are dual demands for high-precision constant voltage output and dynamic load simulation of power supply in testing and application scenarios, and a source-load integrated power supply emerges as the times require. The source-load integrated power supply is a kind of power electronic equipment integrating power supply and load functions, which has the ability of bidirectional energy flow, can output electric energy as a power supply and can absorb electric energy as a load, and is particularly suitable for new energy testing, laboratory power supply, automation production line, electric vehicle, battery detection and other scenes.

[0003] As shown in Figure 1 A system control block diagram of a source-load integrated power supply provided by the related art, the source-load integrated power supply is composed of a front-stage PFC (Power Factor Correction, power factor correction) circuit, a middle-stage CLLL circuit (Capacitor-Inductor-Inductor-Capacitor Resonant Converter Circuit, capacitor-inductor-inductor-capacitor resonant converter circuit) and a rear-stage BUCK-BOOST circuit.

[0004] In the power supply mode, the 220V AC power input from the power grid is first filtered by a two-stage EMI (Electromagnetic Interference) filter, which prevents power grid interference from entering the previous stage circuit and ensures that the electromagnetic interference signals generated by the system are not transmitted back to the power grid. The current transformer is set before the previous stage PFC circuit and is responsible for sampling the power grid current. Before the system starts, the temperature sensors of the previous stage PFC circuit and the subsequent BUCK-BOOST circuit collect temperature data (PFC side radiator temperature sampling and BUCK side radiator temperature sampling) and send them to the FPGA (Field Programmable Gate Array) for comparison. When the temperature exceeds the threshold value, the system shuts down to protect the components in the system. Before the previous stage circuit starts, the auxiliary power supply provides power for the control system to ensure normal startup and operation of the system. The previous stage can use an FPGA with the model Artix-7-A100T as the main control chip of the previous stage PFC circuit, which generates four PWM (Pulse Width Modulation) signals to drive the four MOSFETs in the previous stage PFC circuit. The FPGA with the model Artix-7-A100T also controls the switching tubes of the intermediate CLLC circuit by outputting four PWM signals to control the conduction and shutdown of the switching tubes in the intermediate CLLC circuit. The output four PWM signals, two PWM signals are used to drive the left side MOSFET of the transformer, and the other two PWM signals are used to drive the right side MOSFET of the transformer. Since the left side MOSFET is responsible for converting DC power into AC power, an isolation chip is added when driving the right side MOSFET to enhance the safety of the system. Another FPGA in the system establishes serial communication with the main MCU (Microcontroller Unit) to realize data exchange and instruction control. The model of the other FPGA can be FLEX8000, and the model of the main MCU can be STM32F412RGT6. The BUCK-BOOST circuit in the subsequent stage uses an FPGA with the model FLEX8000 to generate two PWM signals to control the switching tubes in the BUCK-BOOST circuit. Considering the output accuracy requirement (within 1mV), the system selects a 16-bit ADC (Analog-to-Digital Converter) to meet the high precision requirement. The protection devices of the system are composed of various sensors and the previous stage PFGA, which can monitor the output overvoltage of the previous stage PFC circuit, the overcurrent of the power grid current, and the over-power of the intermediate CLLC circuit. Once an abnormality is detected, the previous stage FPGA will adjust the conduction time of the MOSFET or completely stop its conduction to protect the system and avoid damaging the components.

[0005] In the load mode, the to-be-tested power supply is connected to the system for discharging, and the system inputs direct current to the rear-stage BUCK-BOOST circuit by adjusting the discharging mode (CC mode or CV mode) of the to-be-tested power supply according to the upper computer (set by human being). At this time, the rear-stage BUCK-BOOST circuit boosts the input direct current to 76V direct current, and inputs the 76V direct current into the intermediate-stage CLLC circuit, and then the intermediate-stage CLLC circuit reversely boosts the 76V direct current to 380V direct current and sends the 380V direct current into the front-stage PFC circuit. At this time, the current is inverted to 220V / 50HZ alternating current which can be fed into the power grid after passing through the front-stage PFC circuit, and the energy feedback process in the discharging test is completed, and the environmental protection of electric energy is realized.

[0006] The source-load integrated power supply provided in the related art feeds back electric energy to the power grid in the load mode. Due to the influence of the power grid, it is difficult for the source-load integrated power supply to output high-precision voltage and current; the electric energy feedback to the power grid has large ripple; when the electric energy is fed back to the power grid, the power electronic switch (such as IGBT (Insulated Gate Bipolar Transistor)) in the source-load integrated power supply will generate high-frequency switching action, which may inject harmonic current into the power grid, although the device is internally provided with a filter, but it may still cause electromagnetic interference (EMI, Electromagnetic Interference) to other precision instruments under the same power grid; in addition, the source-load integrated power supply works in the load mode, and feeds back electric energy to the power grid, which depends on a stable and reliable power grid. If the voltage or frequency of the power grid fluctuates sharply, or the power grid is powered off, the source-load integrated power supply will not work normally, and may even stop running for protection; a large amount of electric energy feedback to the power grid may also affect the stability of the power grid, and also affect the stability of the source-load integrated power supply. SUMMARY

[0007] The present application provides a source-load integrated power supply to solve the problems that when the source-load integrated power supply works in the load mode, the output voltage and current have low precision, large ripple, may cause electromagnetic interference to other devices under the same power grid, when the voltage or frequency of the power grid fluctuates sharply or the power grid is powered off, the source-load integrated power supply cannot work normally, and may also affect the stability of the power grid, and also affect the stability of the source-load integrated power supply.

[0008] The embodiment of the present application provides a source-load integrated power supply, which comprises an alternating current-direct current conversion module, a direct current-direct current conversion module and a controllable load module.

[0009] The AC-DC conversion module is electrically connected with the DC-DC conversion module, and the controllable load module is electrically connected with the first DC bus between the AC-DC conversion module and the DC-DC conversion module.

[0010] The AC-DC conversion module is configured to convert the first AC power inputted from outside into the first DC power when the source-load integrated power supply works in the power supply mode.

[0011] The DC-DC conversion module is configured to convert the first DC power into the second DC power and output the second DC power when the source-load integrated power supply works in the power supply mode, and convert the third DC power inputted from outside into the fourth DC power when the source-load integrated power supply works in the load mode.

[0012] The controllable load module is configured to not work when the source-load integrated power supply works in the power supply mode, and consume the power inputted into the controllable load module when the source-load integrated power supply works in the load mode.

[0013] In a possible implementation, the source-load integrated power supply further includes a voltage and current sampling module and a master control module.

[0014] The sampling end of the voltage and current sampling module is electrically connected with the second DC bus of one end of the DC-DC conversion module outputting the second DC power, and the master control module is electrically connected with the control end of the DC-DC conversion module and the output end of the voltage and current sampling module respectively.

[0015] The voltage and current sampling module is configured to sample the DC power of the second DC bus to obtain a voltage signal and / or a current signal.

[0016] The master control module is configured to control the conduction and the turn-off of a switch tube in the DC-DC conversion module based on the voltage signal and / or the current signal.

[0017] In a possible implementation, the source-load integrated power supply further includes a filtering module.

[0018] The filtering module is electrically connected with the DC-DC conversion module.

[0019] The filtering module is configured to perform filtering processing on the second DC power outputted by the DC-DC conversion module and output the second DC power to supply power for a load when the source-load integrated power supply works in the power supply mode, and perform filtering processing on the third DC power inputted from outside and output the filtered DC power to the DC-DC conversion module when the source-load integrated power supply works in the load mode.

[0020] In a possible implementation, the controllable load module is specifically configured to:

[0021] consume the power input to the controllable load module when the bus voltage of the first DC bus is greater than or equal to a preset threshold.

[0022] In a possible implementation, the controllable load module comprises a first load driving circuit and a first heat dissipation circuit.

[0023] The first load driving circuit is configured to output a driving signal for controlling the first heat dissipation circuit to work when the bus voltage is greater than or equal to the preset threshold.

[0024] The first heat dissipation circuit is configured to consume the power input to the controllable load module under the control of the driving signal.

[0025] In a possible implementation, the first load driving circuit comprises a first resistor, a second resistor, a first capacitor, and a first power amplifier.

[0026] A first end of the first resistor is electrically connected to a positive bus of the first DC bus, and a second end of the first resistor is electrically connected to a first end of the second resistor and a same-direction input end of the first power amplifier.

[0027] A second end of the second resistor is electrically connected to a ground end of the first power amplifier and grounded.

[0028] A reverse input end of the first power amplifier is electrically connected to a first end of the first capacitor for inputting a reference voltage, a power supply end of the first power amplifier is configured to input a first power supply voltage, and an output end of the first power amplifier is electrically connected to a second end of the first capacitor for outputting the driving signal.

[0029] In a possible implementation, the first load driving circuit comprises a fourth resistor, a fifth resistor, a sixth capacitor, a second power amplifier, and a digital-to-analog converter (DAC).

[0030] A first end of the fourth resistor is electrically connected to a positive bus of the first DC bus for inputting a bus voltage, and a second end of the fourth resistor is electrically connected to a first end of the fifth resistor and a same-direction input end of the second power amplifier.

[0031] A second end of the fifth resistor is electrically connected to a ground end of the second power amplifier and grounded.

[0032] The second power amplifier is electrically connected to the DAC and a first end of the sixth capacitor through a reverse input end, a power supply end of the second power amplifier is configured to input a first power supply voltage, and an output end of the second power amplifier is electrically connected to a second end of the sixth capacitor for outputting the driving signal.

[0033] The DAC is configured to output a reference voltage.

[0034] In a possible implementation, the master module is further configured to determine, after the source integrated power supply operates in the load mode, to send an enable signal to the controllable load module;

[0035] The controllable load module is specifically configured to, after receiving the enable signal and determining that the bus voltage of the first DC bus is greater than or equal to a preset threshold, consume power input to the controllable load module.

[0036] In a possible implementation, the controllable load module includes a second load driving circuit and a first heat dissipation circuit.

[0037] The second load driving circuit is configured to, after receiving the enable signal and determining that the bus voltage is greater than or equal to the preset threshold, output a driving signal for controlling the first heat dissipation circuit to work.

[0038] The first heat dissipation circuit is configured to, under the control of the driving signal, consume power input to the controllable load module.

[0039] In a possible implementation, the second load driving circuit includes a ninth resistor, a tenth resistor, a seventh capacitor, a third power amplifier, and a first switch.

[0040] A first end of the ninth resistor is electrically connected to a positive bus of the first DC bus, configured to input the bus voltage, a second end of the ninth resistor is electrically connected to a first end of the tenth resistor and a same-direction input end of the third power amplifier;

[0041] A second end of the tenth resistor is electrically connected to a ground end of the third power amplifier and grounded.

[0042] A reverse input end of the third power amplifier is electrically connected to a first end of the seventh capacitor, configured to input a reference voltage, a power supply end of the third power amplifier is electrically connected to a first end of the first switch, and an output end of the third power amplifier is electrically connected to a second end of the seventh capacitor, configured to output the driving signal.

[0043] A second end of the first switch is configured to input a first power supply voltage, and a control end of the first switch is electrically connected to the master module, configured to receive the enable signal.

[0044] In a possible implementation, the second load driving circuit includes an eleventh resistor, a twelfth resistor, an eighth capacitor, a fourth power amplifier, and a second switch.

[0045] The first end of the eleventh resistor is electrically connected with the first end of the positive bus of the first DC bus, for inputting the bus voltage, and the second end of the eleventh resistor is electrically connected with the co-directional input end of the fourth power amplifier, the first end of the twelfth resistor and the first end of the second switch tube;

[0046] The second end of the twelfth resistor is electrically connected with the second end of the second switch tube and the ground end of the fourth power amplifier, and grounded;

[0047] The reverse input end of the fourth power amplifier is electrically connected with the first end of the eighth capacitor, for inputting a reference voltage, the power supply end of the fourth power amplifier is for inputting a first power supply voltage, and the output end of the fourth power amplifier is electrically connected with the second end of the eighth capacitor, for outputting the driving signal;

[0048] The control end of the second switch tube is electrically connected with the master control module, for receiving the enable signal.

[0049] In a possible implementation, the second load driving circuit comprises a thirteenth resistor, a fourteenth resistor, a ninth capacitor, a fifth power amplifier and a second switch;

[0050] The first end of the thirteenth resistor is electrically connected with the positive bus of the first DC bus, for inputting the bus voltage, and the second end of the thirteenth resistor is electrically connected with the first end of the fourteenth resistor and the co-directional input end of the fifth power amplifier;

[0051] The second end of the fourteenth resistor is electrically connected with the ground end of the fifth power amplifier, and grounded;

[0052] The reverse input end of the fifth power amplifier is for inputting a reference voltage, the power supply end of the fifth power amplifier is for inputting a first power supply voltage, and the output end of the fifth power amplifier is electrically connected with the first end of the second switch;

[0053] The second end of the second switch is electrically connected with the second end of the ninth capacitor, for outputting the driving signal, and the control end of the second switch is electrically connected with the master control module, for receiving the enable signal.

[0054] In a possible implementation, the first heat dissipation circuit comprises at least one first heat dissipation sub-circuit;

[0055] For each first heat dissipation sub-circuit, the first heat dissipation sub-circuit comprises a first switch tube, a sixth resistor, a seventh resistor and an eighth resistor;

[0056] The first end of the first switch tube is electrically connected with the positive bus of the first DC bus, the second end of the first switch tube is electrically connected with the first end of the eighth resistor, and the control end of the first switch tube is electrically connected with the first end of the sixth resistor and the first end of the seventh resistor;

[0057] The second end of the sixth resistor is used for inputting the driving signal;

[0058] The second end of the seventh resistor and the second end of the eighth resistor are grounded.

[0059] In a possible implementation, the master module is further configured to determine, when the source-load integrated power supply works in the load mode, to send an enable signal to the controllable load module;

[0060] The controllable load module is specifically configured to consume power input to the controllable load module after receiving the enable signal.

[0061] In a possible implementation, the controllable load module comprises a third load driving circuit and a second heat dissipation circuit;

[0062] The first end of the third load driving circuit is used for inputting the enable signal, the second end of the third load driving circuit is electrically connected with the second end of the second heat dissipation circuit, the third end of the third load driving circuit is electrically connected with the third end of the second heat dissipation circuit, and the second end of the second heat dissipation circuit is used for inputting the bus voltage.

[0063] The third load driving circuit is configured to output a driving signal for controlling the second heat dissipation circuit to work after receiving the enable signal.

[0064] The second heat dissipation circuit is configured to consume power input to the controllable load module under the control of the driving signal.

[0065] In a possible implementation, the third load driving circuit comprises a sixth power amplifier, a sixteenth resistor, a seventeenth resistor and a diode;

[0066] The same-direction input end of the sixth power amplifier serves as the first end of the third load driving circuit, the reverse input end of the sixth power amplifier is electrically connected with the anode of the diode, the first end of the sixteenth resistor and the first end of the seventeenth resistor, the output end of the sixth power amplifier is electrically connected with the cathode of the diode and serves as the third end of the third load driving circuit, the power supply end of the sixth power amplifier is used for inputting a first power supply voltage, and the ground end of the sixth power amplifier is used for inputting a second power supply voltage.

[0067] The second end of the sixteenth resistor is the second end of the third load driving circuit;

[0068] The second end of the seventeenth resistor is grounded.

[0069] In a possible implementation, the second heat dissipation circuit includes a switch-on-off sub-circuit and at least one second heat dissipation sub-circuit;

[0070] In the case of including one second heat dissipation sub-circuit, the first end of the second heat dissipation sub-circuit and the second end of the second heat dissipation sub-circuit are both electrically connected to the third end of the switch-on-off sub-circuit, and the third end of the second heat dissipation sub-circuit is the first end of the second heat dissipation circuit;

[0071] In the case of including multiple second heat dissipation sub-circuits, the third end of a preceding second heat dissipation sub-circuit is electrically connected to the first end and the second end of a following second heat dissipation sub-circuit, the first end and the second end of a first second heat dissipation sub-circuit are both electrically connected to the third end of the switch-on-off sub-circuit, and the third end of a last second heat dissipation sub-circuit is the first end of the second heat dissipation circuit;

[0072] The first end of the switch-on-off sub-circuit is the second end of the second heat dissipation circuit, and the second end of the switch-on-off sub-circuit is the third end of the second heat dissipation circuit;

[0073] The switch-on-off sub-circuit is configured to, after receiving the driving signal, turn on a path between the first end of the switch-on-off sub-circuit and the third end of the switch-on-off sub-circuit;

[0074] For each second heat dissipation sub-circuit, the second heat dissipation sub-circuit is configured to, after the path between the first end of the switch-on-off sub-circuit and the third end of the switch-on-off sub-circuit is turned on, turn on a path between the first end of the second heat dissipation sub-circuit and the third end of the second heat dissipation sub-circuit, and turn on a path between the second end of the second heat dissipation sub-circuit and the third end of the second heat dissipation sub-circuit.

[0075] In a possible implementation, the switch-on-off sub-circuit includes an eighteenth resistor, a nineteenth resistor, a twentieth resistor, and a third switch tube;

[0076] The first end of the eighteenth resistor is electrically connected to the first end of the nineteenth resistor and the first end of the third switch tube, and serves as the first end of the switch-on-off sub-circuit, and the second end of the eighteenth resistor is grounded;

[0077] The second end of the nineteenth resistor is electrically connected to the second end of the third switch tube, and serves as the third end of the switch-on-off sub-circuit;

[0078] The first end of the twentieth resistor is the second end of the on-off sub-circuit, and the second end of the twentieth resistor is electrically connected with the control end of the third switch tube.

[0079] In a possible implementation, the second heat dissipation sub-circuit comprises a fourth switch tube, a twenty-first resistor and a voltage stabilizing tube.

[0080] The first end of the fourth switch tube is the second end of the second heat dissipation sub-circuit, the second end of the fourth switch tube is electrically connected with the cathode of the voltage stabilizing tube and serves as the third end of the second heat dissipation sub-circuit, and the control end of the fourth switch tube is electrically connected with the second end of the twenty-first resistor and the anode of the voltage stabilizing tube.

[0081] The first end of the twenty-first resistor serves as the first end of the second heat dissipation sub-circuit.

[0082] The present application has the following advantages:

[0083] The source-load integrated power supply provided in the present application converts the first alternating current input from outside into the first direct current by the AC-DC conversion module when the source-load integrated power supply works in the power supply mode, converts the first direct current into the second direct current by the DC-DC conversion module, and outputs the second direct current to supply power to the load. When the source-load integrated power supply works in the load mode, the DC-DC conversion module converts the third direct current input from outside into the fourth direct current, and the controllable load module consumes the power input to the controllable load module. Since the power is consumed by the controllable load module when the source-load integrated power supply works in the load mode, it is not necessary to input to the power grid, so that the source-load integrated power supply is not affected by the power grid, thereby outputting high-precision voltage and current. Since the power is not fed back to the power grid, the ripple can be reduced. Since the power is not fed back to the power grid, the harmonic current is not injected into the power grid, thereby reducing the electromagnetic interference problem caused to other devices under the same power grid. Since the power is not fed back to the power grid, the source-load integrated power supply will not be unable to work normally due to the abnormality of the power grid, and the influence on the stability of the power grid can be reduced, and the stability of the source-load integrated power supply can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0084] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative labor.

[0085] Figure 1 A system control block diagram of a source-load integrated power supply provided by the related art is provided.

[0086] Figure 2 A structure diagram of a source-carrying integrated power supply provided for an embodiment of the present application;

[0087] Figure 3 A structure diagram of a source-carrying integrated power supply provided for another embodiment of the present application;

[0088] Figure 4 A structure diagram of a source-carrying integrated power supply provided for another embodiment of the present application;

[0089] Figure 5 A structure diagram of a controllable load module provided for an embodiment of the present application;

[0090] Figure 6 A circuit diagram of a first load driving circuit provided for an embodiment of the present application;

[0091] Figure 7 A circuit diagram of a first load driving circuit provided for another embodiment of the present application;

[0092] Figure 8 A circuit diagram of a first load driving circuit provided for another embodiment of the present application;

[0093] Figure 9 A circuit diagram of a first heat dissipation circuit provided for an embodiment of the present application;

[0094] Figure 10 A structure diagram of a source-carrying integrated power supply provided for another embodiment of the present application;

[0095] Figure 11 A structure diagram of a controllable load module provided for another embodiment of the present application;

[0096] Figure 12 A circuit diagram of a second load driving circuit provided for an embodiment of the present application;

[0097] Figure 13 A circuit diagram of a second load driving circuit provided for another embodiment of the present application;

[0098] Figure 14 A circuit diagram of a second load driving circuit provided for another embodiment of the present application;

[0099] Figure 15 A structure diagram of a controllable load module provided for another embodiment of the present application;

[0100] Figure 16 A circuit diagram of a third load driving circuit provided for an embodiment of the present application;

[0101] Figure 17A circuit schematic diagram of a second heat dissipation circuit provided for an embodiment of the present application is shown in FIG. 1.

[0102] Figure 18 A circuit schematic diagram of an interleaved parallel BUCK architecture provided for an embodiment of the present application is shown in FIG. 2.

[0103] Figure 19 A circuit schematic diagram of a full-wave rectification full-bridge topology architecture provided for an embodiment of the present application is shown in FIG. 3.

[0104] Figure 20 A circuit schematic diagram of a full-bridge rectification full-bridge topology architecture provided for an embodiment of the present application is shown in FIG. 4. DETAILED DESCRIPTION

[0105] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0106] In order to solve the problem that when the source-load integrated power supply works in the load mode, the output voltage and current are low in precision, the ripple is large, and the electromagnetic interference on other devices under the same power grid is caused, when the grid voltage or frequency fluctuates sharply or the power grid is powered off, the source-load integrated power supply cannot work normally, and the stability of the power grid is also affected, and the stability of the source-load integrated power supply is also affected, the present application provides a source-load integrated power supply. When the source-load integrated power supply works in the load mode, the controllable load module consumes the power input to the controllable load module. Since the power is consumed by the controllable load module when the source-load integrated power supply works in the load mode, there is no need to input to the power grid, so that the source-load integrated power supply is not affected by the power grid, thereby outputting high-precision voltage and current. The power is not fed back to the power grid, and the ripple can also be reduced. The power is not fed back to the power grid, so that the harmonic current is not injected into the power grid, thereby reducing the electromagnetic interference problem on other devices under the same power grid. The power is not fed back to the power grid, so that the source-load integrated power supply cannot work normally due to the abnormal power grid, and the influence on the stability of the power grid is also reduced, and the stability of the source-load integrated power supply is improved.

[0107] In order to facilitate understanding, the source-load integrated power supply provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0108] As Figure 2As shown, a structure schematic diagram of a source-load integrated power supply provided by an embodiment of the present application is shown, and the source-load integrated power supply comprises: an AC-DC conversion module 21, a DC-DC conversion module 22 and a controllable load module 24.

[0109] The AC-DC conversion module 21 and the DC-DC conversion module 22 are electrically connected, and the controllable load module 24 is electrically connected with the first DC bus between the AC-DC conversion module 21 and the DC-DC conversion module 22.

[0110] The AC-DC conversion module 21 is configured to convert the externally input first AC power into first DC power when the source-load integrated power supply works in a power supply mode.

[0111] The DC-DC conversion module 22 is configured to convert the first DC power into second DC power and output when the source-load integrated power supply works in the power supply mode, and convert the externally input third DC power into fourth DC power when the source-load integrated power supply works in a load mode.

[0112] The controllable load module 24 is configured to not work when the source-load integrated power supply works in the power supply mode, and consume the power input to the controllable load module 24 when the source-load integrated power supply works in the load mode.

[0113] In the embodiment of the present application, when the source-load integrated power supply works in the power supply mode, the AC-DC conversion module 21 converts the externally input first AC power into first DC power, and the DC-DC conversion module 22 converts the first DC power into second DC power and outputs to supply power to the load; when the source-load integrated power supply works in the load mode, the DC-DC conversion module 22 converts the externally input third DC power into fourth DC power, and the controllable load module 24 consumes the power input to the controllable load module 24. Since the electric energy is consumed by the controllable load module 24 when the source-load integrated power supply works in the load mode, it is not necessary to input to the power grid, so that the source-load integrated power supply can not be affected by the power grid, thereby outputting high-precision voltage and current; the electric energy is not fed back to the power grid, and the ripple can also be reduced; the electric energy is not fed back to the power grid, and the harmonic current is not injected into the power grid, thereby reducing the electromagnetic interference problem caused to other devices under the same power grid; the electric energy is not fed back to the power grid, and the source-load integrated power supply will not be unable to work normally due to the abnormal power grid, and the influence on the stability of the power grid can also be reduced, and the stability of the source-load integrated power supply can be improved.

[0114] It should be noted that in the embodiment of the present application, when the source-load integrated power supply works in the load mode, the AC-DC conversion module 21 does not work.

[0115] As Figure 3As shown, the integrated power supply provided in this application embodiment may further include a voltage and current sampling module 25 and a main control module 26. The sampling terminal of the voltage and current sampling module 25 is electrically connected to the second DC bus at one end of the DC-DC conversion module 22 that outputs the second DC power. The main control module 26 is electrically connected to the control terminal of the DC-DC conversion module 22 and the output terminal of the voltage and current sampling module 25, respectively.

[0116] The voltage and current sampling module 25 is used to sample the DC current of the second DC bus to obtain voltage and / or current signals;

[0117] The main control module 26 is used to control the switching transistors in the DC-DC conversion module 22 to turn on and off based on voltage and / or current signals.

[0118] In this embodiment, the DC-DC conversion module 22 is a bidirectional module. The main control module 26 can determine the working mode of the integrated source-carrier power supply based on voltage and / or current signals. When the integrated source-carrier power supply is determined to be working in power supply mode, the main control module 26 controls the DC-DC conversion module 22 to convert the input first DC power into the second DC power. When the main control module 26 determines that the integrated source-carrier power supply is working in load mode, it controls the DC-DC conversion module 22 to convert the externally input third DC power into the fourth DC power.

[0119] It should be noted that the DC-DC converter module 22 converts DC power to DC power, and the voltage of the DC power before and after conversion is different.

[0120] like Figure 3 As shown, the main control module 26 provided in this application embodiment may include a pulse width modulator, a controller, and an analog-to-digital converter. The analog-to-digital converter converts the voltage signal and / or current signal collected by the voltage and current sampling module 25 into a digital signal and sends it to the controller. Based on the received digital signal, the controller sends a control signal to the pulse width modulator to control the output of the PWM signal that controls the switching transistor in the DC-DC conversion module 22 to turn on and off.

[0121] In addition, the main control module 26 runs a digital control algorithm to comprehensively detect, regulate, and protect the power supply's voltage, current, power, frequency, timing, and other parameters.

[0122] like Figure 4As shown, the source-load integrated power supply can further include a filtering module 23 electrically connected with the DC-DC conversion module 22, i.e., the AC-DC conversion module 21, the DC-DC conversion module 22 and the filtering module 23 are electrically connected in sequence, the filtering module 23 is configured to perform filtering processing on the second DC power output by the DC-DC conversion module 22 when the source-load integrated power supply works in the power supply mode, and output the filtered DC power to supply power to the load, and perform filtering processing on the third DC power input from outside and output the filtered DC power to the DC-DC conversion module 22 when the source-load integrated power supply works in the load mode.

[0123] Figure 4 As shown, the source-load integrated power supply, one end of the filtering module 23 is electrically connected with the DC-DC conversion module 22, and the other end of the filtering module 23 is electrically connected with the sampling end of the voltage and current sampling module 25, the voltage and current sampling module 25 samples the filtered DC power output by the filtering module 23 when the source-load integrated power supply works in the power supply mode, and the DC-DC conversion module 22 converts the filtered DC power output by the filtering module 23 into the fourth DC power when the source-load integrated power supply works in the load mode.

[0124] The above is the description of the overall structure of the source-load integrated power supply, and the controllable load module disclosed in the embodiments of the present application will be described below.

[0125] In one embodiment, the controllable load module 24 consumes the power input to the controllable load module 24 when the bus voltage at the input end of the controllable load module 24 is greater than or equal to a preset threshold.

[0126] Specifically, as shown in Figure 5 As shown, a structure schematic diagram of a controllable load module provided by the embodiments of the present application, the controllable load module 24 includes a first load driving circuit 241 and a first heat dissipation circuit 242.

[0127] The first load driving circuit 241 is configured to output a driving signal Drv for controlling the operation of the first heat dissipation circuit 242 when the bus voltage at the input end of the controllable load module 24 is greater than or equal to a preset threshold.

[0128] The first heat dissipation circuit 242 is configured to consume the power input to the controllable load module 24 under the control of the driving signal Drv.

[0129] The preset threshold can be the operating voltage of the controllable load module 24.

[0130] In this embodiment, when the integrated source and load power supply operates in load mode, the voltage of the input power to the controllable load module 24 is greater than or equal to a preset threshold, that is, the voltage of the DC power input to the first load drive circuit 241 is greater than or equal to the preset threshold, which is also the voltage of the fourth DC power input is greater than or equal to the preset threshold. The first load drive circuit 241 outputs a drive signal Drv, such as a high-level signal. After receiving the drive signal Drv (high-level signal), the first heat dissipation circuit 242 consumes the power input to the controllable load module 24 to control the bus voltage to remain constant. When the source... When the integrated power supply operates in power mode, the voltage input to the controllable load module 24 is less than a preset threshold, that is, the DC voltage input to the first load drive circuit 241 is less than the preset threshold, and the voltage of the first DC voltage is less than the preset threshold. At this time, the first load drive circuit 241 outputs a non-drive signal that cannot drive the first heat dissipation circuit 242 to work, such as a low-level signal. After receiving the non-drive signal (low-level signal), the first heat dissipation circuit 242 does not work, that is, the controllable load module 24 does not work and does not consume the power input to the controllable load module 24.

[0131] In this embodiment, when the integrated source-load power supply operates in power mode, the first heat dissipation circuit 242 in the controllable load module 24 does not operate, and therefore does not consume the power input to the controllable load module 24. When the integrated source-load power supply operates in load mode, the first heat dissipation circuit 242 in the controllable load module 24 operates and consumes the power input to the controllable load module 24. Thus, without affecting the normal operation of the integrated source-load power supply, when the integrated source-load power supply operates in load mode, the energy fed back to the power supply is reduced, thereby reducing the impact on the stability of the power grid and improving the stability of the integrated source-load power supply.

[0132] like Figure 6 The diagram shown is a circuit diagram of a first load driving circuit provided in an embodiment of this application. (Refer to...) Figure 6 The first load drive circuit 241 includes a first resistor R1, a second resistor R2, a first capacitor C1, and a first power amplifier U1;

[0133] The first end of the first resistor R1 is electrically connected to the positive bus of the first DC bus, and the second end of the first resistor R1 is electrically connected to the first end of the second resistor R2 and the non-inverting input terminal of the first power amplifier U1.

[0134] The second end of the second resistor R2 is electrically connected to the ground terminal of the first power amplifier U1 and is grounded;

[0135] The reverse input end of the first power amplifier U1 is electrically connected with the first end of the first capacitor C1, for inputting a reference voltage Vref, the power supply end of the first power amplifier U1 is for inputting a first power supply voltage +VEE, and the output end of the first power amplifier U1 is electrically connected with the second end of the first capacitor C1, for outputting a driving signal Drv.

[0136] In the embodiment of the application, the first resistor R1 divides the input bus voltage, and inputs the divided voltage to the co-directional input end of the first power amplifier U1, the first power amplifier U1 compares the voltage inputted by the co-directional input end with the reference voltage Vref inputted by the reverse input end, when the voltage inputted by the co-directional input end is greater than or equal to the reference voltage Vref, the first power amplifier U1 outputs a high level signal, that is, the driving signal Drv, and when the voltage inputted by the co-directional input end is less than the reference voltage Vref, the first power amplifier U1 outputs a low level signal, that is, the non-driving signal.

[0137] It should be noted that the reference voltage Vref in the embodiment of the application is equal to the preset threshold value.

[0138] In another embodiment, as shown in FIG. 2, another circuit schematic diagram of the first load driving circuit provided by the embodiment of the application is provided, referring to Figure 7 , the first load driving circuit 241 further includes a third resistor R3, a second capacitor C2, a third capacitor C3, a fourth capacitor C4 and a fifth capacitor C5. Figure 7 The third resistor R3 is connected between the second end of the first resistor R1 and the co-directional input end of the first power amplifier U1.

[0139] The first end of the second capacitor C2 is electrically connected with the first end of the third capacitor C3 and the power supply end of the first power amplifier U1, the second end of the second capacitor C2 is electrically connected with the second end of the third capacitor C3, and is grounded.

[0140] The first end of the fourth capacitor C4 is electrically connected with the first end of the fifth capacitor C5 and the reverse input end of the first power amplifier U1, the second end of the fourth capacitor C4 is electrically connected with the second end of the fifth capacitor C5, and is grounded.

[0141] In the embodiment of the application, the second capacitor C2 and the third capacitor C3 are used to eliminate the power supply ripple of the first power supply voltage +VEE, and the fourth capacitor C4 and the fifth capacitor C5 make the reference voltage Vref more stable.

[0142] It should be noted that in the embodiment of the application

[0143] Figure 7 ​The first load driving circuit shown in the embodiment of the present application includes resistors and capacitors. The number of resistors and the number of capacitors are only illustrative. In specific embodiments, the number of resistors and the number of capacitors can also be other numbers, which are not limited in the embodiment of the present application.

[0144] As shown in Figure 8 , the circuit schematic diagram of another first load driving circuit provided by the embodiment of the present application is shown. Referring to Figure 8 , the first load driving circuit includes a fourth resistor R4, a fifth resistor R5, a sixth capacitor C6, a second power amplifier U2 and a DAC (Digital-to-Analog Converter, digital-to-analog converter);

[0145] The first end of the fourth resistor R4 is electrically connected to the positive bus of the first DC bus, for inputting the bus voltage. The second end of the fourth resistor R4 is electrically connected to the first end of the fifth resistor R5 and the same direction input end of the second power amplifier U2.

[0146] The second end of the fifth resistor R5 is electrically connected to the ground end of the second power amplifier U2 and grounded.

[0147] The reverse input end of the second power amplifier U2 is electrically connected to the DAC and the first end of the sixth capacitor C6. The power supply end of the second power amplifier U2 is used for inputting the first power supply voltage +VEE. The output end of the second power amplifier U2 is electrically connected to the second end of the sixth capacitor C6, and outputs the driving signal Drv.

[0148] The DAC is used for outputting the reference voltage Vref.

[0149] In the embodiment of the present application, the voltage value of the reference voltage Vref output by the DAC is adjustable. The reference voltage Vref output by the DAC can be adjusted according to actual needs to output a suitable voltage value, thereby improving the flexibility of the first load driving circuit.

[0150] The first heat dissipation circuit provided by the embodiment of the present application will be described in detail below.

[0151] As shown in Figure 9 , the circuit schematic diagram of a first heat dissipation circuit provided by the embodiment of the present application is shown, Figure 9 In the embodiment of the present application, the first heat dissipation circuit includes at least one first heat dissipation sub-circuit 2421.

[0152] For each first heat dissipation sub-circuit 2421, the first heat dissipation sub-circuit 2421 includes a first switch tube Q1, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8.

[0153] The first terminal of the first switch Q1 is electrically connected to the positive bus of the first DC bus, the second terminal of the first switch Q1 is electrically connected to the first terminal of the eighth resistor R8, and the control terminal of the first switch Q1 is electrically connected to the first terminals of the sixth resistor R6 and the seventh resistor R7.

[0154] The second terminal of the sixth resistor R6 is used to input the drive signal Drv;

[0155] The second terminal of the seventh resistor R7 and the second terminal of the eighth resistor R8 are both grounded.

[0156] It should be noted that, Figure 9 The first heat dissipation circuit includes six first heat dissipation sub-circuits 2421. In this embodiment, the number of first heat dissipation sub-circuits in the first heat dissipation circuit is only an example, and this embodiment does not limit it in any way.

[0157] In this embodiment, the first switching transistor Q1 can be a MOSFET. A parallel circuit of load MOSFETs is used, and all MOSFETs have the same operating voltage. The source-side resistor (sixth resistor R6) plays the role of current negative feedback. When the current of a certain MOSFET is too large, the voltage drop across the resistor also increases, the G (gate) and S (source) voltage of the MOSFET decreases, and the current flowing through the MOSFET also decreases accordingly.

[0158] For each first heat dissipation sub-circuit 2421, when the MOSFET in the first heat dissipation sub-circuit 2421 receives the drive signal Drv, the MOSFET operates in the linear region, and the MOSFET and resistor in the first heat dissipation sub-circuit 2421 consume the power input to the controllable load module 24.

[0159] In another embodiment, the main control module 26 is also used to send an enable signal EN to the controllable load module 24 after determining that the source-load integrated power supply is working in load mode. When the controllable load module 24 receives the enable signal EN and determines that the bus voltage of the first DC bus is greater than or equal to a preset threshold, it consumes the power input to the controllable load module 24.

[0160] Specifically, such as Figure 10 The diagram shown is a structural schematic of another source-carrier integrated power supply provided in an embodiment of this application. (Refer to...) Figure 10 The main control module 26 is also electrically connected to the controllable load module 24. When the main control module 26 determines that the integrated source and load power supply is working in load mode based on the voltage signal and / or current signal, it sends an enable signal EN to the controllable load module 24. When the controllable load module 24 receives the enable signal EN and determines that the bus voltage is greater than or equal to the preset threshold, it consumes the power input to the controllable load module 24.

[0161] In the embodiment, the controllable load module 24 consumes the power input to the controllable load module when the enable signal EN is received and it is determined that the bus voltage is greater than or equal to the preset threshold, which can prevent misoperation and improve the reliability of the controllable load module.

[0162] It should be noted that, Figure 10 This is only one specific embodiment, and in specific implementation, the source-load integrated power supply can also not include the filter module 23.

[0163] In one embodiment, the analog-to-digital converter in the main control module 26 converts the voltage signal and / or the current signal collected by the voltage and current sampling module 25 into a digital signal and sends it to the controller. The controller determines the working mode of the source-load integrated power supply based on the received digital signal. If it is determined that the source-load integrated power supply works in the power supply mode, the controller outputs a non-enable signal, such as a low-level signal. After the controllable load module 24 receives the non-enable signal, the controllable load module 24 is controlled not to work. If it is determined that the source-load integrated power supply works in the load mode, the controller sends an enable signal EN, such as a high-level signal, to the controllable load module 24.

[0164] In another embodiment, when the source-load integrated power supply works in the load mode, the voltage of the external power supply is greater than the set voltage of the source-load integrated power supply working in the power supply mode. Therefore, the current flows reversely from the external power supply into the source-load integrated power supply. When the main control module 26 detects the reverse current, it is determined that the source-load integrated power supply works in the load mode. Specifically, the main control module 26 can also include a bidirectional current detection amplifier circuit to realize the detection of the current direction.

[0165] In the embodiment, the enable control of the controllable load module 24 is added. When the source-load integrated power supply works in the power supply mode, the main control module 26 sends a non-enable signal. Whether the bus voltage of the input end of the controllable load module 24 exceeds the preset threshold, the controllable load module 24 does not work, which can prevent the misoperation of the controllable load module 24 and improve the reliability of the controllable load module 24.

[0166] In one embodiment, as Figure 11 shown, another structure of the controllable load module provided in the embodiment is shown in FIG. 6. Referring to Figure 11 , the controllable load module 24 includes a second load driving circuit 243 and a first heat dissipation circuit 242.

[0167] The second load driving circuit 243 is configured to output a driving signal Drv for controlling the working of the first heat dissipation circuit 242 when the enable signal EN is received and it is determined that the bus voltage is greater than or equal to the preset threshold.

[0168] The first heat dissipation circuit 242 is configured to consume power input to the controllable load module 24 under control of the driving signal Drv.

[0169] In the embodiment, the second load driving circuit 243 outputs the driving signal Drv based on the enable signal EN and the bus voltage, which can improve reliability of the controllable load module compared with outputting the driving signal Drv only based on the bus voltage.

[0170] In one embodiment, as shown in Figure 12 , a circuit schematic diagram of a second load driving circuit provided in the embodiment is provided, which is described in detail with reference to Figure 12 . The second load driving circuit includes a ninth resistor R9, a tenth resistor R10, a seventh capacitor C7, a third power amplifier U3, and a first switch S1.

[0171] The first end of the ninth resistor R9 is electrically connected to the positive bus of the first DC bus for inputting the bus voltage. The second end of the ninth resistor R9 is electrically connected to the first end of the tenth resistor R10 and the same direction input end of the third power amplifier U3.

[0172] The second end of the tenth resistor R10 is electrically connected to the ground end of the third power amplifier U3 and grounded.

[0173] The reverse input end of the third power amplifier U3 is electrically connected to the first end of the seventh capacitor C7 for inputting the reference voltage Vref. The power supply end of the third power amplifier U3 is electrically connected to the first end of the first switch S1. The output end of the third power amplifier U3 is electrically connected to the second end of the seventh capacitor C7 for outputting the driving signal Drv.

[0174] The second end of the first switch S1 is configured to input the first power supply voltage +VEE. The control end of the first switch S1 is electrically connected to the master control module 26 for receiving the enable signal EN.

[0175] In the embodiment, the first switch S1 is arranged at the power supply of the third operational amplifier U3. When the first switch S1 is disconnected, the third operational amplifier U3 has no power supply, and the driving function is disabled. Specifically, when the enable signal EN acts on the control end of the first switch S1, the first switch S1 is turned on, the power supply end of the third power amplifier U3 inputs the first power supply voltage +VEE, and the third power amplifier U3 starts to work. When the bus voltage is greater than or equal to the reference voltage Vref, the third power amplifier U3 outputs the driving signal Drv.

[0176] As shown in Figure 13 , a circuit schematic diagram of another second load driving circuit provided in the embodiment is provided, which is described in detail with reference to Figure 13The second load drive circuit includes an eleventh resistor R11, a twelfth resistor R12, an eighth capacitor C8, a fourth power amplifier U4, and a second switch Q2.

[0177] The first end of the eleventh resistor R11 is electrically connected to the positive bus of the first DC bus and is used to input the bus voltage. The second end of the eleventh resistor R11 is electrically connected to the non-inverting input terminal of the fourth power amplifier U4, the first end of the twelfth resistor R12, and the first end of the second switch Q2.

[0178] The second terminal of the twelfth resistor R12 is electrically connected to the second terminal of the second switch Q2 and the ground terminal of the fourth power amplifier U4, and is also grounded;

[0179] The inverting input terminal of the fourth power amplifier U4 is electrically connected to the first terminal of the eighth capacitor C8 and is used to input the reference voltage Vref. The power supply terminal of the fourth power amplifier U4 is used to input the first power supply voltage +VEE. The output terminal of the fourth power amplifier U4 is electrically connected to the second terminal of the eighth capacitor C8 and is used to output the drive signal Drv.

[0180] The control terminal of the second switch Q2 is electrically connected to the main control module 26 and is used to receive the enable signal EN.

[0181] In this embodiment, the second switch Q2 is connected in parallel with the pull-down resistor (the twelfth resistor R12). When the second switch Q2 is turned on, the pull-down resistor is short-circuited, and the voltage at the non-inverting input terminal of the fourth operational amplifier U4 is always less than the voltage at the inverting input terminal. The fourth operational amplifier U4 always outputs a low-level signal.

[0182] When the signal applied to the control terminal of the second switch Q2 is a non-enable signal, the second switch Q2 is turned on, the twelfth resistor R12 is short-circuited, the voltage at the non-inverting input terminal of the fourth operational amplifier U4 is always less than the voltage at the inverting input terminal, and the fourth operational amplifier U4 outputs a non-drive signal (low-level signal); when the signal applied to the control terminal of the second switch Q2 is the enable signal EN, the second switch Q2 is turned off. At this time, if the voltage after voltage division by the eleventh resistor R11 is greater than or equal to the reference voltage Vref, the fourth power amplifier U4 outputs a drive signal Drv (high-level signal).

[0183] like Figure 14 The diagram shown is a circuit schematic of another second load driving circuit provided in an embodiment of this application. (Refer to...) Figure 14 The second load drive circuit includes a thirteenth resistor R13, a fourteenth resistor R14, a ninth capacitor C9, a fifth power amplifier U5, and a second switch S2.

[0184] A first end of the thirteenth resistor R13 is electrically connected with a positive bus of the first DC bus, for inputting a bus voltage, a second end of the thirteenth resistor R13 is electrically connected with a first end of the fourteenth resistor R14 and a same direction input end of the fifth power amplifier U5;

[0185] A second end of the fourteenth resistor R14 is electrically connected with a ground end of the fifth power amplifier U5, and grounded;

[0186] A reverse input end of the fifth power amplifier U5 is used for inputting a reference voltage Vref, a power supply end of the fifth power amplifier U5 is used for inputting a first power supply voltage +VEE, and an output end of the fifth power amplifier U5 is electrically connected with a first end of the second switch S2;

[0187] A second end of the second switch S2 is electrically connected with a second end of the ninth capacitor C9, for outputting a driving signal Drv, and a control end of the second switch S2 is electrically connected with the main control module 26, for receiving an enable signal EN.

[0188] In the embodiment of the application, the second switch S2 is arranged at the output end of the fifth power amplifier U5, when the second switch S2 is opened, the signal output by the fifth power amplifier U5 cannot be transmitted to the first heat dissipation circuit, and the second load driving circuit is disabled.

[0189] That is, when the signal acting on the control end of the second switch S2 is a non-enable signal, the second switch S2 is opened, and the signal output by the fifth power amplifier U5 cannot be output through the second switch S2; when the signal acting on the control end of the second switch S2 is the enable signal EN, the second switch S2 is closed, at this time, if the voltage after voltage division by the thirteenth resistor R13 is greater than or equal to the reference voltage Vref, the driving signal Drv output by the fifth operational amplifier U5 is output through the second switch S2.

[0190] The above is the description of the second load driving circuit, the circuit structure of the first heat dissipation circuit 242 in the embodiment of the application can refer to the specific structure of the first heat dissipation circuit 242 in the above embodiment, which will not be repeated here.

[0191] In another embodiment, when the main control module 26 determines that the source load integrated power supply works in the load mode, the main control module 26 sends the enable signal EN to the controllable load module 24, and the controllable load module 24 consumes the power input to the controllable load module after receiving the enable signal EN.

[0192] Specifically, as shown in FIG. 4, another structure schematic diagram of a controllable load module provided by the embodiment of the application is provided, the controllable load module 24 includes a third load driving circuit 244 and a second heat dissipation circuit 245; Figure 15

[0193] ​The first end of the third load driving circuit 244 is configured to input an enable signal EN, the second end of the third load driving circuit 244 is electrically connected with the second end of the second heat dissipation circuit 245, the third end of the third load driving circuit 244 is electrically connected with the third end of the second heat dissipation circuit 245, and the third end of the third load driving circuit 244 is configured to output a driving signal Drv; and the first end of the second heat dissipation circuit 245 is configured to input a bus voltage.

[0194] The third load driving circuit 244 is configured to output the driving signal Drv for controlling the second heat dissipation circuit 245 to work after receiving the enable signal EN.

[0195] The second heat dissipation circuit 245 is configured to consume the power input to the controllable load module 24 under the control of the driving signal Drv.

[0196] In the embodiment, the main control module 26 outputs the enable signal EN when the source load integrated power supply works in the load mode, and the third load driving circuit 244 outputs the driving signal Drv as long as the enable signal EN is received, so that the second heat dissipation circuit consumes the power input to the controllable load module 24.

[0197] In the embodiment, the main control module 26 outputs the enable signal EN when the source load integrated power supply works in the load mode, and the third load driving circuit 244 outputs the driving signal Drv as long as the enable signal EN is received, so that the second heat dissipation circuit consumes the power input to the controllable load module 24. Figure 16 As shown in the circuit schematic diagram of the third load driving circuit provided by the embodiment, the third load driving circuit 244 includes a sixth power amplifier U6, a sixteenth resistor R16, a seventeenth resistor R17 and a diode D1.

[0198] The same direction input end of the sixth power amplifier U6 is used as the first end of the third load driving circuit 244 and is configured to input the enable signal EN, the reverse input end of the sixth power amplifier U6 is electrically connected with the anode of the diode D1, the first end of the sixteenth resistor R16 and the first end of the seventeenth resistor R17, the output end of the sixth power amplifier U6 is electrically connected with the cathode of the diode D1 and is used as the third end of the third load driving circuit 244 and is configured to output the driving signal Drv, the power supply end of the sixth power amplifier U6 is configured to input the first power supply voltage +VEE, and the grounding end of the sixth power amplifier U6 is configured to input the second power supply voltage -VEE.

[0199] The second end of the sixteenth resistor is used as the second end of the third load driving circuit 244.

[0200] The second end of the seventeenth resistor R17 is grounded.

[0201] In the embodiment, the same direction input end of the sixth power amplifier U6 inputs the enable signal EN (high level signal) and outputs the driving signal Drv (high level signal), wherein the diode D1 is used for preventing reverse, and the sixteenth resistor R16 and the seventeenth resistor R17 are used as voltage dividing resistors.

[0202] As Figure 17 shown, a circuit schematic diagram of a second heat dissipation circuit provided by an embodiment of the present application is provided, referring to Figure 17 , the second heat dissipation circuit includes a switch-on / off sub-circuit 2451 and at least one second heat dissipation sub-circuit 2452;

[0203] In the case of including one second heat dissipation sub-circuit, the first end of the second heat dissipation sub-circuit 2452 and the second end of the second heat dissipation sub-circuit 2452 are both electrically connected to the third end of the switch-on / off sub-circuit 2451, and the third end of the second heat dissipation sub-circuit 2452 serves as the first end of the second heat dissipation circuit, for inputting the bus voltage;

[0204] In the case of including multiple second heat dissipation sub-circuits, the third end of the front-stage second heat dissipation sub-circuit 2452 is electrically connected to the first end and the second end of the rear-stage second heat dissipation sub-circuit 2452, the first end and the second end of the first-stage second heat dissipation sub-circuit 2452 are both electrically connected to the third end of the switch-on / off sub-circuit 2451, and the third end of the last-stage second heat dissipation sub-circuit 2452 serves as the first end of the second heat dissipation circuit 245, for inputting the bus voltage;

[0205] The first end of the switch-on / off sub-circuit 2451 serves as the second end of the second heat dissipation circuit 245, and the second end of the switch-on / off sub-circuit 2451 serves as the third end of the second heat dissipation circuit 245, for receiving the driving signal Drv;

[0206] The switch-on / off sub-circuit 2451 is configured to, after receiving the driving signal Drv, turn on the path between the first end and the third end of the switch-on / off sub-circuit 2451;

[0207] For each second heat dissipation sub-circuit 2452, the second heat dissipation sub-circuit 2452 is configured to, after the path between the first end and the third end of the switch-on / off sub-circuit 2451 is turned on, turn on the path between the first end and the third end of the second heat dissipation sub-circuit 2452, and turn on the path between the second end and the third end of the second heat dissipation sub-circuit 2452.

[0208] In specific implementation, referring to Figure 17 , the switch-on / off sub-circuit 2451 includes an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, and a third switch tube Q3;

[0209] The first end of the eighteenth resistor R18 is electrically connected with the first end of the nineteenth resistor R19 and the first end of the third switch tube Q3, and serves as the first end of the on-off sub-circuit 2451, and the second end of the eighteenth resistor R18 is grounded;

[0210] The second end of the nineteenth resistor R19 is electrically connected with the second end of the third switch tube Q3, and serves as the third end of the on-off sub-circuit 2451;

[0211] The first end of the twentieth resistor R20 serves as the second end of the on-off sub-circuit 2451, and the second end of the twentieth resistor R20 is electrically connected with the control end of the third switch tube Q30.

[0212] Referring to Figure 17 The second heat dissipation sub-circuit 2452 includes the fourth switch tube Q4, the twenty-first resistor R21 and the voltage stabilizing tube Z1.

[0213] The first end of the fourth switch tube Q4 serves as the second end of the second heat dissipation sub-circuit 2452, the second end of the fourth switch Q4 is electrically connected with the cathode of the voltage stabilizing tube Z1, and serves as the third end of the second heat dissipation sub-circuit 2452, and the control end of the fourth switch tube Q4 is electrically connected with the second end of the twenty-first resistor R21 and the anode of the voltage stabilizing tube Z1.

[0214] The first end of the twenty-first resistor R21 serves as the first end of the second heat dissipation sub-circuit 2452.

[0215] It should be noted that, Figure 17 The second heat dissipation circuit 245 includes three second heat dissipation sub-circuits 2452 in the embodiment. Figure 17 The number of the second heat dissipation sub-circuits is only illustrative, and the embodiment of the present application does not make any limitation on this.

[0216] Referring to Figure 16 and Figure 17 When the source load integrated power supply works in the load mode, the sixth power amplifier U6 receives the enable signal EN and outputs the driving signal Drv, and after the on-off sub-circuit 2451 receives the driving signal Drv, the third switch tube Q3 is turned on, and after the third switch tube Q3 is turned on, the voltage stabilizing tube Z1 in series with the third switch tube Q3 is also turned on, and after the voltage stabilizing tube Z1 is turned on, the fourth switch tube Q4 is turned on.

[0217] In the embodiment of the present application, the fourth switch tube Q4 can be a MOSFET, and the MOSFET is turned on, thereby consuming the power output by the direct-current-direct-current conversion module 22, that is, consuming the power input to the second heat dissipation sub-circuit 2452. That is, the load MOS series circuit is adopted, which can ensure that the current flowing through each MOS tube is the same. In addition, the third switch tube Q3 in the embodiment of the present application can also be a MOSFET, and after the third switch tube Q3 is turned on, the input power can also be consumed.

[0218] The above is the description of the specific structure of the controllable load module in the embodiment of the present application. The specific structure of other modules of the source-load integrated power supply disclosed in the embodiment of the present application is described in detail below.

[0219] The AC-DC conversion module 21 in the embodiment of the present application can be a bidirectional AC-DC converter, which can convert the external input AC into DC, or convert DC into AC.

[0220] The source-load integrated power supply provided by the related art adopts a PFC circuit to convert between AC and DC. The control of the inverter mode of the PFC circuit presents a considerable challenge: when the PFC circuit is used as a grid-connected inverter, the core challenge lies in the quality of the grid-connected current. The inverter mentioned in the related art converts 220V / 50Hz AC, which requires a very precise phase-locked loop (PLL) to synchronize the phase and frequency of the grid, and a precise current loop control to ensure that the output current is a high-quality sine wave and in phase with the grid voltage (high power factor). There is a great challenge in high-precision phase-locked loop and low total harmonic distortion (THD) grid-connected current control.

[0221] The embodiment of the present application adopts an AC-DC converter to convert between AC and DC, which does not require a phase-locked loop and a current loop control compared to the PFC circuit, thereby reducing the control difficulty of the source-load integrated power supply.

[0222] The DC-DC conversion module 22 in the embodiment of the present application can be a bidirectional DC-DC converter, which can convert the input DC voltage into a higher or lower DC voltage. Since its energy can be stored in an electric field (capacitor) or a magnetic field (inductor or transformer), the efficiency is usually higher than 90%, even 95%, which is the main part of power energy transmission.

[0223] The source-load integrated power supply provided by the related art adopts a CLLC circuit to convert between DC and DC. On the one hand, due to the inconsistent bidirectional characteristics of the CLLC circuit, although the CLLC circuit supports bidirectional energy flow, its resonance parameters (resonant inductance, resonant capacitance) are usually optimized for a certain specific direction and power point. When the working direction is reversed (from load mode to power supply mode), the working frequency and voltage gain characteristics will change, making it difficult to achieve optimal efficiency and wide range of soft switching (ZVS / ZCS) in both directions, which may result in significant increase in switching loss and serious heating in a certain working mode.

[0224] On the other hand, controlling bidirectional CLLC circuits is far more complex than controlling unidirectional ones. Bidirectional CLLC circuits need to maintain stable output in both directions and handle the dynamic process during direction switching. Control strategies (typically frequency-modulated PFM or phase-shifted PSM) require drastically different adjustments in both forward and reverse modes, posing a significant challenge to FPGA algorithm design.

[0225] The embodiments of this application use a bidirectional DC-DC converter to convert DC power into DC power of different voltages. Compared with using a CLLC circuit, the control is simpler, and the switching loss and heat generation are smaller.

[0226] In one embodiment, the bidirectional DC-DC converter can be an interleaved parallel BUCK architecture, a full-wave rectified full-bridge topology architecture, or a full-bridge rectified full-bridge topology architecture. In specific implementations, in addition to the above three architectures, the bidirectional DC-DC converter can also be other structures used for DC-DC conversion, and the embodiments of this application do not limit this.

[0227] like Figure 18 The diagram shown is a circuit schematic of an interleaved parallel BUCK architecture provided in an embodiment of this application. Figure 18 In the interleaved parallel BUCK architecture, there are switches Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, inductors L1 and L2, and capacitors C13 and C14.

[0228] The first terminals of switching transistors Q11, Q15, Q13, and Q17 are electrically connected as the first positive terminal of the interleaved parallel BUCK architecture. The first terminals of switching transistors Q12, Q16, Q14, and Q18 are electrically connected as the first negative terminal of the interleaved parallel BUCK architecture.

[0229] The second terminal of switch Q11 is electrically connected to the second terminal of switch Q15, the first terminal of switch Q12, the first terminal of switch Q16, and the first terminal of inductor L1.

[0230] The second terminal of switch Q12 is electrically connected to the second terminal of switch Q16, capacitor C13, the second terminal of switch Q14, the second terminal of switch Q18 and the second terminal of capacitor C14, and grounded, serving as the second negative terminal of the interleaved parallel BUCK architecture;

[0231] One end of inductor L1 is electrically connected to one end of capacitor C13, one end of inductor L2 and one end of capacitor C14, serving as the second positive terminal of the interleaved parallel BUCK architecture;

[0232] The second terminal of switch Q13 is electrically connected to the second terminal of switch Q17, the first terminal of switch Q14, the first terminal of switch Q18, and the first terminal of inductor L2.

[0233] The first positive and first negative terminals of the interleaved parallel BUCK architecture are electrically connected to the AC-DC conversion module 21, and the second positive and second negative terminals of the interleaved parallel BUCK architecture are electrically connected to the filter module.

[0234] In this embodiment, the bidirectional DC-DC converter adopts an interleaved parallel BUCK architecture, suitable for products with an output voltage of less than 40V. When the source-load integrated power supply operates in power mode, the interleaved parallel BUCK architecture operates in BUCK topology; when the source-load integrated power supply operates in load mode, the interleaved parallel BUCK architecture operates in BOOST topology.

[0235] like Figure 19 The diagram shown is a circuit schematic of a full-wave rectifier full-bridge topology provided in an embodiment of this application. Figure 19 In the full-wave rectifier full-bridge topology, there are switches Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, inductors L3 and L4, capacitors C15 and C16, isolation transformers T1 and T2.

[0236] The first terminal of switch Q21 is electrically connected to the first terminals of switch Q23, switch Q27 and switch Q29, serving as the first positive terminal of the full-wave rectifier full-bridge topology. The second terminal of switch Q21 is electrically connected to the first terminal of switch Q22 and the first terminal of the primary winding of isolation transformer T1.

[0237] The second terminal of switching transistor Q23 is electrically connected to the first terminal of switching transistor Q24 and the second terminal of the primary winding of isolation transformer T1;

[0238] The second terminal of switch Q22 is electrically connected to the second terminals of switch Q24, switch Q28 and switch Q30, serving as the first negative terminal of the full-wave rectifier full-bridge topology.

[0239] The second terminal of switching transistor Q27 is electrically connected to the first terminal of switching transistor Q28 and the first terminal of the primary winding of isolation transformer T2.

[0240] The second terminal of switching transistor Q29 is electrically connected to the first terminal of switching transistor Q30 and the second terminal of the primary winding of isolation transformer T2.

[0241] The first terminal of the secondary coil of isolation transformer T1 is electrically connected to the second terminal of switching transistor Q25. The second terminal of the secondary coil of isolation transformer T1 is electrically connected to the second terminal of capacitor C15, the second terminal of inductor L4, and the second terminal of capacitor C16. The third terminal of the secondary coil of isolation transformer T1 is electrically connected to the second terminal of switching transistor Q26.

[0242] The first terminal of switching transistor Q25 is electrically connected to the first terminal of switching transistor Q26 and the first terminal of inductor L3;

[0243] The second terminal of inductor L3 is electrically connected to the first terminal of capacitor C15, serving as the second positive terminal of the full-wave rectifier full-bridge topology.

[0244] The first terminal of the secondary winding of isolation transformer T2 is electrically connected to the second terminal of switching transistor Q31, the second terminal of the secondary winding of isolation transformer T2 is electrically connected to the second terminal of capacitor C16, serving as the second negative terminal of the full-wave rectifier full-bridge topology, and the third terminal of the secondary winding of isolation transformer T2 is electrically connected to the second terminal of switching transistor Q32.

[0245] The first terminal of the switching transistor Q31 is electrically connected to the first terminal of the switching transistor Q32 and the first terminal of the inductor L4.

[0246] In this embodiment, the full-wave rectifier full-bridge topology is suitable for products with an output voltage greater than 60V. When the source-load integrated power supply operates in power mode, the full-wave rectifier full-bridge topology operates in full-bridge topology; when the source-load integrated power supply operates in load mode, the full-wave rectifier full-bridge topology operates in push-pull topology.

[0247] like Figure 20 The diagram shown is a circuit schematic of a full-bridge rectifier topology provided in an embodiment of this application. Specifically, the full-bridge rectifier topology includes switching transistors Q33, Q34, Q35, Q36, Q37, Q38, Q39, Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, isolation transformers T3 and T4, capacitors C17 and C18.

[0248] The first terminal of switch Q33 is electrically connected to the first terminals of switch Q35, switch Q37 and switch Q39, serving as the first positive terminal of the full-bridge rectifier topology. The second terminal of switch Q33 is electrically connected to the first terminal of switch Q34 and the first terminal of the primary winding of isolation transformer T3.

[0249] The second end of the switch tube Q34 is electrically connected with the second end of the switch tube Q36, the second end of the switch tube Q38 and the second end of the switch tube Q40, as the first negative end of the full-bridge rectification full-bridge topology architecture.

[0250] The second end of the switch tube Q35 is electrically connected with the first end of the switch tube Q36 and the second end of the primary coil of the isolation transformer T3.

[0251] The second end of the switch tube Q37 is electrically connected with the first end of the switch tube Q38 and the first end of the primary coil of the isolation transformer T4.

[0252] The second end of the switch tube Q39 is electrically connected with the first end of the switch tube Q40 and the second end of the primary coil of the isolation transformer T4.

[0253] The first end of the secondary coil of the isolation transformer T3 is electrically connected with the second end of the switch tube Q41 and the first end of the switch tube Q42, and the second end of the secondary coil of the isolation transformer T3 is electrically connected with the second end of the switch tube Q43 and the first end of the switch tube Q44.

[0254] The first end of the switch tube Q41 is electrically connected with the first end of the switch tube Q43 and the first end of the capacitor C17, as the second positive end of the full-bridge rectification full-bridge topology architecture.

[0255] The second end of the switch tube Q42 is electrically connected with the second end of the switch tube Q44, the second end of the capacitor C17, the first end of the switch tube Q45, the first end of the switch tube Q47 and the first end of the capacitor C18.

[0256] The first end of the secondary coil of the isolation transformer T4 is electrically connected with the second end of the switch tube Q45 and the first end of the switch tube Q46, and the second end of the secondary coil of the isolation transformer T4 is electrically connected with the second end of the switch tube Q47 and the first end of the switch tube Q48.

[0257] The second end of the switch tube Q46 is electrically connected with the second end of the switch tube Q48 and the second end of the capacitor C18, as the second negative end of the full-bridge rectification full-bridge topology architecture.

[0258] The filter module 23 in the embodiment of the application can be an LC filter circuit, a CLC filter circuit or other filter circuit, and the embodiment of the application does not limit this.

[0259] It should be noted that, Figure 18 , Figure 19 and Figure 20 In addition to the direct-current-direct-current conversion module, the filter module is also included.

[0260] The voltage and current sampling module 25 in the embodiment of the application can be a differential sampling circuit, the positive and negative input ends of a differential operational amplifier are connected to the positive phase end and the negative phase end of the bus respectively, and the output differential signal is used as the output signal of the sampling module.

[0261] The source-load integrated power supply provided by the embodiment of the application can be applied to the following application scenarios: new energy field and energy storage system testing, automatic production line and ATE system, lithium battery testing system, and DC power supply of switching power supply architecture requiring integration of power supply and load. The controllable load module is a carrier for realizing the load function. The load consumes the input power in the reverse transmission of the power supply, and the independent analog constant voltage loop is used to keep the bus voltage constant.

[0262] The embodiment of the application adopts an independent controllable constant voltage loop to realize controllable bus voltage. Compared with the traditional source-load integrated power supply, the controllable constant voltage loop has a simple structure and independent control, and does not conflict with the main power loop in loop control. Therefore, not only the cost is saved, but also the stability of the power supply is improved.

[0263] Those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application belong to the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims

1. A source-carrier integrated power supply, characterized in that, include: AC-DC conversion module, DC-DC conversion module, and controllable load module; The AC-DC conversion module is electrically connected to the DC-DC conversion module, and the controllable load module is electrically connected to the first DC bus between the AC-DC conversion module and the DC-DC conversion module. The AC-DC conversion module is used to convert the externally input AC power into the first DC power when the integrated power supply is operating in power mode. The DC-DC conversion module is used to convert the first DC power into the second DC power and output it when the integrated source and load power supply is working in power mode; and to convert the third DC power input from the outside into the fourth DC power when the integrated source and load power supply is working in load mode. The controllable load module is configured to not operate when the integrated power supply is in power mode, and to consume the power input to the controllable load module when the integrated power supply is in load mode. The integrated power supply also includes a main control module; The main control module is used to send an enable signal to the controllable load module after determining that the integrated source and load power supply is working in load mode. The controllable load module is specifically used to consume the power input to the controllable load module when it receives the enable signal and determines that the bus voltage of the first DC bus is greater than or equal to a preset threshold. The controllable load module includes a second load drive circuit and a first heat dissipation circuit. The second load drive circuit is used to output a drive signal to control the operation of the first heat dissipation circuit when it receives the enable signal and determines that the bus voltage is greater than or equal to the preset threshold. The first heat dissipation circuit is used to consume the power input to the controllable load module under the control of the drive signal; The second load drive circuit includes an eleventh resistor, a twelfth resistor, an eighth capacitor, a fourth power amplifier, and a second switching transistor; The first end of the eleventh resistor is electrically connected to the first end of the positive bus of the first DC bus, and is used to input the bus voltage. The second end of the eleventh resistor is electrically connected to the non-inverting input terminal of the fourth power amplifier, the first end of the twelfth resistor, and the first end of the second switching transistor. The second terminal of the twelfth resistor is electrically connected to the second terminal of the second switching transistor and the ground terminal of the fourth power amplifier, and is grounded. The inverting input terminal of the fourth power amplifier is electrically connected to the first terminal of the eighth capacitor for inputting a reference voltage. The power supply terminal of the fourth power amplifier is used to input a first power supply voltage. The output terminal of the fourth power amplifier is electrically connected to the second terminal of the eighth capacitor for outputting the driving signal. The control terminal of the second switching transistor is electrically connected to the main control module and is used to receive the enable signal.

2. The power supply as described in claim 1, characterized in that, It also includes a voltage and current sampling module; The sampling terminal of the voltage and current sampling module is electrically connected to the second DC bus of the DC-DC converter module at the end where the second DC power is output. The main control module is electrically connected to the control terminal of the DC-DC converter module and the output terminal of the voltage and current sampling module. The voltage and current sampling module is used to sample the DC current of the second DC bus to obtain voltage signals and / or current signals; The main control module is used to control the switching transistors in the DC-DC conversion module to turn on and off based on the voltage signal and / or the current signal.

3. The power supply as described in claim 2, characterized in that, It also includes a filtering module; The filtering module is electrically connected to the DC-DC conversion module; The filtering module is used to filter the second DC power output by the DC-DC converter module and output it to power the load when the integrated source and load power supply is working in power mode. When the integrated source and load power supply is working in load mode, it filters the third DC power input from the outside and outputs the filtered DC power to the DC-DC converter module.

4. The power supply as described in claim 1, characterized in that, The controllable load module includes a first load drive circuit and a first heat dissipation circuit. The first load drive circuit is used to output a drive signal to control the operation of the first heat dissipation circuit when the bus voltage is greater than or equal to the preset threshold. The first heat dissipation circuit is used to consume the power input to the controllable load module under the control of the drive signal.

Images