Power amplifier and radio frequency chip

Abstract

The application relates to the field of wireless communication technology and provides a power amplifier and a radio frequency chip, which comprise input matching circuit, first-stage amplifier, first-stage inter-amplifier matching circuit, second-stage amplifier, second-stage inter-amplifier matching circuit, third-stage amplifier and output matching circuit which are electrically connected in sequence; the power amplifier further comprises a control module, a direct-current power supply module, a first bias circuit, a second bias circuit, a third bias circuit, a fourth bias circuit, a power amplification network and a switch control circuit; the switch control circuit comprises a diode, a first triode, a second triode, a first resistor and a second resistor; the positive electrode of the diode serves as the input end of the switch control circuit, and the negative electrode of the diode is connected with the collector of the second triode and serves as the output end of the switch control circuit; and the application can optimize the low-power consumption mode current and the gain of the power amplifier.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and more particularly to a power amplifier and a radio frequency chip. Background Technology

[0002] In wireless communication systems, power amplifiers are key components for the wireless transmission of radio frequency (RF) signals. With the continuous development of mobile communication technology, especially the widespread adoption of 5G, higher demands are placed on the power consumption of communication systems. The signals received by base stations from mobile phones and other communication terminals are easily affected by objective conditions such as distance, terrain, and weather. To meet the base station's requirements for signal stability and linearity, RF power amplifiers typically employ multiple power modes. Under favorable mobile communication conditions, the system will put the mobile phone power amplifier into a low-gain, low-power mode. This low-power mode requires the power amplifier to maintain good linearity performance under low current and low gain conditions. Typically, in low-power mode, the output power requirement of the power amplifier is less than 10dBm to meet communication requirements, and the gain cannot be too high. Traditional low-power current reduction methods achieve the effect of reducing current and gain by lowering the bias of each stage of the power amplifier. However, simply reducing the bias has limited effect on achieving low power consumption, and excessively low bias reduction can easily lead to nonlinear distortion in the power amplifier.

[0003] Currently, such as Figure 1 As shown, the power amplifier in this technology typically consists of an input matching circuit, a first-stage amplifier (PA), a first-stage inter-stage matching circuit, a second-stage amplifier, a second-stage inter-stage matching circuit, a third-stage amplifier, an output matching circuit, a control module, a first bias circuit, a second bias circuit, a third bias circuit, and a battery power supply module, all connected in sequence. The control module receives logic commands and controls the battery power supply module to supply power to the first, second, and third bias circuits, which in turn provide bias voltages to the first, second, and third-stage amplifiers, respectively. When the mobile phone is in a good communication environment, it does not need to transmit high power. The external logic circuit sends commands to the control module to control the power amplifier to reduce the bias voltage and lower the quiescent current, thereby achieving low power consumption.

[0004] However, the control module described above provides bias voltages to the corresponding amplifiers through three bias circuits, which only achieves the performance of reducing power consumption; but in the low power and low gain mode, it is easy to cause the power amplifier current and gain to be too high. Summary of the Invention

[0005] To address the shortcomings of the existing technologies, this invention proposes a power amplifier to solve the problem of excessive current and gain in the low-power mode of existing power amplifiers.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0007] In a first aspect, embodiments of the present invention provide a power amplifier, comprising an input matching circuit, a first-stage amplifier, a first-stage inter-stage matching circuit, a second-stage amplifier, a second-stage inter-stage matching circuit, a third-stage amplifier, and an output matching circuit, which are connected in sequence. The power amplifier further comprises a control module, a DC power supply module, a first bias circuit, a second bias circuit, a third bias circuit, a fourth bias circuit, a power amplification network, and a switch control circuit. The DC power supply module is used to supply power to the control module, the first-stage amplifier, the second-stage amplifier, and the third-stage amplifier, respectively.

[0008] The control module is used to receive an external logic enable signal, and control the first bias circuit, the second bias circuit and the third bias circuit to provide bias voltages to the first stage amplifier, the second stage amplifier and the third stage amplifier respectively according to the external logic enable signal;

[0009] The first input terminal of the power amplifier network is connected to the input terminal of the first stage amplifier and respectively connected to the radio frequency signal. The second input terminal of the power amplifier network is used to connect to the fourth bias circuit. The first output terminal of the power amplifier network is connected to the input terminal of the switch control circuit. The second output terminal of the power amplifier network is connected to the DC power supply module. The output terminal of the switch control circuit is connected to the output terminal of the output matching circuit.

[0010] The switching control circuit includes a diode, a first transistor, a second transistor, a first resistor, and a second resistor. The anode of the diode serves as the input terminal of the switching control circuit, and the cathode of the diode is connected to the collector of the second transistor and serves as the output terminal of the switching control circuit. The emitter of the second transistor is connected in series with the second resistor and used to receive an external control signal. The base of the second transistor is connected to the first terminal of the first resistor, the base of the first transistor, and the collector of the first transistor. The emitter of the first transistor is grounded, and the second terminal of the first resistor is used to connect to the power supply.

[0011] When the control module receives the external logic enable signal and enters a non-low power, low gain mode, the external control signal outputs a high level, the overall path is left floating, and the diode is turned off; when the control module receives the external logic enable signal and enters a low power, low gain mode, the external control signal outputs a low level, and the diode is turned on.

[0012] Preferably, the power amplifier network includes a third transistor, a fourth transistor, a third resistor, a fourth resistor, a first capacitor, a first inductor, a second capacitor, and a first back via.

[0013] The first terminal of the first capacitor serves as the first input terminal of the power amplifier network. The second terminal of the first capacitor is connected to the first terminal of the third resistor and the base of the third transistor. The second terminal of the third resistor is connected to the first terminal of the fourth resistor, the base of the fourth transistor, and the collector of the fourth transistor. The emitter of the fourth transistor is grounded. The second terminal of the fourth resistor serves as the second input terminal of the power amplifier network.

[0014] The emitter of the third transistor is grounded after being connected in series with the first back hole; the collector of the third transistor serves as the first output terminal of the power amplifier network; the collector of the third transistor is connected to the first terminal of the first inductor, the second terminal of the first inductor is connected to the first terminal of the second capacitor and serves as the second output terminal of the power amplifier network, and the second terminal of the second capacitor is grounded.

[0015] Preferably, the power amplifier further includes a third capacitor, the first end of which is connected to the output terminal of the switch control circuit, and the second end of which is connected to the output terminal of the output matching circuit.

[0016] Preferably, the first bias circuit includes a fifth resistor, a fourth capacitor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0017] The first end of the fifth resistor serves as the input terminal of the first bias circuit and is connected to the control module. The second end of the fifth resistor is connected to the collector and base of the fifth transistor, respectively. The emitter of the fifth transistor is connected to the collector and base of the sixth transistor, respectively. The emitter of the sixth transistor is grounded. The base of the fifth transistor is connected to the first end of the fourth capacitor and the base of the seventh transistor, respectively. The collector of the seventh transistor is used to connect to the DC power supply module. The emitter of the sixth transistor serves as the output terminal of the first bias circuit and is connected to the first stage amplifier.

[0018] Preferably, the second bias circuit includes a sixth resistor, a fifth capacitor, an eighth transistor, a ninth transistor, and a thirteenth transistor;

[0019] The first end of the sixth resistor is connected to the control module as the input terminal of the second bias circuit. The second end of the sixth resistor is connected to the collector and base of the eighth transistor. The emitter of the eighth transistor is connected to the collector and base of the ninth transistor. The emitter of the ninth transistor is grounded. The base of the eighth transistor is connected to the first end of the fifth capacitor and the base of the thirteenth transistor. The collector of the thirteenth transistor is connected to the DC power supply module. The emitter of the ninth transistor is connected to the second stage amplifier as the output terminal of the second bias circuit.

[0020] Preferably, the third bias circuit includes a seventh resistor, a sixth capacitor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

[0021] The first end of the seventh resistor is connected to the control module as the input terminal of the third bias circuit. The second end of the seventh resistor is connected to the collector and base of the eleventh transistor. The emitter of the eleventh transistor is connected to the collector and base of the twelfth transistor. The emitter of the twelfth transistor is grounded. The base of the eleventh transistor is connected to the first end of the sixth capacitor and the base of the thirteenth transistor. The collector of the thirteenth transistor is connected to the DC power supply module. The emitter of the twelfth transistor is connected to the third stage amplifier as the output terminal of the third bias circuit.

[0022] Preferably, the fourth bias circuit includes an eighth resistor, a seventh capacitor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;

[0023] The first end of the eighth resistor is connected to the control module as the input terminal of the fourth bias circuit. The second end of the eighth resistor is connected to the collector and base of the fourteenth transistor. The emitter of the fourteenth transistor is connected to the collector and base of the fifteenth transistor. The emitter of the fifteenth transistor is grounded. The base of the fourteenth transistor is connected to the first end of the seventh capacitor and the base of the sixteenth transistor. The collector of the sixteenth transistor is connected to the DC power supply module. The emitter of the sixteenth transistor is connected to the second input terminal of the power amplifier network as the output terminal of the fourth bias circuit.

[0024] Preferably, the power amplifier further includes a second back hole, a third back hole, and a fourth back hole, wherein the second back hole, the third back hole, and the fourth back hole are connected in parallel with the first stage amplifier, the second stage amplifier, and the third stage amplifier, respectively, and then grounded.

[0025] Preferably, the input matching circuit is an eighth capacitor, the first end of the eighth capacitor serves as the input terminal of the input matching circuit for connecting to the radio frequency signal, and the second end of the eighth capacitor serves as the output terminal of the input matching circuit connected to the input terminal of the first stage amplifier.

[0026] Secondly, embodiments of the present invention also provide a radio frequency chip, including the power amplifier as described above.

[0027] Compared with related technologies, in the embodiments of the present invention, a DC power supply module is used to supply power to the control module, the first-stage amplifier, the second-stage amplifier, and the third-stage amplifier respectively; the control module is used to receive an external logic enable signal and control the first bias circuit, the second bias circuit, and the third bias circuit to provide bias voltages to the first-stage amplifier, the second-stage amplifier, and the third-stage amplifier respectively according to the external logic enable signal; the positive terminal of the diode in the switching control circuit is used as the input terminal of the switching control circuit, the negative terminal of the diode is connected to the collector of the second transistor and used as the output terminal of the switching control circuit, and the emitter of the second transistor is connected in series with a second resistor and used as the output terminal of the switching control circuit. The system receives external control signals. The base of the second transistor is connected to the first terminal of the first resistor, the base of the first transistor, and the collector of the first transistor. The emitter of the first transistor is grounded, and the second terminal of the first resistor is used to connect to the power supply. When the control module receives an external logic enable signal and enters a non-low-power, low-gain mode, the external control signal is output at a high level, the entire path is left floating, and the diode is turned off. When the control module receives an external logic enable signal and enters a low-power, low-gain mode, the external control signal is output at a low level, and the diode is turned on. This effectively optimizes the low-power mode current and gain of the power amplifier, achieving the goal of saving power in the mobile phone. Attached Figure Description

[0028] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0029] Figure 1 A circuit block diagram of a power amplifier provided for the prior art;

[0030] Figure 2 A circuit block diagram of a power amplifier provided in an embodiment of the present invention;

[0031] Figure 3A circuit diagram of the first bias circuit of the power amplifier provided in an embodiment of the present invention;

[0032] Figure 4 A circuit diagram of the second bias circuit of the power amplifier provided in an embodiment of the present invention;

[0033] Figure 5 A circuit diagram of the third bias circuit of a power amplifier provided in an embodiment of the present invention;

[0034] Figure 6 A circuit diagram of the fourth bias circuit of a power amplifier provided in an embodiment of the present invention;

[0035] Figure 7a A comparison chart of power and current simulation curves for power amplifiers provided by existing technologies;

[0036] Figure 7b A comparison chart of power and current simulation curves of a power amplifier provided for an embodiment of the present invention;

[0037] Figure 8a A comparison chart of power and gain simulation curves for power amplifiers provided by existing technologies;

[0038] Figure 8b A comparison chart of power and gain simulation curves of the power amplifier provided in the embodiments of the present invention.

[0039] Among them, 100 is the power amplifier, 1 is the input matching circuit, 2 is the first stage amplifier, 3 is the first stage inter-stage matching circuit, 4 is the second stage amplifier, 5 is the second stage inter-stage matching circuit, 6 is the third stage amplifier, 7 is the output matching circuit, 8 is the control module, 9 is the DC power supply module, 10 is the power amplifier network, 11 is the first bias circuit, 12 is the second bias circuit, 13 is the third bias circuit, 14 is the fourth bias circuit, 15 is the first back hole, 16 is the second back hole, 17 is the third back hole, 18 is the fourth back hole, and 19 is the switch control circuit. Detailed Implementation

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0041] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] Example 1

[0044] Please see Figures 2-6 As shown, this embodiment of the invention provides a power amplifier 100, including an input matching circuit 1, a first-stage amplifier 2, a first-stage inter-stage matching circuit 3, a second-stage amplifier 4, a second-stage inter-stage matching circuit 5, a third-stage amplifier 6, and an output matching circuit 7, all electrically connected in sequence. The power amplifier 100 also includes a control module 8, a DC power supply module 9, a first bias circuit 11, a second bias circuit 12, a third bias circuit 13, a fourth bias circuit 14, a power amplification network 10, and a switch control circuit 19. The DC power supply module 9 supplies power to the control module 8, the first-stage amplifier 2, the second-stage amplifier 4, and the third-stage amplifier 6, respectively. The control module 8 receives an external logic enable signal and controls the first bias circuit 11, the second bias circuit 12, and the third bias circuit 13 to provide bias voltages to the first-stage amplifier 2, the second-stage amplifier 4, and the third-stage amplifier 6, respectively, according to the external logic enable signal. The DC power supply module 9 is battery-powered and can be a DC power supply or a battery, etc.

[0045] The first input terminal of the power amplifier network 10 is connected to the input terminal of the first stage amplifier 2 and respectively connected to the radio frequency signal. The second input terminal of the power amplifier network 10 is used to connect to the fourth bias circuit 14. The first output terminal of the power amplifier network 10 is connected to the input terminal of the switch control circuit 19. The second output terminal of the power amplifier network 10 is connected to the DC power supply module 9. The output terminal of the switch control circuit 19 is connected to the output terminal of the output matching circuit 7.

[0046] The switch control circuit 19 includes a diode D1, a first transistor Q1, a second transistor Q2, a first resistor R1, and a second resistor R2. The anode of the diode D1 serves as the input terminal of the switch control circuit 19, and the cathode of the diode D1 is connected to the collector of the second transistor Q2 and serves as the output terminal of the switch control circuit 19. The emitter of the second transistor Q2 is connected in series with the second resistor R2 and used to receive an external control signal. The base of the second transistor Q2 is connected to the first terminal of the first resistor R1, the base of the first transistor Q1, and the collector of the first transistor Q1. The emitter of the first transistor Q1 is grounded, and the second terminal of the first resistor R1 is used to connect to the power supply.

[0047] When the control module 8 receives the external logic enable signal and enters a non-low-power, low-gain mode, the external control signal outputs a high level, the entire path is left floating, and diode D1 is turned off. When the control module 8 receives the external logic enable signal and enters a low-power, low-gain mode, the external control signal outputs a low level, and diode D1 is turned on. Specifically, when the first bias circuit 11, the second bias circuit 12, and the third bias circuit 13 are powered normally, and the fourth bias circuit 14 is not powered, with an output voltage of 0V, the voltage of the external control signal is high. When the external control signal provides a voltage identical to the DC power supply, the voltage difference across diode D1 is less than its forward voltage, and diode D1 is turned off, thus achieving an isolation effect. When the first bias circuit 11, the second bias circuit 12, and the third bias circuit 13 are not powered, the output voltage is 0V; when the fourth bias circuit 14 is powered normally and the voltage of the external control signal is low, diode D1 conducts when the voltage difference across it is less than its forward voltage; the power amplifier network 10 outputs power normally. This effectively optimizes the low-power mode current and gain of the power amplifier 100, achieving power saving for the mobile phone.

[0048] A fixed power supply is achieved by connecting a second transistor Q2 in series with a second resistor R2 and then connecting it to an external control signal. This puts the second transistor Q2 into conduction mode, and the output of the power amplifier network 10 is powered by the DC power supply module 9. When the external control signal voltage is 0V, the voltage difference across diode D1 is greater than its forward voltage, causing diode D1 to conduct and the power amplifier network 10 to output a signal. When the external control signal provides a voltage identical to the DC power supply, the voltage difference across diode D1 is less than its forward voltage, causing diode D1 to deactivate and the power amplifier network 10 to shut down, thus achieving isolation.

[0049] In this embodiment, the power amplifier network 10 includes a third transistor Q3, a fourth transistor Q4, a third resistor R3, a fourth resistor R4, a first capacitor C1, a first inductor, a second capacitor C2, and a first back hole 15.

[0050] The first terminal of the first capacitor C1 serves as the first input terminal of the power amplifier network 10. The second terminal of the first capacitor C1 is connected to the first terminal of the third resistor R3 and the base of the third transistor Q3. The second terminal of the third resistor R3 is connected to the first terminal of the fourth resistor R4, the base of the fourth transistor Q4, and the collector of the fourth transistor Q4. The emitter of the fourth transistor Q4 is grounded. The second terminal of the fourth resistor R4 serves as the second input terminal of the power amplifier network 10.

[0051] The emitter of the third transistor Q3 is grounded after being connected in series with the first back hole 15; the collector of the third transistor Q3 serves as the first output terminal of the power amplifier network 10; the collector of the third transistor Q3 is connected to the first terminal of the first inductor, the second terminal of the first inductor is connected to the first terminal of the second capacitor C2 and serves as the second output terminal of the power amplifier network 10, and the second terminal of the second capacitor C2 is grounded. By connecting the first back hole 15 to the emitter of the third transistor Q3 and grounding it, the overall performance of the PA is improved through the coordinated optimization of five dimensions: signal integrity, heat dissipation, grounding, matching, and power supply.

[0052] Specifically, when the power amplifier 100 needs to operate in high-power, high-gain mode, the control module 8 supplies normal power to the first bias circuit 11, the second bias circuit 12, and the third bias circuit 13, respectively. The voltage of the fourth bias circuit 14 is 0V, the third transistor Q3 is off, the voltage of the external control signal is high, and the diode D1 is off, forming an isolation state. When the power amplifier 100 needs to operate in low-power, low-gain mode, the supply voltage of the first bias circuit 11, the second bias circuit 12, and the third bias circuit 13 is 0V. The first-stage amplifier 2, the second-stage amplifier 4, and the third-stage amplifier 6 are all off and do not work. The fourth bias circuit 14 is normally powered, the third transistor Q3 is powered on, the external control signal is at a low level of 0V, the diode D1 is turned on, and the third transistor Q3 provides normal output power to the output port. Although the output matching of the third transistor Q3 is in parallel with the output matching of the first-stage amplifier 2, the second-stage amplifier 4, and the third-stage amplifier 6 in this mode, the output impedance of the third transistor Q3, being a single-stage low-power amplifier, is inherently required to be relatively high. Therefore, the output matching of the third transistor Q3 can be corrected by adjusting the first inductor. This effectively optimizes the low-power mode current and gain of the power amplifier 100, achieving the goal of saving power in mobile phones.

[0053] In this embodiment, the power amplifier 100 further includes a third capacitor C3. The first end of the third capacitor C3 is connected to the output terminal of the switch control circuit 19, and the second end of the third capacitor C3 is connected to the output terminal of the output matching circuit 7. The output matching of the third transistor Q3 can be corrected by adjusting the combination of the first inductor and the third capacitor C3.

[0054] In this embodiment, as Figure 3 As shown, the first bias circuit 11 includes a fifth resistor R5, a fourth capacitor C4, a fifth transistor Q5, a sixth transistor Q6, and a seventh transistor Q7.

[0055] The first end of the fifth resistor R5 serves as the input terminal of the first bias circuit 11 and is connected to the control module 8. The second end of the fifth resistor R5 is connected to the collector and base of the fifth transistor Q5. The emitter of the fifth transistor Q5 is connected to the collector and base of the sixth transistor Q6, and the emitter of the sixth transistor Q6 is grounded. The base of the fifth transistor Q5 is connected to the first end of the fourth capacitor C4 and the base of the seventh transistor Q7. The collector of the seventh transistor Q7 is connected to the DC power supply module 9. The emitter of the sixth transistor Q6 serves as the output terminal of the first bias circuit 11 and is connected to the first stage amplifier 2. The control module 8 supplies power to the fifth transistor Q5 and the sixth transistor Q6 via the fifth resistor R5. The fifth transistor Q5 and the sixth transistor Q6 are used as voltage regulators and temperature compensation transistors. The fourth capacitor C4 stores power for the overall bias circuit. The seventh transistor Q7 is used as the bias driver for the first-stage amplifier 2, providing bias power to the first-stage amplifier 2. Optionally, the DC power supply module 9 provides power to the battery of the mobile phone system.

[0056] In this embodiment, as Figure 4 As shown, the second bias circuit 12 includes a sixth resistor R6, a fifth capacitor C5, an eighth transistor Q8, a ninth transistor Q9, and a thirteenth transistor Q10.

[0057] The first end of the sixth resistor R6 serves as the input terminal of the second bias circuit 12 and is connected to the control module 8. The second end of the sixth resistor R6 is connected to the collector and base of the eighth transistor Q8. The emitter of the eighth transistor Q8 is connected to the collector and base of the ninth transistor Q9, and the emitter of the ninth transistor Q9 is grounded. The base of the eighth transistor Q8 is connected to the first end of the fifth capacitor C5 and the base of the thirteenth transistor Q10. The collector of the thirteenth transistor Q10 is connected to the DC power supply module 9, and the emitter of the ninth transistor Q9 serves as the output terminal of the second bias circuit 12 and is connected to the second stage amplifier 4. The control module 8 supplies power to the eighth transistor Q8 and the ninth transistor Q9 through the sixth resistor R6. The eighth transistor Q8 and the ninth transistor Q9 are used as voltage regulators and temperature compensation transistors. The thirteenth transistor Q10 is used as the bias drive transistor of the second stage amplifier 4 to provide bias power to the second stage amplifier 4.

[0058] In this embodiment, as Figure 5 As shown, the third bias circuit 13 includes a seventh resistor R7, a sixth capacitor C6, an eleventh transistor Q11, a twelfth transistor Q12, and a thirteenth transistor Q13.

[0059] The first end of the seventh resistor R7 serves as the input terminal of the third bias circuit 13 and is connected to the control module 8. The second end of the seventh resistor R7 is connected to the collector and base of the eleventh transistor Q11. The emitter of the eleventh transistor Q11 is connected to the collector and base of the twelfth transistor Q12. The emitter of the twelfth transistor Q12 is grounded. The base of the eleventh transistor Q11 is connected to the first end of the sixth capacitor C6 and the base of the thirteenth transistor Q13. The collector of the thirteenth transistor Q13 is connected to the DC power supply module 9. The emitter of the twelfth transistor Q12 serves as the output terminal of the third bias circuit 13 and is connected to the third-stage amplifier 6. The control module 8 supplies power to the eleventh transistor Q11 and the twelfth transistor Q12 through the seventh resistor R7. The eleventh transistor Q11 and the twelfth transistor Q12 are used as voltage regulators and temperature compensation transistors. The thirteenth transistor Q13 is used as the bias drive transistor of the third stage amplifier 6 to provide bias power to the third stage amplifier 6.

[0060] In this embodiment, as Figure 6 As shown, the fourth bias circuit 14 includes an eighth resistor R8, a seventh capacitor C7, a fourteenth transistor Q14, a fifteenth transistor Q15, and a sixteenth transistor Q16.

[0061] The first end of the eighth resistor R8 serves as the input terminal of the fourth bias circuit 14 and is connected to the control module 8. The second end of the eighth resistor R8 is connected to the collector and base of the fourteenth transistor Q14. The emitter of the fourteenth transistor Q14 is connected to the collector and base of the fifteenth transistor Q15, and the emitter of the fifteenth transistor Q15 is grounded. The base of the fourteenth transistor Q14 is connected to the first end of the seventh capacitor C7 and the base of the sixteenth transistor Q16. The collector of the sixteenth transistor Q16 is connected to the DC power supply module 9, and the emitter of the sixteenth transistor Q16 serves as the output terminal of the fourth bias circuit 14 and is connected to the second input terminal of the power amplifier network 10. The control module 8 supplies power to the fourteenth transistor Q14 and the fifteenth transistor Q15 via the eighth resistor R8. The fourteenth and fifteenth transistors Q14 and Q15 are used as voltage regulators and temperature compensation transistors, respectively. The sixteenth transistor Q16 serves as the bias driver for the amplifier, providing bias power to the first-stage amplifier 2, the second-stage amplifier 4, and the third-stage amplifier 6. Different bias voltages provided by the first bias circuit 11, the second bias circuit 12, the third bias circuit 13, and the fourth bias circuit 14 enable the switching on and off of diode D1. This effectively optimizes the low-power mode current and gain of the power amplifier 100, achieving power saving for the mobile phone.

[0062] In this embodiment, the power amplifier 100 further includes a second back port 16, a third back port 17, and a fourth back port 18. The second back port 16, the third back port 17, and the fourth back port 18 are connected in parallel with the first stage amplifier 2, the second stage amplifier 4, and the third stage amplifier 6, respectively, and then grounded. By connecting the second back port 16, the third back port 17, and the fourth back port 18 in parallel with the first stage amplifier 2, the second stage amplifier 4, and the third stage amplifier 6, respectively, and then grounding them, the overall performance of the PA is improved through synergistic optimization of five dimensions: signal integrity, heat dissipation, grounding, matching, and power supply.

[0063] In this embodiment, the input matching circuit 1 is an eighth capacitor C8. The first terminal of the eighth capacitor C8 serves as the input terminal of the input matching circuit 1, used to connect to the radio frequency signal. The second terminal of the eighth capacitor C8 serves as the output terminal of the input matching circuit 1, connected to the input terminal of the first stage amplifier 2. Input matching can be achieved through the eighth capacitor C8.

[0064] In this embodiment, the output matching circuit 7 can be an inductor or an inductor, or a combination of an inductor and a capacitor connected in series, or a combination of an inductor and a capacitor connected in parallel, etc.

[0065] In this embodiment, Figure 7a The image shows a comparison of power current simulation curves for traditional architectures in existing technologies. Figure 7b A comparison chart of the power current simulation curves of the power amplifier 100 of the present invention. The results clearly show that, compared to the traditional architecture, the present invention significantly optimizes the current, reducing it by nearly 130mA, an improvement of 81%.

[0066] In this embodiment, Figure 8a The figure shown is a comparison of the power gain simulation curves of the traditional architecture in the prior art. Figure 8b This is a comparison chart of the simulated power gain curves for this invention. The results show that, compared to the traditional architecture, this invention significantly optimizes the gain reduction. The traditional structure has a gain of 30.5dB, while this invention has a gain of approximately 12dB, demonstrating a significant improvement.

[0067] Example 2

[0068] This invention also provides an RF chip, including the power amplifier 100 as described above.

[0069] It should be noted that the various embodiments described above with reference to the accompanying drawings are merely illustrative of the present invention and not intended to limit its scope. Those skilled in the art should understand that any modifications or equivalent substitutions made to the present invention without departing from its spirit and scope should be included within the scope of the present invention. Furthermore, unless the context otherwise requires, words appearing in the singular include those in the plural, and vice versa. Additionally, unless specifically stated otherwise, all or part of any embodiment may be used in conjunction with all or part of any other embodiment.

Claims

1. A power amplifier comprising, in series electrical connection, an input matching circuit, a first stage amplifier, a first inter-stage matching circuit, a second stage amplifier, a second inter-stage matching circuit, a third stage amplifier, and an output matching circuit; characterized by, The power amplifier further comprises a control module, a direct current power supply module, a first bias circuit, a second bias circuit, a third bias circuit, a fourth bias circuit, a power amplification network and a switch control circuit; The direct current power supply module is used for supplying power to the control module, the first-stage amplifier, the second-stage amplifier and the third-stage amplifier respectively; The control module is used for receiving an external logic enable signal and controlling the first bias circuit, the second bias circuit and the third bias circuit to provide bias voltages for the first-stage amplifier, the second-stage amplifier and the third-stage amplifier respectively according to the external logic enable signal; A first input end of the power amplification network is connected with an input end of the first-stage amplifier and inputs a radio frequency signal respectively, a second input end of the power amplification network is used for connecting the fourth bias circuit, a first output end of the power amplification network is connected with an input end of the switch control circuit, a second output end of the power amplification network is connected with the direct current power supply module, and an output end of the switch control circuit is connected with an output end of the output matching circuit; The switch control circuit comprises a diode, a first triode, a second triode, a first resistor and a second resistor, a positive electrode of the diode is used as an input end of the switch control circuit, a negative electrode of the diode is connected with a collector of the second triode and used as an output end of the switch control circuit, an emitter of the second triode is connected with the second resistor in series and is used for inputting an external control signal, a base of the second triode is connected with a first end of the first resistor, a base of the first triode and a collector of the first triode respectively, an emitter of the first triode is grounded, and a second end of the first resistor is used for connecting a power supply; When the control module receives the external logic enable signal and enters a non-low-power-consumption low-gain mode, the external control signal outputs a high level, the whole path is suspended, and the diode is turned off; When the control module receives the external logic enable signal and enters a low-power-consumption low-gain mode, the external control signal outputs a low level, and the diode is turned on.

2. The power amplifier of claim 1, wherein, The power amplification network comprises a third triode, a fourth triode, a third resistor, a fourth resistor, a first capacitor, a first inductor, a second capacitor and a first back hole; A first end of the first capacitor is used as a first input end of the power amplification network, a second end of the first capacitor is connected with a first end of the third resistor and a base of the third triode respectively, a second end of the third resistor is connected with a first end of the fourth resistor, a base of the fourth triode and a collector of the fourth triode respectively, an emitter of the fourth triode is grounded, and a second end of the fourth resistor is used as a second input end of the power amplification network; An emitter of the third triode is connected to ground through the first back hole; a collector of the third triode is used as a first output end of the power amplifier network; the collector of the third triode is connected to a first end of the first inductor, and a second end of the first inductor is connected to a first end of the second capacitor and used as a second output end of the power amplifier network, and a second end of the second capacitor is connected to ground.

3. The power amplifier of claim 1, wherein, The power amplifier further comprises a third capacitor, a first end of the third capacitor is connected to an output end of the switch control circuit, and a second end of the third capacitor is connected to an output end of the output matching circuit.

4. The power amplifier of claim 1, wherein, The first bias circuit comprises a fifth resistor, a fourth capacitor, a fifth triode, a sixth triode and a seventh triode; A first end of the fifth resistor is connected to the control module as an input end of the first bias circuit, a second end of the fifth resistor is connected to a collector of the fifth triode and a base of the fifth triode respectively, an emitter of the fifth triode is connected to a collector of the sixth triode and a base of the sixth triode respectively, and an emitter of the sixth triode is connected to ground; a base of the fifth triode is connected to a first end of the fourth capacitor and a base of the seventh triode respectively, a collector of the seventh triode is used for being connected to the DC power supply module, and an emitter of the sixth triode is connected to the first-stage amplifier as an output end of the first bias circuit.

5. The power amplifier of claim 1, wherein, The second bias circuit comprises a sixth resistor, a fifth capacitor, an eighth triode, a ninth triode and a thirteenth triode; A first end of the sixth resistor is connected to the control module as an input end of the second bias circuit, a second end of the sixth resistor is connected to a collector of the eighth triode and a base of the eighth triode respectively, an emitter of the eighth triode is connected to a collector of the ninth triode and a base of the ninth triode respectively, and an emitter of the ninth triode is connected to ground; a base of the eighth triode is connected to a first end of the fifth capacitor and a base of the thirteenth triode respectively, a collector of the thirteenth triode is used for being connected to the DC power supply module, and an emitter of the ninth triode is connected to the second-stage amplifier as an output end of the second bias circuit.

6. The power amplifier of claim 1, wherein, The third bias circuit comprises a seventh resistor, a sixth capacitor, an eleventh triode, a twelfth triode and a tenth triode; A first end of the seventh resistor is connected to the control module as an input end of the third bias circuit, a second end of the seventh resistor is connected to a collector of the eleventh triode and a base of the eleventh triode respectively, an emitter of the eleventh triode is connected to a collector of the twelfth triode and a base of the twelfth triode respectively, and an emitter of the twelfth triode is connected to ground; a base of the eleventh triode is connected to a first end of the sixth capacitor and a base of the tenth triode respectively, a collector of the tenth triode is used for being connected to the DC power supply module, and an emitter of the twelfth triode is connected to the third-stage amplifier as an output end of the third bias circuit.

7. The power amplifier of claim 1, wherein, The fourth bias circuit comprises an eighth resistor, a seventh capacitor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor; A first end of the eighth resistor is connected to the control module as an input end of the fourth bias circuit, a second end of the eighth resistor is connected to a collector of the fourteenth transistor and a base of the fourteenth transistor respectively, an emitter of the fourteenth transistor is connected to a collector of the fifteenth transistor and a base of the fifteenth transistor respectively, an emitter of the fifteenth transistor is grounded; the base of the fourteenth transistor is connected to a first end of the seventh capacitor and a base of the sixteenth transistor respectively, a collector of the sixteenth transistor is connected to the direct current power supply module, and an emitter of the sixteenth transistor is connected to a second input end of the power amplification network as an output end of the fourth bias circuit.

8. The power amplifier of claim 1, wherein, The power amplifier further comprises a second back hole, a third back hole and a fourth back hole, the second back hole, the third back hole and the fourth back hole are connected to the first stage amplifier, the second stage amplifier and the third stage amplifier respectively and then grounded in parallel.

9. The power amplifier of claim 1, wherein, The input matching circuit is an eighth capacitor, a first end of the eighth capacitor is used as an input end of the input matching circuit and is connected to a radio frequency signal, and a second end of the eighth capacitor is connected to an input end of the first stage amplifier as an output end of the input matching circuit.

10. A radio frequency chip, characterized by The power amplifier comprises the power amplifier according to any one of claims 1-9.

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