Digital filtering system

Abstract

The application discloses a digital filtering system, which comprises five-stage cascaded FIR filters, wherein the fourth-stage FIR filter comprises two delay chains respectively formed by n delay elements; the input end of the i-th selector in n selectors is connected with the output end of the i-th delay element of the delay chain, and the i-th delay element transmits real part data or imaginary part data alternately output according to a clock period, and the selection of the n selectors is the same at the same time; the i-th multiplier in n multipliers multiplies the output of the i-th selector with a coefficient; a plurality of adders add the outputs of the n multipliers to obtain real part filtering data or imaginary part filtering data, and the fourth-stage FIR filter outputs the real part filtering data and the imaginary part filtering data to the fifth-stage FIR filter alternately in a single channel. The application processes the real part data and the imaginary part data of the complex number signal in a single channel time division multiplexing mode, and reduces the occupation of hardware resources.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital signal, in particular to a digital filtering system. BACKGROUND

[0002] In the field of modern wireless communication and radar signal processing, real-time down-sampling of high-speed data stream and high-precision filtering technology have core application value. However, the existing technology generally has single-stage optimization limitation, especially the processing of complex signals needs independent double-channel architecture, which greatly increases the hardware resource occupancy rate, and the processing of data through the double-channel architecture may also have timing mismatch problem, resulting in phase error of output data. SUMMARY

[0003] In order to solve the problems of the prior art, the present application adopts the following technical scheme:

[0004] The present application provides a digital filtering system, which comprises:

[0005] a five-stage cascaded FIR filter, wherein the fourth-stage FIR filter comprises a quadrature time division interleaving processing module, the quadrature time division interleaving processing module comprises a first delay chain and a second delay chain respectively formed by cascading n delay elements, the first delay chain is configured to transmit the real part data through step-by-step delay of the n delay elements, and the second delay chain is configured to transmit the imaginary part data through step-by-step delay of the n delay elements;

[0006] n selectors, two input ends of an i-th selector of the n selectors are connected with output ends of i-th stage delay elements of two delay chains respectively, and the i-th selector is configured to alternately select the real part data or the imaginary part data transmitted by the two i-th stage delay elements according to a clock cycle, and selections of the n selectors are the same at the same time;

[0007] n multipliers, an i-th multiplier of the n multipliers is configured to multiply an output of an i-th selector with a coefficient, and the coefficient is determined by a stage number of the i-th stage delay element in the delay chain;

[0008] a plurality of adders configured to add outputs of the n multipliers to obtain real part filtering data or imaginary part filtering data, and the fourth-stage FIR filter is configured to alternately output the real part filtering data and the imaginary part filtering data to a fifth-stage FIR filter in a single channel.

[0009] In summary, the digital filtering system provided in the application includes a quadrature time interleaving processing module for the fourth-stage FIR filter, adopts a quadrature time interleaving processing strategy, processes real part data and imaginary part data through a double-delay link design, makes the real part data and the imaginary part data be transmitted through corresponding delay chains in a step-by-step delay manner, and selects the real part data or the imaginary part data output by the corresponding delay element according to a clock cycle, so that the selection of all selectors is consistent at the same time, and the real part data and the imaginary part data are processed through a single-channel time-division multiplexing manner at different clock cycles, the double-channel processing is optimized to single-channel time-division processing, the redundant design of processing complex signals through double channels is broken through, the occupation of hardware resources is greatly reduced, and the circuit structure is simplified.

[0010] Further, the fourth-stage FIR filter further includes a FIFO data reconstruction module, the FIFO data reconstruction module is arranged between the quadrature time interleaving processing module and the fifth-stage FIR filter, and the FIFO data reconstruction module is configured to adopt a bit width conversion and buffering mechanism to perform phase alignment and data recombination on the real part filter data and the imaginary part filter data output by the fourth-stage FIR filter, obtain reconstruction combination data with a bit width twice that of the real part filter data, and transmit the reconstruction combination data to the fifth-stage FIR filter.

[0011] Further, the digital filtering system further includes:

[0012] A serial output shift register is arranged between any delay element and the input end of the selector, the bit number of each shift register is the same, and the same clock is used for driving.

[0013] Further, the digital filtering system further includes:

[0014] A first depth register group is configured to buffer real part data of a signal output by the third-stage FIR filter and send the real part data to the first delay chain.

[0015] A second depth register group is configured to buffer imaginary part data of the signal output by the third-stage FIR filter and send the imaginary part data to the second delay chain.

[0016] Further, in the five-stage cascaded FIR filter, the first-stage FIR filter is configured to have a 2-fold decimation rate, the second-stage FIR filter is configured to have a 4-fold decimation rate, the third-stage FIR filter is configured to have a 2-fold decimation rate, the fourth-stage FIR filter is configured to have a 2-fold decimation rate, and the fifth-stage FIR filter is configured to have a 2-fold decimation rate.

[0017] Further, in the five-stage cascaded FIR filter, the first to third stage FIR filters adopt differential transition band design, the transition band of the first stage FIR filter is wider than that of the second stage FIR filter, and the transition band of the second stage FIR filter is wider than that of the third stage FIR filter.

[0018] Further, the first stage FIR filter has a set order of 18, the second stage FIR filter has a set order of 22, and the third stage FIR filter has a set order of 54.

[0019] Further, in the five-stage cascaded FIR filter, each stage FIR filter is driven by the same clock.

[0020] Further, the fourth stage FIR filter adopts an equal ripple optimization algorithm to determine the order.

[0021] Further, the selector is driven by a modulo-2 counter. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 A schematic diagram of an architecture of a five-stage cascaded FIR filter in a digital filtering system according to an embodiment of the present application is provided;

[0023] Figure 2 A schematic diagram of a structure of a quadrature time interleaving processing module according to an embodiment of the present application is provided;

[0024] Figure 3 A schematic diagram of a five-stage cascaded FIR filter in a digital filtering system according to an embodiment of the present application performing down-sampling rate processing on a signal is provided;

[0025] Figure 4 A schematic diagram of an amplitude-frequency response of a first stage FIR filter in a digital filtering system according to an embodiment of the present application is provided;

[0026] Figure 5 A schematic diagram of an amplitude-frequency response of a second stage FIR filter in a digital filtering system according to an embodiment of the present application is provided;

[0027] Figure 6 A schematic diagram of an amplitude-frequency response of a third stage FIR filter in a digital filtering system according to an embodiment of the present application is provided;

[0028] Figure 7 A schematic diagram of a simulation result of decimation filtering of the first to third stage FIR filters in a digital filtering system according to an embodiment of the present application is provided;

[0029] Figure 8The simulation result diagram of the fourth stage and the fifth stage FIR filter decimation filtering in the digital filtering system provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0030] The present application will be described in detail below with reference to the specific embodiments shown in the drawings, but these embodiments do not limit the present application, and the structural, method, or functional changes made by those skilled in the art based on these embodiments are included in the protection scope of the present application.

[0031] In order to solve the problems in the prior art, an embodiment of the present application provides a digital filtering system, which comprises a five-stage cascaded FIR filter, n selectors, n multipliers, and a plurality of adders.

[0032] In the five-stage cascaded FIR filter, the fourth stage FIR filter comprises a quadrature time division interleaving processing module, the quadrature time division interleaving processing module comprises a first delay chain and a second delay chain which are respectively formed by cascading n delay elements, the first delay chain is configured to delay the transmission real part data by the n delay elements stage by stage, and the second delay chain is configured to delay the transmission imaginary part data by the n delay elements stage by stage.

[0033] Two input ends of an i-th selector of the n selectors are respectively connected with output ends of i-th stage delay elements of the two delay chains, and the i-th selector is configured to alternately select the real part data or the imaginary part data transmitted by the two i-th stage delay elements according to a clock cycle, and the selections of the n selectors are the same at the same time.

[0034] An i-th multiplier of the n multipliers is configured to multiply the output of the i-th selector with a coefficient, and the coefficient is determined by the number of stages of the i-th stage delay element in the delay chain.

[0035] The plurality of adders are configured to add the outputs of the n multipliers to obtain real part filtering data or imaginary part filtering data, and the fourth stage FIR filter outputs the real part filtering data and the imaginary part filtering data to the fifth stage FIR filter alternately in a single channel.

[0036] Specifically, the transfer function of the single-channel FIR filter can be represented by the following formula:

[0037] ;

[0038] In the formula, x(n) represents single-channel input data, h(k) represents an FIR filter coefficient, y(n) represents FIR filter output data, and N represents the order of the FIR filter.

[0039] The structure of the five-stage cascaded FIR filter 100 is shown in Figure 1As shown in the five-stage cascade FIR filter 100, the first-stage FIR filter 11 is located at the front end of the signal processing chain, and the first-stage FIR filter 11 can be configured as a half-band filter. The first-stage FIR filter 11 performs preliminary anti-aliasing filtering on the input high-frequency signal, and realizes coarse decimation of the input signal. The second-stage FIR filter 12 is configured as a medium-order FIR filter, and the performance of the second-stage FIR filter 12 is between that of the first-stage FIR filter 11 and that of the third-stage FIR filter 13. The second-stage FIR filter 11 optimizes resource utilization while ensuring performance through a 2-times decimation characteristic, and completes decimation of the input signal. The third-stage FIR filter 13 is configured as a high-order half-band filter, and the third-stage FIR filter 13 further decimates the input signal, and outputs a complex signal containing real part data and imaginary part data. The fourth-stage FIR filter 14 adopts a quadrature time interleaving processing strategy, and processes the real part data and the imaginary part data of the complex signal through single-channel time interleaving alternately. The fifth-stage FIR filter 15 performs fine filtering on the signal output by the fourth-stage FIR filter 14, and outputs a low-frequency signal, thereby completing the frequency reduction processing of the high sampling rate signal.

[0040] In the fourth-stage FIR filter 14, the structure of the quadrature time interleaving processing module is as shown in Figure 2 The quadrature time interleaving processing module includes a first delay chain 141 and a second delay chain 142 respectively composed of n delay elements 1411, and the fourth-stage FIR filter 14 further includes n selectors 143, n multipliers 144, and a plurality of adders 145. It should be noted that Figure 2 For the convenience of description of the fourth-stage FIR filter, the number of devices included in the quadrature time interleaving processing module is not limited to Figure 2 The number of delay elements in the first delay chain 141 and the second delay chain 142 is determined by the order of the fourth-stage FIR filter. In the fourth-stage FIR filter 14, the first delay chain 141 and the second delay chain 142 are each composed of n delay elements 1411. The first delay chain 141 is used to receive the real part data in the complex signal x(n), and the second delay chain 142 is used to receive the imaginary part data in the complex signal x(n).

[0041] The first delay chain 141 is responsible for transmission and delay processing of the real part data. When the real part data enters the fourth-stage FIR filter 14, it successively passes through the n delay elements 1411 in the first delay chain 141. Each delay element 1411 delays the real part data for a certain time, so that the real part data at different times can be transmitted in time sequence one by one, forming a continuous delay data stream, thereby providing real part data samples at different time points for subsequent filtering calculation, meeting the requirement of the FIR filter for multi-tap data.

[0042] Correspondingly, the second delay chain 142 is responsible for the transmission and delay processing of the imaginary part data. After the imaginary part data enters the fourth-stage FIR filter 14, it is sequentially delayed by the n delay elements 1411 in the second delay chain 142. The delay manner and time are consistent with those of the first delay chain 141, ensuring that the real part data and the imaginary part data can be synchronized in the time dimension.

[0043] Further, in the fourth-stage FIR filter 14, the real part data and the imaginary part data are processed by the n selectors 143 in time-sharing mode. The two input ends of the i-th selector 143 are connected to the output ends of the i-th delay element 1411 of the first delay chain 141 and the second delay chain 142, respectively. The real part data or the imaginary part data output by each delay element 1411 is transmitted to the corresponding selector 143, and the selector 143 can obtain the real part data and the imaginary part data from the same delay stage.

[0044] In the operation process of the filtering system, the timing control is performed by the clock signal, and the selector 143 alternately selects the real part data or the imaginary part data according to the clock period. The fourth-stage FIR filter 14 adopts the orthogonal time-interleaving processing technology. When in a certain clock period, all the selectors 143 uniformly select the real part data; and when in the next clock period, all the selectors 143 are switched to output the imaginary part data synchronously, and the cycle is repeated. The selections of the n selectors 143 at the same time are consistent, ensuring that in any clock period, all the selectors 143 output the real part data or the imaginary part data, avoiding the situation of data type confusion. Through the above-mentioned alternate selection mechanism, the real part data and the imaginary part data originally needing to be processed by two independent channels can be processed by a single channel in time-sharing mode, realizing the conversion of the real part data and the imaginary part data transmitted by the double delay chain into the alternate data stream of a single channel, and effectively reducing the consumption of hardware resources.

[0045] Further, the fourth-stage FIR filter 14 further includes n multipliers 144, each of which is connected to the corresponding selector 143. The input end of the i-th multiplier 144 is connected to the output end of the i-th selector 143. The real part data or the imaginary part data output by the selector 143 directly enters the corresponding multiplier 144. The multiplier 144 multiplies the input data with a preset coefficient to provide the effective data processed preliminarily for the subsequent accumulation operation of the adder 145. It should be noted that the preset coefficient is determined by the stage number of the i-th delay element 1411 in the delay chain, and the coefficient can be obtained by the function calculation of matlab.

[0046] The fourth-stage FIR filter 14 further includes n adders 145, each of which receives output data from the plurality of multipliers 144, and the plurality of adders 145 accumulatively calculates all data processed by the multipliers 144, when the selector 143 outputs real part data, the multipliers 144 perform weighting processing on the real part data, and the real part filter data is obtained through the accumulative calculation of the adder 145; when the selector 143 outputs imaginary part data, the multipliers 144 perform weighting processing on the imaginary part data, and the imaginary part filter data is obtained through the accumulative calculation of the adder 145. Further, the number of adders 145 is determined according to the number of delay elements in the filter, so as to ensure that the accumulative calculation can be efficiently completed, and the situation of data congestion or processing delay can be avoided. For example, in an embodiment, when there are 2n delay elements 1411 in the filter, the number of adders 145 is set to n-1.

[0047] After the real part filter data and the imaginary part filter data are obtained through the operation of the adder 145 of the fourth-stage FIR filter 14, when the real part filter data is generated in one clock cycle, the real part filter data is output through a single channel; when the imaginary part filter data is generated in the next clock cycle, the imaginary part filter data is output through the same channel, and the above-mentioned process is alternately performed, so that the data is output to the fifth-stage FIR filter 15 in the form of single-channel alternation, thereby further saving the hardware resources and avoiding the timing deviation problem that may be caused by double-channel output, and ensuring the phase consistency between the real part filter data and the imaginary part filter data.

[0048] According to the above description, the digital filtering system provided by the embodiment of the present application adopts the orthogonal time interleaving processing strategy for the fourth-stage FIR filter, processes the real part data and the imaginary part data through the double-delay link design respectively, so that the real part data and the imaginary part data are transmitted through the corresponding delay chain in a step-by-step delay manner, the selectors alternately select the real part data or the imaginary part data output by the corresponding delay elements according to the clock cycle, and the selection of all selectors at the same time is consistent, so that the real part data and the imaginary part data are processed through single-channel time division multiplexing in different clock cycles, the double-channel processing is optimized to single-channel time division processing, the redundant design of processing the complex signal through double channels is broken through, the occupation of hardware resources is greatly reduced, and the circuit structure is simplified.

[0049] Further, the digital filtering system provided by the embodiment of the present application realizes effective filtering and down-sampling of high-speed signal streams through the multi-stage cascaded filter design, and each FIR filter cooperatively completes the conversion from the initial high sampling rate signal to the target low sampling rate signal in the signal processing link, so as to ensure the signal processing accuracy, avoid the timing deviation that may occur in data output, ensure the spectral purity and anti-aliasing performance of the signal, and optimize the utilization of hardware resources.

[0050] As an optional implementation, in the five-stage cascaded FIR filter, the first-stage FIR filter is configured with a 2-fold decimation rate, the second-stage FIR filter is configured with a 4-fold decimation rate, the third-stage FIR filter is configured with a 2-fold decimation rate, the fourth-stage FIR filter is configured with a 2-fold decimation rate, and the fifth-stage FIR filter is configured with a 2-fold decimation rate.

[0051] Specifically, the first-stage FIR filter is located at the front end of the signal processing chain, and the 2-fold decimation rate setting of the first-stage FIR filter can reduce the sampling rate of the input high-speed signal by half, and filter out the high-frequency components generated by mixing through a larger stopband attenuation. The second-stage FIR filter adopts a 4-fold decimation rate, which has a larger decimation multiple than the first-stage FIR filter. After processing by the first-stage FIR filter, the bandwidth of the signal is compressed, and at this time, a higher multiple of the decimation rate can further reduce the data volume while balancing the transition band requirement and resource efficiency.

[0052] The third-stage FIR filter is configured with a 2-fold decimation rate. At this time, after the signal is processed by the first two-stage filters, the sampling rate has been significantly reduced, and the third-stage FIR filter continues to adjust the sampling rate through 2-fold decimation, while further suppressing out-of-band noise through filtering to ensure the spectral purity of the signal. The fourth-stage FIR filter and the fifth-stage FIR filter both adopt a 2-fold decimation rate. In the processing process, the fourth-stage FIR filter uses a processing mechanism of alternately processing real data and imaginary data in a single channel to ensure data format compatibility while completing 2-fold decimation. The fifth-stage FIR filter completes the final sampling rate adjustment through 2-fold decimation and outputs low-frequency data that meets the requirements.

[0053] To further illustrate, an example of the five-stage cascaded FIR filter of the embodiments of the present application is provided as follows: Figure 3As shown, the initial sampling rate of the setting signal is 4800MHz, the decimation rate of the first-stage FIR filter is configured as 2 times, the sampling rate of the signal after the first-stage FIR filter processing is reduced to 2400MHz, the first-stage FIR filter outputs the signal to the second-stage FIR filter; the decimation rate of the second-stage FIR filter is configured as 4 times, the sampling rate of the signal after the second-stage FIR filter processing is reduced to 600MHz, the second-stage FIR filter outputs the signal to the third-stage FIR filter; the decimation rate of the third-stage FIR filter is configured as 2 times, the sampling rate of the signal after the third-stage FIR filter processing is reduced to 300MHz, the third-stage FIR filter outputs the signal to the fourth-stage FIR filter; the decimation rate of the fourth-stage FIR filter is configured as 2 times, the sampling rate of the signal after the fourth-stage FIR filter processing is reduced to 150MHz, the fourth-stage FIR filter outputs the signal to the fifth-stage FIR filter; the decimation rate of the fifth-stage FIR filter is configured as 2 times, the sampling rate of the signal after the fifth-stage FIR filter processing is reduced to 75MHz.

[0054] The product of the decimation rates of the five-stage cascaded FIR filters is 64, which realizes 64 times decimation effect of the input signal. Through the way of step-by-step decimation, the filter performance decline (such as the problem of too wide transition band, insufficient stopband attenuation, etc.) caused by too large single decimation multiple can be effectively avoided, and each stage of filter only needs to process the signal of the corresponding sampling rate, which reduces the requirement for hardware resources, effectively reduces the hardware burden of each stage of filter while ensuring the processing precision, and realizes the smooth transition from the initial high sampling rate to the target low sampling rate.

[0055] Further, as an optional implementation manner, in the five-stage cascaded FIR filters, the first to third-stage FIR filters adopt differential transition band design, the transition band of the first-stage FIR filter is wider than that of the second-stage FIR filter, and the transition band of the second-stage FIR filter is wider than that of the third-stage FIR filter.

[0056] Specifically, the first-stage FIR filter is the front end of the entire cascaded architecture, which directly processes the input signal, at this time, the sampling rate of the signal is the highest, and the data amount is large, the transition band of the first-stage FIR filter is configured to be wider than that of the second-stage FIR filter, so that the first-stage FIR filter can complete the preliminary anti-aliasing filtering and decimation, and quickly reduce the data rate, avoiding the influence of the narrow transition band of the first-stage FIR filter on the processing performance of the system.

[0057] The second-stage FIR filter processes the signal that has been down-sampled by the first-stage FIR filter, the sampling rate of the signal is reduced, the data amount is reduced, the transition band of the second-stage FIR filter is designed to be narrower than that of the first-stage FIR filter, so as to further suppress the out-of-band noise and interference signal, and avoid the out-of-band components that are not completely filtered by the first-stage FIR filter from entering the subsequent link. Meanwhile, the transition band of the second-stage FIR filter is designed to be wider than that of the third-stage FIR filter, the transition band width of the second-stage FIR filter is between that of the first-stage FIR filter and that of the third-stage FIR filter, a balance is achieved between "further suppressing noise" and "controlling resource consumption", a cleaner signal is provided for subsequent processing, while the hardware burden is not increased, and the filter order is not increased, so as to cause resource waste.

[0058] After the signal is down-sampled by the first two-stage filters, the sampling rate of the signal is significantly reduced, and the data processing pressure is reduced, the transition band of the third-stage FIR filter is designed to be narrower than that of the second-stage FIR filter, so as to more accurately filter out the out-of-band noise of the signal, ensure the in-band flatness and out-of-band suppression capability of the output signal, avoid the out-of-band noise leakage caused by the excessively wide transition band, solve the in-band ripple deterioration problem caused by the overlapping of the transition bands in the traditional simple cascade architecture, and provide a high-quality input signal for subsequent orthogonal time division interleaving processing and final down-sampling through the differential transition band design.

[0059] Further, as an optional implementation manner, in the first three-stage filters, the first-stage FIR filter is set to have an order of 18, the second-stage FIR filter is set to have an order of 22, and the third-stage FIR filter is set to have an order of 54.

[0060] Specifically, the first-stage FIR filter is the front end of the entire cascade system, at this time, the sampling rate of the input signal is high, the data amount is large, the transition band of the first-stage FIR filter is relatively wide compared with the last two-stage filters, the requirement for filtering accuracy is relatively low, the first-stage FIR filter is set to have an order of 18, can effectively filter out part of the high-frequency out-of-band noise, complete 2 times down-sampling to reduce the data rate, and meanwhile avoid excessive consumption of resources caused by excessively high order, and reduce the hardware pressure for subsequent processing.

[0061] The signal processed by the second-stage FIR filter is down-sampled by the first-stage FIR filter, the sampling rate of the signal is significantly reduced, the data amount is reduced, and meanwhile the transition band width of the second-stage FIR filter is narrower than that of the first-stage FIR filter, the requirement for filtering accuracy is improved, the second-stage FIR filter is set to have an order of 22, compared with the first-stage FIR filter, the second-stage FIR filter can further suppress the out-of-band noise on the premise of avoiding unnecessary waste of resources.

[0062] The transition band of the third-stage FIR filter is the narrowest compared to the first two-stage filters, and the third-stage FIR filter has the highest requirement for out-of-band rejection capability. At this time, after the signal is down-sampled by the first two-stage filters, the sampling rate is greatly reduced, and the data processing pressure is reduced. The third-stage FIR filter is set to 54 orders to achieve high stopband attenuation, effectively filter out the out-of-band noise that is not completely suppressed by the first two-stage filters, and bring the out-of-band rejection of the signal to above the preset threshold. Optionally, in the embodiment of the present application, the preset threshold is 60 dB.

[0063] To further illustrate, an example of the first three-stage FIR filter in the embodiment of the present application is provided as follows:

[0064] The initial sampling rate of the signal is set to 4800 MHz, the first-stage FIR filter is configured to a 2-fold down-sampling rate, and the first-stage FIR filter is set to 18 orders. The amplitude-frequency response of the first-stage FIR filter is as shown in FIG. 4, the first-stage FIR filter reduces the sampling rate of the signal from 4800 MHz to 2400 GHz, and the parallel channel number is reduced from 16 to 8. Figure 4 The second-stage FIR filter is configured to a 4-fold down-sampling rate, and the second-stage FIR filter is set to 22 orders. The amplitude-frequency response of the second-stage FIR filter is as shown in FIG. 5, the second-stage FIR filter reduces the sampling rate of the signal from 2400 MHz to 600 GHz, and the parallel channel number is reduced from 8 to 2. Figure 5 The third-stage FIR filter is configured to a 2-fold down-sampling rate, and the third-stage FIR filter is set to 54 orders. The amplitude-frequency response of the third-stage FIR filter is as shown in FIG. 6, the third-stage FIR filter reduces the sampling rate of the signal from 600 MHz to 300 GHz, and the parallel channel number is reduced from 2 to 1. Figure 6

[0065] As an optional implementation, in the digital filtering system provided by the embodiment of the present application, there are also a first deep register group and a second deep register group between the third-stage FIR filter and the fourth-stage FIR filter. The first deep register group is configured to buffer the real part data of the signal output by the third-stage FIR filter and send the real part data to the first delay chain; and the second deep register group is configured to buffer the imaginary part data of the signal output by the third-stage FIR filter and send the imaginary part data to the second delay chain.

[0066] Specifically, the third-stage FIR filter is the end of the first three-stage filter processing, the third-stage FIR filter outputs a complex signal after preliminary filtering and down-sampling, which includes a real part and an imaginary part. The two parts of data enter the first deep register group and the second deep register group respectively, so as to respectively perform corresponding processing links of the fourth-stage FIR filter.

[0067] ​The first deep register group is responsible for the transmission of real part data, temporarily stores the real part data output by the third FIR filter, and avoids loss or disorder caused by mismatching of data transmission speed through buffering. After completing buffering, the first deep register group sends the real part data to the first delay chain of the fourth FIR filter according to the processing requirements of the first delay chain, to ensure that the real part data can enter the subsequent signal processing link.

[0068] Correspondingly, the second deep register group is responsible for the transmission of imaginary part data, the imaginary part data output by the third FIR filter is stored in the second deep register group, and the data flow speed between the two filters is balanced through the buffering mechanism. Subsequently, the second deep register group transmits the buffered imaginary part data to the second delay chain of the fourth FIR filter, to provide an input source for the step-by-step delay processing of the imaginary part data.

[0069] Through the design of the double register groups, the real part data and the imaginary part data are completely independent in the transmission path, avoiding mutual interference and ensuring the integrity and purity of both in the transmission process. Through the buffering and distribution mechanism of the register groups, the complex signals output by the third FIR filter can efficiently and orderly enter the double delay chains of the fourth FIR filter, laying a data foundation for the fourth FIR filter to realize single-channel alternating processing of real part and imaginary part data, and ensuring the stability and accuracy of the entire filtering system when processing complex signals.

[0070] As an optional implementation, in the fourth FIR filter, a serial output shift register is arranged between any delay element and the input end of the selector, and the number of bits of each shift register is the same and driven by the same clock.

[0071] Specifically, the fourth FIR filter includes a first delay chain and a second delay chain formed by cascading n delay elements, and the output end of each delay element is connected to the input end of the corresponding selector. A shift register is arranged between each delay element and the input end of the selector, and the data output by the delay element is serially output to the selector corresponding to the delay element through the shift register. The characteristic of serial output of the shift register enables the signal to be transmitted bit by bit in a time-ordered manner, avoiding the instantaneous current impact and signal interference of multiple signals during transmission, and further improving the stability of signal transmission. Moreover, the driving load borne by the delay element is shared by the shift register, and the data is output to the selector through the shift register, solving the high fan-out problem of high-speed signals.

[0072] Further, each shift register adopts the same bit number design, ensuring that the data width and transmission rhythm of the signals output by different delay elements remain consistent after being processed by the shift register, ensuring that the selector selects the real part data and the imaginary part data from the same series of delay elements at the same time. Moreover, each shift register is driven by the same clock, and the transmission delay of data is controlled within one clock cycle, ensuring that the working timing of all shift registers is strictly synchronized, avoiding the problem of inconsistent signal transmission delay caused by clock deviation, and ensuring that the real part data and the imaginary part data can maintain an accurate phase relationship when reaching the selector, providing a reliable timing basis for subsequent alternating selection and multiplication operation.

[0073] As an optional implementation, in the fourth-stage FIR filter, the selector is driven by a modulo-2 counter.

[0074] Specifically, the modulo-2 counter alternately outputs 0 or 1 according to the clock cycle, and the counting logic is that when the value of the modulo-2 counter reaches 1, the next clock trigger jumps back to 0, forming a cycle. The selector is driven by the modulo-2 counter, and the n selectors in the fourth-stage FIR filter alternately select the real part data or the imaginary part data according to the clock cycle, and the selection of all selectors at the same time remains consistent, ensuring the ordered output of the real part data and the imaginary part data.

[0075] Moreover, the output state of the modulo-2 counter is triggered only by the clock cycle and is not disturbed by other signals, which can provide stable and reliable control signals, avoiding the error operation of the selector caused by unstable control signals, and ensuring the alternating output of the real part data and the imaginary part data.

[0076] As an optional implementation, in the digital filtering system provided in the embodiments of the present application, the fourth-stage FIR filter adopts an equal-ripple optimization algorithm to determine the order.

[0077] Specifically, the equal-ripple optimization algorithm optimizes the frequency response of the filter to make the ripple distribution in the passband and the stopband as uniform as possible, while meeting the preset performance indicators (such as the transition bandwidth, the stopband attenuation, the passband fluctuation, etc.), and finds the minimum order that can achieve these indicators. The equal-ripple optimization algorithm adjusts the order of the filter to make the ripples in the passband and the stopband of the filter distribute at approximately equal amplitudes, and the maximum ripple value does not exceed the preset threshold. When the equal-ripple optimization algorithm finds the minimum order that can meet the performance indicators of the filter, the order of the fourth-stage FIR filter is determined, which can avoid the waste of hardware resources caused by too high order, and prevent the problem of not meeting the filtering performance requirements caused by too low order, ensuring that the fourth-stage FIR filter can effectively suppress the noise that is not completely filtered by the first three-stage filters.

[0078] The equal-ripple optimization algorithm can calculate the minimum order by the following formula:

[0079] ;

[0080] N represents the minimum order, represents the normalized transition bandwidth, represents the passband ripple, represents the stopband ripple. In the fourth-order FIR filter of the embodiment of the present application, the normalized transition bandwidth is 0.05, the passband ripple and the stopband ripple are 0.0001.

[0081] To further illustrate, an example of calculating the minimum order of the fourth-order FIR filter by the equal-ripple optimization algorithm is given below: if the target stopband attenuation of the fourth-order FIR filter is greater than 80 dB and the target transition bandwidth is less than 5% of the sampling rate (i.e. the 150 MHz transition band needs to be less than 7.5 MHz), based on the equal-ripple optimization algorithm, according to the corresponding relationship between the target stopband attenuation and the target transition bandwidth, it can be calculated that: under the sampling rate of 150 MHz, the minimum order of the fourth-order FIR filter is 54, then the stopband attenuation greater than 80 dB and the transition bandwidth less than 5% can be achieved; and when the minimum order of the fourth-order FIR filter is 54, the fourth-order FIR filter has 55 delay elements.

[0082] As an optional implementation manner, the fourth-order FIR filter provided by the embodiment of the present application further includes a FIFO data reconstruction module, the FIFO data reconstruction module is arranged between the quadrature time interleaving processing module and the fifth-order FIR filter, and the FIFO data reconstruction module is configured to adopt a bit width conversion and buffering mechanism to perform phase alignment and data recombination on the real part filter data and the imaginary part filter data output by the fourth-order FIR filter, to obtain reconstruction combined data twice the bit width of the real part filter data, and the FIFO data reconstruction module transmits the reconstruction combined data to the fifth-order FIR filter.

[0083] Specifically, the fourth-order FIR filter outputs the real part filter data and the imaginary part filter data alternately in a single channel by the quadrature time interleaving processing technology, the FIFO data reconstruction module is arranged between the quadrature time interleaving processing module and the fifth-order FIR filter, thereby avoiding the problems of time sequence deviation or phase inconsistency of the real part filter data and the imaginary part filter data output by the fifth-order FIR filter.

[0084] The FIFO data reconstruction module is configured to adopt a bit width conversion mechanism and a buffering mechanism. The bit width conversion mechanism integrates the real part filtered data and the imaginary part filtered data according to the bit width characteristics of the real part filtered data and the imaginary part filtered data output by the fourth-stage FIR filter. For example, if the bit width of the real part filtered data and the imaginary part filtered data output by the fourth-stage FIR filter is 16 bits, the FIFO data reconstruction module combines the two into 32-bit reconstructed data through bit width conversion, obtains reconstructed combined data twice the bit width of the real part filtered data, more efficiently utilizes the data transmission bandwidth, integrates the alternately appearing real part and imaginary part data, and facilitates the processing of the fifth-stage FIR filter.

[0085] The buffering mechanism is used to temporarily store the data output by the fourth-stage FIR filter. Through the buffering depth design, the buffering mechanism absorbs the instantaneous fluctuation in the data transmission process, avoids overflow or loss caused by burst data transmission, and ensures that each group of real part filtered data and imaginary part filtered data is strictly aligned in time through the timing control logic, avoids the possible small time difference between the real part filtered data and the imaginary part filtered data, and eliminates the phase deviation caused by the alternate output.

[0086] The FIFO data reconstruction module transmits the reconstructed combined data to the fifth-stage FIR filter. The reconstructed combined data retains the complete information of the real part filtered data and the imaginary part filtered data, ensures the continuity and accuracy of the data flow conversion between the two filters, lays a foundation for the efficient filtering processing of the fifth-stage FIR filter, and further guarantees the spectral purity and processing accuracy of the entire multi-stage cascaded FIR filter system.

[0087] As an optional implementation manner, in the five-stage cascaded FIR filter, the FIR filters at each stage are driven by the same clock.

[0088] Specifically, the application of the same clock provides a unified time reference for the five-stage cascaded FIR filter, ensures that the processing rhythm of each stage of filter strictly matches the data transmission rhythm. In each clock cycle, each stage of filter completes the receiving, processing and outputting operations according to the preset working logic, ensures that there is no time difference in data transmission, effectively eliminates the phase error and data loss problem caused by inconsistent clock. Optionally, in the embodiment of the present application, the working clock of each stage of FIR filter is 300 MHz.

[0089] Furthermore, using the same clock to drive each stage of the FIR filter simplifies the system's clock management design. It eliminates the need for clock conversion circuits or synchronization mechanisms for different filter stages, reducing hardware resource consumption caused by clock division, multiplication, or phase adjustment, and lowering system design complexity and error probability. Moreover, using the same clock to drive each stage of the FIR filter ensures that the real and imaginary data maintain the correct phase relationship during transmission and processing, avoiding I / Q imbalance problems caused by clock inconsistencies.

[0090] To further illustrate the effectiveness of the digital filtering system provided in this application's embodiments, an experimental comparison was conducted between the digital filtering system provided in this application's embodiments and traditional filtering methods. Under the condition of 54th-order FIR filter coefficients, the resource consumption of the traditional filtering method is shown in Table 1, and the resource consumption of the digital filtering system provided in this application's embodiments is shown in Table 2.

[0091]

[0092] Table 1

[0093]

[0094] Table 2

[0095] Furthermore, the decimation filtering simulation results of the first-stage FIR filter, second-stage FIR filter, and third-stage FIR filter of the digital filtering system provided in this application embodiment are as follows: Figure 7 As shown, the maximum error between the hardware simulation results and the theoretical error of the first to third stage FIR filters does not exceed 0.4%; the decimation filtering simulation results of the fourth and fifth stage FIR filters are as follows. Figure 8 As shown, the hardware simulation results of the fourth-stage FIR filter and the fifth-stage FIR filter have an error of less than 0.12% compared with the theoretical results.

[0096] As shown in Tables 1 and 2, under the condition of 54th order filter coefficients, the digital filtering system provided in this application embodiment can reduce the digital signal processor usage by 50%, significantly alleviating the problem of digital signal processor resource shortage in preprocessing operations. At the same time, the consumption of lookup table and register resources is also significantly reduced, further optimizing the overall resource utilization.

[0097] According to the above description, the digital filtering system provided by the embodiment of the present application adopts a quadrature time interleaving processing strategy for the fourth-stage FIR filter, processes the real part data and the imaginary part data through a double-delay link design respectively, makes the real part data and the imaginary part data be transmitted through the corresponding delay chains in a step-by-step delay manner, and the selector alternately selects the real part data or the imaginary part data output by the corresponding delay element according to the clock period, and the selection of all the selectors is consistent at the same time, so that the real part data and the imaginary part data are processed through single-channel time-division multiplexing at different clock periods, the double-channel processing is optimized to single-channel time-division processing, the redundant design of processing complex signals through double channels is broken through, the occupation of hardware resources is greatly reduced, and the circuit structure is simplified.

[0098] In addition, the digital filtering system provided by the embodiment of the present application realizes effective filtering and down-sampling of high-speed signal streams through the design of a multi-stage cascaded filter, and each stage of the FIR filter cooperatively completes the conversion from an initial high sampling rate signal to a target low sampling rate signal in the signal processing link, thereby ensuring the signal processing accuracy, the spectral purity and the anti-aliasing performance of the signal, and optimizing the utilization of hardware resources. Further, the anti-aliasing performance is optimized step by step through the differential transition band design of the multi-stage filter, thereby reserving the sampling advantage while reducing the FPGA resource occupation.

[0099] It can be understood that the word "exemplary" used in this text means "as an example, example or illustration". Any embodiment described as "exemplary" is not necessarily superior to or superior to other embodiments and / or does not exclude the features combined with other embodiments. It should be understood that certain features of the present application described in the context of separate embodiments for the sake of clarity can also be provided in combination in a single embodiment. Conversely, various features of the present application described in the context of a single embodiment for the sake of clarity can also be provided separately or in any suitable combination or as an embodiment of the present application described anywhere else.

[0100] In the description of the present application, unless otherwise specified, " / " means "or", for example, A / B can mean A or B. "And / or" in this text is only a description of the relationship between the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. In addition, "at least one" means one or more, and "multiple" means two or more. "First", "second", etc. do not limit the quantity and execution order, and "first", "second", etc. do not necessarily mean different.

[0101] The above disclosed is only the preferred embodiment of the present application, and is not intended to limit the scope of the present application. Those skilled in the art can understand that changes, modifications, substitutions, combinations, simplifications, etc. made without departing from the spirit and scope of the present application and the appended claims should be equivalent replacements and still fall within the scope of the present application.

Claims

1. A digital filtering system, characterized by The digital filtering system comprises: a five-stage cascaded FIR filter, wherein the fourth-stage FIR filter comprises a quadrature time interleaving processing module, the quadrature time interleaving processing module comprises a first delay chain and a second delay chain respectively formed by cascading n delay elements, the first delay chain is configured to delay transmission real part data by the n delay elements stage by stage, and the second delay chain is configured to delay transmission imaginary part data by the n delay elements stage by stage; n selectors, two inputs of an i-th selector of the n selectors are connected with outputs of i-th stage delay elements of two delay chains respectively, and the i-th selector is configured to alternately select the real part data or the imaginary part data transmitted by the two i-th stage delay elements according to a clock cycle, and selections of the n selectors are the same at the same time; n multipliers, an i-th multiplier of the n multipliers is configured to multiply an output of the i-th selector with a coefficient, and the coefficient is determined by a stage number of the i-th stage delay element in the delay chain; a plurality of adders configured to add outputs of the n multipliers to obtain real part filtering data or imaginary part filtering data, and the fourth-stage FIR filter outputs the real part filtering data and the imaginary part filtering data to a fifth-stage FIR filter in a single channel alternately.

2. The digital filtering system according to claim 1, wherein the fourth-stage FIR filter further comprises a FIFO data reconstruction module, the FIFO data reconstruction module is arranged between the quadrature time interleaving processing module and the fifth-stage FIR filter, the FIFO data reconstruction module is configured to perform phase alignment and data recombination on the real part filtering data and the imaginary part filtering data output by the fourth-stage FIR filter by using a bit width conversion and a buffering mechanism to obtain reconstruction combined data with a bit width twice that of the real part filtering data, and the FIFO data reconstruction module transmits the reconstruction combined data to the fifth-stage FIR filter.

3. The digital filtering system of claim 1, wherein, The digital filtering system further comprises: a shift register arranged in series between any delay element and an input of the selector, and each shift register has the same bit number and is driven by the same clock.

4. The digital filtering system of claim 1, wherein, The digital filtering system further comprises: a first depth register group configured to buffer real part data of a signal output by a third-stage FIR filter and send the real part data to the first delay chain; a second depth register group configured to buffer imaginary part data of the signal output by the third-stage FIR filter and send the imaginary part data to the second delay chain.

5. The digital filtering system according to claim 1, wherein in the five-stage cascaded FIR filter, a first-stage FIR filter is configured to have a 2-fold downsampling rate, a second-stage FIR filter is configured to have a 4-fold downsampling rate, a third-stage FIR filter is configured to have a 2-fold downsampling rate, a fourth-stage FIR filter is configured to have a 2-fold downsampling rate, and a fifth-stage FIR filter is configured to have a 2-fold downsampling rate.

6. The digital filtering system of claim 1, wherein, in the five-stage cascaded FIR filter, the first-stage to third-stage FIR filters are designed with different transition bands, the first-stage FIR filter has a wider transition band than the second-stage FIR filter, and the second-stage FIR filter has a wider transition band than the third-stage FIR filter.

7. The digital filtering system of claim 6, wherein, the first-stage FIR filter is configured with 18 taps, the second-stage FIR filter is configured with 22 taps, and the third-stage FIR filter is configured with 54 taps.

8. The digital filtering system of claim 1, wherein, in the five-stage cascaded FIR filter, each of the FIR filters is driven by the same clock.

9. The digital filtering system of claim 1, wherein, the fourth-stage FIR filter is configured with a number of taps determined by an equal-ripple optimization algorithm.

10. The digital filtering system of claim 1, wherein, the selector is driven by a modulo-2 counter.

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