A data acquisition method and data acquisition card

Abstract

The embodiment of the present application discloses a data acquisition method and a data acquisition card. The data acquisition method is applied to the data acquisition card, and the data acquisition card comprises a comparator, a delay module in communication connection with the comparator, a fan-out module in communication connection with the delay module and used for N equal division of a trigger signal output by the delay module, N being an integer greater than 1, a field programmable gate array in communication connection with the fan-out module, the field programmable gate array comprising a clock unit, and an analog-to-digital conversion module in communication connection with the field programmable gate array. The data acquisition method comprises the following steps: receiving an instruction; controlling the clock unit to have clock signals with the same frequency and N equal division of phases according to the instruction; receiving a trigger signal transmitted by the fan-out module and a digital signal transmitted by the analog-to-digital conversion module, processing the trigger signal based on the clock signal, and reordering the digital signal according to the processed trigger signal. The technical scheme provided by the embodiment of the present application can improve the data acquisition precision.

Description

Technical Field

[0001] This invention relates to data acquisition technology, and more particularly to a data acquisition method and a data acquisition card. Background Technology

[0002] Data collection is necessary in any scenario that requires data processing or analysis. Currently, existing data collection methods suffer from low data collection accuracy. Summary of the Invention

[0003] This invention provides a data acquisition method and a data acquisition card to improve data acquisition accuracy.

[0004] In a first aspect, embodiments of the present invention provide a data acquisition method, wherein the data acquisition method is applied to a data acquisition card, the data acquisition card comprising:

[0005] A comparator is used to receive a trigger signal and a trigger threshold, and outputs the trigger signal when the amplitude of the trigger signal is greater than or equal to the trigger threshold;

[0006] The delay module is communicatively connected to the comparator and is used to delay the trigger signal output by the comparator and output the delayed trigger signal.

[0007] The fan-out module is communicatively connected to the delay module and is used to divide the trigger signal output by the delay module into N equal parts, resulting in N trigger signals, and output each trigger signal, where N is an integer greater than 1.

[0008] A field-programmable gate array (FPGA) is communicatively connected to the fan-out module, and the FPGA includes a clock unit.

[0009] An analog-to-digital converter module is communicatively connected to the field-programmable gate array (FPGA) and is used to receive analog signals, convert the analog signals into digital signals, and output them to the FPGA.

[0010] The data acquisition method includes:

[0011] Receive instructions;

[0012] According to the instructions, the clock signals of the clock unit are controlled to have the same frequency and the phase is divided into N equal parts;

[0013] The system receives the trigger signal transmitted by the fan-out module and the digital signal transmitted by the analog-to-digital converter module, processes the trigger signal based on the clock signal, and reorders the digital signal according to the processed trigger signal.

[0014] Optionally, before the clock signals of the control clock unit have the same frequency and are divided into N equal phases, the following steps are included:

[0015] Delay calibration is performed on the delay module and the field-programmable gate array.

[0016] Optionally, before performing delay calibration on the delay module and the field-programmable gate array, the following steps are included:

[0017] The clock signals of the clock unit are controlled to be in phase and frequency.

[0018] Optionally, processing the trigger signal based on the clock signal and reordering the digital signal according to the processed trigger signal includes:

[0019] The trigger signal is converted from serial to parallel based on the clock signal, and the trigger data of the converted trigger signal is spliced ​​together. The target signal is then extracted from the spliced ​​trigger data.

[0020] The digital signals are reordered according to the target signal.

[0021] Secondly, embodiments of the present invention provide a data acquisition card, including:

[0022] A comparator is used to receive a trigger signal and a trigger threshold, and outputs the trigger signal when the amplitude of the trigger signal is greater than or equal to the trigger threshold;

[0023] The delay module is communicatively connected to the comparator and is used to delay the trigger signal output by the comparator and output the delayed trigger signal.

[0024] The fan-out module is communicatively connected to the delay module and is used to divide the trigger signal output by the delay module into N equal parts, resulting in N trigger signals, and output each trigger signal, where N is an integer greater than 1.

[0025] A field-programmable gate array (FPGA) is communicatively connected to the fan-out module. The FPGA includes a clock unit, wherein each clock signal in the clock unit has the same frequency and a phase divided into N equal parts. The FPGA is used to receive each trigger signal output by the fan-out module and process the trigger signals based on the clock signals.

[0026] An analog-to-digital converter module, communicatively connected to the field-programmable gate array (FPGA), is used to receive analog signals, convert the analog signals into digital signals, and output them to the FPGA. The FPGA is also used to reorder the digital signals according to the processed trigger signal.

[0027] Optionally, there are at least two delay modules and at least two fan-out modules. The delay modules and fan-out modules correspond one-to-one. Each delay module is communicatively connected to the corresponding fan-out module. Each delay module is used to sequentially delay the trigger signal output by the comparator.

[0028] Optionally, the field-programmable gate array includes a trigger module and a data sorting module. The trigger module is communicatively connected to the fan-out module and the data sorting module, and the data sorting module is communicatively connected to the analog-to-digital converter module. The trigger module is used to receive each trigger signal output by the fan-out module and process the trigger signal based on the clock signal. The data sorting module is used to reorder the digital signal transmitted by the analog-to-digital converter module according to the processed trigger signal.

[0029] Optionally, the triggering module includes a clock unit, a serial-to-parallel conversion unit, and a trigger data processing unit. The clock unit is communicatively connected to the serial-to-parallel conversion unit, and the fan-out module, the serial-to-parallel conversion unit, and the trigger data processing unit are communicatively connected in sequence. The clock unit is used to transmit a clock signal with N equal phase divisions at the same frequency to the serial-to-parallel conversion unit. The serial-to-parallel conversion unit is used to perform serial-to-parallel conversion on the trigger signal transmitted by the fan-out module according to the clock signal. The trigger data processing unit is used to splice the trigger data of the serial-to-parallel converted trigger signal and extract the target signal from the spliced ​​trigger data. The data sorting module is used to reorder the digital signal according to the target signal.

[0030] Optionally, the number of the delay module, the fan-out module, the clock unit, and the trigger data processing unit are all n and correspond one-to-one. The number of serial-to-parallel conversion units is n×N. Each fan-out module and each clock unit corresponds to N serial-to-parallel conversion units, where n is an integer greater than 1, and n and N may be equal or different. The clock unit is used to transmit N clock signals with the same frequency and phase divided into N equal parts to the corresponding N serial-to-parallel conversion units. The N serial-to-parallel conversion units corresponding to the same clock unit are used to perform serial-to-parallel conversion on the N trigger signals transmitted by the fan-out module according to the clock signal in sequence according to the equally spaced phases.

[0031] Optionally, the data acquisition card also includes an analog front-end module, which is communicatively connected to the analog-to-digital conversion module. The analog front-end module is used to receive analog signals, process the analog signals, and transmit the processed analog signals to the analog-to-digital conversion module.

[0032] This invention provides a data acquisition method and a data acquisition card. The data acquisition method is applied to the data acquisition card, which includes: a comparator for receiving a trigger signal and a trigger threshold, and outputting a trigger signal when the amplitude of the trigger signal is greater than or equal to the trigger threshold; a delay module, communicatively connected to the comparator, for delaying the trigger signal output by the comparator and outputting the delayed trigger signal; a fan-out module, communicatively connected to the delay module, for dividing the trigger signal output by the delay module into N equal parts, dividing it into N trigger signals and outputting each trigger signal, where N is an integer greater than 1; a field-programmable gate array (FPGA), communicatively connected to the fan-out module, which includes a clock unit; and an analog-to-digital converter (ADC), communicatively connected to the FPGA, for receiving analog signals, converting the analog signals into digital signals, and outputting them to the FPGA. The data acquisition method includes: receiving an instruction; controlling the clock signals of the clock unit to have the same frequency and N equal phases according to the instruction; receiving the trigger signal transmitted by the fan-out module and the digital signal transmitted by the ADC; processing the trigger signal based on the clock signal; and reordering the digital signal according to the processed trigger signal. The data acquisition method and data acquisition card provided in this embodiment of the invention improve the acquisition accuracy of the trigger signal by controlling the clock signals of each clock unit to have the same frequency and N equally divided phases, and processing the trigger signal based on the clock signals with the same frequency and N equally divided phases. Attached Figure Description

[0033] Figure 1 This is a flowchart of a data acquisition method provided in Embodiment 1 of the present invention;

[0034] Figure 2 This is a flowchart of a data acquisition method provided in Embodiment 2 of the present invention;

[0035] Figure 3 This is a structural block diagram of a data acquisition card provided in Embodiment 3 of the present invention;

[0036] Figure 4 This is a structural block diagram of a trigger module provided in Embodiment 3 of the present invention. Detailed Implementation

[0037] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0038] Example 1

[0039] Figure 1This is a flowchart of a data acquisition method provided in Embodiment 1 of the present invention. This embodiment is applicable to data acquisition using data acquisition cards, etc. The data acquisition method is applied to a data acquisition card, which includes: a comparator for receiving a trigger signal and a trigger threshold, and outputting a trigger signal when the amplitude of the trigger signal is greater than or equal to the trigger threshold; a delay module, communicatively connected to the comparator, for delaying the trigger signal output by the comparator and outputting the delayed trigger signal; a fan-out module, communicatively connected to the delay module, for dividing the trigger signal output by the delay module into N equal parts, dividing it into N trigger signals and outputting each trigger signal, where N is an integer greater than 1; a field-programmable gate array (FPGA), communicatively connected to the fan-out module, which includes a clock unit; and an analog-to-digital converter (ADC), communicatively connected to the FPGA, for receiving analog signals, converting the analog signals into digital signals, and outputting them to the FPGA. This method can be executed by the FPGA, and specifically includes the following steps:

[0040] Step 110: Receive instructions.

[0041] The instruction can be an enable instruction for the FPGA (Field-Programmable Gate Array).

[0042] Step 120: According to the instruction, control the clock signals of each clock unit to have the same frequency and the phase to be divided into N equal parts.

[0043] Specifically, after receiving the instruction, the FPGA controls the clock signals of its own clock unit to have the same frequency and the phase to be divided into N equal parts. Before the clock signals of the control clock unit have the same frequency and the phase to be divided into N equal parts, the clock signals of the control clock unit are in phase and the delay module and the field programmable gate array are calibrated for delay.

[0044] Step 130: Receive the trigger signal transmitted by the fan-out module and the digital signal transmitted by the analog-to-digital converter module, process the trigger signal based on the clock signal, and reorder the digital signal according to the processed trigger signal.

[0045] Specifically, the trigger signal is converted from serial to parallel based on the clock signal, and the trigger data of the converted trigger signal is spliced ​​together. The target signal is extracted from the spliced ​​trigger data, and the digital signal is reordered according to the target signal.

[0046] It should be noted that the specific size of N mentioned above can be determined according to the actual data collection needs, and is not limited here.

[0047] The data acquisition method provided in this embodiment includes: receiving an instruction; controlling the clock signals of the clock unit to have the same frequency and N equal phases according to the instruction; receiving a trigger signal transmitted by the fan-out module and a digital signal transmitted by the analog-to-digital conversion module; processing the trigger signal based on the clock signal; and reordering the digital signal according to the processed trigger signal. The data acquisition method provided in this embodiment improves the acquisition accuracy of the trigger signal by controlling the clock signals of the clock unit to have the same frequency and N equal phases, thereby improving the overall data acquisition accuracy.

[0048] Example 2

[0049] Figure 2 This is a flowchart of a data acquisition method provided in Embodiment 2 of the present invention. This embodiment is applicable to data acquisition using data acquisition cards, etc. The data acquisition method is applied to a data acquisition card, which includes: a comparator for receiving a trigger signal and a trigger threshold, and outputting a trigger signal when the amplitude of the trigger signal is greater than or equal to the trigger threshold; a delay module, communicatively connected to the comparator, for delaying the trigger signal output by the comparator and outputting the delayed trigger signal; a fan-out module, communicatively connected to the delay module, for dividing the trigger signal output by the delay module into N equal parts, dividing it into N trigger signals and outputting each trigger signal, where N is an integer greater than 1; a field-programmable gate array (FPGA), communicatively connected to the fan-out module, which includes a clock unit; and an analog-to-digital converter (ADC), communicatively connected to the FPGA, for receiving analog signals, converting the analog signals into digital signals, and outputting them to the FPGA. This method can be executed by the FPGA, and specifically includes the following steps:

[0050] Step 210: Receive instructions.

[0051] The instruction can be the FPGA enable instruction.

[0052] Step 220: Control the clock signals of each clock unit to be in phase and frequency.

[0053] Specifically, an FPGA includes multiple clock units, each of which can output multiple clock signals. The FPGA controls each clock unit to output clock signals with the same frequency and phase according to instructions.

[0054] Step 230: Perform delay calibration on the delay module and the field programmable gate array.

[0055] The delay calibration includes the delay calibration of the delay module and the delay calibration of each serial-to-parallel conversion unit in the FPGA. The specific calibration process can be found in the relevant calibration process in the existing technology, and will not be repeated here.

[0056] Step 240: Control the clock signals of each clock unit to have the same frequency and the phase to be divided into N equal parts.

[0057] Specifically, phase N equal division means dividing the phase between 0 and 360 degrees into N equal parts. For example, if N is 3, then the phase of each clock signal is 0 degrees, 180 degrees and 240 degrees respectively.

[0058] Step 250: Perform serial-to-parallel conversion on the trigger signal based on the clock signal, and concatenate the trigger data of the serial-to-parallel converted trigger signal to extract the target signal from the concatenated trigger data.

[0059] Specifically, N clock signals are divided into N equal phases. N trigger signals are converted from serial to parallel based on N clock signals of the same frequency and N equal phases to low-frequency, multi-bit-width signals. The trigger signals after serial-to-parallel conversion are spliced ​​together to determine the position of the signal, such as the position of the signal transition, in order to extract the target signal and achieve high-precision extraction of the trigger signal.

[0060] Step 260: Reorder the digital signals according to the target signal.

[0061] For example, the digital signal before the rising edge of the target signal is removed from the digital signal, while the digital signal after the rising edge of the target signal is retained to ensure the accuracy of the digital signal.

[0062] It should be noted that the size of N in this embodiment is only for illustrative purposes and can be determined according to actual data collection needs, and is not limited here.

[0063] The data acquisition method provided in this embodiment includes: receiving an instruction; controlling the clock signals of the clock unit to be in phase and frequency according to the instruction, performing delay calibration on the delay module and the field-programmable gate array, controlling the clock signals of the clock unit to have the same frequency and N equal phases; performing serial-to-parallel conversion on the trigger signal based on the clock signal, and splicing the trigger data of the serial-to-parallel converted trigger signal, extracting the target signal from the spliced ​​trigger data, and reordering the digital signal according to the target signal. The data acquisition method provided in this embodiment improves the acquisition accuracy of the trigger signal by controlling the clock signals of the clock unit to have the same frequency and N equal phases, thereby improving the overall data acquisition accuracy.

[0064] Example 3

[0065] Figure 3 This is a structural block diagram of a data acquisition card provided in Embodiment 3 of the present invention. (Reference) Figure 3The data acquisition card includes: a comparator 10, a delay module 20, a fan-out module 30, a field-programmable gate array 40, and an analog-to-digital converter 50. The comparator 10 receives a trigger signal and a trigger threshold, and outputs a trigger signal when the amplitude of the trigger signal is greater than or equal to the trigger threshold. The delay module 20 is communicatively connected to the comparator 10 and delays the trigger signal output by the comparator 10, then outputs the delayed trigger signal. The fan-out module 30 is communicatively connected to the delay module 20 and divides the trigger signal output by the delay module 20 into N equal parts, creating N trigger signals, and outputs each trigger signal, where N is the maximum value. The field-programmable gate array (FPGA) 40 is communicatively connected to the fan-out module 30. The FPGA 40 includes a clock unit, and the clock signals of the clock unit have the same frequency and are divided into N equal phases. The FPGA 40 is used to receive the trigger signals output by the fan-out module 30 and process the trigger signals based on the clock signals. The analog-to-digital converter (ADC) 50 is communicatively connected to the FPGA 40 and is used to receive analog signals, convert the analog signals into digital signals, and output them to the FPGA 40. The FPGA 40 is also used to reorder the digital signals according to the processed trigger signals.

[0066] The specific process of data acquisition for the 40 pairs of programmable gate arrays can be referred to any of the above embodiments, and will not be repeated here. Furthermore, FPGA is a product of further development based on programmable devices such as PAL (Programmable Array Logic), GAL (Generic Array Logic), and CPLD (Complex programmable logic device). It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASICs), solving the shortcomings of custom circuits and overcoming the limitation of the limited gate count of traditional programmable devices. FPGAs are characterized by high flexibility, short development cycle, strong parallel processing capability, and reconfigurability. High flexibility: They can be customized according to user needs to implement various different logic functions, suitable for various application scenarios such as digital signal processing, image processing, and communication systems. Short development cycle: Compared with traditional ASIC designs, FPGAs do not require complex manufacturing processes, and modifications and debugging can be easily performed during development, greatly shortening the development cycle. Strong parallel processing capability: They have a large number of internal logic units, which can process multiple tasks simultaneously, achieving parallel computing and improving data processing efficiency. Reconfigurability: FPGAs can be reconfigured during operation to meet different application requirements, exhibiting strong adaptability and scalability. Therefore, FPGAs are widely used in various fields such as communications and digital signal processing.

[0067] Optionally, there are at least two delay modules 20 and fan-out modules 30. The delay modules 20 and fan-out modules 30 correspond one-to-one. Each delay module 20 is communicatively connected to the corresponding fan-out module 30. Each delay module 20 is used to sequentially delay the trigger signal output by the comparator 10.

[0068] For example, there are two delay modules 20 and two fan-out modules 30. One delay module 20 has a delay time of 0, and the other delay module 20 has a delay time of 1 / 2*N of the clock cycle. If there are multiple delay modules 20 and multiple fan-out modules 30, the delay time of the delay module 20 increases sequentially to improve the accuracy of the trigger signal.

[0069] refer to Figure 3 Optionally, the field-programmable gate array includes a trigger module 41 and a data sorting module 42. The trigger module 41 is communicatively connected to the fan-out module 30 and the data sorting module 42, and the data sorting module 42 is communicatively connected to the analog-to-digital converter module 50. The trigger module 41 is used to receive the trigger signals output by the fan-out module 30 and process the trigger signals based on the clock signal. The data sorting module 42 is used to reorder the digital signals transmitted by the analog-to-digital converter module 50 according to the processed trigger signals.

[0070] Specifically, the trigger module 41 performs serial-to-parallel conversion on N clock signals with the same frequency and N equal phases, and splices the trigger data of the serial-to-parallel converted trigger signals. The target signal is extracted from the spliced ​​trigger data so that the data sorting module 42 can reorder the digital signals according to the target signal.

[0071] Figure 4 This is a structural block diagram of a trigger module provided in Embodiment 3 of the present invention. (See reference) Figure 4 Optionally, the trigger module 41 includes a clock unit 411, a serial-to-parallel conversion unit 412, and a trigger data processing unit 413. The clock unit 411 is communicatively connected to the serial-to-parallel conversion unit 412, and the fan-out module 30, the serial-to-parallel conversion unit 412, and the trigger data processing unit 413 are communicatively connected in sequence. The clock unit 411 is used to transmit clock signals with N equal phases at the same frequency to the serial-to-parallel conversion unit 412. The serial-to-parallel conversion unit 412 is used to convert the trigger signal transmitted by the fan-out module 30 into a serial-to-parallel signal according to the clock signal. The trigger data processing unit 413 is used to splice the trigger data of the serial-to-parallel converted trigger signal and extract the target signal from the spliced ​​trigger data. The data sorting module 42 is used to reorder the digital signal according to the target signal.

[0072] Specifically, taking N serial-to-parallel conversion units 412 as an example, each of the N serial-to-parallel conversion units 412 performs serial-to-parallel conversion on its respective received trigger signal based on N clock signals of the same frequency and N equally divided phases. That is, the trigger signals received by different serial-to-parallel conversion units are sequentially converted according to the equally spaced phases of the clock signals. The trigger data processing unit 413 concatenates the trigger data after serial-to-parallel conversion and extracts the signal at the target position from the concatenated trigger data (the target position can be the position where the signal changes, such as the rising edge of the signal). This allows the data sorting module 42 to reorder the digital signals according to the signal extracted by the trigger data processing unit 413.

[0073] Optionally, the number of delay modules 20, fan-out modules 30, clock units 411, and trigger data processing units 413 are all n and correspond one-to-one. The number of serial-to-parallel conversion units 412 is n×N. Each fan-out module 30 and each clock unit 411 corresponds to N serial-to-parallel conversion units, where n is an integer greater than 1, and n may be equal to or different from N. The clock unit 411 is used to transmit N clock signals with the same frequency and phase divided into N equal parts to the corresponding N serial-to-parallel conversion units 412. The N serial-to-parallel conversion units 412 corresponding to the same clock unit 411 are used to perform serial-to-parallel conversion on the N trigger signals transmitted by the fan-out module 30 according to the clock signal and in sequence according to the equally spaced phases.

[0074] For example, if n is 2 and N is 4, the data acquisition card includes two delay modules, two fan-out modules, two clock units, two trigger data processing units, and eight serial-to-parallel conversion units. Four of the eight serial-to-parallel conversion units correspond to one delay unit, one fan-out module, one trigger data processing unit, and one clock unit, and are communicatively connected to their respective clock units. The other four correspond to another delay unit, another fan-out module, another trigger data processing unit, and another clock unit, and are also communicatively connected to their respective clock units. Each clock unit outputs four clock signals with the same frequency and four equally divided phases, and transmits these four clock signals to their respective four serial-to-parallel conversion units. The four serial-to-parallel conversion units, based on the four clock signals with the same frequency and four equally divided phases, sequentially convert the received trigger signals into serial-to-parallel signals according to equal phase intervals, achieving high-speed acquisition of the trigger signals.

[0075] refer to Figure 3 Optionally, the data acquisition card also includes an analog front-end module 60, which is communicatively connected to the analog-to-digital conversion module 50. The analog front-end module 60 receives and processes analog signals, and then transmits the processed analog signals to the analog-to-digital conversion module 50. The analog front-end module 60 performs signal processing such as gain adjustment, acting as a conditioning mechanism. The specific processing can be determined according to actual data acquisition needs and is not limited here.

[0076] It should be noted that the values ​​of n and N in this embodiment are only for illustrative purposes and can be determined according to actual data collection needs, and are not limited here.

[0077] The data acquisition card provided in this embodiment belongs to the same inventive concept as the data acquisition method provided in any embodiment of the present invention and has corresponding beneficial effects. For technical details not covered in this embodiment, please refer to the data acquisition method provided in any embodiment of the present invention.

[0078] Example 4

[0079] Embodiment 4 of the present invention also provides a computer-readable storage medium storing a computer program thereon. When executed by a processor, the program implements the data acquisition method provided in the embodiments of the present invention. The data acquisition method is applied to a data acquisition card, which includes: a comparator for receiving a trigger signal and a trigger threshold, and outputting a trigger signal when the amplitude of the trigger signal is greater than or equal to the trigger threshold; a delay module, communicatively connected to the comparator, for delaying the trigger signal output by the comparator and outputting the delayed trigger signal; a fan-out module, communicatively connected to the delay module, for dividing the trigger signal output by the delay module into N equal parts, dividing it into N trigger signals and outputting each trigger signal, where N is an integer greater than 1; a field-programmable gate array (FPGA), communicatively connected to the fan-out module, the FPGA including a clock unit; and an analog-to-digital converter (ADC), communicatively connected to the FPGA, for receiving analog signals, converting the analog signals into digital signals, and outputting them to the FPGA; the data acquisition method includes:

[0080] Receive instructions;

[0081] According to the instructions, the clock signals of the control clock unit have the same frequency and the phase is divided into N equal parts;

[0082] It receives the trigger signal transmitted by the fan-out module and the digital signal transmitted by the analog-to-digital converter module, processes the trigger signal based on the clock signal, and reorders the digital signal according to the processed trigger signal.

[0083] The computer storage medium of this invention can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0084] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0085] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including—but not limited to—wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0086] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or terminal. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0087] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, rearrangements, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A data acquisition method, characterized in that, The data acquisition method is applied to a data acquisition card, the data acquisition card comprising: A comparator is used to receive a trigger signal and a trigger threshold, and outputs the trigger signal when the amplitude of the trigger signal is greater than or equal to the trigger threshold; The delay module is communicatively connected to the comparator and is used to delay the trigger signal output by the comparator and output the delayed trigger signal. The fan-out module is communicatively connected to the delay module and is used to divide the trigger signal output by the delay module into N equal parts, resulting in N trigger signals, and output each trigger signal, where N is an integer greater than 1. A field-programmable gate array (FPGA) is communicatively connected to the fan-out module, and the FPGA includes a clock unit. An analog-to-digital converter module is communicatively connected to the field-programmable gate array (FPGA) and is used to receive analog signals, convert the analog signals into digital signals, and output them to the FPGA. The data acquisition method includes: Receive instructions; According to the instructions, the clock signals of the clock unit are controlled to have the same frequency and the phase is divided into N equal parts; The system receives the trigger signal transmitted by the fan-out module and the digital signal transmitted by the analog-to-digital converter module, processes the trigger signal based on the clock signal, and reorders the digital signal according to the processed trigger signal. The step of processing the trigger signal based on the clock signal and reordering the digital signal according to the processed trigger signal includes: The trigger signal is converted from serial to parallel based on the clock signal, and the trigger data of the converted trigger signal is spliced ​​together. The target signal is then extracted from the spliced ​​trigger data. The digital signals are reordered according to the target signal; The step of performing serial-to-parallel conversion on the trigger signal based on the clock signal, concatenating the trigger data of the converted trigger signal, and extracting the target signal from the concatenated trigger data includes: N clock signals are divided into N equal phases. N trigger signals are converted from serial to parallel based on N clock signals of the same frequency and N equal phases to low-frequency, multi-bit-width signals. The trigger signals after serial-to-parallel conversion are spliced ​​together to determine the position of the signal in order to extract the target signal.

2. The data acquisition method according to claim 1, characterized in that, Before the clock signals controlling the clock unit have the same frequency and their phases are divided into N equal parts, the following are included: Delay calibration is performed on the delay module and the field-programmable gate array.

3. The data acquisition method according to claim 2, characterized in that, Before performing delay calibration on the delay module and the field-programmable gate array, the following steps are included: The clock signals of the clock unit are controlled to be in phase and frequency.

4. A data acquisition card, characterized in that, include: A comparator is used to receive a trigger signal and a trigger threshold, and outputs the trigger signal when the amplitude of the trigger signal is greater than or equal to the trigger threshold; The delay module is communicatively connected to the comparator and is used to delay the trigger signal output by the comparator and output the delayed trigger signal. The fan-out module is communicatively connected to the delay module and is used to divide the trigger signal output by the delay module into N equal parts, resulting in N trigger signals, and output each trigger signal, where N is an integer greater than 1. A field-programmable gate array (FPGA) is communicatively connected to the fan-out module. The FPGA includes a clock unit, wherein each clock signal in the clock unit has the same frequency and its phase is divided into N equal parts. The field-programmable gate array is used to receive the trigger signals output by the fan-out module and process the trigger signals based on the clock signal; An analog-to-digital converter module, communicatively connected to the field-programmable gate array (FPGA), is used to receive analog signals, convert the analog signals into digital signals, and output them to the FPGA. The FPGA is also used to reorder the digital signals according to the processed trigger signals. The field-programmable gate array includes a trigger module and a data sorting module. The trigger module is communicatively connected to the fan-out module and the data sorting module, and the data sorting module is communicatively connected to the analog-to-digital converter module. The trigger module includes a clock unit, a serial-to-parallel converter unit, and a trigger data processing unit. The clock unit is communicatively connected to the serial-to-parallel converter unit, and the fan-out module, the serial-to-parallel converter unit, and the trigger data processing unit are communicatively connected in sequence. The clock unit is used to transmit clock signals with the same frequency and phase divided into N equal parts to the serial-to-parallel conversion unit. The serial-to-parallel conversion unit is used to convert the trigger signal transmitted by the fan-out module into a serial-to-parallel signal according to the clock signal. The trigger data processing unit is used to splice the trigger data of the serial-to-parallel converted trigger signal and extract the target signal from the spliced ​​trigger data. The data sorting module is used to reorder the digital signal according to the target signal. The clock unit is used to transmit N clock signals with the same frequency and phase divided into N equal parts to the corresponding N serial-to-parallel conversion units. The N serial-to-parallel conversion units corresponding to the same clock unit are used to perform serial-to-parallel conversion on the N trigger signals transmitted by the fan-out module according to the clock signal in sequence according to the equally spaced phases.

5. The data acquisition card according to claim 4, characterized in that, There are at least two delay modules and at least two fan-out modules. The delay modules and fan-out modules correspond one-to-one. Each delay module is communicatively connected to its corresponding fan-out module. Each delay module is used to sequentially delay the trigger signal output by the comparator.

6. The data acquisition card according to claim 4, characterized in that, The field-programmable gate array includes a trigger module and a data sorting module. The trigger module is communicatively connected to the fan-out module and the data sorting module, and the data sorting module is communicatively connected to the analog-to-digital converter module. The trigger module is used to receive each trigger signal output by the fan-out module and process the trigger signal based on the clock signal. The data sorting module is used to reorder the digital signal transmitted by the analog-to-digital converter module according to the processed trigger signal.

7. The data acquisition card according to claim 6, characterized in that, The triggering module includes a clock unit, a serial-to-parallel conversion unit, and a trigger data processing unit. The clock unit is communicatively connected to the serial-to-parallel conversion unit, and the fan-out module, the serial-to-parallel conversion unit, and the trigger data processing unit are communicatively connected in sequence. The clock unit is used to transmit a clock signal with N equal phase divisions at the same frequency to the serial-to-parallel conversion unit. The serial-to-parallel conversion unit is used to perform serial-to-parallel conversion on the trigger signal transmitted by the fan-out module according to the clock signal. The trigger data processing unit is used to splice the trigger data of the serial-to-parallel converted trigger signal and extract the target signal from the spliced ​​trigger data. The data sorting module is used to reorder the digital signal according to the target signal.

8. The data acquisition card according to claim 7, characterized in that, The number of delay modules, fan-out modules, clock units, and trigger data processing units are all n and correspond one-to-one. The number of serial-to-parallel conversion units is n×N. Each fan-out module and each clock unit corresponds to N serial-to-parallel conversion units, where n is an integer greater than 1, and n and N may be equal or different. The clock unit is used to transmit N clock signals with the same frequency and phase divided into N equal parts to the corresponding N serial-to-parallel conversion units. The N serial-to-parallel conversion units corresponding to the same clock unit are used to perform serial-to-parallel conversion on the N trigger signals transmitted by the fan-out module according to the clock signal in a serially-to-parallel manner with equal-interval phases.

9. The data acquisition card according to claim 4, characterized in that, It also includes an analog front-end module, which is communicatively connected to the analog-to-digital conversion module. The analog front-end module is used to receive analog signals, process the analog signals, and transmit the processed analog signals to the analog-to-digital conversion module.

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