A trigger signal acquisition circuit, an ADC sampling device and a sampling method
By coordinating the comparison module, buffer module, data acquisition module, and clock module in the trigger signal acquisition circuit, a clock signal with the same frequency and phase is output and a delay calibration is performed, which solves the problem of low trigger signal acquisition accuracy and realizes high-precision trigger signal acquisition.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ACELA MICROELECTRONICS (SUZHOU) CO LTD
- Filing Date
- 2025-06-30
- Publication Date
- 2026-05-12
AI Technical Summary
The current technology has low acquisition accuracy of trigger signals, which cannot meet the needs of high-precision trigger acquisition.
A trigger signal acquisition circuit is adopted, including a comparison module, a buffer module, a data acquisition module, and a clock module. By outputting N clock signals with the same frequency and phase, the control chip is used to calibrate and delay the trigger signal to ensure that the time difference of the trigger signal at adjacent moments is equal. The data acquisition module performs serial-to-parallel conversion to improve the sampling point density.
It improves the acquisition accuracy of the trigger signal, meets the requirements of high-precision trigger acquisition, increases the sampling point density, and improves the sampling frequency.
Smart Images
Figure CN120811377B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of signal acquisition technology, and in particular to a trigger signal acquisition circuit, an ADC sampling device, and a sampling method. Background Technology
[0002] ADC (Analog-to-Digital Converter) sampling primarily converts continuously changing analog signals into discrete digital signals. In practical applications, the trigger signal precisely determines when the ADC sampling device begins sampling. In high-precision trigger acquisition, the accuracy of each captured trigger signal must be greater than the ADC's sampling accuracy.
[0003] As the sampling rate of high-speed ADCs increases, the accuracy of capturing trigger signals also increases. Currently, the clock of FPGA (Field Programmable Gate Array) is generally used to capture trigger signals directly, but the accuracy of capturing trigger signals is low and cannot meet the needs of high-precision trigger acquisition. Summary of the Invention
[0004] This invention provides a trigger signal acquisition circuit, an ADC sampling device, and a sampling method to solve the problem that the acquisition accuracy of trigger signals in the prior art is low and cannot meet the requirements of high-precision trigger acquisition.
[0005] According to one aspect of the present invention, a trigger signal acquisition circuit is provided, comprising a comparison module, a buffer module, a data acquisition module, and a clock module;
[0006] The clock module is used to output N clock signals, wherein the N clock signals have the same frequency and phase, and N is greater than or equal to 2;
[0007] The comparison module receives a first trigger signal and a trigger threshold, and the comparison module is used to output a second trigger signal based on the first trigger signal and the trigger threshold.
[0008] The buffer module is connected to the comparison module, and the buffer module is used to copy and output N channels of the second trigger signal according to the second trigger signal;
[0009] The data acquisition module is connected to the buffer module and the clock module. The data acquisition module is used to acquire the third trigger signal according to the clock signal and convert it to output the fourth trigger signal. The number of third trigger signals is N. When N is greater than 2, the time difference between two adjacent third trigger signals in the N third trigger signals is equal.
[0010] Optionally, the trigger signal acquisition circuit further includes a control chip. The data acquisition module and the clock module are disposed inside the control chip. The control chip is connected to the buffer module. The control chip is used to calibrate the N second trigger signals according to the N clock signals so that the delays of the N second trigger signals are the same. The control chip is also used to perform delay control on the N second trigger signals and output N third trigger signals so that when the number of third trigger signals is greater than two, the time difference between two adjacent third trigger signals in the N third trigger signals is equal, wherein the product of the time difference and N is equal to the period of the clock signal.
[0011] Optionally, the data acquisition module includes N serial-to-parallel conversion units, which are connected to the buffer module and the clock module. The N serial-to-parallel conversion units are used to perform serial-to-parallel conversion on the N third trigger signals according to the N clock signals. The clock signals, the third trigger signals and the serial-to-parallel conversion units correspond one-to-one, and one serial-to-parallel conversion unit performs serial-to-parallel conversion on one third trigger signal according to one clock signal.
[0012] According to another aspect of the present invention, an ADC sampling device is provided, including the trigger signal acquisition circuit, an analog-to-digital conversion module, and a data reconstruction module. The analog-to-digital conversion module is used to convert an input analog signal into a digital signal. The data reconstruction module is connected to the trigger signal acquisition circuit and the analog-to-digital conversion module. The data reconstruction module is used to reconstruct the digital signal according to a fourth trigger signal output by the trigger signal acquisition circuit.
[0013] Optionally, the ADC sampling device further includes a front-end processing module, which is connected to the analog-to-digital conversion module and is used to filter the analog signal before inputting it into the analog-to-digital conversion module.
[0014] According to another aspect of the present invention, an ADC sampling method is provided, performed by the ADC sampling device, the method comprising:
[0015] The comparison module outputs a second trigger signal based on the first trigger signal and the trigger threshold.
[0016] The buffer module copies and outputs N channels of the second trigger signal according to the second trigger signal;
[0017] The clock module outputs N clock signals;
[0018] The data acquisition module acquires the third trigger signal based on the clock signal and converts it to output the fourth trigger signal;
[0019] The analog-to-digital converter module converts the received analog signal into a digital signal;
[0020] The data reconstruction module reconstructs the digital signal according to the fourth trigger signal.
[0021] Optionally, the trigger signal acquisition circuit includes a control chip, and before the data acquisition module acquires the third trigger signal according to the clock signal and converts it to output the fourth trigger signal, it further includes: the control chip calibrates the delay of the N second trigger signals to be the same according to the N clock signals.
[0022] Optionally, after the control chip calibrates the delays of the N second trigger signals to be the same according to the N clock signals, the method further includes: the control chip performs delay control on the N second trigger signals and outputs N third trigger signals, so that when the number of third trigger signals is greater than two, the time difference between two adjacent third trigger signals in the N third trigger signals is equal.
[0023] Optionally, the data acquisition module acquires and converts the third trigger signal according to the clock signal and outputs the fourth trigger signal, including: performing serial-to-parallel conversion on the data of N channels of the third trigger signal.
[0024] Optionally, the serial-to-parallel conversion of the data of the N third trigger signals includes: concatenating the data of the N third trigger signals; and extracting the concatenated data to obtain the fourth trigger signal.
[0025] The technical solution of this invention provides a trigger signal acquisition circuit, including a comparison module, a buffer module, a data acquisition module, and a clock module. The clock module outputs N clock signals. The comparison module outputs a second trigger signal based on a first trigger signal and a trigger threshold. The buffer module copies and outputs N second trigger signals based on the second trigger signal. The data acquisition module acquires and converts a third trigger signal based on the clock signals, outputting a fourth trigger signal. The number of third trigger signals is N. The clock module outputs N clock signals with the same phase and frequency. When the number of third trigger signals is greater than two, the time difference between adjacent times of the N third trigger signals is equal. The data acquisition module acquires the third trigger signals sequentially at equal time intervals based on the N clock signals. Compared to sampling based on a single clock signal, sampling based on N clock signals increases the sampling point density and improves the accuracy of trigger signal acquisition. This solves the problem of low trigger signal acquisition accuracy in the prior art, which cannot meet the requirements of high-precision trigger acquisition.
[0026] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1 This is a schematic diagram of a trigger signal acquisition circuit provided in an embodiment of the present invention;
[0029] Figure 2 This is a circuit diagram of the data acquisition module provided in an embodiment of the present invention;
[0030] Figure 3 This is a schematic diagram of the structure of an ADC sampling device provided in an embodiment of the present invention;
[0031] Figure 4 This is a flowchart of an ADC sampling method provided in an embodiment of the present invention;
[0032] Figure 5 This is a flowchart of another ADC sampling method provided in an embodiment of the present invention. Detailed Implementation
[0033] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0034] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0035] This invention provides a trigger signal acquisition circuit. Figure 1 This is a schematic diagram of a trigger signal acquisition circuit provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the trigger signal acquisition circuit 100 includes a comparison module 110, a buffer module 120, a data acquisition module 130, and a clock module 140. The clock module 140 outputs N clock signals S, where the N clock signals S have the same frequency and phase, and N is greater than or equal to 2. The comparison module 110 receives a first trigger signal a1 and a trigger threshold c, and outputs a second trigger signal a2 based on the first trigger signal a1 and the trigger threshold c. The buffer module 120 is connected to the comparison module 110 and is used to copy and output N second trigger signals a2 based on the second trigger signal a2. The data acquisition module 130 is connected to the buffer module 120 and the clock module 140 and is used to acquire and convert a third trigger signal a3 based on the clock signal S, and output a fourth trigger signal a4. The number of third trigger signals a3 is equal to the number of clock signals, and when the number of third trigger signals is greater than two, the time difference between two adjacent third trigger signals in the N third trigger signals a3 is equal.
[0036] In this embodiment, the trigger signal acquisition circuit 100 is the circuit that acquires the trigger signal. It is a key component that significantly affects the ADC sampling effect. Working in conjunction with ADC sampling, it can accurately acquire analog signals that meet the requirements. The comparison module 110 is a module that quickly compares the input signal with a reference value. For example, in the field of high-precision triggering, the comparison module 110 uses a high-speed comparator, with a processing speed typically reaching the nanosecond level, suitable for high-speed signal processing applications. The buffer module 120 is a module that buffers and copies the input signal. For example, the buffer module 120 includes a buffer that copies the second trigger signal based on the input second trigger signal to obtain N second trigger signals. The data acquisition module 130 is a module that acquires the third trigger signal based on the clock signal output by the clock module 140. The number of clock signals is the same as the number of third trigger signals. For example, the data acquisition module 130 can be set in the controller, and the third trigger signal is the signal obtained by the controller after delaying the second trigger signal. The clock module 140 is a module that provides a time reference, ensuring that the various parts of the system can execute in a predetermined time sequence. The N clock signals output by the clock module 140 have the same phase and frequency.
[0037] In this embodiment, the comparison module 110 outputs a second trigger signal after comparing the input first trigger signal with the trigger threshold. For example, the first trigger signal is a square wave signal. When the first trigger signal is less than the trigger threshold, the comparison module 110 outputs a low-level signal; when the first trigger signal is higher than the trigger threshold, the comparison module 110 outputs a high-level signal. The buffer module 120 copies the second trigger signal and outputs N channels of second trigger signals. The data acquisition module 130 acquires the third trigger signal sequentially at equal time intervals based on the N clock signals, and performs data conversion processing on the acquired data. For example, the acquired third trigger signal is converted from serial to parallel to obtain a fourth trigger signal.
[0038] This invention provides a trigger signal acquisition circuit, including a comparison module, a buffer module, a data acquisition module, and a clock module. The clock module outputs N clock signals. The comparison module outputs a second trigger signal based on a first trigger signal and a trigger threshold. The buffer module copies and outputs N second trigger signals based on the second trigger signal. The number of third trigger signals is equal to the number of clock signals. The data acquisition module acquires and converts the third trigger signals based on the clock signals, outputting a fourth trigger signal. The clock module outputs N clock signals with the same phase and frequency. When the number of third trigger signals is greater than two, the time difference between adjacent times of the N third trigger signals is equal. The data acquisition module acquires the third trigger signals sequentially at equal time intervals based on the N clock signals. Compared to sampling based on a single clock signal, sampling based on N clock signals increases the sampling point density and improves the accuracy of trigger signal acquisition. This solves the problem of low trigger signal acquisition accuracy in the prior art, which cannot meet the requirements of high-precision trigger acquisition.
[0039] Figure 2 This is a circuit diagram of the data acquisition module provided in an embodiment of the present invention, such as... Figure 2 As shown, the data acquisition module 130 includes N serial-to-parallel conversion units. These N units are connected to the buffer module and the clock module. The N units are used to convert N third trigger signals into serial signals based on N clock signals. Each clock signal and third trigger signal corresponds one-to-one with a serial-to-parallel conversion unit, and each unit acquires one third trigger signal based on one clock signal.
[0040] In this embodiment of the invention, the serial-to-parallel conversion unit is a unit that converts serial data into parallel data. It enables high-speed acquisition of trigger signals and conversion into low-frequency, multi-bit-width signals. For example, the serial-to-parallel conversion unit internally includes circuit structures such as shift registers. Serial data sequentially enters the shift register, and according to a clock signal, all bits of data stored in the shift register are simultaneously output at specific times, completing the conversion to parallel data. In many devices requiring high-speed data processing, parallel data transmission is often used to improve data transmission efficiency when transferring data between the processor and components such as memory. The serial-to-parallel conversion unit converts serial data into a parallel data format, facilitating subsequent rapid data computation, storage, and other operations.
[0041] Continue to refer to Figure 2The trigger signal acquisition circuit also includes a control chip 210, a data acquisition module 130 and a clock module 140, which are located inside the control chip 210. The control chip 210 is connected to the buffer module 120. The control chip 210 is used to calibrate N second trigger signals according to N clock signals so that the delay of the N second trigger signals is the same. The control chip is also used to perform delay control on the N second trigger signals and output N third trigger signals so that when the number of third trigger signals is greater than two, the time difference between two adjacent third trigger signals in the N third trigger signals is equal, wherein the product of the time difference and N is equal to the period of the clock signal.
[0042] In this embodiment of the invention, the control chip 210 plays a crucial role in ADC sampling. The control chip 210 has functions such as ADC sampling timing control, data processing and buffering, and implementation of complex logic and algorithms. For example, the control chip 210 uses an FPGA and has built-in delay functionality. First, the control chip 210 detects N second trigger signals. If the delays at which the N second trigger signals arrive at the control chip are different, the control chip 210 adjusts the internal delay to make the delays of the N second trigger signals the same, thus eliminating the inconsistencies in delay caused by different external signal input circuits and circuit board wiring. Based on the above embodiment, the control chip controls the delay of each second trigger signal to be different, resulting in N third trigger signals. When the number of third trigger signals is greater than two, the time difference between two adjacent third trigger signals is equal. The N third trigger signals are transmitted sequentially to the input terminal of the data acquisition module at equal time intervals. For example, if the number of third trigger signals is N, and the N third trigger signals are delayed by the same time t, then t*N is equal to the period of the clock signal, which allows the acquisition of N third trigger signals within one clock cycle, thereby increasing the sampling frequency and improving the accuracy of capturing trigger signals.
[0043] In this embodiment of the invention, the trigger signal acquisition circuit 100 compares the first trigger signal and the trigger threshold using the comparison module 110 and outputs a second trigger signal. The buffer module 120 copies the second trigger signal and outputs N channels of second trigger signals. The data acquisition module 130 acquires N channels of third trigger signals sequentially at equal time intervals based on the N clock signals, and converts the acquired N channels of third trigger signals to obtain a fourth trigger signal. Since the N clock signals output by the clock module 140 are in phase and frequency, the data acquisition module samples based on the N clock signals, increasing the sampling point density and improving the accuracy of capturing the trigger signal, thus providing a basis for reordering the digital signal after the analog signal is converted by the ADC.
[0044] This invention also provides an ADC sampling device. Figure 3This is a schematic diagram of the structure of an ADC sampling device provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the ADC sampling device in this embodiment includes the trigger signal acquisition circuit 100 in the above embodiment, as well as the analog-to-digital conversion module 310 and the data reconstruction module 320. The analog-to-digital conversion module 310 is used to convert the input analog signal A into a digital signal D. The data reconstruction module 320 is connected to the trigger signal acquisition circuit 100 and the analog-to-digital conversion module 310. The data reconstruction module 320 is used to reconstruct the digital signal according to the fourth trigger signal output by the trigger signal acquisition circuit 100.
[0045] In this embodiment of the invention, the analog-to-digital converter (ADC) module 310 converts analog signals into digital signals. In the field of high-precision trigger acquisition, the ADC module 310 includes a high-speed ADC, which has the advantages of fast conversion rate and high sampling frequency, and can process high-speed signals, making it suitable for application scenarios with extremely high requirements for signal digitization speed. The data reconstruction module 320 is a module that rearranges and integrates the sampled data output by the ADC module 310 according to specific rules based on the trigger signal output by the trigger signal acquisition circuit 100. The data reconstruction module 320 is located inside the control chip 210. By reconstructing the digital signals, the data reconstruction module 320 makes the data organization form more in line with the requirements of subsequent processing (such as digital signal processing, storage, transmission, etc.).
[0046] Continue to refer to Figure 3 The ADC sampling device 100 also includes a front-end processing module 330, which is connected to the analog-to-digital conversion module 310. The front-end processing module 330 filters the analog signal A before inputting it to the analog-to-digital conversion module 310. The front-end processing module 330 is a module that preprocesses the input analog signal. Its main purpose is to shape the original analog signal into a form more suitable for accurate and efficient sampling and conversion by the ADC. For example, the preprocessing of the analog signal by the front-end processing module 330 includes signal amplification and signal filtering.
[0047] This invention also provides an ADC sampling method, executed by the ADC sampling device in any of the above embodiments. Figure 4 This is a flowchart of an ADC sampling method provided in an embodiment of the present invention, such as... Figure 4 As shown, the ADC sampling methods include:
[0048] S10. The comparison module outputs a second trigger signal based on the first trigger signal and the trigger threshold.
[0049] S20, The buffer module copies and outputs N channels of the second trigger signal according to the second trigger signal.
[0050] S30, the clock module outputs N clock signals.
[0051] S40. The data acquisition module acquires the third trigger signal based on the clock signal and converts it to output the fourth trigger signal.
[0052] The S50 analog-to-digital converter module converts the input analog signal into a digital signal.
[0053] S60, The data reconstruction module reconstructs the digital signal according to the fourth trigger signal.
[0054] In this embodiment of the invention, a comparison module compares the first trigger signal with a trigger threshold and outputs a second trigger signal. This process is fast and accurate, ensuring the reliability and efficiency of data processing. A buffer module copies the second trigger signal and outputs N channels of second trigger signals. A data acquisition module, based on N clock signals, sequentially acquires N channels of third trigger signals at equal time intervals, and then processes the acquired data to obtain a fourth trigger signal. Since the clock module outputs N clock signals with the same frequency and phase, the data acquisition module samples based on these N clock signals, increasing the sampling point density and improving the accuracy of trigger signal capture. A data reconstruction module, based on the fourth trigger signal, rearranges and integrates the digital signal according to specific rules, making the data organization more suitable for subsequent processing requirements.
[0055] Referring to the above embodiments, the trigger signal acquisition circuit includes a control chip. Figure 5 This is a flowchart of another ADC sampling method provided in an embodiment of the present invention, such as... Figure 5 As shown, before the data acquisition module acquires the third trigger signal based on the clock signal and converts it to output the fourth trigger signal, it also includes:
[0056] S11. The control chip calibrates the delay of the N second trigger signals according to the N clock signals.
[0057] In this embodiment of the invention, the N clock signals are in phase and frequency. The control chip detects the N second trigger signals based on the clock signals in phase and frequency. If the delays of the N second trigger signals arriving at the control chip are different, the control chip adjusts the internal delay to make the delays of the N second trigger signals the same, which can eliminate the delay inconsistencies caused by different external signal input circuits and circuit board wiring.
[0058] After the control chip calibrates the delays of the N second trigger signals to be the same based on the N clock signals, it also includes:
[0059] S12. The control chip performs delay control on N second trigger signals and outputs N third trigger signals so that when the number of third trigger signals is greater than two, the time difference between two adjacent third trigger signals in the N third trigger signals is equal.
[0060] Based on the above embodiment, the control chip controls the delay time of each third trigger signal to be different, so that when the number of third trigger signals is greater than two, the time difference between two adjacent third trigger signals is equal. The N third trigger signals are transmitted sequentially to the input of the data acquisition module at equal time intervals. This enables the acquisition of N third trigger signals within one clock cycle, improving the sampling frequency.
[0061] Based on the above embodiments, the data acquisition module acquires and converts the third trigger signal according to the clock signal and outputs the fourth trigger signal, including: performing serial-to-parallel conversion on the data of N third trigger signals. Specifically, performing serial-to-parallel conversion on the data of N third trigger signals includes: concatenating the N parallel data; and extracting the concatenated data to obtain the fourth trigger signal. For example, in devices requiring high-speed data processing, when transmitting data between the processor and components such as memory, parallel data transmission is often used to improve data transmission efficiency. This involves converting serial data into a parallel data format to facilitate subsequent rapid data processing, storage, and other operations.
[0062] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.
[0063] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.
Claims
1. A trigger signal acquisition circuit, characterized in that, It includes a comparison module, a buffer module, a data acquisition module, and a clock module; The clock module is used to output N clock signals, wherein the N clock signals have the same frequency and phase, and N is greater than or equal to 2; The comparison module receives a first trigger signal and a trigger threshold, and the comparison module is used to output a second trigger signal based on the first trigger signal and the trigger threshold. The buffer module is connected to the comparison module, and the buffer module is used to copy and output N channels of the second trigger signal according to the second trigger signal; The data acquisition module is connected to the buffer module and the clock module. The data acquisition module is used to acquire the third trigger signal according to the clock signal and convert it to output the fourth trigger signal. The number of third trigger signals is N. When N is greater than 2, the time difference between two adjacent third trigger signals in the N third trigger signals is equal. The trigger signal acquisition circuit further includes a control chip. The data acquisition module and the clock module are disposed inside the control chip. The control chip is connected to the buffer module. The control chip is used to calibrate the N second trigger signals according to the N clock signals so that the delays of the N second trigger signals are the same. The control chip is also used to perform delay control on the N second trigger signals and output N third trigger signals so that when the number of third trigger signals is greater than two, the time difference between two adjacent third trigger signals in the N third trigger signals is equal, wherein the product of the time difference and N is equal to the period of the clock signal.
2. The trigger signal acquisition circuit according to claim 1, characterized in that, The data acquisition module includes N serial-to-parallel conversion units, which are connected to the buffer module and the clock module. The N serial-to-parallel conversion units are used to perform serial-to-parallel conversion on the N third trigger signals according to the N clock signals. The clock signals, the third trigger signals and the serial-to-parallel conversion units correspond one-to-one. One serial-to-parallel conversion unit performs serial-to-parallel conversion on one third trigger signal according to one clock signal.
3. An ADC sampling device, characterized in that, The system includes the trigger signal acquisition circuit, analog-to-digital conversion module, and data reconstruction module as described in any one of claims 1-2. The analog-to-digital conversion module is used to convert the input analog signal into a digital signal. The data reconstruction module is connected to the trigger signal acquisition circuit and the analog-to-digital conversion module. The data reconstruction module is used to reconstruct the digital signal according to the fourth trigger signal output by the trigger signal acquisition circuit.
4. The ADC sampling device according to claim 3, characterized in that, It also includes a front-end processing module, which is connected to the analog-to-digital conversion module. The front-end processing module is used to filter the analog signal and then input it to the analog-to-digital conversion module.
5. An ADC sampling method, characterized in that, Performed by the ADC sampling device of claim 3, the method includes: The comparison module outputs a second trigger signal based on the first trigger signal and the trigger threshold. The buffer module copies and outputs N channels of the second trigger signal according to the second trigger signal; The clock module outputs N clock signals; The data acquisition module acquires the third trigger signal based on the clock signal and converts it to output the fourth trigger signal; The analog-to-digital converter module converts the received analog signal into a digital signal; The data reconstruction module reconstructs the digital signal according to the fourth trigger signal.
6. The ADC sampling method according to claim 5, characterized in that, The trigger signal acquisition circuit includes a control chip, and before the data acquisition module acquires the third trigger signal according to the clock signal and converts it to output the fourth trigger signal, it further includes: The control chip calibrates the delay of the N second trigger signals to be the same according to the N clock signals.
7. The ADC sampling method according to claim 6, characterized in that, After the control chip calibrates the delays of the N second trigger signals to be the same according to the N clock signals, it further includes: The control chip performs delay control on N channels of the second trigger signal and outputs N channels of the third trigger signal, so that when the number of the third trigger signal is greater than two, the time difference between two adjacent third trigger signals in the N channels of the third trigger signal is equal.
8. The ADC sampling method according to claim 5, characterized in that, The data acquisition module acquires the third trigger signal based on the clock signal and converts and outputs the fourth trigger signal, including: Perform serial-to-parallel conversion on the data of the N channels of the third trigger signal.
9. The ADC sampling method according to claim 8, characterized in that, The serial-to-parallel conversion of the data from the N channels of the third trigger signals includes: Data splicing is performed on the N channels of the third trigger signal; The spliced data is extracted to obtain the fourth trigger signal.