Photovoltaic cells and their manufacturing methods, photovoltaic modules

Abstract

This disclosure relates to the photovoltaic field, providing a photovoltaic cell and its manufacturing method, as well as a photovoltaic module. The manufacturing method of the photovoltaic cell includes: placing a substrate in a support structure, at least one surface of the substrate including a plurality of mutually spaced first regions, the first regions being located at the edges of the surface; forming a semiconductor layer on the surface; performing a diffusion process on the semiconductor layer to convert the semiconductor layer into a doped layer, and forming a protective layer on the side of the doped layer away from the substrate; wherein, in the step of forming the semiconductor layer, nitrogen gas and silane are introduced into a reaction chamber used to prepare the semiconductor layer, and the ratio of the nitrogen gas flow rate to the silane gas flow rate is controlled to be 0.7~1; and / or, the diffusion process includes sequentially performed oxygen-free annealing and oxygen-containing annealing, the ratio of the oxygen-containing annealing duration to the oxygen-free annealing duration being greater than 1. This disclosure at least helps to avoid excessive erosion of the doped layer located on the first region.

Description

Technical Field

[0001] This disclosure relates to the photovoltaic field, and in particular to a photovoltaic cell and its manufacturing method, and a photovoltaic module. Background Technology

[0002] With the rapid development of solar photovoltaic technology, photovoltaic cells are becoming increasingly widely used as a sustainable and clean energy source. A photovoltaic cell is a device that uses the photovoltaic principle to generate charge carriers to convert solar energy into electrical energy. Electrodes are typically used in photovoltaic cells to extract these charge carriers, thus efficiently utilizing the electrical energy. Currently, the mainstream types of photovoltaic cells include BC cells (Back Contact), TOPCON (Tunnel Oxide Passivated Contact), PERC cells (Passivated emitter and real cell), and heterojunction cells (Heterojunction with Intrinsic Thin-film, abbreviated as HIT or HJT).

[0003] However, in the production process of photovoltaic cells, containers are typically used to hold semi-finished cells that have completed some processes, allowing them to circulate on the production line and be removed for subsequent processes. Therefore, whether the process of circulating the semi-finished cells on the production line and the containers holding them affect subsequent processes, and whether targeted improvements to the process flow are necessary, requires further research. Summary of the Invention

[0004] This disclosure provides a photovoltaic cell and its manufacturing method, as well as a photovoltaic module, which at least helps to avoid excessive erosion of the doped layer located on the first region.

[0005] This disclosure provides a method for manufacturing a photovoltaic cell, comprising: placing a substrate in a support structure, wherein at least one surface of the substrate includes a plurality of mutually spaced first regions, the first regions being located at the edges of the surface; forming a semiconductor layer on the surface; performing a diffusion process on the semiconductor layer to convert the semiconductor layer into a doped layer, and forming a protective layer on the side of the doped layer away from the substrate; wherein, in the step of forming the semiconductor layer, nitrogen and silane are introduced into a reaction chamber for preparing the semiconductor layer, and the ratio of the flow rate of nitrogen to the flow rate of silane is controlled to be 0.7 to 1; and / or, the diffusion process includes sequentially performed oxygen-free annealing and oxygen-enriched annealing, wherein the ratio of the duration of oxygen-enriched annealing to the duration of oxygen-free annealing is greater than 1.

[0006] Optionally, the surface includes a third region and a fourth region alternately arranged along a second direction, with a portion of the first regions located in the third region and a portion of the first regions located in the fourth region; the method of manufacturing the photovoltaic cell further includes: removing the protective layer located on one of the third region and the fourth region; using the protective layer located on the other of the third region and the fourth region as a mask, removing at least the doped layer not covered by the mask.

[0007] Optionally, the steps of forming the semiconductor layer and performing the diffusion process include: forming a first semiconductor layer on the surface, performing a first diffusion process on the first semiconductor layer to transform the first semiconductor layer into a first doped layer, and forming a first protective layer on the side of the first doped layer away from the substrate; forming a second semiconductor layer on the surface, performing a second diffusion process on the second semiconductor layer to transform the second semiconductor layer into a second doped layer, and forming a second protective layer on the side of the second doped layer away from the substrate; wherein, after forming the first protective layer and before forming the second semiconductor layer, the method for manufacturing the photovoltaic cell further includes: removing... The method of manufacturing a photovoltaic cell further includes: removing the first protective layer located on one of the third and fourth regions; using the first protective layer located on the other of the third and fourth regions as a first mask to remove at least the first doped layer not covered by the first mask; forming a second semiconductor layer on the surface formed by the remaining first doped layer and the substrate; and after forming the second protective layer, removing the second protective layer located on the other of the third and fourth regions; using the second protective layer located on one of the third and fourth regions as a second mask to remove at least the second doped layer not covered by the second mask.

[0008] Optionally, the protective layer and the doped layer are doped with the same type of doping element. The protective layer includes a first layer and a second layer stacked along a first direction. The doping concentration of the doping element in the first layer is less than that in the second layer, and the density of the first layer is higher than that of the second layer. The first direction is the thickness direction of the substrate.

[0009] Optionally, before forming the semiconductor layer, the method further includes: forming an oxide layer between the substrate and the semiconductor layer, wherein the thickness of the oxide layer located in the first region is controlled to be less than 1.7 nm in a first direction, wherein the first direction is the thickness direction of the substrate.

[0010] Optionally, before forming the semiconductor layer, the method further includes: forming an oxide layer between the substrate and the semiconductor layer; the step of forming the oxide layer includes at least: performing a first polishing treatment on the substrate, wherein at least during the first polishing treatment, the moisture content of the environment in which the substrate is located is controlled to be 6 g / kg to 12 g / kg, so as to form a first oxide layer on the surface of the substrate that has undergone the first polishing treatment.

[0011] Optionally, before forming the semiconductor layer, the process further includes: forming an oxide layer between the substrate and the semiconductor layer; the step of forming the oxide layer and the semiconductor layer includes at least: employing a first deposition process including a first stage and a second stage, forming a first dielectric layer in the first stage, and forming a first semiconductor layer on the side of the first dielectric layer away from the substrate in the second stage to obtain a first semi-finished product; the diffusion process includes at least: performing a first diffusion process on the first semi-finished product to convert the first semiconductor layer into a first doped layer, and forming a first protective layer on the side of the first doped layer away from the substrate; and / or, the step of forming the oxide layer and the semiconductor layer includes at least: The method includes: employing a second deposition process comprising a third stage and a fourth stage, wherein a second dielectric layer is formed in the third stage, and a second semiconductor layer is formed on the side of the second dielectric layer away from the substrate in the fourth stage to obtain a second semi-finished product; the diffusion process includes at least: performing a second diffusion process on the second semi-finished product to convert the second semiconductor layer into a second doped layer, and forming a second protective layer on the side of the second doped layer away from the substrate; wherein the oxide layer includes the first dielectric layer and / or the second dielectric layer, the doped layer includes the first doped layer and / or the second doped layer, and the first doped layer and the second doped layer are doped with different types of doping elements.

[0012] Optionally, in the steps of performing the first deposition process, the first diffusion process, the second deposition process, and / or the second diffusion process, the idle time of the support structure is controlled to be less than or equal to 120 minutes; and / or, in the steps of performing the first deposition process, the first diffusion process, the second deposition process, and / or the second diffusion process, if the idle time of the support structure is greater than 120 minutes, the support structure is baked to reduce the amount of water adsorbed by the support structure during the idle period.

[0013] Optionally, the semi-finished photovoltaic cells in the manufacturing process are regarded as semi-finished products to be picked up. During the process of transporting the semi-finished products to be picked up or transporting the supporting structure with a paddle, the idle time of the paddle is controlled to be less than or equal to 30 minutes; and / or, if the idle time of the paddle is greater than 30 minutes, the paddle is subjected to a baking treatment to reduce the amount of water absorbed by the paddle during the idle process.

[0014] Optionally, the surface includes a third region and a fourth region alternately arranged along a second direction, a portion of the first region being located in the third region, a portion of the first region being located in the fourth region, and the second direction intersecting with the first direction; the oxide layer includes a first dielectric layer and a second dielectric layer, and the doped layer includes a first doped layer and a second doped layer; after forming the first doped layer and before forming the second dielectric layer, the method for manufacturing the photovoltaic cell further includes: patterning the first dielectric layer and the first doped layer, removing the first dielectric layer and the first doped layer located in the third region or the fourth region to expose the substrate, and at least in the step of performing the patterning process, controlling the moisture content of the environment in which the substrate is located to be 6 g / kg to 12 g / kg, so as to form a second oxide layer on the surface of the substrate that has undergone the patterning process, and then performing the second deposition process.

[0015] Optionally, before performing the first deposition process, the step of forming the oxide layer further includes: performing a first polishing treatment on the substrate, and forming a first oxide layer on the surface of the substrate that has undergone the first polishing treatment; wherein, along the first direction, the thickness of the first oxide layer is less than the thickness of the second oxide layer; and / or, the total thickness of the first oxide layer and the first dielectric layer is less than the total thickness of the second oxide layer and the second dielectric layer.

[0016] Optionally, the surface includes a third region and a fourth region alternately arranged along a second direction, a portion of the first region being located in the third region, a portion of the first region being located in the fourth region, and the second direction intersecting with the first direction; the oxide layer includes a first dielectric layer and a second dielectric layer, and the doped layer includes a first doped layer and a second doped layer; after forming the first doped layer and before forming the second dielectric layer, the method for manufacturing the photovoltaic cell further includes: patterning the first dielectric layer and the first doped layer, removing the first dielectric layer and the first doped layer located in the third region or the fourth region, and controlling the time interval from the end of the patterning process to the start of the second deposition process to be less than or equal to 60 minutes.

[0017] Optionally, in the first diffusion process, the doping element is a P-type doping element; in the second diffusion process, the doping element is an N-type doping element; wherein the deposition temperature for forming the first semiconductor layer is lower than the deposition temperature for forming the second semiconductor layer; and / or, the crystallinity of the first semiconductor layer is lower than the crystallinity of the second semiconductor layer; and / or, along the first direction, the thickness of the first semiconductor layer is greater than the thickness of the second semiconductor layer.

[0018] Optionally, before performing the first deposition process or before performing the second deposition process, the step of forming the oxide layer further includes: performing a first polishing treatment on the substrate, and forming a first oxide layer on the surface of the substrate that has undergone the first polishing treatment; wherein the time interval between the end of the first polishing treatment and the start of the first deposition process is controlled to be less than or equal to 60 minutes, or the time interval between the end of the first polishing treatment and the start of the second deposition process is controlled to be less than or equal to 60 minutes.

[0019] Optionally, after forming the first semiconductor layer and before performing the first diffusion process, the method for manufacturing the photovoltaic cell further includes: performing at least one third deposition process including a fifth stage and a sixth stage, forming a first dielectric film in the fifth stage, forming a first semiconductor film on the side of the first dielectric film away from the substrate in the sixth stage, controlling the time for forming the first dielectric film to be less than the time for forming the first dielectric layer, and the time for forming the first dielectric film to be less than or equal to 500 s; and / or, after forming the second semiconductor layer and before performing the second diffusion process, the method for manufacturing the photovoltaic cell further includes: performing at least one fourth deposition process including a seventh stage and an eighth stage, forming a second dielectric film in the seventh stage, forming a second semiconductor film on the side of the second dielectric film away from the substrate in the eighth stage, controlling the time for forming the second dielectric film to be less than the time for forming the second dielectric layer, and the time for forming the second dielectric film to be less than or equal to 500 s.

[0020] Optionally, in the first diffusion process, the dopant element is a P-type dopant element, and the P-type dopant element is controlled to diffuse into the substrate, with the depth of the P-type dopant element in the substrate being 15nm~45nm; and / or, in the second diffusion process, the dopant element is an N-type dopant element, and the N-type dopant element is controlled to diffuse into the substrate, with the depth of the N-type dopant element in the substrate being 55nm~165nm.

[0021] Optionally, the oxide layer includes a first dielectric layer and a second dielectric layer, and the doped layer includes a first doped layer and a second doped layer; the first diffusion process includes a first oxygen-free annealing and a first oxygen-enriched annealing connected in sequence, and the second diffusion process includes a second oxygen-free annealing and a second oxygen-enriched annealing connected in sequence; wherein, the process temperature of the first oxygen-free annealing is greater than or equal to the process temperature of the second oxygen-free annealing; and / or, the process duration of the first oxygen-free annealing is less than or equal to the process duration of the second oxygen-free annealing; and / or, the process temperature of the first oxygen-enriched annealing is greater than or equal to the process temperature of the second oxygen-enriched annealing.

[0022] Optionally, the area on the surface other than the first region is the second region; before forming the semiconductor layer, the method further includes: forming an oxide layer between the substrate and the semiconductor layer, and controlling the difference between the thickness of the oxide layer located in the first region and the thickness of the oxide layer located in the second region to be less than or equal to 0.35 nm.

[0023] This disclosure also provides a photovoltaic cell formed by the manufacturing method of a photovoltaic cell as described in any of the preceding claims.

[0024] Optionally, the photovoltaic cell may further include: an oxide layer located between the substrate and the doped layer, wherein the thickness of the oxide layer located in the first region is less than 1.7 nm in a first direction, wherein the first direction is the thickness direction of the substrate.

[0025] Optionally, the photovoltaic cell may further include: an oxide layer located between the substrate and the doped layer; wherein the oxide layer includes a first oxide layer and a first dielectric layer stacked along a first direction, and the doped layer includes a first doped layer located on the side of the first dielectric layer away from the substrate; and / or, the oxide layer includes a second oxide layer and a second dielectric layer stacked along the first direction, and the doped layer includes a second doped layer located on the side of the second dielectric layer away from the substrate.

[0026] Optionally, the surface includes a third region and a fourth region alternately arranged along a second direction, with a portion of the first region located in the third region and a portion of the first region located in the fourth region; the oxide layer includes a first oxide layer and a first dielectric layer located on one of the third region and the fourth region, and a second oxide layer and a second dielectric layer located on the other of the third region and the fourth region; the doped layer includes a first doped layer located on the side of the first dielectric layer away from the substrate, and a second doped layer located on the side of the second dielectric layer away from the substrate, wherein the first doped layer and the second doped layer are doped with different types of doping elements.

[0027] Optionally, the first doped layer is doped with a P-type dopant element, and the second doped layer is doped with an N-type dopant element, wherein the thickness of the first doped layer is greater than the thickness of the second doped layer along the first direction.

[0028] Optionally, the first doped layer is doped with a p-type dopant, and the doping concentration of the p-type dopant in the first doped layer is 4 × 10⁻⁶. 19 atom / cm 3 ~7×10 19 atom / cm 3 ; and / or, the second doped layer is doped with an N-type dopant element, the doping concentration of the N-type dopant element in the second doped layer being 3 × 10⁻⁶. 20 atom / cm 3 ~7×10 20 atom / cm 3 .

[0029] This disclosure also provides a photovoltaic module, comprising: a battery string, which is formed by connecting a plurality of photovoltaic cells manufactured by any of the above methods, or by connecting a plurality of photovoltaic cells as described above; an encapsulating film for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulating film opposite to the battery string.

[0030] The technical solution provided in this disclosure has at least the following advantages: On the one hand, in the step of forming the semiconductor layer, the ratio of nitrogen gas flow rate to silane gas flow rate can be controlled to be 0.7~1. Increasing the nitrogen gas flow rate enhances the dilution effect of nitrogen on silane, preventing excessive collisions of gaseous silane to form clusters or particles, thereby increasing the density of the prepared semiconductor layer. This, in turn, can improve the density of the doped layer formed based on the semiconductor layer transformation, avoiding excessive erosion of the doped layer during subsequent patterning processes, such as avoiding excessive erosion of the doped layer located in the first region, thus ensuring good film quality of the final retained doped layer. On the other hand, designing the ratio of oxygen annealing time to oxygen-free annealing time to be greater than 1 is beneficial for improving the density of the portion of the protective layer near the substrate through longer oxygen annealing time. This enhances the protective effect of the protective layer on the doped layer during subsequent patterning processes, preventing excessive erosion of the doped layer that needs to be retained, such as avoiding excessive erosion of the doped layer located in the first region. Thus, when performing EL or PL tests on photovoltaic cells, controlling the density of the protective layer and / or the semiconductor layer helps to avoid the problem of blackening in the first region caused by excessive erosion of the doped layer that needs to be retained, thereby improving the yield of photovoltaic cells. Attached Figure Description

[0031] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0032] Figure 1 A process flow diagram of a method for manufacturing a photovoltaic cell according to an embodiment of this disclosure; Figure 2 This is a partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure, in which a substrate is placed in a supporting structure. Figure 3 This is a partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after the formation of a semiconductor layer; Figure 4 This is a partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method according to an embodiment of the present disclosure after a diffusion process. Figure 5 This is a top view schematic diagram of a substrate used in a method for manufacturing a photovoltaic cell according to an embodiment of the present disclosure; Figure 6 This is a partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after the formation of the first semiconductor layer; Figure 7 This is a partial cross-sectional view of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after the formation of the first protective layer; Figure 8 This is a partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after at least the first doped layer has been patterned. Figure 9 This is a first partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after the formation of the second semiconductor layer; Figure 10 This is a first partial cross-sectional view of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after the formation of the second protective layer; Figure 11 This is a partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after at least the second doped layer has been patterned. Figure 12 This is a second partial cross-sectional view of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after the formation of the second semiconductor layer; Figure 13 This is a second partial cross-sectional view of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after the formation of the second protective layer; Figure 14 This is a partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after the formation of a first semiconductor film; Figure 15 This is a partial cross-sectional schematic diagram of the photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after the formation of the second semiconductor film; Figure 16 A partial three-dimensional schematic diagram of a cell string in a photovoltaic module provided in yet another embodiment of this disclosure; Figure 17 This is a partial cross-sectional schematic diagram of a photovoltaic module provided in yet another embodiment of the present disclosure.

[0033] Explanation of reference numerals in the attached figures: 100. Substrate; 10. Surface; 110. First region; 120. Second region; 130. Third region; 140. Fourth region; 101. Supporting structure; 102. Oxide layer; 112. First oxide layer; 122. Second oxide layer; 103. Doped layer; 113. First doped layer; 123. Second doped layer; 114. First dielectric layer; 124. Second dielectric layer; 134. First dielectric film; 144. Second dielectric film; 105. Semiconductor Body layer; 115, First semiconductor layer; 125, Second semiconductor layer; 135, First semiconductor film; 145, Second semiconductor film; 106, Protective layer; 1061, First layer; 1062, Second layer; 116, First protective layer; 1161, First part; 1162, Second part; 126, Second protective layer; 1261, Third part; 1262, Fourth part; 40, Photovoltaic cell; 41, Encapsulating film; 42, Cover plate; 43, Solder ribbon. Detailed Implementation

[0034] As can be seen from the background technology, the production process of photovoltaic cells needs further improvement.

[0035] This disclosure provides a photovoltaic cell and its manufacturing method, as well as a photovoltaic module. In the manufacturing method of the photovoltaic cell, on the one hand, in the step of forming the semiconductor layer, the ratio of nitrogen gas flow rate to silane gas flow rate can be controlled to be 0.7~1. Increasing the nitrogen gas flow rate enhances the dilution effect of nitrogen on silane, preventing excessive collisions between gaseous silane to form clusters or particles, thereby increasing the density of the prepared semiconductor layer. This, in turn, can improve the density of the doped layer formed based on the semiconductor layer transformation, avoiding excessive erosion of the doped layer by subsequent patterning processing, such as avoiding excessive erosion of the doped layer located in the first region, to ensure good film quality of the final retained doped layer. On the other hand, designing the ratio of oxygen annealing time to oxygen-free annealing time to be greater than 1 is beneficial to improve the density of the portion of the protective layer near the substrate by using longer oxygen annealing time. This improves the protective effect of the protective layer on the doped layer in the subsequent patterning processing step, preventing excessive erosion of the doped layer that needs to be retained, such as avoiding excessive erosion of the doped layer located in the first region. Thus, when performing EL or PL tests on photovoltaic cells, controlling the density of the protective layer and / or the semiconductor layer helps to avoid the problem of blackening in the first region caused by excessive erosion of the doped layer that needs to be retained, thereby improving the yield of photovoltaic cells.

[0036] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0037] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0038] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. In addition, the character " / " in this document generally indicates that the related objects before and after it have an "or" relationship.

[0039] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0040] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0041] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0042] In the accompanying drawings corresponding to the embodiments of this application, the thickness and area of ​​the layers are enlarged for better understanding and ease of description. When describing a component (such as a layer, film, region, or substrate) on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be a third component between the two components. Conversely, when describing a component on the surface of another component, or when another component is formed or disposed on the surface of a component, it indicates that there is no third component between the two components. Furthermore, when describing a component as being "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0043] In the description of the embodiments of this application, when a component "includes" another component, other components are not excluded unless otherwise stated, and other components may be further included. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "on / located" on another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component may be present therein. Moreover, when a component such as a layer, film, region, or plate is "directly located" on another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it indicates that no other components are located therein.

[0044] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "component" is also intended to include the plural form unless the context clearly indicates otherwise. Components include layers, films, regions, or plates, etc.

[0045] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0046] This disclosure provides a method for manufacturing a photovoltaic cell according to an embodiment. The method for manufacturing a photovoltaic cell according to an embodiment of this disclosure will be described in detail below with reference to the accompanying drawings.

[0047] Reference Figures 1 to 4 , Figure 1 This is a process flow diagram of a method for manufacturing a photovoltaic cell according to an embodiment of the present disclosure. The method for manufacturing a photovoltaic cell may include at least the following steps: S1: Reference Figure 2 , Figure 2 This is a partial cross-sectional view of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure, in which a substrate is placed in a support structure. The substrate 100 is placed in the support structure 101, and at least one surface 10 of the substrate 100 includes a plurality of mutually spaced first regions 110, with the first regions 110 located at the edges of the surface 10.

[0048] S2: Reference Figure 3 , Figure 3 This is a partial cross-sectional view of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after the formation of a semiconductor layer, wherein a semiconductor layer 105 is formed on surface 10.

[0049] S3: Refer to Figure 3 and Figure 4 , Figure 4This is a partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method according to an embodiment of the present disclosure, after a diffusion process. The semiconductor layer 105 is subjected to a diffusion process to transform the semiconductor layer 105 into a doped layer 103, and a protective layer 106 is formed on the side of the doped layer 103 away from the substrate 100. In the step of forming the semiconductor layer 105, nitrogen and silane are introduced into the reaction chamber used to prepare the semiconductor layer 105, and the ratio of the gas flow rate of nitrogen to the gas flow rate of silane is controlled to be 0.7 to 1. And / or, the diffusion process includes sequential oxygen-free annealing and oxygen annealing, and the ratio of the duration of oxygen annealing to the duration of oxygen-free annealing is greater than 1.

[0050] It is worth noting that during other etching processes after the formation of the doped layer 103, such as the step of patterning the doped layer 103 in a local area, there is a phenomenon where the doped layer 103 that needs to be retained is over-etched. In particular, the doped layer 103 located near the first region 110 at the edge is susceptible to over-etching by the etching solution, which in turn affects the film quality of the doped layer 103 and the passivation effect on the substrate 100. Therefore, during the formation of the doped layer 103, the protective layer 106 formed thereafter can be used to prevent the doped layer 103 that needs to be retained from being over-etched, or the etching resistance of the doped layer 103 itself can be improved to prevent it from being over-etched.

[0051] Analysis revealed that, on the one hand, the etching resistance of the doped layer 103 itself can be improved by increasing the density of the doped layer 103. Since the doped layer 103 is formed based on the semiconductor layer 105 through a diffusion process, the density of the doped layer 103 is closely related to the density of the semiconductor layer 105. In the step of forming the semiconductor layer 105, if the flow rate of nitrogen gas is too small, for example, if the ratio of the flow rate of nitrogen gas to the flow rate of silane is less than 0.7, the dilution effect of nitrogen gas on silane is not good. This makes it easy for the gaseous silane to collide with each other at the outlet of the pipe that introduces silane into the reaction chamber, forming large clusters or particles of silane-hydrogen compounds. When these clusters or particles are deposited on the substrate 100, they appear as loose powder. After subsequent accumulation, they form a porous, loose semiconductor layer 105 with poor adhesion, which is easily corroded by acid or alkali solutions during subsequent patterning processing. On the other hand, the density of the protective layer 106 is related to the duration of oxygen-free annealing and oxygen annealing in the diffusion process. Increasing the duration of oxygen annealing can increase the oxygen content in the portion of the protective layer 106 near the substrate 100, thereby improving the density of the portion of the protective layer 106 near the substrate 100.

[0052] Based on this, on the one hand, in the step of forming the semiconductor layer 105, the ratio of nitrogen gas flow rate to silane gas flow rate can be controlled to be 0.7~1. Increasing the nitrogen gas flow rate can improve the dilution effect of nitrogen on silane, avoiding excessive collisions of gaseous silane to form clusters or particles, thereby increasing the density of the prepared semiconductor layer 105. This can further improve the density of the doped layer 103 formed subsequently based on the transformation of the semiconductor layer 105, and avoid excessive etching of the doped layer 103 by subsequent patterning processes, such as avoiding etching of the doped layer 103 located in the first region 110. Excessive etching of the doped layer 103 is avoided to ensure good film quality of the ultimately retained doped layer 103. On the other hand, the ratio of oxygen-containing annealing time to oxygen-free annealing time is designed to be greater than 1. This allows for a longer oxygen-containing annealing time to improve the density of the portion of the protective layer 106 near the substrate 100, thus enhancing the protective effect of the protective layer 106 on the doped layer 103 during subsequent patterning steps. This prevents excessive etching of the doped layer 103 that needs to be retained, such as avoiding excessive etching of the doped layer 103 located in the first region 110. It should be noted that the protective layer 106 on the retained doped layer 103 can be removed subsequently using acid.

[0053] Thus, when performing EL (Electroluminescence Testing) or PL (Photoluminescence Testing) tests on photovoltaic cells, controlling the density of the protective layer 106 and / or the semiconductor layer 105 helps to avoid the problem of the first region 110 turning black due to excessive erosion of the doped layer 103 that needs to be retained, thereby improving the yield of photovoltaic cells.

[0054] It should be noted that anaerobic annealing is performed in a gaseous atmosphere without oxygen, such as a nitrogen atmosphere; while aerobic annealing is performed in a gaseous atmosphere with oxygen, such as an oxygen atmosphere or a mixture of nitrogen and oxygen.

[0055] The following will describe in more detail a method for manufacturing a photovoltaic cell according to an embodiment of the present disclosure, with reference to the accompanying drawings.

[0056] In some embodiments, in conjunction with reference Figure 2 and Figure 5 , Figure 5 This is a top view of a substrate in a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure. The substrate 100 can be regarded as a semi-finished product in the manufacturing process of the photovoltaic cell. In order to place the substrate 100 stably in the support structure 101, at least one surface 10 of the substrate 100 will have a first region 110 in direct contact with the support structure 101 to ensure a good support effect on the substrate 100.

[0057] It should be noted that, Figure 5 The first area 110 of surface 10 is indicated by a dashed line.

[0058] In some cases, continue to combine references Figure 2 and Figure 5 The supporting structure on which the base 100 is placed can be a quartz boat. The base 100 is inserted into the slot of the quartz boat to fix the base 100. In one example, the edge of the quartz boat and the edge of the base 100 are directly opposite each other. The edge of the quartz boat is provided with teeth, which contact the first area 110 of the base 100 to fix or limit the base 100. The area of ​​the quartz boat other than the teeth does not directly contact the surface 10 of the base 100; in other words, there is a gap between them.

[0059] In other cases, the supporting structure for placing the substrate can also be a graphite boat or a basket. It should be noted that quartz boats are mainly used in high-temperature oxidation or high-temperature annealing processes, or as external containers for graphite boats; graphite boats are mainly used in diffusion or chemical vapor deposition processes, specifically, the substrate is inserted into the slot of the graphite boat; baskets are mainly used in wet processes such as texturing, cleaning, and etching that require acid or alkali tanks, specifically, the substrate is inserted into the slot of a specially designed basket, and the entire basket is immersed in or passes through the acid or alkali tank.

[0060] In some embodiments, in conjunction with reference Figure 7 and Figure 8 or in conjunction with references Figure 10 and Figure 11 Surface 10 may include a third region 130 and a fourth region 140 alternately arranged along the second direction Y, with a portion of the first region 110 located in the third region 130 and a portion of the first region 110 located in the fourth region 140. The method for manufacturing a photovoltaic cell may further include: removing a protective layer 106 located on one of the third region 130 and the fourth region 140; and using the protective layer 106 located on the other of the third region 130 and the fourth region 140 as a mask to remove at least the unmasked doped layer 103. It should be noted that further details will follow... Figure 7 , Figure 8 , Figure 10 and Figure 11 Please provide a detailed explanation.

[0061] Thus, by designing a diffusion process with an oxygen-containing annealing time to an oxygen-free annealing time greater than 1, the density of the protective layer 106, which serves as a mask, can be improved. This enhances the protective effect of the protective layer 106 on the doped layer 103, thereby ensuring the good film quality of the ultimately retained doped layer 103. It should be noted that the protective layer 106 located on the other of the third region 130 and the fourth region 140 can be removed subsequently using acid.

[0062] The steps for forming the protective layer 106 are described in detail below.

[0063] In some cases, the steps of forming the semiconductor layer 105 and performing the diffusion process may include: combining with a reference Figures 6 to 8 A first semiconductor layer 115 is formed on surface 10, and a first diffusion process is performed on the first semiconductor layer 115 to transform the first semiconductor layer 115 into a first doped layer 113, and a first protective layer 116 is formed on the side of the first doped layer 113 away from the substrate 100; in conjunction with reference Figures 8 to 11 A second semiconductor layer 125 is formed on the surface 10, and a second diffusion process is performed on the second semiconductor layer 125 to transform the second semiconductor layer 125 into a second doped layer 123, and a second protective layer 126 is formed on the side of the second doped layer 123 away from the substrate 100.

[0064] Among them, in conjunction with reference Figures 7 to 8 After forming the first protective layer 116 and before forming the second semiconductor layer 125, the method for manufacturing a photovoltaic cell may further include: removing the first protective layer 116 located on one of the third region 130 and the fourth region 140; using the first protective layer 116 located on the other of the third region 130 and the fourth region 140 as a first mask, removing at least the first doped layer 113 not covered by the first mask; in conjunction with reference to... Figures 8 to 9 The second semiconductor layer 125 is formed on the surface formed by the remaining first doped layer 113 and the substrate 100. In other words, the first protective layer 116 located on the other of the third region 130 and the fourth region 140 is used as a first mask to pattern at least the first doped layer 113.

[0065] Thus, the first diffusion process may include a first oxygen-free annealing and a first oxygen-enriched annealing connected in sequence, and the first protective layer 116 includes a first part 1161 and a second part 1162 stacked along the first direction X.

[0066] Based on this, the ratio of the first oxygen-enriched annealing time to the first oxygen-free annealing time is designed to be greater than 1. This is beneficial for forming a denser first part 1161 through the first oxygen-enriched annealing, thereby improving the protective effect of the first protective layer 116 on the first doped layer 113 during subsequent patterning processes, and preventing the retained first doped layer 113 from being excessively eroded. It should be noted that the first protective layer 116 located on the retained first doped layer 113 can be removed subsequently using acid.

[0067] In some examples, the material of the first part 1161 can be a silicon oxide layer containing a small amount of p-type dopant; the material of the second part 1162 can be a silicon oxide layer containing a large amount of p-type dopant, for example, a borosilicate glass layer. In subsequent patterning steps, the etching rate of the first part 1161 is lower than the etching rate of the second part 1162.

[0068] In some examples, prior to the first oxygen-free annealing, the first diffusion process may also include a first source stage to gradually diffuse the dopant element into the first semiconductor layer 115 and form the second part 1162; subsequently, the first oxygen-free annealing and the first oxygen annealing are used to further promote the diffusion of the dopant element in the first semiconductor layer 115 and the substrate 100 and form the first part 1161.

[0069] In one example, the steps of the first source-injection stage may include: controlling the temperature of the reaction chamber to 830℃~850℃, maintaining the ratio of oxygen gas flow rate to boron trichloride gas flow rate in the reaction chamber to 2.5~5, controlling the pressure of the reaction chamber to 100mbar~250mbar, and the processing time of the first source-injection stage to 800s~1400s.

[0070] In some examples, after the first aerobic annealing, the first diffusion process may also include a first cooling oxidation, for example, controlling the temperature of the reaction chamber to 750°C to 780°C and maintaining the processing time to 500s to 1000s.

[0071] Furthermore, in conjunction with references Figure 10 and Figure 11 After forming the second protective layer 126, the photovoltaic cell manufacturing method may further include: removing the second protective layer 126 located on the other of the third region 130 and the fourth region 140; using the second protective layer 126 located on one of the third region 130 and the fourth region 140 as a second mask, at least removing the second doped layer 123 that is not covered by the second mask. In other words, using the second protective layer 126 located on one of the third region 130 and the fourth region 140 as a second mask, at least the second doped layer 123 is patterned.

[0072] Thus, the second diffusion process may include a second oxygen-free annealing and a second oxygen-enriched annealing connected in sequence, and the second protective layer 126 includes a third part 1261 and a fourth part 1262 stacked along the first direction X.

[0073] Based on this, the ratio of the second oxygen-enriched annealing time to the second oxygen-free annealing time is designed to be greater than 1. This is beneficial for forming a denser third layer 1261 through the second oxygen-enriched annealing, thereby improving the protective effect of the second protective layer 126 on the second doped layer 123 during subsequent patterning processes, and preventing the retained second doped layer 123 from being over-etched. It should be noted that the second protective layer 126 located on the retained second doped layer 123 can be removed subsequently using acid.

[0074] In some examples, the material of the third part 1261 can be a silicon oxide layer containing a small amount of N-type doped elements; the material of the fourth part 1262 can be a silicon oxide layer containing a large amount of N-type doped elements, for example, a phosphosilicate glass layer. In the subsequent patterning process, the etching rate of the third part 1261 is lower than the etching rate of the fourth part 1262.

[0075] In one example, along the first direction X, the thickness of the second protective layer 126 can be 50nm to 70nm, for example, it can be 50nm, 51nm, 52nm, 53nm, 54nm, 55nm, 56nm, 57nm, 58nm, 59nm, 60nm, 61nm, 62nm, 63nm, 64nm, 65nm, 66nm, 67nm, 68nm, 69nm or 70nm, etc.

[0076] In some examples, prior to the second oxygen-free annealing, the second diffusion process further includes a second source stage to progressively diffuse the dopant element into the second semiconductor layer 125 and form a fourth part 1262; subsequently, the second oxygen-free annealing and the second oxygen-containing annealing are used to further promote the diffusion of the dopant element in the second semiconductor layer 125 and the substrate 100 and form a third part 1261.

[0077] In one example, the steps of the second source-injection stage may include: controlling the temperature of the reaction chamber to 830℃~850℃, maintaining the ratio of the flow rate of nitrogen carrying phosphorus oxychloride to the flow rate of oxygen in the reaction chamber to 1.5~2, controlling the pressure of the reaction chamber to 100mbar~250mbar, and the processing time of the first source-injection stage to 1800s~2200s.

[0078] In some examples, after the second aerobic annealing, the second diffusion process may also include a second cooling oxidation, for example, controlling the temperature of the reaction chamber to 750°C to 780°C and maintaining the processing time to 1000s to 1500s.

[0079] It should be noted that, Figure 6 This is a partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after the formation of the first semiconductor layer; Figure 7This is a partial cross-sectional view of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after the formation of the first protective layer; Figure 8 This is a partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after at least the first doped layer has been patterned. Figure 9 This is a first partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after the formation of the second semiconductor layer; Figure 10 This is a first partial cross-sectional view of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after the formation of the second protective layer; Figure 11 This is a partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after at least the second doped layer has been patterned.

[0080] In some embodiments, in conjunction with reference Figure 4 , Figure 7 and Figure 10 The protective layer 106 and the doped layer 103 are doped with the same type of doping element. The protective layer 106 may include a first layer 1061 and a second layer 1062 stacked along the first direction X. The doping concentration of the doping element in the first layer 1061 is less than the doping concentration in the second layer 1062, and the density of the first layer 1061 is higher than the density of the second layer 1062. The first direction X is the thickness direction of the substrate 100.

[0081] It is worth noting that the first layer 1061 is located on the side of the doped layer 103 away from the substrate 100, and the second layer 1062 is located on the side of the first layer 1061 away from the doped layer 103. The second layer 1062 is formed at the initial stage of the diffusion process, and the first layer 1061 is subsequently formed during oxygen annealing. It is understood that the first part 1161 mentioned in the foregoing embodiments can be considered as one type of first layer 1061, and the second part 1162 can be considered as one type of second layer 1062; the third part 1261 mentioned in the foregoing embodiments can be considered as another type of first layer 1061, and the fourth part 1262 can be considered as another type of second layer 1062.

[0082] In some cases, the first layer 1061 can be a silicon oxide layer containing a small amount of doped elements; the second layer 1062 can be a silicon oxide layer containing a large amount of doped elements, for example, a borosilicate glass layer or a phosphosilicate glass layer. In subsequent patterning steps, because the density of the first layer 1061 is higher than that of the second layer 1062, the etching rate of the first layer 1061 is lower than that of the second layer 1062, thereby improving the protective effect of the protective layer 106 on the doped layer 103. It should be noted that the layout of the protective layer 106 on the substrate 100 will be described in detail later.

[0083] The steps for forming oxide layer 102 are described in detail below.

[0084] In some embodiments, reference Figure 5 or Figure 9 Before forming the semiconductor layer 105, the method may further include: forming an oxide layer 102 between the substrate 100 and the semiconductor layer 105, wherein the thickness of the oxide layer 102 located in the first region 110 is controlled to be less than 1.7 nm in a first direction, where the first direction X is the thickness direction of the substrate 100.

[0085] It is worth noting that, in conjunction with references Figures 5 to 11 On the one hand, in the step of forming the doped layer 103, some dopants diffuse into the substrate 100, which helps to improve the electrical performance of the substrate 100 and reduce the contact resistance between the substrate 100 and the oxide layer 102. This, in turn, reduces the transmission resistance of photogenerated carriers from the substrate 100 to the electrode after the electrode is formed on the substrate 100. On the other hand, in the step of forming the oxide layer 102, the thickness of the oxide layer 102 in the first direction X affects the diffusion depth of dopants into the substrate 100 in the subsequent diffusion process. Generally speaking, increasing the thickness of the oxide layer 102 in the first direction X increases the difficulty of dopants diffusing into the substrate 100 in the diffusion process, reduces the diffusion depth of dopants in the substrate 100, and thus reduces the electrical performance of the substrate 100.

[0086] Based on this, in the step of forming oxide layer 102, the thickness of oxide layer 102 in the first region 110 in the first direction X is controlled to be less than 1.7 nm. This is beneficial for accurately controlling the thickness of oxide layer 102 in the first region 110, thereby reducing the difficulty of dopant elements diffusing into substrate 100 in the first region 110 during the diffusion process. This effectively avoids the reduction in diffusion depth of dopant elements in substrate 100 in the first region 110 due to excessive thickness of oxide layer 102, thereby avoiding the reduction in electrical performance of substrate 100 in the first region 110. For example, after forming electrodes on substrate 100, excessive transmission resistance is avoided during the process of photogenerated carriers being transported from substrate 100 in the first region 110 to the electrodes.

[0087] Thus, when performing EL testing on photovoltaic cells, controlling the thickness of the oxide layer 102 in the first region 110 along the first direction X helps avoid the problem of blackening of the first region 110 caused by a decrease in the diffusion depth of the dopant element in the substrate 100 of the first region 110. Furthermore, in practical applications, when the diffusion depth of the dopant element in the substrate of the first region is too low, the diffusion concentration of the dopant element in the substrate of the first region will also be very low, which will significantly affect the field passivation effect on the substrate. Therefore, the problem of blackening of the first region will also occur when performing PL testing on photovoltaic cells. However, in the photovoltaic cell manufacturing method provided in an embodiment of this disclosure, the problem of blackening of the first region 110 during PL testing can also be effectively avoided by controlling the thickness of the oxide layer 102 in the first direction X of the first region 110.

[0088] It should be noted that in the step of forming the doped layer 103, the diffusion depth of the dopant element in the substrate 100 located in the first region 110 is related to the diffusion concentration of the dopant element in the substrate 100 located in the first region 110, and together they affect the transport resistance of photogenerated carriers in the substrate 100. The diffusion depth and diffusion concentration of the dopant element in the substrate 100 located in the first region 110 will be explained in detail later. In addition, the oxide layer 102 serves as a tunneling layer. The thickness of the oxide layer 102 located in the first region 110 in the first direction X is designed to be less than 1.7 nm. Therefore, the oxide layer 102 is thinner than the thickness of a conventional tunneling layer, but it can still provide a good passivation effect on the substrate 100. It can also effectively prevent the reduction of the diffusion depth of the dopant element in the substrate 100 located in the first region 110 during the step of forming the doped layer 103, thereby avoiding the degradation of the electrical performance of the substrate 100 located in the first region 110.

[0089] In some cases, in conjunction with references Figure 1 , Figure 2 and Figure 5 The area of ​​surface 10 other than the first region 110 can be the second region 120. The second region 120 generally does not directly contact the supporting structure 101; in other words, there is a gap between the second region 120 and the supporting structure 101. When the oxide layer 102 is formed (see reference...) Figure 6In the first region 110, since it is in direct contact with the support structure 101, it can directly obtain more heat per unit time through the support structure 101 compared to the second region 120, making it easier to form a thicker oxide layer 102 on the first region 110. Based on this, when the thickness of the oxide layer 102 in the first region 110 along the first direction X is controlled to be less than 1.7 nm, the thickness of the oxide layer 102 in the second region 120 along the first direction X will also be less than 1.7 nm, and the thickness of the oxide layer 102 in the second region 120 along the first direction X will be less than the thickness of the oxide layer 102 in the first region 110. This not only reduces the difficulty of subsequent dopant diffusion into the substrate 100 in the first region 110, but also reduces the difficulty of subsequent dopant diffusion into the substrate 100 in the second region 120, resulting in good electrical performance throughout the entire substrate 100.

[0090] In some embodiments, in conjunction with reference Figure 1 , Figure 2 and Figure 5 The area of ​​surface 10 other than the first region 110 is the second region 120, which generally does not directly contact the load-bearing structure 101; Reference Figure 6 or Figure 9 Before forming the semiconductor layer 105, the process may further include forming an oxide layer 102 between the substrate 100 and the semiconductor layer 105.

[0091] In some cases, during the formation of oxide layer 102, it is easier to form a thicker oxide layer 102 on the first region 110 than on the second region 120. Therefore, controlling the difference between the thickness of the oxide layer 102 in the first region 110 and the thickness of the oxide layer 102 in the second region 120 to be less than or equal to 0.35 nm is beneficial in reducing the difficulty of dopant diffusion into the substrate 100 while minimizing the difference in diffusion depth between the substrate 100 in the first region 110 and the substrate 100 in the second region 120, thereby reducing the risk of uneven electrical performance in different regions of the substrate 100.

[0092] It should be noted that, depending on the manufacturing process, the oxide layer 102 can be a single-layer structure or a multilayer structure, but in both cases, the difference between the thickness of the oxide layer 102 in the first region 110 and the thickness of the oxide layer 102 in the second region 120 can be controlled to be less than or equal to 0.35 nm. The manufacturing method of the oxide layer 102 and the thickness of the oxide layer 102 in different regions have been described in detail in the foregoing embodiments, and will not be repeated here. Furthermore, the difference between the thickness of the oxide layer 102 in the first region 110 and the thickness of the oxide layer 102 in the second region 120 is very small. Figure 6 or Figure 9The difference in thickness of oxide layer 102 in different regions is not reflected in the data.

[0093] In some embodiments, in conjunction with reference Figures 1 to 11 In the diffusion process, the diffusion depth and diffusion concentration of the dopant element into the substrate 100 are closely related. Generally, along the direction from the surface of the substrate 100 inwards, as diffusion deepens, fewer and fewer dopant elements diffuse into the deeper parts of the substrate 100. Based on this, a minimum diffusion concentration is usually set as a benchmark to determine the diffusion depth of the dopant element in the substrate 100. It is understandable that if the concentration of the dopant element per unit space in the deeper regions of the substrate 100 is too low, the gain on the electrical performance of the substrate 100 will not be significant; therefore, a diffusion concentration benchmark is set.

[0094] Furthermore, the dopant element can be either a P-type or an N-type dopant element, and the current benchmark for the diffusion concentration of the dopant element in the substrate 100 mainly includes the following two scenarios: In some cases, when the dopant element is a p-type dopant, the baseline for the diffusion concentration of the dopant element in the substrate 100 can be set to 1 × 10⁻⁶. 19 atom / cm 3 If the photovoltaic cell manufacturing method provided in one embodiment of the present disclosure is adopted, the thickness of the oxide layer 102 located in the first region 110 in the first direction is controlled to be less than 1.7 nm, which is beneficial to promote the diffusion depth of dopant elements in the substrate 100 in the range of 15 nm to 25 nm.

[0095] In other cases, the baseline for the diffusion concentration of the dopant element in the substrate 100 can be set to 1 × 10⁻⁶. 18 atom / cm 3 If the photovoltaic cell manufacturing method provided in one embodiment of this disclosure is adopted, the thickness of the oxide layer 102 located in the first region 110 in the first direction is controlled to be less than 1.7 nm, which is beneficial to promote the diffusion depth of dopant elements in the substrate 100 in the range of 35 nm to 45 nm.

[0096] It should be noted that the above example only uses P-type dopant as an example. The diffusion depth of the dopant in the substrate 100 when the dopant is P-type or N-type will be described in detail later with reference to the embodiments.

[0097] In some examples, the P-type dopant can be at least one of group III elements such as boron (B), aluminum (Al), gallium (Ga), or gallium (In); the N-type dopant can be at least one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As).

[0098] In some embodiments, reference Figure 6 or Figure 12 , Figure 12 This is a second partial cross-sectional view of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after the formation of the second semiconductor layer. Before forming the semiconductor layer 105, the method may further include: forming an oxide layer 102 between the substrate 100 and the semiconductor layer 105. The step of forming the oxide layer 102 may include at least: performing a first polishing treatment on the substrate 100. At least in the step of performing the first polishing treatment, the moisture content of the environment in which the substrate 100 is located is controlled to be 6 g / kg to 12 g / kg, so as to form a first oxide layer 112 on the surface of the substrate 100 after the first polishing treatment.

[0099] It is worth noting that the environment in which the substrate 100 is located is the same production environment provided during the first polishing process. Under high temperature conditions, the moisture absorbed by the surface 10 of the substrate 100 evaporates, generating wet oxygen oxidation, which causes the surface 10 of the substrate 100 to be oxidized and naturally grow a first oxide layer 112. Furthermore, in conjunction with the reference... Figure 2 and Figure 6 or in conjunction with references Figure 2 and Figure 12 The area in the bearing structure 101 that is in contact with the first region 110 will absorb water vapor in the production environment. Under high temperature conditions, the water vapor absorbed in the bearing structure 101 will evaporate and produce wet oxygen oxidation. The wet oxygen oxidation rate is relatively fast, which will further increase the thickness of the first oxide layer 112 located in the first region 110. Subsequently, the first oxide layer 112 can be used as a sub-part of the oxide layer 102 without removing it.

[0100] Based on this, the humidity of the environment in which the substrate 100 is located is designed to be between 6 g / kg and 12 g / kg. This helps to prevent the substrate 100 and the supporting structure 101 from absorbing excessive moisture in the production environment, thereby avoiding an excessively thick first oxide layer 112 in the first direction X. This, in turn, helps to prevent a decrease in the doping depth of the dopant elements in the substrate 100 during the diffusion process. Furthermore, in addition to controlling the humidity of the environment in which the substrate 100 is located to be between 6 g / kg and 12 g / kg during the first polishing step, the humidity of the production environment can also be controlled to be between 6 g / kg and 12 g / kg in subsequent process steps.

[0101] It should be noted that the humidity of the environment in which the substrate 100 is located is 6 g / kg, which means that there is 6 g of water vapor in 1 kg of air. Similarly, the humidity of the environment in which the substrate 100 is located is 12 g / kg, which means that there is 12 g of water vapor in 1 kg of air.

[0102] In some cases, the moisture content of the environment in which the substrate 100 is located can be 6 g / kg, 7 g / kg, 8 g / kg, 9 g / kg, 10 g / kg, 11 g / kg or 12 g / kg, etc.

[0103] In some cases, the thickness of the first oxide layer 112 along the first direction X can be 0.4 nm to 0.6 nm, for example, it can be 0.4 nm, 0.41 nm, 0.42 nm, 0.43 nm, 0.44 nm, 0.45 nm, 0.46 nm, 0.47 nm, 0.48 nm, 0.49 nm, 0.5 nm, 0.51 nm, 0.52 nm, 0.53 nm, 0.54 nm, 0.55 nm, 0.56 nm, 0.57 nm, 0.58 nm, 0.59 nm or 0.6 nm, etc.

[0104] In some cases, the method for performing a first polishing treatment on the substrate 100 may include using a hot alkaline solution to give the surface 10 of the substrate 100 a pyramidal base morphology. It should be noted that the pyramidal base morphology can be understood as a polished surface. Compared to a textured surface, a polished surface has a flatter surface morphology, which is more conducive to improving the thickness uniformity of the film layer formed on the surface 10, such as forming an oxide layer 102 and a doped layer 103 with better film quality. The pyramidal base can be considered as the base part of a pyramid structure, that is, the remaining structure after the pyramid's apex has been removed; or the surface 10 may be described as including multiple square base surfaces.

[0105] In one example, substrate 100 can be a silicon wafer with N-type doped elements or a silicon wafer with P-type doped elements.

[0106] In some embodiments, in conjunction with reference Figures 6 to 13 Before forming the semiconductor layer 105, the process may further include forming an oxide layer 102 between the substrate 100 and the semiconductor layer 105.

[0107] Reference Figures 6 to 8 The steps of forming oxide layer 102 and semiconductor layer 105 include at least: employing a first deposition process including a first stage and a second stage, forming a first dielectric layer 114 in the first stage, and forming a first semiconductor layer 115 on the side of the first dielectric layer 114 away from the substrate 100 in the second stage to obtain a first semi-finished product; the diffusion process includes at least: performing a first diffusion process on the first semi-finished product to convert the first semiconductor layer 115 into a first doped layer 113, and forming a first protective layer 116 on the side of the first doped layer 113 away from the substrate 100.

[0108] It is worth noting that in the first diffusion process, the dopant elements will further diffuse into the substrate 100.

[0109] In some cases, in conjunction with references Figure 6 and Figure 7 The photovoltaic cell formed is a cell with electrodes on both sides; in the step of forming the first dielectric layer 114 and the first doped layer 113 using the first deposition process and the first diffusion process, the first dielectric layer 114 and the first doped layer 113 can be located on the entire surface 10.

[0110] Furthermore, in some examples, the reference continues to be used. Figure 6 and Figure 7 Before forming the first dielectric layer 114 and the first doped layer 113 using the first deposition process and the first diffusion process, the method for manufacturing a photovoltaic cell may further include: performing a first polishing process on the substrate 100, and forming a first oxide layer 112 on the surface of the substrate 100 after the first polishing process. Thus, the formed oxide layer 102 includes the first oxide layer 112 and the first dielectric layer 114, and the formed doped layer 103 includes the first doped layer 113. In other examples, the first oxide layer may be removed, such that the formed oxide layer includes the first dielectric layer, and the formed doped layer includes the first doped layer.

[0111] In other cases, in conjunction with references Figures 6 to 8 The resulting photovoltaic cell is a cell with an electrode on one side. After forming the first dielectric layer 114 and the first doped layer 113 using the first deposition process and the first diffusion process, the first dielectric layer 114 and the first doped layer 113 will be patterned. The steps for forming the oxide layer 102 and the doped layer 103 also include other processes, which will be described in detail later.

[0112] In both of the above scenarios, the materials of the first oxide layer 112 and the first dielectric layer 114 may include silicon oxide; the first semiconductor layer 115 may be a silicon monolayer.

[0113] In both of the above scenarios, the second stage step may include: introducing nitrogen and silane into the reaction chamber used to prepare the first semiconductor layer 115, controlling the ratio of nitrogen gas flow rate to silane gas flow rate to be 0.7~1, which is beneficial to improve the dilution effect of nitrogen on silane, avoid excessive gaseous silane from colliding with each other to form clusters or particles, thereby improving the density of the prepared first semiconductor layer 115, which in turn can improve the density of the first doped layer 113 formed based on the transformation of the first semiconductor layer 115, avoid excessive erosion of the first doped layer 113 by subsequent patterning processing, ensure good film quality of the final retained first doped layer 113, and thus improve the yield of photovoltaic cells.

[0114] In some examples, the first stage of forming the first dielectric layer 114 may include the following steps: controlling the temperature of the reaction chamber to 560°C to 620°C, introducing sufficient oxygen, and maintaining the oxidation time to 1000s to 1500s.

[0115] In other embodiments, in conjunction with reference to Figures 12 to 13 Or combine with references Figures 9 to 11 The steps of forming oxide layer 102 and semiconductor layer 105 may include at least: employing a second deposition process including a third stage and a fourth stage, forming a second dielectric layer 124 in the third stage, and forming a second semiconductor layer 125 on the side of the second dielectric layer 124 away from the substrate 100 in the fourth stage to obtain a second semi-finished product; the diffusion process steps include at least: performing a second diffusion process on the second semi-finished product to convert the second semiconductor layer 125 into a second doped layer 123, and forming a second protective layer 126 on the side of the second doped layer 123 away from the substrate 100.

[0116] It is worth noting that in the second diffusion process, the dopant element further diffuses into the substrate 100. Among these, Figure 13 This is a second partial cross-sectional view of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after the formation of the second protective layer.

[0117] In some cases, in conjunction with references Figures 12 to 13 The photovoltaic cell formed is a cell with electrodes on both sides; in the step of forming the second dielectric layer 124 and the second doped layer 123 using the second deposition process and the second diffusion process, the second dielectric layer 124 and the second doped layer 123 can be located on the entire surface 10.

[0118] Furthermore, in some examples, the reference continues to be used. Figures 12 to 13 Before forming the second dielectric layer 124 and the second doped layer 123 using the second deposition process and the second diffusion process, the method for manufacturing a photovoltaic cell may further include: performing a first polishing treatment on a substrate 100, and forming a first oxide layer 112 on the surface of the substrate 100 after the first polishing treatment. Thus, the formed oxide layer 102 includes the first oxide layer 112 and the second dielectric layer 124, and the formed doped layer 103 includes the second doped layer 123. In other examples, the first oxide layer may be removed, such that the formed oxide layer includes the second dielectric layer, and the formed doped layer includes the second doped layer.

[0119] In other cases, the resulting photovoltaic cell is a cell with electrodes on only one side; referring to the reference. Figures 6 to 11Before forming the second dielectric layer 124 and the second doped layer 123 using the second deposition process and the second diffusion process, the first dielectric layer 114 and the first doped layer 113 are formed using the first deposition process and the first diffusion process, and then the first dielectric layer 114 and the first doped layer 113 are patterned. Therefore, the step of forming the oxide layer 102 includes not only forming the first dielectric layer 114 but also forming the second dielectric layer 124, and the step of forming the doped layer 103 includes not only forming the first doped layer 113 but also forming the second doped layer 123.

[0120] Furthermore, in some examples, in conjunction with references Figures 6 to 8 Before forming the first dielectric layer 114 and the first doped layer 113 using the first deposition process and the first diffusion process, the photovoltaic cell manufacturing method may further include: performing a first polishing treatment on the substrate 100, and forming a first oxide layer 112 on the surface of the substrate 100 after the first polishing treatment. (Refer to reference...) Figures 7 to 9 In the subsequent step of patterning the first dielectric layer 114 and the first doped layer 113, the first oxide layer 112 is also patterned, and a second oxide layer 122 is formed on a portion of the surface 10. Thus, the step of forming the oxide layer 102 generally includes forming the first oxide layer 112, forming the first dielectric layer 114, forming the second oxide layer 122, and forming the second dielectric layer 124, which will be described in detail later.

[0121] In both of the above cases, the materials of the second oxide layer 122 and the second dielectric layer 124 may also include silicon oxide; the second semiconductor layer 125 may also be a silicon monolayer.

[0122] In both of the above scenarios, the fourth stage step may include: introducing nitrogen and silane into the reaction chamber used to prepare the second semiconductor layer 125, controlling the ratio of nitrogen gas flow rate to silane gas flow rate to be 0.7~1, which is beneficial to improve the dilution effect of nitrogen on silane, avoid excessive collision of gaseous silane to form clusters or particles, thereby improving the density of the prepared second semiconductor layer 125, which in turn can improve the density of the second doped layer 123 formed based on the transformation of the second semiconductor layer 125, avoid excessive erosion of the second doped layer 123 by subsequent patterning processing, ensure good film quality of the finally retained second doped layer 123, and thus improve the yield of photovoltaic cells.

[0123] It should be noted that when the formed doped layer 103 includes a first doped layer 113 and a second doped layer 123, the first doped layer 113 and the second doped layer 123 are doped with different types of doping elements.

[0124] In some examples, the third stage of forming the second dielectric layer 124 may include the following steps: controlling the temperature of the reaction chamber to 560°C to 620°C, introducing sufficient oxygen, and maintaining the oxidation time to 1000s to 1500s.

[0125] The first deposition process, the first diffusion process, the second deposition process, and the second diffusion process are described in detail below.

[0126] In some cases, during the steps of performing the first deposition process, the first diffusion process, the second deposition process, and / or the second diffusion process, the idle time of the support structure 101 is controlled to be less than or equal to 120 minutes.

[0127] It should be noted that the first deposition process, the first diffusion process, the second deposition process, and the second diffusion process are each considered as one step, in conjunction with the reference. Figure 2 as well as Figures 6 to 13 The idle time of the support structure 101 refers to the time elapsed between the completion of one process and the start of another process, which is the support structure 101 carrying the substrate 100. It can also be understood as the time during which the support structure 101 is not in operation. Furthermore, the longer the idle time of the support structure 101, the more water vapor it adsorbs from the external environment. In subsequent processes, more water vapor will evaporate from the support structure 101, leading to more water vapor participating in the reaction. This not only increases the thickness of the first dielectric layer 114 or the second dielectric layer 124, but also affects the film quality of the first doped layer 113 and the second doped layer 123.

[0128] Based on this, in the steps of performing the first deposition process, the first diffusion process, the second deposition process, and / or the second diffusion process, controlling the idle time of the support structure 101 to be less than or equal to 120 minutes helps to avoid excessive water vapor adsorbed by the support structure 101 during the intervals between different processes, thereby avoiding excessive thickness of the first dielectric layer 114 or the second dielectric layer 124, thus ensuring that the thickness of the final oxide layer 102 is relatively thin, for example, less than 1.7 nm, and also helps to form a doped layer 103 with less oxygen content, so as to ensure that the doped layer 103 has a good passivation effect on the substrate 100.

[0129] In some examples, during the steps of performing the first deposition process, the first diffusion process, the second deposition process, and / or the second diffusion process, the idle time of the support structure 101 can be controlled to be 120 min, 110 min, 100 min, 90 min, 80 min, 70 min, 60 min, 50 min, 40 min, 30 min, 20 min, or 10 min, etc.

[0130] In other cases, in conjunction with references Figure 2 as well as Figures 6 to 13 In the steps of performing the first deposition process, the first diffusion process, the second deposition process and / or the second diffusion process, if the idle time of the support structure 101 is greater than 120 minutes, the support structure 101 is baked to reduce the amount of water adsorbed by the support structure 101 during the idle process.

[0131] It is understandable that, due to design requirements or operational errors between different processes, the idle time of the support structure 101 may exceed 120 minutes. In this case, the support structure 101 can be baked before proceeding to the next process to reduce the amount of water adsorbed by the support structure 101 during the idle process. This can also prevent the thickness of the first dielectric layer 114 or the second dielectric layer 124 from being too thick, thereby ensuring that the thickness of the final oxide layer 102 is relatively thin, for example, less than 1.7 nm. Moreover, it is beneficial to form a doped layer 103 with less oxygen content, so as to ensure that the doped layer 103 has a good passivation effect on the substrate 100.

[0132] In some examples, the method of baking the load-bearing structure 101 includes baking the load-bearing structure 101 at a temperature higher than 500°C for a time of more than 20 minutes.

[0133] In some cases, in conjunction with references Figure 2 as well as Figures 6 to 13 The semi-finished photovoltaic cells in the manufacturing process are regarded as semi-finished products to be picked up. During the process of transporting the semi-finished products to be picked up or the transport support structure 101 by a paddle (not shown in the figure), the idle time of the paddle is controlled to be less than or equal to 30 minutes.

[0134] It should be noted that, due to the complexity of the manufacturing process of photovoltaic cells, a paddle is typically used to pick up and place the support structure 101, or to pick up and place the semi-finished product contained in the support structure 101. Therefore, the paddle will come into contact with the support structure 101 or the semi-finished product contained within it, causing water vapor adsorbed by the paddle from the environment to affect the moisture content inside the support structure 101 or the semi-finished product. Furthermore, the idle time of the paddle refers to the time elapsed from when the paddle places one item until it picks up another; it can also be understood as the time during which the paddle is not in a working state. Thus, the longer the paddle is idle, the more water vapor it will adsorb from the external environment, and the greater the impact on the water content inside the bearing structure 101 or the semi-finished product to be taken. In subsequent processes, more water vapor will evaporate, leading to more water vapor participating in the reaction. This will not only increase the thickness of the first dielectric layer 114 or the second dielectric layer 124, but also affect the quality of the first doped layer 113 and the second doped layer 123.

[0135] Based on this, during the process of transporting the semi-finished product to be picked up or transporting the carrier structure 101 by the paddle, controlling the idle time of the paddle to be less than or equal to 30 minutes is beneficial to avoid excessive water vapor adsorbed by the paddle during the period of inactivity, so as to avoid the thickness of the first dielectric layer 114 or the second dielectric layer 124 being too thick, thereby ensuring that the thickness of the final oxide layer 102 is relatively thin, for example, less than 1.7 nm, and is also beneficial to forming a doped layer 103 with less oxygen content, so as to ensure that the doped layer 103 has a good passivation effect on the substrate 100.

[0136] In some examples, during the process of transporting the semi-finished product to be picked up or transporting the load-bearing structure 101 by a paddle (not shown in the figure), the idle time of the paddle can be controlled to be 30 min, 25 min, 20 min, 15 min, 10 min or 5 min, etc.

[0137] In other cases, in conjunction with references Figure 2 as well as Figures 6 to 13 If the paddle is idle for more than 30 minutes, it should be baked to reduce the amount of water absorbed by the paddle during the idle period.

[0138] It is understandable that design requirements or operational errors between different processes may cause the paddle to be idle for more than 30 minutes. In this case, the paddle can be baked before it starts working to reduce the amount of water adsorbed by the paddle during idle time. This can also prevent the thickness of the first dielectric layer 114 or the second dielectric layer 124 from being too thick, thereby ensuring that the thickness of the final oxide layer 102 is thin, for example, less than 1.7 nm. It is also beneficial to form a doped layer 103 with less oxygen content, so as to ensure that the doped layer 103 has a good passivation effect on the substrate 100.

[0139] In some examples, the method of baking the paddles includes baking the paddles at a temperature above 500°C for a time of more than 20 minutes.

[0140] The following provides a detailed description of embodiments of photovoltaic cell manufacturing methods that include both a first deposition process and a first diffusion process, as well as a second deposition process and a second diffusion process.

[0141] In some cases, in conjunction with references Figure 2 , Figure 5 and Figure 11 The surface 10 may include a third region 130 and a fourth region 140 alternately arranged along the second direction Y, a portion of the first region 110 is located in the third region 130, a portion of the first region 110 is located in the fourth region 140, and the second direction Y intersects with the first direction X; the oxide layer 102 includes a first dielectric layer 114 and a second dielectric layer 124, and the doped layer 103 includes a first doped layer 113 and a second doped layer 123.

[0142] Based on this, after forming the first doped layer 113 and before forming the second dielectric layer 124, the method for manufacturing a photovoltaic cell may further include: combining with reference to... Figures 7 to 9 The first dielectric layer 114 and the first doped layer 113 are patterned to remove the first dielectric layer 114 and the first doped layer 113 located in the third region 130 or the fourth region 140 and expose the substrate 100. At least during the patterning process, the moisture content of the environment in which the substrate 100 is located is controlled to be 6 g / kg to 12 g / kg so as to form a second oxide layer 122 on the surface of the patterned substrate 100, and then a second deposition process is performed.

[0143] It is worth noting that during the patterning process, the substrate 100 located in the third zone 130 or the fourth zone 140 is exposed to the production environment. Under high temperatures, the moisture absorbed by the exposed substrate 100 evaporates, generating wet oxygen oxidation, which causes the exposed substrate 100 to be oxidized and naturally grow a second oxide layer 122. Furthermore, the supporting structure 101 (reference...) Figure 2The area in contact with zone 110 in the production environment will absorb moisture, and under high temperature conditions, the area in zone 110 (refer to...) will... Figure 2 The thickness of the first oxide layer 112 is further increased, so the second oxide layer 122 can be used as a sub-part of the oxide layer 102 without removing it.

[0144] In some examples, the method of patterning the first dielectric layer 114 and the first doped layer 113 includes: irradiating the first dielectric layer 114 and the first doped layer 113 located in the third region 130 or the fourth region 140 with a laser; and etching away the first dielectric layer 114 and the first doped layer 113 irradiated by the laser with a hot alkaline solution to expose the substrate 100 located in the third region 130 or the fourth region 140, and forming a second oxide layer 122 on the exposed substrate 100.

[0145] It is worth noting that after etching the first dielectric layer 114 and the first doped layer 113 after laser irradiation with a hot alkaline solution, the exposed surface of the substrate 100 can also exhibit a pyramidal base morphology.

[0146] In some examples, the step of forming oxide layer 102 before performing the first deposition process may further include: performing a first polishing treatment on substrate 100, and forming a first oxide layer 112 on the surface of substrate 100 after the first polishing treatment. Based on this, in the patterning step, the first oxide layer 112 opposite to the first dielectric layer 114 irradiated by laser is also removed, and the remaining first oxide layer 112 serves as a sub-part of oxide layer 102.

[0147] It is worth noting that after patterning and before the second deposition process, the remaining first oxide layer 112 and the remaining first dielectric layer 114 constitute a first tunneling layer (not shown in the figure), which is located on one of the third region 130 and the fourth region 140. After the subsequent second deposition and second diffusion processes, the second oxide layer 122, the second dielectric layer 124, and the second doped layer 123 will be patterned again, so that the remaining second oxide layer 122, the remaining second dielectric layer 124, and the remaining second doped layer 123 are located on at least one of the third region 130 and the fourth region 140. The remaining second oxide layer 122 and the remaining second dielectric layer 124 constitute a second tunneling layer (not shown in the figure), which is located on at least one of the third region 130 and the fourth region 140. It should be noted that the first tunneling layer and the second tunneling layer can be considered as two types of oxide layers 102, with at least partial structures located on different regions of the surface 10.

[0148] In some examples, the thickness of the first oxide layer 112 along the first direction X can be less than the thickness of the second oxide layer 122. It is worth noting that although both the first oxide layer 112 and the second oxide layer 122 can be formed on a substrate 100 with a pyramidal base morphology, the alkali content of the hot alkaline solution used to form the first oxide layer 112 differs from that used to form the second oxide layer 122. Furthermore, the surface of the substrate 100 corresponding to the formation of the second oxide layer 122 can be considered as having undergone two etching processes with hot alkaline solutions. This results in a larger pyramidal base structure on the surface of the substrate 100 corresponding to the formation of the first oxide layer 112 compared to the size of the pyramidal base structure on the surface of the substrate 100 corresponding to the formation of the second oxide layer 122. Consequently, the surface area is smaller, making it easier to form a thicker second oxide layer 122.

[0149] In one example, along the first direction X, the thickness of the first oxide layer 112 can be 0.4 nm to 0.6 nm; the thickness of the second oxide layer 122 can be 0.5 nm to 0.7 nm, for example, it can be 0.5 nm, 0.51 nm, 0.52 nm, 0.53 nm, 0.54 nm, 0.55 nm, 0.56 nm, 0.57 nm, 0.58 nm, 0.59 nm, 0.6 nm, 0.61 nm, 0.62 nm, 0.63 nm, 0.64 nm, 0.65 nm, 0.66 nm, 0.67 nm, 0.68 nm, 0.69 nm, or 0.7 nm, etc. It is worth noting that if the thickness of the first oxide layer 112 is too large, it will affect the thickness of the subsequently formed first dielectric layer 114, resulting in an increase in the total thickness of the oxide layer 102 formed in the first region 110; similarly, if the thickness of the second oxide layer 122 is too large, it will affect the thickness of the subsequently formed second dielectric layer 124, resulting in an increase in the total thickness of the oxide layer 102 formed in the first region 110. Therefore, the thickness of the first oxide layer 112 is designed to be 0.4 nm to 0.6 nm, and the thickness of the second oxide layer 122 is designed to be 0.5 nm to 0.7 nm, which helps to ensure that the thickness of the oxide layer 102 located in the first region 110 is less than 1.7 nm in the first direction.

[0150] In some examples, along the first direction X, the total thickness of the first oxide layer 112 and the first dielectric layer 114 may be less than the total thickness of the second oxide layer 122 and the second dielectric layer 124. The first oxide layer 112 and the first dielectric layer 114 can be considered as a first tunneling layer, and the second oxide layer 122 and the second dielectric layer 124 can be considered as a second tunneling layer.

[0151] It is worth noting that, compared to the size of the base structure on the surface of the substrate 100 when the first oxide layer 112 is formed, the size of the base structure on the surface of the substrate 100 when the second oxide layer 122 is formed is larger, resulting in a smaller specific surface area. On the one hand, this makes it easier for the thickness of the formed second oxide layer 122 to be greater than the thickness of the first oxide layer 112, thus promoting the total thickness of the first oxide layer 112 and the first dielectric layer 114 to be less than the total thickness of the second oxide layer 122 and the second dielectric layer 124. On the other hand, it may also make the thickness of the formed second dielectric layer 124 greater than the thickness of the formed first dielectric layer 114, further promoting the total thickness of the first oxide layer 112 and the first dielectric layer 114 to be less than the total thickness of the second oxide layer 122 and the second dielectric layer 124.

[0152] In one example, the first diffusion process uses a P-type dopant, such as boron; the second diffusion process uses an N-type dopant, such as phosphorus. Compared to N-type dopant, P-type dopant is more difficult to diffuse into the substrate 100. Therefore, the total thickness of the first oxide layer 112 and the first dielectric layer 114 is designed to be less than the total thickness of the second oxide layer 122 and the second dielectric layer 124. This reduces the difficulty of P-type dopant diffusion into the substrate 100, ensuring that the final diffusion depth of the P-type dopant into the substrate 100 meets the requirements, thus ensuring good electrical performance of the substrate 100. Furthermore, the process temperatures in the first and second diffusion processes can be adjusted to match the different thicknesses of the first and second tunneling layers, ensuring that both P-type and N-type dopant have the required diffusion depths in the substrate 100, thus ensuring good electrical performance in both the third region 130 and the fourth region 140 of the substrate 100.

[0153] In one example, along the first direction X, the total thickness of the first oxide layer 112 and the first dielectric layer 114 can be 1.3 nm to 1.5 nm, for example, it can be 1.3 nm, 1.31 nm, 1.32 nm, 1.33 nm, 1.34 nm, 1.35 nm, 1.36 nm, 1.37 nm, 1.38 nm, 1.39 nm, 1.4 nm, 1.41 nm, 1.42 nm, 1.43 nm, 1.44 nm, 1.45 nm, 1.46 nm, 1.47 nm, 1.48 nm, 1.49 nm, or 1.5 nm. Along the first direction X, the total thickness of the second oxide layer 122 and the second dielectric layer 124 can be 1.35nm to 1.55nm, for example, it can be 1.35nm, 1.36nm, 1.37nm, 1.38nm, 1.39nm, 1.4nm, 1.41nm, 1.42nm, 1.43nm, 1.44nm, 1.45nm, 1.46nm, 1.47nm, 1.48nm, 1.49nm, 1.5nm, 1.51nm, 1.52nm, 1.53nm, 1.54nm, or 1.55nm, etc.

[0154] It should be noted that the thickness of the first oxide layer 112, the thickness of the second oxide layer 122, the total thickness of the first oxide layer 112 and the first dielectric layer 114, and the total thickness of the second oxide layer 122 and the second dielectric layer 124 mentioned in the foregoing embodiments all refer to the thickness of the film layer or the combined film layer located in the second region 120. The thickness of the film layer or the combined film layer located in the first region 110 can be understood as the thickness of the oxide layer 102 located in the first region 110.

[0155] In one example, the oxide layer 102 located in the first region 110 includes two cases: the thickness of the oxide layer 102 located at the overlap of the first region 110 and the third region 130 is less than 1.65 nm; the thickness of the oxide layer 102 located at the overlap of the first region 110 and the fourth region 140 is less than 1.7 nm. This facilitates accurate control of the thickness of the oxide layer 102 in different regions of the photovoltaic cell, reducing the difficulty of dopant diffusion into the substrate 100 located in the first region 110 during the diffusion process, thus avoiding a decrease in the electrical performance of the substrate 100 located in the first region 110, and ensuring that the photovoltaic cell shows no blackening phenomenon in both EL and PL tests.

[0156] In some cases, refer to Figure 11The surface 10 may include a third region 130 and a fourth region 140 alternately arranged along the second direction Y, a portion of the first region 110 is located in the third region 130, a portion of the first region 110 is located in the fourth region 140, and the second direction Y intersects with the first direction X; the oxide layer 102 includes a first dielectric layer 114 and a second dielectric layer 124, and the doped layer 103 includes a first doped layer 113 and a second doped layer 123.

[0157] Based on this, and in conjunction with references Figures 7 to 9 After the formation of the first doped layer 113 and before the formation of the second dielectric layer 124, the manufacturing method of the photovoltaic cell may further include: patterning the first dielectric layer 114 and the first doped layer 113, removing the first dielectric layer 114 and the first doped layer 113 located in the third region 130 or the fourth region 140, and controlling the time interval from the end of the patterning process to the start of the second deposition process to be less than or equal to 60 minutes.

[0158] The time interval between the end of the patterning process and the start of the second deposition process can be understood as the transportation and transfer time of the semi-finished battery. Designing it to be less than or equal to 60 minutes helps to avoid damage to the semi-finished battery or the supporting structure 101 (reference). Figure 2 This process allows for the adsorption of excessive water vapor during this period, preventing the subsequent formation of an excessively thick second dielectric layer 124 and facilitating the formation of a second doped layer 123 with lower oxygen content. In some examples, it also helps prevent the subsequent formation of an excessively thick second oxide layer 122.

[0159] In all the above scenarios, the doping element in the first diffusion process is a P-type doping element, and the doping element in the second diffusion process is an N-type doping element. Based on this, the various parameters in the first and second diffusion processes are explained in detail.

[0160] In some examples, in conjunction with references Figures 6 to 11The deposition temperature for forming the first semiconductor layer 115 can be lower than the deposition temperature for forming the second semiconductor layer 125. It is worth noting that, compared to the difficulty of N-type dopant diffusion into the second semiconductor layer 125, P-type dopant diffusion into the first semiconductor layer 115 is more difficult; moreover, a decrease in the crystallinity of the first semiconductor layer 115 is beneficial to promoting the doping of P-type dopant into the first semiconductor layer 115. Based on this, the deposition temperature for forming the first semiconductor layer 115 is designed to be lower than the deposition temperature for forming the second semiconductor layer 125. This is beneficial for reducing the crystallinity of the first semiconductor layer 115 by using a lower deposition temperature, thereby reducing the difficulty of P-type dopant diffusion into the first semiconductor layer 115 and further reducing the difficulty of P-type dopant diffusion into the substrate 100. This ensures that the P-type dopant ultimately has a suitable doping concentration in both the first doped layer 113 and the substrate 100. Moreover, by using a higher deposition temperature to increase the crystallinity of the second semiconductor layer 125, it is also possible to avoid excessive doping of N-type dopant in both the second doped layer 123 and the substrate 100. This ensures that the N-type dopant ultimately has a suitable doping concentration in both the second doped layer 123 and the substrate 100.

[0161] In some examples, the deposition temperature for forming the first semiconductor layer 115 can be 550°C to 580°C, for example, 550°C, 555°C, 560°C, 565°C, 570°C, 575°C, or 580°C; the deposition temperature for forming the second semiconductor layer 125 can be 570°C to 630°C, for example, 570°C, 575°C, 580°C, 585°C, 590°C, 595°C, 600°C, 605°C, 610°C, 615°C, 620°C, 625°C, or 630°C.

[0162] In some examples, the crystallinity of the first semiconductor layer 115 can be lower than that of the second semiconductor layer 125. In this way, on the one hand, the lower crystallinity of the first semiconductor layer 115 reduces the difficulty of P-type dopant diffusion into both the first semiconductor layer 115 and the substrate 100, ensuring that the P-type dopant ultimately has a suitable doping concentration in both the first doped layer 113 and the substrate 100; on the other hand, the higher crystallinity of the second semiconductor layer 125 prevents excessive doping of N-type dopant in both the second doped layer 123 and the substrate 100, ensuring that the N-type dopant ultimately has a suitable doping concentration in both the second doped layer 123 and the substrate 100.

[0163] In some examples, the thickness of the first semiconductor layer 115 along the first direction X can be greater than the thickness of the second semiconductor layer 125.

[0164] It is worth noting that the photogenerated carriers generated in the substrate 100 are divided into electrons and holes. A p-type dopant is doped into the first semiconductor layer 115 to form a first doped layer 113, which is used to transport holes generated in the substrate 100. An n-type dopant is doped into the second semiconductor layer 125 to form a second doped layer 123, which is used to transport electrons generated in the substrate 100. Generally, the mobility of electrons is significantly higher than that of holes. Furthermore, the film properties of the doped layer, such as burn-through resistance, are affected by the dopants present in the doped layer. In the subsequent electrode fabrication step, compared to the second doped layer 123 being doped with an n-type dopant, the first doped layer 113 being doped with a p-type dopant makes it more susceptible to burn-through by the electrode.

[0165] Based on this, the thickness of the first semiconductor layer 115 is designed to be greater than the thickness of the second semiconductor layer 125. This is beneficial because the thickness of the first doped layer 113 is greater than the thickness of the second doped layer 123. On the one hand, compared with the second doped layer 123, the thicker first doped layer 113 can generate a higher electric field to drive the migration of holes and make up for the difference between the mobility of electrons and holes. On the other hand, compared with the second doped layer 123, the thicker first doped layer 113 can reduce the risk of the electrode burning through the first doped layer 113 during electrode fabrication.

[0166] In some examples, along the first direction X, the thickness of the first semiconductor layer 115 can be 190nm to 330nm, for example, it can be 190nm, 200nm, 210nm, 220nm, 230nm, 240nm, 250nm, 260nm, 270nm, 280nm, 290nm, 300nm, 310nm, 320nm or 330nm, etc.; the thickness of the second semiconductor layer 125 can be 160nm to 300nm, for example, it can be 160nm, 170nm, 180nm, 190nm, 200nm, 210nm, 220nm, 230nm, 240nm, 250nm, 260nm, 270nm, 280nm, 290nm or 300nm, etc.

[0167] It should be noted that the deposition temperature, crystallinity, and thickness of the first semiconductor layer 115 and the second semiconductor layer 125 can be adjusted synchronously to ensure that the P-type dopant and the N-type dopant have appropriate doping concentrations in the substrate 100 to improve the electrical performance of the substrate 100, while reducing the difference in carrier transport resistance between the first doped layer 113 and the second doped layer 123 and reducing the risk of electrode burn-through of the first doped layer 113, thereby comprehensively improving the photoelectric conversion efficiency of the photovoltaic cell.

[0168] In some cases, refer to Figure 6 The step of forming oxide layer 102 before performing the first deposition process or before performing the second deposition process may further include: performing a first polishing treatment on substrate 100, and forming a first oxide layer 112 on the surface of substrate 100 that has undergone the first polishing treatment.

[0169] In some examples, the first deposition process and the first diffusion process can be performed without the second deposition process and the second diffusion process; in other examples, the first deposition process and the first diffusion process can be performed first, followed by the second deposition process and the second diffusion process. In both of these examples, controlling the time interval between the end of the first polishing process and the start of the first deposition process to be less than or equal to 60 minutes is beneficial in avoiding the production of semi-finished batteries or support structures 101 (see reference). Figure 2 During this period, excessive water vapor is adsorbed to avoid the subsequent formation of the first dielectric layer 114 (reference). Figure 6 The thickness of the first doped layer 113 is too thick, which is beneficial for forming a first doped layer with a lower oxygen content (reference). Figure 7 ).

[0170] In some other examples, a second deposition process and a second diffusion process can be performed without the first deposition process and the first diffusion process. Based on this, controlling the time interval between the end of the first polishing process and the start of the second deposition process to be less than or equal to 60 minutes helps avoid damage to the semi-finished battery or the support structure 101 (see reference). Figure 2 This period of time allows for the adsorption of excessive water vapor to prevent the subsequent formation of the second dielectric layer 124 (reference). Figure 9 The thickness of the layer is too thick, and it is beneficial to form a second doped layer with less oxygen content 123 (reference). Figure 10 ).

[0171] In some cases, refer to Figure 14 , Figure 14 This is a partial cross-sectional view of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after the formation of a first semiconductor film. After the formation of the first semiconductor layer 115 and before the first diffusion process, the photovoltaic cell manufacturing method may further include: performing at least one third deposition process including a fifth stage and a sixth stage, forming a first dielectric film 134 in the fifth stage, forming a first semiconductor film 135 on the side of the first dielectric film 134 away from the substrate 100 in the sixth stage, controlling the time for forming the first dielectric film 134 to be less than the time for forming the first dielectric layer 114, and the time for forming the first dielectric film 134 to be less than or equal to 500s.

[0172] It is worth noting that before forming the first semiconductor layer 115, a first dielectric layer 114 has already been formed on the surface 10. The first dielectric layer 114 and the first semiconductor layer 115 constitute a first stacked structure. Based on this, a first dielectric film 134 and a first semiconductor film 135 constitute a second stacked structure. At least one second stacked structure can also be formed on at least the side of the first stacked structure away from the substrate 100. The first stacked structure and at least one second stacked structure will subsequently undergo a first diffusion process together, ultimately forming a P-type stacked structure on the third region 130 or the fourth region 140 to improve the passivation effect on the substrate 100; the oxide layer 102 corresponding to the P-type stacked structure (see reference) Figure 11 It includes not only the first dielectric layer 114 but also at least one first dielectric film 134.

[0173] Based on this, the time for forming the first dielectric film 134 is controlled to be less than the time for forming the first dielectric layer 114, and the time for forming the first dielectric film 134 is less than or equal to 500s. In the first direction X, this is beneficial to make the thickness of the first dielectric film 134 less than the thickness of the first dielectric layer 114, avoiding the first dielectric film 134 from being too thick, thereby reducing the difficulty of subsequent diffusion of doped elements into the substrate 100, and making the substrate 100 have good electrical performance.

[0174] In some examples, the thickness of the first dielectric film 134 in the first direction X can be less than 1 nm.

[0175] In some examples, the sixth stage may also include: introducing nitrogen and silane into the reaction chamber used to prepare the first semiconductor film 135, controlling the ratio of nitrogen gas flow rate to silane gas flow rate to be 0.7~1, which is beneficial to improve the dilution effect of nitrogen on silane and avoid excessive collision of gaseous silane to form clusters or particles, thereby improving the density of the prepared first semiconductor film 135. During the subsequent first diffusion process, the first semiconductor film 135 is transformed into a first doped film (not shown in the figure), which can avoid excessive erosion of the first doped film by the subsequent patterning process, ensuring the good film quality of the final retained first doped film, thereby improving the yield of photovoltaic cells.

[0176] In some cases, refer to Figure 15 , Figure 15This is a partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method provided in an embodiment of the present disclosure after the formation of the second semiconductor film. After the formation of the second semiconductor layer 125 and before the second diffusion process, the photovoltaic cell manufacturing method may further include: performing at least one fourth deposition process including a seventh stage and an eighth stage, forming a second dielectric film 144 in the seventh stage, forming a second semiconductor film 145 on the side of the second dielectric film 144 away from the substrate 100 in the eighth stage, controlling the time for forming the second dielectric film 144 to be less than the time for forming the second dielectric layer 124, and the time for forming the second dielectric film 144 to be less than or equal to 500s.

[0177] It is worth noting that before forming the second semiconductor layer 125, a second dielectric layer 124 has already been formed on the surface 10. The second dielectric layer 124 and the second semiconductor layer 125 constitute a third stacked structure. Based on this, a second dielectric film 144 and a second semiconductor film 145 constitute a fourth stacked structure. At least one fourth stacked structure can also be formed on at least the side of the third stacked structure away from the substrate 100. The third stacked structure and at least one fourth stacked structure will subsequently undergo a second diffusion process together, ultimately forming an N-type stacked structure on the third region 130 or the fourth region 140 to improve the passivation effect on the substrate 100; the oxide layer 102 formed corresponding to the N-type stacked structure (see reference) Figure 11 It includes not only the second dielectric layer 124 but also at least one second dielectric film 144.

[0178] Based on this, the time for forming the second dielectric film 144 is controlled to be less than the time for forming the second dielectric layer 124, and the time for forming the second dielectric film 144 is less than or equal to 500s. In the first direction X, this is beneficial to make the thickness of the formed second dielectric film 144 less than the thickness of the second dielectric layer 124, avoiding the second dielectric film 144 from being too thick, thereby reducing the difficulty of subsequent diffusion of doped elements into the substrate 100, and making the substrate 100 have good electrical performance.

[0179] In some examples, the thickness of the second dielectric film 144 in the first direction X can be less than 1 nm.

[0180] In some examples, the eighth stage may also include: introducing nitrogen and silane into the reaction chamber used to prepare the second semiconductor film 145, controlling the ratio of nitrogen gas flow rate to silane gas flow rate to be 0.7~1, which is beneficial to improve the density of the prepared second semiconductor film 145. During the subsequent second diffusion process, the second semiconductor film 145 is transformed into a second doped film (not shown in the figure), which can avoid excessive erosion of the second doped film by the subsequent patterning process, so as to ensure the good film quality of the final retained second doped film, thereby improving the yield of photovoltaic cells.

[0181] It should be noted that in the same photovoltaic cell, both the P-type stacked structure and the N-type stacked structure can include multi-layer stacked structures, or one can include multi-layer stacked structures while the other includes only one-layer stacked structure.

[0182] Furthermore, regardless of which stage in the aforementioned embodiments nitrogen and silane are introduced into the reaction chamber, there can be multiple pipelines for both nitrogen and silane. The ratio of nitrogen flow rate to silane flow rate being controlled at 0.7 to 1 means that the average nitrogen flow rate from multiple nitrogen-introducing pipelines is equal to the average nitrogen flow rate from multiple silane-introducing pipelines. In practical applications, the ratio of nitrogen flow rate to silane flow rate from a single pipeline can be 0.7 to 1, or it can be adjusted to other values, as long as the average value remains between 0.7 and 1. For example, the ratio can also be between 0.5 and 1.5.

[0183] The following provides a detailed description of the depth to which the P-type dopant extends into the substrate 100.

[0184] In some cases, in conjunction with references Figure 6 and Figure 7 In the first diffusion process, the dopant element is a p-type dopant element, and the diffusion of the p-type dopant element into the substrate 100 is controlled, with the diffusion depth of the p-type dopant element into the substrate 100 being 15 nm to 45 nm. In other words, the diffusion depth of the p-type dopant element in the substrate 100 can be 15 nm to 45 nm.

[0185] It should be noted that all the above-mentioned methods of controlling the thickness of oxide layer 102 are conducive to promoting the inward expansion of p-type dopant elements into the substrate 100 to a depth of 15nm~45nm, so as to ensure that the substrate 100 has good electrical performance.

[0186] It is worth noting that the current benchmark for the diffusion concentration of dopant elements in substrate 100 mainly includes the following two cases: In some cases, the benchmark for the diffusion concentration of p-type dopant elements in substrate 100 is set as 1 × 10⁻⁶. 19 atom / cm 3 The diffusion depth of the p-type dopant in the substrate 100 can be 15 nm to 25 nm, for example, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, or 25 nm, etc.; in other cases, the baseline for the diffusion concentration of the p-type dopant in the substrate 100 is set to 1 × 10⁻⁶. 18 atom / cm3 The diffusion depth of the p-type dopant in the substrate 100 can be 35nm~45nm, for example, it can be 35nm, 36nm, 37nm, 38nm, 39nm, 40nm, 41nm, 42nm, 43nm, 44nm or 45nm, etc.

[0187] In some cases, in conjunction with references Figure 9 and Figure 10 or in conjunction with references Figure 12 and Figure 13 In the second diffusion process, the dopant element is an N-type dopant element, and the diffusion of the N-type dopant element into the substrate 100 is controlled to a depth of 55 nm to 165 nm. In other words, the diffusion depth of the N-type dopant element in the substrate 100 can be 55 nm to 165 nm.

[0188] It should be noted that all the above-mentioned methods of controlling the thickness of oxide layer 102 are conducive to promoting the inward expansion of N-type dopant elements into the substrate 100 to a depth of 55nm~165nm, so as to ensure that the substrate 100 has good electrical performance.

[0189] It is worth noting that the current benchmark for the diffusion concentration of dopant elements in substrate 100 mainly includes the following two cases: In some cases, the benchmark for the diffusion concentration of N-type dopant elements in substrate 100 is set to 1×10¹⁹ atom / cm³, and the diffusion depth of N-type dopant elements in substrate 100 can be 55nm~65nm, for example, 55nm, 56nm, 57nm, 58nm, 59nm, 60nm, 61nm, 62nm, 63nm, 64nm or 65nm, etc.; In other cases, the benchmark for the diffusion concentration of P-type dopant elements in substrate 100 is set to 1×10¹⁸ atom / cm³, and the diffusion depth of N-type dopant elements in substrate 100 can be 155nm~165nm, for example, 155nm, 156nm, 157nm, 158nm, 159nm, 160nm, 161nm, 162nm, 163nm, 164nm or 165nm, etc.

[0190] In some cases, refer to Figure 11 The oxide layer 102 may include a first dielectric layer 114 and a second dielectric layer 124, and the doped layer 103 may include a first doped layer 113 and a second doped layer 123; the first diffusion process may include a first oxygen-free annealing and a first oxygen-containing annealing connected in sequence, and the second diffusion process may include a second oxygen-free annealing and a second oxygen-containing annealing connected in sequence.

[0191] In some examples, the process temperature of the first oxygen-free annealing can be greater than or equal to the process temperature of the second oxygen-free annealing.

[0192] In one example, the process temperature for the first oxygen-free annealing can be 950℃~980℃, for example, 950℃, 960℃, 970℃ or 980℃; the process temperature for the second oxygen-free annealing can be 880℃~950℃, for example, 880℃, 890℃, 900℃, 910℃, 920℃, 930℃, 940℃ or 950℃.

[0193] In some examples, the process time for the first oxygen-free annealing may be less than or equal to the process time for the second oxygen-free annealing.

[0194] In one example, the process time for the first oxygen-free annealing can be 500s to 1000s, for example, 500s, 600s, 700s, 800s, 900s, or 1000s; the process time for the second oxygen-free annealing can be 1000s to 1400s, for example, 1000s, 1100s, 1200s, 1300s, or 1400s.

[0195] In some examples, the process temperature of the first aerobic annealing can be greater than or equal to the process temperature of the second aerobic annealing.

[0196] In one example, the process temperature for the first aerobic annealing can be 950℃~980℃; the process temperature for the second aerobic annealing can be 880℃~950℃.

[0197] In one example, the process time for the first aerobic annealing can be 1000s to 2000s, for example, 1000s, 1100s, 1200s, 1300s, 1400s, 1500s, 1600s, 1700s, 1800s, 1900s, or 2000s, etc.; the process time for the second aerobic annealing can be greater than 1400s, for example, 1500s, 1600s, 1700s, 1800s, or 2000s, etc.

[0198] It should be noted that the setting of relevant process parameters in each stage of the first diffusion process and the second diffusion process is conducive to forming the first doped layer 113 and the second doped layer 123 with the required thickness and doping concentration.

[0199] In some embodiments, reference Figure 7 , Figure 11 or Figure 13The processes for forming the oxide layer 102 and the doped layer 103 can both be LPCVD (Low Pressure Chemical Vapor Deposition) processes.

[0200] In some embodiments, reference Figure 7 or Figure 11 The first doped layer 113 is doped with a P-type dopant element, and the doping concentration of the P-type dopant element in the first doped layer 113 can be 4 × 10⁻⁶. 19 atom / cm 3 ~7×10 19 atom / cm 3 For example, it can be 4×10 19 atom / cm 3 5×10 19 atom / cm 3 7×10 19 atom / cm 3 Or 8×10 19 atom / cm 3 wait.

[0201] In some embodiments, reference Figure 11 or Figure 13 The second doped layer 123 is doped with an N-type dopant element, and the doping concentration of the N-type dopant element in the second doped layer 123 can be 3 × 10⁻⁶. 20 atom / cm 3 ~7×10 20 atom / cm 3 For example, it can be 3×10 20 atom / cm 3 4×10 20 atom / cm 3 5×10 20 atom / cm 3 6×10 20 atom / cm 3 Or 7×10 20 atom / cm 3 wait.

[0202] In summary, on the one hand, in the step of forming the semiconductor layer 105, the ratio of nitrogen gas flow rate to silane gas flow rate can be controlled to be 0.7~1. Increasing the nitrogen gas flow rate enhances the dilution effect of nitrogen on silane, preventing excessive collisions of gaseous silane to form clusters or particles, thereby increasing the density of the prepared semiconductor layer 105. This, in turn, can improve the density of the doped layer 103 formed subsequently based on the semiconductor layer 105, and prevent excessive etching of the doped layer 103 by subsequent patterning processes, such as avoiding etching of the first region 110. To prevent excessive etching of the doped layer 103, ensuring good film quality of the ultimately retained doped layer 103; on the other hand, designing the ratio of oxygen annealing time to oxygen-free annealing time to be greater than 1 is beneficial for improving the density of the portion of the protective layer 106 near the substrate 100 through longer oxygen annealing time. This enhances the protective effect of the protective layer 106 on the doped layer 103 during subsequent patterning steps, preventing excessive etching of the doped layer 103 that needs to be retained, such as avoiding excessive etching of the doped layer 103 located in the first region 110. Thus, during EL or PL testing of photovoltaic cells, controlling the density of the protective layer 106 and / or the semiconductor layer 105 helps avoid the problem of blackening of the first region 110 caused by excessive etching of the retained doped layer 103, thereby improving the yield of photovoltaic cells.

[0203] Another embodiment of this disclosure provides a photovoltaic cell, formed by the manufacturing method of the photovoltaic cell provided in the foregoing embodiments. The photovoltaic cell provided in another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that parts that are the same as or corresponding to those in the foregoing embodiments will not be repeated here.

[0204] refer to Figure 7 , Figure 11 or Figure 13 The photovoltaic cell can be formed by the photovoltaic cell manufacturing method provided in the foregoing embodiments.

[0205] In some embodiments, reference Figure 7 , Figure 11 or Figure 13 The photovoltaic cell may further include an oxide layer 102 located between the substrate 100 and the doped layer 103, wherein the thickness of the oxide layer 102 in the first region 110 is less than 1.7 nm in a first direction, where the first direction X is the thickness direction of the substrate 100. This allows for the reduction of the difficulty in diffusion of dopants from the doped layer 103 into the substrate 100 in the first region 110 by utilizing the thinner oxide layer 102 in the first region 110, thereby improving the electrical performance of the substrate 100 in the first region 110. Subsequently, after forming electrodes on the substrate 100, the transport resistance during the transport of photogenerated carriers from the substrate 100 in the first region 110 to the electrodes is reduced.

[0206] In some embodiments, the photovoltaic cell is a cell with electrodes on both sides, and the photovoltaic cell may further include: an oxide layer 102 located between the substrate 100 and the doped layer 103. In some cases, refer to Figure 7 The oxide layer 102 may include a first oxide layer 112 and a first dielectric layer 114 stacked along the first direction X, and the doped layer 103 may include a first doped layer 113 located on the side of the first dielectric layer 114 away from the substrate 100; or, in other cases, refer to Figure 13 The oxide layer 102 may include a second oxide layer 122 and a second dielectric layer 124 stacked along the first direction X, and the doped layer 103 may include a second doped layer 123 located on the side of the second dielectric layer 124 away from the substrate 100.

[0207] In other embodiments, the photovoltaic cell is a cell with electrodes on one side only; see reference. Figure 11 Surface 10 may include a third region 130 and a fourth region 140 alternately arranged along the second direction Y, with a portion of the first region 110 located in the third region 130 and a portion of the first region 110 located in the fourth region 140; oxide layer 102 includes a first oxide layer 112 and a first dielectric layer 114 located on one of the third region 130 and the fourth region 140, and a second oxide layer 122 and a second dielectric layer 124 located on the other of the third region 130 and the fourth region 140; doped layer 103 includes a first doped layer 113 located on the side of the first dielectric layer 114 away from the substrate 100, and a second doped layer 123 located on the side of the second dielectric layer 124 away from the substrate 100, wherein the first doped layer 113 and the second doped layer 123 are doped with different types of doping elements.

[0208] The first oxide layer 112 and the first dielectric layer 114 located on one of the third region 130 and the fourth region 140 can be regarded as the first tunneling layer, and the second oxide layer 122 and the second dielectric layer 124 located on the other of the third region 130 and the fourth region 140 can be regarded as the second tunneling layer.

[0209] It should be noted that in practical applications, the first oxide layer and the second oxide layer can also be removed, so that the oxide layer includes the first dielectric layer and / or the second dielectric layer.

[0210] In some examples, reference Figure 11The first doped layer 113 is doped with a P-type dopant, and the second doped layer 123 is doped with an N-type dopant. Along the first direction X, the thickness of the first doped layer 113 can be greater than the thickness of the second doped layer 123. Thus, on the one hand, compared to the second doped layer 123, the thicker first doped layer 113 can generate a stronger electric field to drive hole migration, compensating for the difference between electron and hole mobility; on the other hand, compared to the second doped layer 123, the thicker first doped layer 113 can reduce the risk of the electrode burning through the first doped layer 113 during electrode fabrication.

[0211] In some embodiments, reference Figure 7 or Figure 11 The first doped layer 113 is doped with a P-type dopant element, and the doping concentration of the P-type dopant element in the first doped layer 113 is 4 × 10⁻⁶. 19 atom / cm 3 ~7×10 19 atom / cm 3 This is to ensure that the first doped layer 113 provides good passivation for the substrate 100.

[0212] In some embodiments, reference Figure 11 or Figure 13 The second doped layer 123 is doped with an N-type dopant element, and the doping concentration of the N-type dopant element in the second doped layer 123 is 3 × 10⁻⁶. 20 atom / cm 3 ~7×10 20 atom / cm 3 This is to ensure that the second doped layer 123 provides good passivation for the substrate 100.

[0213] In some embodiments, reference Figure 11 Along the first direction X, the thickness of the first doped layer 113 can be 190nm~330nm, for example, it can be 190nm, 200nm, 210nm, 220nm, 230nm, 240nm, 250nm, 260nm, 270nm, 280nm, 290nm, 300nm, 310nm, 320nm or 330nm, etc.; the thickness of the second doped layer 123 can be 160nm~300nm, for example, it can be 160nm, 170nm, 180nm, 190nm, 200nm, 210nm, 220nm, 230nm, 240nm, 250nm, 260nm, 270nm, 280nm, 290nm or 300nm, etc.

[0214] Another embodiment of this disclosure provides a photovoltaic module, which will be described in detail below with reference to the accompanying drawings. It should be noted that parts that are the same as or corresponding to those in the foregoing embodiments will not be repeated here.

[0215] Reference Figure 7 , Figure 11 , Figure 13 , Figure 16 and Figure 17 A photovoltaic module includes: a battery string, which is formed by connecting multiple photovoltaic cells 40 provided in the foregoing embodiments, or by connecting multiple photovoltaic cells 40 formed by the manufacturing method of photovoltaic cells provided in the foregoing embodiments; an encapsulating film 41 for covering the surface of the battery string; and a cover plate 42 for covering the surface of the encapsulating film 41 facing away from the battery string.

[0216] It should be noted that, Figure 16 A partial three-dimensional schematic diagram of a cell string in a photovoltaic module provided in yet another embodiment of this disclosure; Figure 17 This is a partial cross-sectional schematic diagram of a photovoltaic module provided in yet another embodiment of this disclosure. Furthermore, Figure 16 and Figure 17 The example used here is a BC photovoltaic cell with a capacity of 40.

[0217] In some embodiments, the photovoltaic cell 40 includes, but is not limited to, one or any combination of PERC cells, BC cells, TOPCON cells, HIT / HJT cells, thin-film solar cells, and tandem cells. BC cells include, but are not limited to, IBC cells (Interdigitated Back Contact), HBC cells (Heterojunction Back Contact), TBC cells (TOPCon Back Contact), or HTBC cells (Hybrid Passivated Back Contact). HTBC cells are heterojunction and tunnel oxide passivated contact hybrid back contact photovoltaic cells (HTBC).

[0218] It should be noted that multiple photovoltaic cells 40 can be electrically connected to each other via solder strips 43. Figure 16 and Figure 17Taking photovoltaic cell 40 as an example of a BC cell, and illustrating only one positional relationship between photovoltaic cells 40, that is, the side of each photovoltaic cell 40 with electrodes is arranged facing the same side, so that the conductive strip 43 connects the same side of two adjacent photovoltaic cells 40 respectively. In other embodiments, the photovoltaic cells may also be arranged such that the electrodes of two adjacent photovoltaic cells are located on different sides, in which case the conductive strip connects the different sides of the two adjacent photovoltaic cells.

[0219] In some embodiments, the photovoltaic cells 40 are electrically connected in the form of a single cell or multiple segments to form multiple cell strings, and the multiple cell strings are electrically connected in series and / or parallel. The photovoltaic cells 40 can be a single cell or a sliced ​​cell, where a sliced ​​cell refers to a cell formed by cutting a complete single cell.

[0220] In some embodiments, the encapsulating film 41 includes a first encapsulating layer and a second encapsulating layer. The first encapsulating layer covers one of the front or back sides of the photovoltaic cell 40, and the second encapsulating layer covers the other of the front or back sides of the photovoltaic cell 40. Specifically, at least one of the first or second encapsulating layer can be an organic encapsulating film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene elastomer (POE) film, or polyethylene terephthalate (PET) film. Alternatively, at least one of the first or second encapsulating layer can also be an EP film, an EPE film, or a PVP film. Here, EP film refers to a co-extruded film composed of stacked EVA film and POE film; EPE film refers to a co-extruded film formed by sequentially stacking EVA film + POE film + EVA film; and PVP film refers to a co-extruded film formed by stacking POE film + EVA film + POE film. Co-extruded films can be prepared by sequentially extruding one or more raw materials onto another pre-made film during the film processing, or by bonding different types of pre-made films together.

[0221] In some cases, the first encapsulation layer and the second encapsulation layer still have a boundary line before lamination. After lamination, the photovoltaic module will no longer have the concept of a first encapsulation layer and a second encapsulation layer. That is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 41.

[0222] In some embodiments, the cover plate 42 can be a glass cover plate, a plastic cover plate, or other cover plate with light-transmitting function. Specifically, the surface of the cover plate 42 facing the encapsulating film 41 can be an uneven surface or a textured surface containing multiple raised structures, thereby increasing the utilization rate of incident light. The cover plate 42 includes a first cover plate and a second cover plate, the first cover plate being opposite to the first encapsulation layer, and the second cover plate being opposite to the second encapsulation layer.

[0223] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for manufacturing a photovoltaic cell, characterized in that, include: The substrate is placed in a supporting structure, and at least one surface of the substrate includes a plurality of first regions spaced apart from each other, the first regions being located at the edges of the surface; A semiconductor layer is formed on the surface; A diffusion process is performed on the semiconductor layer to convert it into a doped layer, and a protective layer is formed on the side of the doped layer away from the substrate. In the step of forming the semiconductor layer, nitrogen and silane are introduced into the reaction chamber used to prepare the semiconductor layer, and the ratio of the nitrogen gas flow rate to the silane gas flow rate is controlled to be 0.7~1; and / or, the diffusion process includes sequential oxygen-free annealing and oxygen-enriched annealing, wherein the ratio of the oxygen-enriched annealing duration to the oxygen-free annealing duration is greater than 1.

2. The method for manufacturing a photovoltaic cell according to claim 1, characterized in that, The surface includes a third region and a fourth region alternately arranged along a second direction, with a portion of the first region located in the third region and a portion of the first region located in the fourth region; The method for manufacturing the photovoltaic cell further includes: removing the protective layer located on one of the third region and the fourth region; Using the protective layer located on the other of the third and fourth regions as a mask, at least the doped layer not covered by the mask is removed.

3. The method for manufacturing a photovoltaic cell according to claim 2, characterized in that, The steps of forming the semiconductor layer and performing the diffusion process include: forming a first semiconductor layer on the surface, performing a first diffusion process on the first semiconductor layer to convert the first semiconductor layer into a first doped layer, and forming a first protective layer on the side of the first doped layer away from the substrate; forming a second semiconductor layer on the surface, performing a second diffusion process on the second semiconductor layer to convert the second semiconductor layer into a second doped layer, and forming a second protective layer on the side of the second doped layer away from the substrate. The method for manufacturing the photovoltaic cell, after forming the first protective layer and before forming the second semiconductor layer, further includes: removing the first protective layer located on one of the third region and the fourth region; using the first protective layer located on the other of the third region and the fourth region as a first mask, removing at least the first doped layer not covered by the first mask; and forming the second semiconductor layer on the surface formed by the remaining first doped layer and the substrate. After forming the second protective layer, the method for manufacturing the photovoltaic cell further includes: removing the second protective layer located on the other of the third region and the fourth region; using the second protective layer located on the other of the third region and the fourth region as a second mask, removing at least the second doped layer that is not covered by the second mask.

4. The method for manufacturing a photovoltaic cell according to claim 1, characterized in that, The protective layer and the doped layer are doped with the same type of doping element. The protective layer includes a first layer and a second layer stacked along a first direction. The doping concentration of the doping element in the first layer is less than that in the second layer, and the density of the first layer is higher than that of the second layer. The first direction is the thickness direction of the substrate.

5. The method for manufacturing a photovoltaic cell according to claim 1, characterized in that, Before forming the semiconductor layer, the method further includes forming an oxide layer between the substrate and the semiconductor layer, wherein the thickness of the oxide layer located in the first region is controlled to be less than 1.7 nm in a first direction, wherein the first direction is the thickness direction of the substrate.

6. The method for manufacturing a photovoltaic cell according to claim 1, characterized in that, Prior to forming the semiconductor layer, the method further includes forming an oxide layer between the substrate and the semiconductor layer; The step of forming the oxide layer includes at least: performing a first polishing treatment on the substrate, wherein at least during the first polishing treatment, the moisture content of the environment in which the substrate is located is controlled to be 6 g / kg to 12 g / kg, so as to form a first oxide layer on the surface of the substrate that has undergone the first polishing treatment.

7. The method for manufacturing a photovoltaic cell according to claim 1, characterized in that, Prior to forming the semiconductor layer, the method further includes forming an oxide layer between the substrate and the semiconductor layer; The steps of forming the oxide layer and the semiconductor layer include at least: employing a first deposition process including a first stage and a second stage, forming a first dielectric layer in the first stage, and forming a first semiconductor layer on the side of the first dielectric layer away from the substrate in the second stage to obtain a first semi-finished product; the diffusion process includes at least: performing a first diffusion process on the first semi-finished product to convert the first semiconductor layer into a first doped layer, and forming a first protective layer on the side of the first doped layer away from the substrate; And / or, the steps of forming the oxide layer and the semiconductor layer include at least: employing a second deposition process including a third stage and a fourth stage, forming a second dielectric layer in the third stage, and forming a second semiconductor layer on the side of the second dielectric layer away from the substrate in the fourth stage to obtain a second semi-finished product; the diffusion process includes at least: performing a second diffusion process on the second semi-finished product to convert the second semiconductor layer into a second doped layer, and forming a second protective layer on the side of the second doped layer away from the substrate; The oxide layer includes the first dielectric layer and / or the second dielectric layer, and the doped layer includes the first doped layer and / or the second doped layer, wherein the first doped layer and the second doped layer are doped with different types of doping elements.

8. The method for manufacturing a photovoltaic cell according to claim 7, characterized in that, During the steps of performing the first deposition process, the first diffusion process, the second deposition process, and / or the second diffusion process, the idle time of the supporting structure is controlled to be less than or equal to 120 minutes. And / or, during the steps of the first deposition process, the first diffusion process, the second deposition process and / or the second diffusion process, if the idle time of the support structure is greater than 120 minutes, the support structure is baked to reduce the amount of water adsorbed by the support structure during the idle period.

9. The method for manufacturing a photovoltaic cell according to claim 7, characterized in that, Semi-finished photovoltaic cells in the manufacturing process are treated as unfinished products to be picked up. During the process of transporting the unfinished products to be picked up or transporting the supporting structure with a paddle, the idle time of the paddle is controlled to be less than or equal to 30 minutes; and / or, if the idle time of the paddle is greater than 30 minutes, the paddle is subjected to a baking treatment to reduce the amount of water absorbed by the paddle during the idle period.

10. The method for manufacturing a photovoltaic cell according to claim 7, characterized in that, The surface includes a third region and a fourth region alternately arranged along a second direction, a portion of the first region is located in the third region, a portion of the first region is located in the fourth region, the second direction intersects the first direction, and the first direction is the thickness direction of the substrate; the oxide layer includes a first dielectric layer and a second dielectric layer, and the doped layer includes a first doped layer and a second doped layer; After forming the first doped layer and before forming the second dielectric layer, the method for manufacturing the photovoltaic cell further includes: The first dielectric layer and the first doped layer are patterned to remove the first dielectric layer and the first doped layer located in the third region or the fourth region and expose the substrate. At least during the patterning process, the humidity of the environment in which the substrate is located is controlled to be 6 g / kg to 12 g / kg so as to form a second oxide layer on the surface of the substrate that has undergone the patterning process, and then the second deposition process is performed.

11. The method for manufacturing a photovoltaic cell according to claim 10, characterized in that, Before performing the first deposition process, the step of forming the oxide layer further includes: performing a first polishing treatment on the substrate, and forming a first oxide layer on the surface of the substrate that has undergone the first polishing treatment; Wherein, along the first direction, the thickness of the first oxide layer is less than the thickness of the second oxide layer; and / or, the total thickness of the first oxide layer and the first dielectric layer is less than the total thickness of the second oxide layer and the second dielectric layer.

12. The method for manufacturing a photovoltaic cell according to claim 7, characterized in that, The surface includes a third region and a fourth region alternately arranged along a second direction, a portion of the first region is located in the third region, a portion of the first region is located in the fourth region, the second direction intersects the first direction, and the first direction is the thickness direction of the substrate; the oxide layer includes a first dielectric layer and a second dielectric layer, and the doped layer includes a first doped layer and a second doped layer; After forming the first doped layer and before forming the second dielectric layer, the method for manufacturing the photovoltaic cell further includes: The first dielectric layer and the first doped layer are patterned to remove the first dielectric layer and the first doped layer located in the third region or the fourth region, and the time interval between the end of the patterning process and the start of the second deposition process is controlled to be less than or equal to 60 minutes.

13. The method for manufacturing a photovoltaic cell according to claim 10 or 12, characterized in that, In the first diffusion process, the doping element is a P-type doping element; in the second diffusion process, the doping element is an N-type doping element. Wherein, the deposition temperature for forming the first semiconductor layer is lower than the deposition temperature for forming the second semiconductor layer; and / or, the crystallinity of the first semiconductor layer is lower than the crystallinity of the second semiconductor layer; and / or, along the first direction, the thickness of the first semiconductor layer is greater than the thickness of the second semiconductor layer.

14. The method for manufacturing a photovoltaic cell according to claim 7, characterized in that, Before performing the first deposition process or before performing the second deposition process, the step of forming the oxide layer further includes: performing a first polishing treatment on the substrate, and forming a first oxide layer on the surface of the substrate that has undergone the first polishing treatment; Wherein, the time interval between the end of the first polishing process and the start of the first deposition process is controlled to be less than or equal to 60 minutes, or the time interval between the end of the first polishing process and the start of the second deposition process is controlled to be less than or equal to 60 minutes.

15. The method for manufacturing a photovoltaic cell according to claim 7, characterized in that, After forming the first semiconductor layer and before performing the first diffusion process, the method for manufacturing the photovoltaic cell further includes: performing at least one third deposition process comprising a fifth stage and a sixth stage, forming a first dielectric film in the fifth stage, forming a first semiconductor film on the side of the first dielectric film away from the substrate in the sixth stage, controlling the time for forming the first dielectric film to be less than the time for forming the first dielectric layer, and controlling the time for forming the first dielectric film to be less than or equal to 500 s; and / or, After the second semiconductor layer is formed and before the second diffusion process is performed, the method for manufacturing the photovoltaic cell further includes: performing at least one fourth deposition process including a seventh stage and an eighth stage, forming a second dielectric film in the seventh stage, forming a second semiconductor film on the side of the second dielectric film away from the substrate in the eighth stage, controlling the time for forming the second dielectric film to be less than the time for forming the second dielectric layer, and the time for forming the second dielectric film to be less than or equal to 500s.

16. The method for manufacturing a photovoltaic cell according to claim 7, characterized in that, In the first diffusion process, the dopant element is a P-type dopant element, and the P-type dopant element is controlled to diffuse into the substrate, with the depth of the P-type dopant element in the substrate being 15nm~45nm; and / or, in the second diffusion process, the dopant element is an N-type dopant element, and the N-type dopant element is controlled to diffuse into the substrate, with the depth of the N-type dopant element in the substrate being 55nm~165nm.

17. The method for manufacturing a photovoltaic cell according to claim 7, characterized in that, The oxide layer includes a first dielectric layer and a second dielectric layer, and the doped layer includes a first doped layer and a second doped layer; the first diffusion process includes a first oxygen-free annealing and a first oxygen-containing annealing connected in sequence, and the second diffusion process includes a second oxygen-free annealing and a second oxygen-containing annealing connected in sequence. Wherein, the process temperature of the first oxygen-free annealing is greater than or equal to the process temperature of the second oxygen-free annealing; and / or, the process duration of the first oxygen-free annealing is less than or equal to the process duration of the second oxygen-free annealing; and / or, the process temperature of the first aerobic annealing is greater than or equal to the process temperature of the second aerobic annealing.

18. The method for manufacturing a photovoltaic cell according to claim 1, characterized in that, The area on the surface other than the first region is the second region; Before forming the semiconductor layer, the method further includes forming an oxide layer between the substrate and the semiconductor layer, and controlling the difference between the thickness of the oxide layer located in the first region and the thickness of the oxide layer located in the second region to be less than or equal to 0.35 nm.

19. A photovoltaic cell, characterized in that, Formed by the manufacturing method of a photovoltaic cell as described in any one of claims 1 to 18.

20. The photovoltaic cell according to claim 19, characterized in that, Also includes: An oxide layer is located between the substrate and the doped layer, and the thickness of the oxide layer in the first region is less than 1.7 nm in a first direction, where the first direction is the thickness direction of the substrate.

21. The photovoltaic cell according to claim 19, characterized in that, Also includes: An oxide layer is located between the substrate and the doped layer; Wherein, the oxide layer includes a first oxide layer and a first dielectric layer stacked along a first direction, and the doped layer includes a first doped layer located on the side of the first dielectric layer away from the substrate; and / or, the oxide layer includes a second oxide layer and a second dielectric layer stacked along the first direction, and the doped layer includes a second doped layer located on the side of the second dielectric layer away from the substrate.

22. The photovoltaic cell according to claim 21, characterized in that, The surface includes a third region and a fourth region alternately arranged along a second direction, with a portion of the first region located in the third region and a portion of the first region located in the fourth region; The oxide layer includes a first oxide layer and a first dielectric layer located on one of the third region and the fourth region, and a second oxide layer and a second dielectric layer located on the other of the third region and the fourth region; The doped layer includes a first doped layer located on the side of the first dielectric layer away from the substrate, and a second doped layer located on the side of the second dielectric layer away from the substrate, wherein the first doped layer and the second doped layer are doped with different types of doping elements.

23. The photovoltaic cell according to claim 22, characterized in that, The first doped layer is doped with a P-type dopant element, and the second doped layer is doped with an N-type dopant element. Along the first direction, the thickness of the first doped layer is greater than the thickness of the second doped layer.

24. The photovoltaic cell according to claim 21, characterized in that, The first doped layer is doped with a p-type dopant, and the doping concentration of the p-type dopant in the first doped layer is 4 × 10⁻⁶. 19 atom / cm 3 ~7×10 19 atom / cm 3 ; and / or, the second doped layer is doped with an N-type dopant element, the doping concentration of the N-type dopant element in the second doped layer being 3 × 10⁻⁶. 20 atom / cm 3 ~7×10 20 atom / cm 3 .

25. A photovoltaic module, characterized in that, include: A battery string is formed by connecting multiple photovoltaic cells manufactured by any one of the photovoltaic cells as described in any one of claims 1 to 18, or by connecting multiple photovoltaic cells as described in any one of claims 19 to 24; An encapsulating film is used to cover the surface of the battery string; A cover plate is used to cover the surface of the encapsulating film that faces away from the battery string.

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