Semiconductor structure and method of forming the same, electronic device

Abstract

The embodiment of the present disclosure provides a semiconductor structure and a forming method thereof, and an electronic device; wherein the forming method of the semiconductor structure comprises the following steps: providing a substrate; the substrate comprises a plurality of storage areas arranged along a first direction; forming a stack structure on the surface of the storage area; the stack structure comprises a plurality of transistors arranged along a second direction and a third direction and extending along the first direction; at least one layer of transistors from top to bottom along the third direction are all serving as selection transistors; etching the stack structure to form a first etching groove extending along the second direction; the first etching groove exposes the source of all the selection transistors in the stack structure; forming a first isolation structure in the first etching groove, and a plurality of selectors arranged along the second direction in the first isolation structure; each selector is connected with the source of the selection transistors arranged along the third direction and does not penetrate through the first isolation structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and relates to but is not limited to a semiconductor structure and a forming method thereof, and an electronic device. BACKGROUND

[0002] Bit line selection transistors are used to select bit lines in a memory array to reduce the capacitance-resistance of the bit lines to affect data reading.

[0003] In the related art, as the semiconductor process node continues to shrink, the distance between the bit line selection transistor and the capacitor structure gradually decreases, thereby increasing the coupling between the bit line selection transistor and the capacitor structure, that is, increasing the coupling of the bit line selection transistor to the ground, and further reducing the accuracy of data reading. Therefore, reducing the coupling between the bit line selection transistor and the capacitor structure is a problem to be solved. SUMMARY

[0004] Therefore, the embodiments of the present disclosure provide a semiconductor structure and a forming method thereof, and an electronic device.

[0005] In a first aspect, the embodiments of the present disclosure provide a forming method of a semiconductor structure, and the method comprises: providing a substrate; the substrate comprises a plurality of memory areas arranged along a first direction; forming a stack structure on a surface of the memory area; the stack structure comprises a plurality of transistors arranged in a second direction and a third direction and extending along the first direction; at least one layer of the transistors from top to bottom along the third direction are all selection transistors; etching the stack structure to form a first etching groove extending along the second direction; the first etching groove exposes the source of all the selection transistors in the stack structure; forming a first isolation structure in the first etching groove, and a plurality of selectors arranged along the second direction in the first isolation structure; each of the selectors is connected with the source of the selection transistor arranged along the third direction and does not penetrate through the first isolation structure; wherein the first direction intersects the second direction and is parallel to the plane where the substrate is located, and the third direction intersects the plane where the substrate is located.

[0006] In some embodiments, forming a first isolation structure in the first etching groove, and a plurality of selectors arranged along the second direction in the first isolation structure comprises: forming an initial first isolation structure in the first etching groove; etching the initial first isolation structure to form a plurality of second etching grooves arranged along the second direction; the remaining initial first isolation structure constitutes the first isolation structure, and each of the second etching grooves exposes the source of the selection transistor arranged along the third direction and does not penetrate the bottom and the side away from the selection transistor of the first isolation structure; forming the selectors in the second etching grooves.

[0007] In some embodiments, forming the initial first isolation structure in the first etching trench comprises: forming at least one initial first sub-isolation structure on the surface exposed by the first etching trench; and forming an initial second sub-isolation structure in the remaining first etching trench; the initial first sub-isolation structure and the initial second sub-isolation structure constitute the initial first isolation structure.

[0008] In some embodiments, etching the initial first isolation structure to form a plurality of second etching trenches arranged along the second direction comprises: etching the initial first sub-isolation structure on the side wall close to the selected transistor, and etching the initial second sub-isolation structure until the bottom surface of the initial first sub-isolation structure is exposed, to form a plurality of the second etching trenches arranged along the second direction; wherein the remaining initial first sub-isolation structure constitutes a first sub-isolation structure, and the remaining initial second sub-isolation structure constitutes a second sub-isolation structure; the first sub-isolation structure and the second sub-isolation structure constitute the first isolation structure.

[0009] In some embodiments, forming the selector in the second etching trench comprises: forming a first contact structure in the second etching trench; the first contact structure is connected to the source of the selected transistor arranged along the third direction, and the top surface of the first contact structure does not exceed the second etching trench; and forming a second contact structure in the remaining second etching trench; the first contact structure and the second contact structure constitute the selector.

[0010] In some embodiments, forming a stack structure on the surface of the memory region comprises: forming an initial stack structure on the surface of the memory region; the initial stack structure comprises an initial semiconductor layer arranged in an array along the second direction and the third direction, and extending along the first direction; etching both sides of the initial semiconductor layer along the first direction, and the remaining initial semiconductor layer constitutes a semiconductor layer; the semiconductor layer comprises a channel structure, and the source and the drain located at both ends of the channel structure along the first direction; a gate dielectric layer and a gate metal layer are sequentially formed on the surface of the channel structure; the gate dielectric layer and the gate metal layer constitute a gate structure; wherein the semiconductor layer and the gate structure constitute the transistor; a plurality of the gate metal layers arranged along the second direction are connected to form a word line structure.

[0011] In some embodiments, the method further comprises: forming a plurality of bit line structures arranged along the second direction; each of the bit line structures is connected to the drain of all the transistors arranged along the third direction.

[0012] In some embodiments, the transistors other than the selection transistor are all access transistors, and the method further comprises: forming a first electrode layer connected to the source of the corresponding access transistor and extending along the first direction; sequentially forming a dielectric layer and a second electrode layer on the surface of the first electrode layer; the first electrode layer, the dielectric layer and the second electrode layer constitute a capacitor structure; and the second electrode layers in the capacitor structures in the plurality of columns arranged along the second direction are integrally connected.

[0013] In some embodiments, the transistors, the capacitor structures and the bit line structures constitute memory cells, and every two adjacent columns of memory cells share the bit line structure or share the second electrode layer along the first direction.

[0014] In the second aspect, the embodiments of the present disclosure provide a semiconductor structure, comprising: a substrate; the substrate comprises a plurality of memory areas arranged along a first direction; a plurality of transistors arranged along a second direction and a third direction on the surface of the memory area and extending along the first direction; at least one layer of the transistors along the third direction from top to bottom are all selection transistors; a first isolation structure located on one side of all the selection transistors and extending along the second direction; a plurality of selectors arranged along the second direction in the first isolation structure; each selector is connected to the source of the selection transistor arranged along the third direction and does not penetrate the first isolation structure; wherein the first direction intersects the second direction and is parallel to the plane where the substrate is located, and the third direction intersects the plane where the substrate is located.

[0015] In some embodiments, the first isolation structure comprises: at least one layer of first sub-isolation structures located at least at the bottom of the selector and extending along the second direction; and a second sub-isolation structure located between the selectors adjacent along the second direction and on the side of the selector away from the selection transistor.

[0016] In some embodiments, the selector comprises: a first contact structure connected to the source of the selection transistor arranged along the third direction and having a top surface not exceeding the first isolation structure; and a second contact structure located on the surface of the first contact structure and having a top surface flush with the first isolation structure.

[0017] In some embodiments, the transistor comprises: a semiconductor layer comprising a channel structure extending along the first direction, and the source and the drain located at both ends of the channel structure along the first direction; and a gate structure comprising a gate dielectric layer and a gate metal layer sequentially located on the surface of the channel structure.

[0018] The plurality of gate metal layers arranged along the second direction are connected to form a word line structure.

[0019] In some embodiments, the transistors other than the selection transistor are all access transistors, and the semiconductor structure further comprises: a plurality of bit line structures arranged along the second direction; each of the bit line structures is connected to the drain of all the transistors arranged along the third direction; a capacitor structure connected to the source of the corresponding access transistor and extending along the first direction; the capacitor structure comprises a first electrode layer connected to the source of each of the access transistors and extending along the first direction, and a dielectric layer and a second electrode layer covering the surface of the first electrode layer in sequence; wherein the second electrode layers in the plurality of capacitor structures arranged along the second direction are integrally connected.

[0020] In a third aspect, the embodiments of the present disclosure provide an electronic device, comprising: a semiconductor structure formed by the method for forming a semiconductor structure according to any one of the above embodiments, or comprising the semiconductor structure according to any one of the above embodiments.

[0021] Here, since the first isolation structure is formed in the first etching groove after the first etching groove is formed, and the selector does not penetrate through the first isolation structure, not only the selector can be isolated by the first isolation structure, reducing the coupling between the selector and other structures (such as the capacitor structure), but also the forming process of the first isolation structure and the selector is relatively simple. BRIEF DESCRIPTION OF DRAWINGS

[0022] In the drawings, which are not necessarily drawn to scale, like numerals can describe similar components in different views. Like numerals having different letter suffixes can represent different instances of similar components. The drawings illustrate generally, by way of example, various embodiments discussed herein.

[0023] Figure 1 A flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure is shown in FIG. 2;

[0024] Figure 2 A structure diagram in a semiconductor structure forming process according to an embodiment of the present disclosure is shown in FIG. 3; Figure 1 ;

[0025] Figure 3 A structure diagram in a semiconductor structure forming process according to an embodiment of the present disclosure is shown in FIG. 4; Figure 2 ;

[0026] Figure 4 A structure diagram in a semiconductor structure forming process according to an embodiment of the present disclosure is shown in FIG. 5; Figure 3 ;

[0027] Figure 5 A structure in a semiconductor structure forming process provided for an embodiment of the present disclosure Figure 4 ;

[0028] Figure 6 A structure in a semiconductor structure forming process provided for an embodiment of the present disclosure Figure 5 ;

[0029] Figure 7 A structure in a semiconductor structure forming process provided for an embodiment of the present disclosure Figure 6 ;

[0030] Figure 8 A structure in a semiconductor structure forming process provided for an embodiment of the present disclosure Figure 7 ;

[0031] Figure 9 A structure in a semiconductor structure forming process provided for an embodiment of the present disclosure Figure 8 ;

[0032] Figure 10 A structure in a semiconductor structure forming process provided for an embodiment of the present disclosure Figure 9 ;

[0033] Figure 11 A structure in a semiconductor structure forming process provided for an embodiment of the present disclosure Figure 10 ;

[0034] Figure 12 A structure in a semiconductor structure forming process provided for an embodiment of the present disclosure Figure 10 ;

[0035] Figure 13 A structure in a semiconductor structure forming process provided for an embodiment of the present disclosure Figure 10 ;

[0036] Figure 14 A structure in a semiconductor structure forming process provided for an embodiment of the present disclosure Figure 10 ;

[0037] Figure 15 A structure in a semiconductor structure forming process provided for an embodiment of the present disclosure Figure 10 ;

[0038] Figure 16 A structure in a semiconductor structure forming process provided for an embodiment of the present disclosure Figure 10 ;

[0039] Figure 17A structure schematic in a semiconductor structure forming process provided by an embodiment of the present disclosure Figure 10 Six;

[0040] Figure 18 A structure schematic in a semiconductor structure forming process provided by an embodiment of the present disclosure Figure 10 Seven;

[0041] Figure 19 A structure schematic in a semiconductor structure forming process provided by an embodiment of the present disclosure Figure 10 Eight;

[0042] Figure 20 A structure schematic in a semiconductor structure forming process provided by an embodiment of the present disclosure Figure 10 Nine;

[0043] Figure 21 A structure schematic in a semiconductor structure forming process provided by an embodiment of the present disclosure Figure 2 Ten;

[0044] Figure 22 A structure schematic in a semiconductor structure forming process provided by an embodiment of the present disclosure Figure 2 Eleven;

[0045] Figure 23 A structure schematic in a semiconductor structure forming process provided by an embodiment of the present disclosure Figure 2 Twelve;

[0046] Figure 24 A structure schematic of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] Exemplary embodiments of the present disclosure will be described hereinafter with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown, it should be understood that the present disclosure can be embodied in many forms and should not be construed as limited to the specific embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In the drawings, the same reference numerals are used to represent the same elements throughout the several views.

[0048] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail so as not to unnecessarily complicate the present disclosure. As used herein, the term "including" means including without limitation.

[0049] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like reference numbers in different drawings can represent the same element, aspect or feature.

[0050] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0051] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0052] Currently, in a semiconductor structure, in addition to a memory array composed of memory cells (such as a 1T1C structure), additional transistors are needed on the memory array; for example, an equalization transistor (EQ transistor), a wordline selector transistor, a bitline selector transistor, and the like. Among them, the bitline selector transistor is used to select a bitline in the memory array, so as to reduce the resistance of the bitline, thereby reducing the influence of the resistance-capacitance (Resistor-Capacitor, RC) of the bitline on data reading.

[0053] Further, the bit line selection transistor usually adopts a planar transistor; for example, a fin field effect transistor (FinFET), a gate-all-around (GAA) transistor, a nano-sheet transistor, etc., and in a three-dimensional (3D) stacked structure memory array, the planar transistor is difficult to be efficiently integrated therein.

[0054] In addition, as the semiconductor process node continues to shrink, on the one hand, the parasitic capacitance between the bit line selection transistors gradually increases, thereby causing the sensing margin to decrease; on the other hand, the distance between the bit line selection transistor and the capacitor structure gradually decreases, thereby increasing the coupling between the bit line selection transistor and the capacitor structure.

[0055] Based on this, the semiconductor structure and the forming method thereof and the electronic device are provided in the embodiments of the present disclosure. In the following, the semiconductor structure and the forming method thereof and the electronic device in the embodiments of the present disclosure are described in detail in combination with the drawings.

[0056] Before introducing the embodiments of the present disclosure, the following embodiments may use the three directions for describing the three-dimensional structure, which can include a first (X-axis) direction, a second (Y-axis) direction and a third (Z-axis) direction. The Z-axis direction can be a direction perpendicular to the plane of the substrate; the X-axis and Y-axis directions are two perpendicular directions in the plane of the substrate, wherein the X-axis direction can be the direction in which the transistor extends.

[0057] The embodiments of the present disclosure provide a forming method of a semiconductor structure 100, Figure 1 The flowchart of the semiconductor structure forming method provided in the embodiments of the present disclosure is shown in FIG. 1. Figure 1 As shown in FIG. 1, the forming method of the semiconductor structure includes the following steps:

[0058] In step S110, a substrate is provided; the substrate includes a plurality of storage areas arranged along the X-axis direction.

[0059] In the embodiments of the present disclosure, the substrate can be a silicon substrate, and can also include other semiconductor elements, for example: germanium (Ge), or include semiconductor compounds, for example: silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimony (InSb), or include other semiconductor alloys, for example: silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), gallium aluminum arsenide (AlGaAs), gallium indium arsenide (GaInAs), indium gallium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or a combination thereof.

[0060] Step S120, forming a stack structure on the surface of the storage region; the stack structure comprises a plurality of transistors arranged in an array along the Y-axis direction and the Z-axis direction and extending along the X-axis direction; and at least one layer of transistors from top to bottom along the Z-axis direction are all selection transistors.

[0061] The transistor involved in the embodiments of the present disclosure refers to an element comprising at least three terminals of gate, source and drain. The transistor has a channel region between the drain (drain electrode terminal, drain region or drain electrode) and the source (source electrode terminal, source region or source electrode), and the gate can control the conductivity of the channel region, so that the current can flow between the source, the channel region and the drain based on the gate control.

[0062] In the embodiments of the present disclosure, the transistor extends along the X-axis direction, that is, the transistor is horizontally shaped. The horizontally shaped transistor can reduce the possibility of tilting or breaking, thereby improving the stability of the semiconductor structure. At the same time, the horizontally shaped transistor can be stacked to form a three-dimensional semiconductor structure, thereby improving the integration of the semiconductor structure and realizing miniaturization.

[0063] In the embodiments of the present disclosure, the selection transistor can be a bit line selection transistor, which is used to select the required bit line in the storage array, so as to reduce the resistance of the bit line, thereby reducing the influence of the resistance-capacitance of the bit line on data reading. In addition, the transistors other than the selection transistor are all access transistors, and the access transistor and the corresponding capacitor structure constitute a storage cell.

[0064] Step S130, etching the stack structure to form a first etching groove extending along the Y-axis direction; the first etching groove exposes the source of all the selection transistors in the stack structure.

[0065] The etching process described in the embodiments of the present disclosure includes but is not limited to dry etching, wet etching and a combination thereof.

[0066] Step S140, forming a first isolation structure in the first etching groove, and a plurality of selectors arranged in the Y-axis direction in the first isolation structure; each selector is connected with the source of the selection transistor arranged in the Z-axis direction and does not penetrate through the first isolation structure.

[0067] In the embodiments of the present disclosure, the first isolation structure can be a single-layer structure or a multi-layer structure. For example, the first isolation structure can be a single-layer structure composed of insulating materials such as silicon oxide or silicon oxynitride. For another example, the first isolation structure can comprise a first sub-isolation structure and a second sub-isolation structure on the surface of the first sub-isolation structure; the first sub-isolation structure can be composed of insulating materials such as silicon nitride, and the second sub-isolation structure can be composed of insulating materials such as silicon oxide.

[0068] In the embodiments of the present disclosure, the selector can be a single-layer structure or a multi-layer structure. For example, the selector can be a single-layer structure composed of conductive materials such as tungsten, cobalt, nickel, copper, aluminum, titanium, or polysilicon. For another example, the selector can include a first contact structure and a second contact structure located above the surface of the first contact structure; the first contact structure can be composed of conductive materials such as polysilicon, and the second contact structure can be composed of conductive materials such as tungsten, cobalt, or nickel.

[0069] In the embodiments of the present disclosure, after the first etching groove extending along the Y-axis direction is formed, the first isolation structure is formed in the first etching groove, and the selector does not penetrate through the first isolation structure, so that the selector can be isolated by the first isolation structure. In this way, on the one hand, the coupling capacitance between the selectors is reduced, and the capacitance value of the coupling capacitance can be reduced to 0.3 fF; on the other hand, the coupling between the selector and other structures (such as the capacitor structure) is reduced; at the same time, the formation process of the first isolation structure and the selector is relatively simple.

[0070] Figures 2-23 The structure schematic diagram in the formation process of the semiconductor structure 100 provided in the embodiments of the present disclosure is described below in combination with Figures 2-23 The formation process of the semiconductor structure 100 provided in the embodiments of the present disclosure is described in detail. Among them, Figures 2-23 including a three-dimensional view, a cross-sectional view along a-a', and a cross-sectional view along b-b'.

[0071] First, refer to Figure 2 , execute step S110 to provide a substrate (not shown); the substrate includes a plurality of storage areas A arranged along the X-axis direction.

[0072] In the embodiments of the present disclosure, each storage area A is used for subsequent formation of a plurality of storage units arranged in the Y-axis direction and the Z-axis direction, and each storage unit is composed of a transistor and a capacitor structure. Here, the position of the storage area A can be understood with reference to Figure 7 ; among them, Figure 7 two storage areas A are shown in detail.

[0073] Next, refer to Figures 2-8 , execute step S120 to form a stack structure 110 as shown in Figure 7 and Figure 8 on the surface of the storage area A; the stack structure 110 includes a plurality of transistors 140 arranged in the Y-axis direction and the Z-axis direction and extending along the X-axis direction; at least one layer of transistors 140 from top to bottom along the Z-axis direction is a selection transistor 140a.

[0074] In some embodiments, step S120 includes steps S121 to S123.

[0075] Step S121, forming an initial stack structure 110a as shown in the figure on the surface of the storage region A; the initial stack structure 110a includes initial semiconductor layers 111b arranged in the Y-axis direction and the Z-axis direction and extending in the X-axis direction. Figure 4

[0076] In practice, refer to Figure 2 and Figure 3 , the first isolation material layers 112a and the active material layers 111a are alternately stacked in the Z-axis direction on the surface of the substrate (i.e. the storage region A). The material of the first isolation material layers 112a can be silicon oxide, silicon nitride, silicon oxynitride, etc., and the materials of the subsequent isolation structures can be understood in the same way; the material of the active material layers 111a can be a semiconductor material such as silicon or germanium, or a metal oxide material such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), etc.

[0077] In the embodiments of the present disclosure, the number of layers of the first isolation material layers 112a and the active material layers 111a can be set according to the needs or the storage density. The more the number of layers of the first isolation material layers 112a and the active material layers 111a, the higher the integration and the greater the capacitance density of the semiconductor structure 100 formed. For example, Figure 2 and Figure 3 The number of layers of the first isolation material layers 112a is 5, and the number of layers of the active material layers 111a is 5.

[0078] The deposition process involved in the embodiments of the present disclosure includes but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and combinations thereof.

[0079] It should be noted that the first isolation material layers 112a are also provided between the active material layers 111a and the substrate (not shown) for isolating the active material layers 111a and the substrate; in addition, Figure 2 and Figure 3 Only one storage region A is shown in

[0080] ​Next, etching the structure shown in Figure 2 and Figure 3 to form a third etching trench (not shown) penetrating to the substrate, and an initial semiconductor layer 111b arranged in an array along the Y-axis and Z-axis directions and extending along the X-axis direction as shown in Figure 4 . Then, the third etching trench is filled with an isolation material to form a second isolation material layer, and the second isolation material layer and the remaining first isolation material layer 112a form a second isolation structure 112b as shown in Figure 4 .

[0081] In the embodiments of the present disclosure, please continue to refer to Figure 4 , after forming the initial semiconductor layer 111b, the forming process of the semiconductor structure 100 further includes: etching the initial semiconductor layer 111b and the second isolation structure 112b on one side of the storage area A along the X-axis direction to form a fourth etching trench (not shown) penetrating to the substrate; then, forming a third isolation structure 113 in the fourth etching trench. Here, the third isolation structure 113 can include a silicon oxide layer and a polysilicon layer covering the surface of the fourth etching trench in sequence; the third isolation structure 113 can isolate the capacitor structure between the adjacent storage units along the X-axis direction in the subsequent process.

[0082] In the embodiments of the present disclosure, two adjacent storage areas A along the X-axis direction can share the third isolation structure 113 (please refer to Figure 7 ). In this way, the integration of the formed semiconductor structure 100 can be improved.

[0083] In the embodiments of the present disclosure, please continue to refer to Figure 4 , the forming method of the semiconductor structure 100 further includes: forming a protective layer 114 on the surface of the third isolation structure 113 and the topmost first isolation material layer 112a; the protective layer 114 can be a single-layer structure or a multi-layer structure. For example, the protective layer 114 can be a single-layer structure composed of a silicon nitride layer. The protective layer 114 can protect the topmost structure from damage during the process.

[0084] In step S122, the initial semiconductor layer 111b along the two sides of the X-axis direction is etched, and the remaining initial semiconductor layer 111b forms a semiconductor layer 111; the semiconductor layer 111 includes a channel structure 1112, and a source 1111 and a drain 1113 located at the two ends of the channel structure 1112 along the X-axis direction.

[0085] Here, first, the structure shown in Figure 4 is etched on one side along the X-axis direction to form a structure as shown in Figure 5The fifth etching groove 115 extending along the Y-axis direction and the Z-axis direction is shown, and the fifth etching groove 115 exposes the sidewall of the drain 1113 in the semiconductor layer 111. The second isolation structure 112b is laterally etched through the fifth etching groove 115 until the surface of the source 1111 in the semiconductor layer 111 is exposed, and a structure as shown in Figure 6 The first lateral groove 116 extending along the Y-axis direction and arranged along the Z-axis direction is shown.

[0086] In the embodiments of the present disclosure, please refer to Figure 7 and Figure 8 After the first lateral groove 116 is formed, the forming method of the semiconductor structure 100 further includes: thinning the semiconductor layer 111 exposed by the first lateral groove 116. Specifically, the thinning can be performed in the following two ways:

[0087] Method one: directly performing dry etching on the semiconductor layer 111 until the required thickness is formed, and then stopping etching.

[0088] Method two: in-situ oxidizing the semiconductor layer 111 to oxidize part of the semiconductor layer 111 into a silicon oxide layer, and removing the silicon oxide layer by wet etching or dry etching technology.

[0089] In the embodiments of the present disclosure, by thinning the semiconductor layer 111, the gap between the two adjacent semiconductor layers 111 is increased, so that the process window of the subsequent formation of the word line structure and the like can be increased. In other embodiments, the thinning process can not be performed.

[0090] It should be noted that the top view (as shown in Figure 7 ) in the embodiments of the present disclosure is used to understand the arrangement direction, extension direction and the like of each structure in the forming process of the semiconductor structure 100, so the top view and the three-dimensional view are not completely corresponding, and the top view can also be a perspective view; in addition, the sectional view (as shown in Figure 8 ) in the embodiments of the present disclosure only shows the structure forming process schematic diagram on one storage area A in the semiconductor structure 100; the subsequent drawings can be understood according to this.

[0091] It should be further noted that in the embodiments of the present disclosure, the other side of the initial semiconductor layer 111b along the X-axis direction can be etched before the subsequent formation of the capacitor structure to expose the source 1111 in the semiconductor layer 111.

[0092] Step S123, on the surface of the channel structure 1112, a structure as shown in Figure 7 and Figure 8The gate dielectric layer 121 and the gate metal layer 122 are shown; the gate dielectric layer 121 and the gate metal layer 122 constitute the gate structure 120; wherein the semiconductor layer 111 and the gate structure 120 constitute the transistor 140; and the plurality of gate metal layers 122 arranged along the Y-axis direction are connected to form a word line structure.

[0093] In implementation, please refer to Figure 7 and Figure 8 , first, the fourth isolation structure 117 is formed on the surface of the source 1111 exposed by the first lateral recess 116, and the fourth isolation structure 117 is used to isolate the subsequently formed gate structure 120 and the capacitor structure; next, the gate dielectric layer 121 and the gate metal layer 122 are sequentially formed on the surface of the channel structure 1112, and the gate dielectric layer 121 and the gate metal layer 122 constitute the gate structure 120; finally, the fifth isolation structure 118 is formed on the surface of the drain 1113, and the fifth isolation structure 118 is used to isolate the subsequently formed gate structure 120 and the bit line structure.

[0094] In the embodiment of the present disclosure, the gate structure 120 is located on the upper surface and the lower surface of the channel structure 1112 (i.e. the semiconductor layer 111) along the Z-axis direction, that is, the gate structure 120 is a double-gate structure, which can further improve the control ability of the gate, and thus the performance of the formed semiconductor structure 100 can be improved. In other embodiments, a single-gate structure or the like can also be formed, and the type of gate structure is not limited in the present disclosure.

[0095] In the embodiment of the present disclosure, the material of the gate dielectric layer 121 can be silicon oxide or other suitable materials; and the material of the gate metal layer 122 can be any one of materials with good conductivity, for example, any one of titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), and copper (Cu).

[0096] In the embodiment of the present disclosure, the forming method of the semiconductor structure 100 further includes: forming a sixth isolation structure 119 in the remaining first lateral recess 116, and the sixth isolation structure 119 is used to isolate two adjacent transistors 140 (i.e. the semiconductor layer 111 and the gate structure 120) along the Y-axis.

[0097] In the embodiment of the present disclosure, before the bit line structure is formed, the forming method of the semiconductor structure 100 further includes: performing metal ion implantation on the drain 1113 of all the transistors 140, which can reduce the contact resistance between the bit line structure and the drain 1113, and thus the power consumption of the semiconductor structure 100 can be reduced.

[0098] In some embodiments, the method for forming the semiconductor structure 100 further comprises: forming a plurality of bit line structures 130 arranged along the Y-axis direction; each bit line structure 130 is connected with the drain 1113 of all transistors 140 arranged along the Z-axis direction.

[0099] In implementation, please continue to refer to Figure 7 and Figure 8 In the fifth etching groove 115, a plurality of bit line structures 130 are formed, which are arranged along the Y-axis direction and extend along the Z-axis direction; and a seventh isolation structure 131 is formed to fill the fifth etching groove 115.

[0100] In the embodiments of the present disclosure, the material of the bit line structure 130 includes tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polysilicon or any combination thereof.

[0101] It should be noted that in the embodiments of the present disclosure, two adjacent storage areas A along the X-axis direction can share the fifth etching groove 115; thus, please refer to Figure 7 Two columns of bit line structures (such as 130 and 130') arranged along the X-axis direction can be formed in the fifth etching groove 115, and each column of bit line structures is connected with the drain 1113 of the transistor 140 in the corresponding storage area A. In this way, the integration of the formed semiconductor structure 100 can be improved.

[0102] Next, please refer to Figure 9 and Figure 10 The step S130 is performed to etch the stack structure 110 to form a first etching trench 150 extending along the Y-axis direction; the first etching trench 150 exposes the source 1111 of all selection transistors 140a in the stack structure 110.

[0103] In the embodiments of the present disclosure, at least one layer of transistors 140 along the Z-axis direction from top to bottom is used as a selection transistor 140a. Specifically, the selection transistor 140a is used to select the bit line structure 130 in the memory array, so the number of layers of the selection transistor 140a is greater than 1 and less than the number of layers of all transistors 140; for example, the number of layers of all transistors 140 is 5, and the number of layers of the selection transistor 140a can be 1, 2, 3, or 4.

[0104] In implementation, taking the number of layers of the selection transistor 140a as 2 layers as an example, please refer to Figure 9 and Figure 10, etching 2 layers of the initial semiconductor layer 111b from top to bottom along the Z-axis direction to form a first etching trench 150, and the remaining initial semiconductor layer 111b constitutes the semiconductor layer 111; at this time, the 2 layers of the semiconductor layer 111 and the corresponding gate structure 120 from top to bottom along the Z-axis direction constitute a selection transistor 140a, and the first etching trench 150 exposes the source 1111 of the selection transistor 140a.

[0105] In the embodiments of the present disclosure, in a first aspect, by controlling the etching depth of the first etching trench 150, the number of layers of the selection transistor 140a can be directly determined, which can adapt to product designs with different requirements for the number of layers of the selection transistor 140a, improve the versatility and flexibility of the process platform, and simplify the process flow, which is conducive to mass production. In a second aspect, by exposing the source 1111 of the selection transistor 140a through the first etching trench 150, the stability of the connection of the source 1111 of the selection transistor 140a in subsequent processes can be ensured, and the contact resistance of the source 1111 of the selection transistor 140a can be reduced.

[0106] Finally, with reference to Figures 11-18 , step S140 is performed to form a first isolation structure 160 as shown in Figure 17 and Figure 18 in the first etching trench 150, and a plurality of selectors 170 arranged along the Y-axis direction in the first isolation structure 160 as shown in Figure 17 and Figure 18 ; each selector 170 is connected with the source 1111 of the selection transistor 140a arranged along the Z-axis direction and does not penetrate through the first isolation structure 160.

[0107] In some embodiments, step S140 includes steps S141 and S143.

[0108] Step S141 forms an initial first isolation structure 160a as shown in Figure 13 and Figure 14 in the first etching trench 150.

[0109] In some embodiments, step S141 specifically includes: forming at least one layer of an initial first sub-isolation structure 161a as shown in Figure 11 and Figure 12 on the surface exposed by the first etching trench 150; in the remaining first etching trench 150, an initial second sub-isolation structure 162a as shown in Figure 13 and Figure 14 is formed; the initial first sub-isolation structure 161a and the initial second sub-isolation structure 162a constitute the initial first isolation structure 160a.

[0110] In the embodiments of the present disclosure, the number of layers of the initial first sub-isolation structure 161a can be set according to actual needs; for example, the number of layers of the initial first sub-isolation structure 161a can be 1 layer, 2 layers, 3 layers, and the like. By setting at least one layer of the initial first sub-isolation structure 161a, the isolation effect between the selector and the capacitor structure formed subsequently at the bottom (that is, the side along the reverse direction of the Z axis) thereof can be increased, and the coupling between devices can be reduced.

[0111] In addition, by depositing at least one layer of the initial first sub-isolation structure 161a, it can be ensured that the complex topography such as the corner in the first etching groove 150 is uniformly covered, and the isolation effect is ensured; by filling the initial second sub-isolation structure 162a in the remaining first etching groove 150, it can be ensured that the first etching groove 150 is completely filled; in this way, the defect rate of the isolation structure in the first etching groove 150 is significantly reduced, and the process stability is improved.

[0112] In the embodiments of the present disclosure, the materials of the initial first sub-isolation structure 161a and the initial second sub-isolation structure 162a are different; for example, the material of the initial first sub-isolation structure 161a is silicon nitride, and the material of the initial second sub-isolation structure 162a can be silicon oxide. In this way, under the same etching conditions, the initial first sub-isolation structure 161a (that is, silicon nitride) has a higher etching selectivity than the initial second sub-isolation structure 162a (that is, silicon oxide), so that the initial first sub-isolation structure 161a can act as an etching stop layer to avoid excessive etching damage to other structures. In other embodiments, the initial first sub-isolation structure 161a and the initial second sub-isolation structure 162a can also be other isolation materials with different etching selectivities.

[0113] It should be noted that in the embodiments of the present disclosure, the initial first isolation structure 160a formed is a multi-layer structure. In other embodiments, the initial first isolation structure 160a formed can also be a single-layer structure; for example, a single-layer structure composed of insulating materials such as silicon oxide or silicon oxynitride.

[0114] In step S142, the initial first isolation structure 160a is etched to form a plurality of second etching grooves 151 arranged along the Y axis direction as shown in FIGS. 16B and 16C; the remaining initial first isolation structure 160a constitutes a first isolation structure 160, and each second etching groove 151 exposes the source 1111 of the selection transistor 140a arranged along the Z axis direction and does not penetrate the bottom of the first isolation structure 160 and the side away from the selection transistor 140a. Figure 15 Figure 16

[0115] ​​In some embodiments, step S142 specifically includes: etching the sidewall of the initial first sub-isolation structure 161a and the initial second sub-isolation structure 162a close to one side of the selection transistor 140a until the bottom surface of the initial first sub-isolation structure 161a is exposed, to form a plurality of second etching grooves 151 arranged along the Y-axis direction.

[0116] Among them, the remaining initial first sub-isolation structure 161a constitutes the first sub-isolation structure 161, and the remaining initial second sub-isolation structure 162a constitutes the second sub-isolation structure 162; the first sub-isolation structure 161 and the second sub-isolation structure 162 constitute the first isolation structure 160.

[0117] In the embodiments of the present disclosure, the first sub-isolation structure 161 can isolate the subsequent selector and the capacitor structure at the bottom (i.e. along the side of the Z-axis in the opposite direction) of the selector, reducing the coupling between devices. The second sub-isolation structure 162 can isolate the coupling between the subsequent selector and the structure adjacent to the side of the selector, for example, the coupling between adjacent selectors, or the coupling between the selector and the capacitor structure.

[0118] In the embodiments of the present disclosure, each second etching groove 151 exposes the source 1111 of a column of selection transistors 140a stacked along the Z-axis direction, so that the subsequent source 1111 of a column of selection transistors 140a can be synchronously electrically connected in the Z-axis direction, simplifying the process steps and improving the reliability of the connection.

[0119] In addition, a plurality of second etching grooves 151 are formed at the same time, not only reducing the number of mask plates used, thereby reducing the cost of photolithography; but also reducing the overlay error when forming a plurality of second etching grooves 151, thereby improving the etching precision.

[0120] Step S143, in the second etching groove 151, a selector 170 as shown in Figure 21 and Figure 22 is formed.

[0121] In some embodiments, step S143 specifically includes steps S11 and S12.

[0122] Step S11, in the second etching groove 151, a first contact structure 171 as shown in Figure 19 and Figure 20 is formed; the first contact structure 171 is connected with the source 1111 of the selection transistor 140a arranged along the Z-axis direction, and the top surface does not exceed the second etching groove 151.

[0123] In implementation, Figure 15 and Figure 16 the structure exposed by the surface, and in the second etching groove 151, a first contact structure 171 as shown inFigure 17 and Figure 18 the initial first contact structure 171a shown in FIG. 17A. Next, the initial first contact structure 171a of the structure surface shown in FIG. 17B is removed, and part of the initial first contact structure 171a in the second etching groove 151 is removed, to form a first contact structure 171 as shown in FIG. 17C. Figure 17 and Figure 18 the initial first contact structure 171a of the structure surface shown in FIG. 17B, and part of the initial first contact structure 171a in the second etching groove 151, to form a first contact structure 171 as shown in FIG. 17C. Figure 19 and Figure 20 the initial first contact structure 171a of the structure surface shown in FIG. 17B, and part of the initial first contact structure 171a in the second etching groove 151, to form a first contact structure 171 as shown in FIG. 17C.

[0124] Step S12, in the remaining second etching groove 151, a second contact structure 172 as shown in FIG. 17D is formed; the first contact structure 171 and the second contact structure 172 constitute the selector 170. Figure 21 and Figure 22 the initial first contact structure 171a of the structure surface shown in FIG. 17B, and part of the initial first contact structure 171a in the second etching groove 151, to form a first contact structure 171 as shown in FIG. 17C.

[0125] In the embodiments of the present disclosure, the materials of the first contact structure 171 and the second contact structure 172 are different; for example, the first contact structure can be composed of a conductive material such as polysilicon, and the second contact structure can be composed of a conductive material such as tungsten, cobalt or nickel. In this way, through the first contact structure 171, the contact resistance between the selector 170 and the source 1111 of the selection transistor 140a can be reduced; and through the second contact structure, the conductivity and current carrying capacity of the selector 170 can be improved.

[0126] It should be noted that in the embodiments of the present disclosure, the selector 170 formed is a multi-layer structure. In other embodiments, the selector 170 formed can also be a single-layer structure; for example, a single-layer structure composed of a conductive material such as tungsten, cobalt, nickel, copper, aluminum, titanium or polysilicon.

[0127] In the embodiments of the present disclosure, since the first etching groove extending along the Y-axis direction is formed first, and then the first isolation structure is formed in the first etching groove, and the selector does not penetrate through the first isolation structure, not only can the selector be isolated by the first isolation structure; in this way, on the one hand, the coupling capacitance between the selectors is reduced, and the capacitance value of the coupling capacitance can be reduced to 0.3 fF; on the other hand, the coupling between the selector and other structures (such as the capacitor structure) is reduced; at the same time, the formation process of the first isolation structure and the selector is also relatively simple.

[0128] In some embodiments, the transistors 140 other than the selection transistors 140a are all access transistors 140b, and the method for forming the semiconductor structure 100 further includes steps S21 and S22.

[0129] Step S21, a structure as shown in FIG. 18A is formed; the structure includes a substrate 110, a plurality of access transistors 140b, and a plurality of selection transistors 140a. Figure 23The first electrode layer 181 is shown connected with the source 1111 of the corresponding access transistor 140b and extends along the X-axis direction.

[0130] In implementation, the third isolation structure 113 and the protective layer 114 above the surface thereof are removed, a sixth etching groove (not shown) is formed, and the sixth etching groove exposes one side of the remaining initial semiconductor layer 111b along the X-axis direction; the initial semiconductor layer 111b is etched laterally through the sixth etching groove until the sidewall of the source 1111 in the semiconductor layer 111 is exposed, a second lateral groove (not shown) is formed; and the first electrode layer 181 is formed in the second lateral groove.

[0131] In the embodiment of the present disclosure, after the first electrode layer 181 is formed, the forming process of the semiconductor structure 100 further includes: etching part of the second isolation structure 112b through the sixth etching groove to form a third lateral groove (not shown).

[0132] In step S22, a dielectric layer 182 and a second electrode layer 183 are sequentially formed on the surface of the first electrode layer 181. Figure 23 The first electrode layer 181, the dielectric layer 182 and the second electrode layer 183 constitute a capacitor structure 180; and the second electrode layers in the plurality of capacitor structures 180 arranged along the Y-axis direction are integrally connected.

[0133] In the embodiment of the present disclosure, the materials of the first electrode layer 181 and the second electrode layer 183 can include metal nitride or metal silicide, for example, titanium nitride. The material of the dielectric layer 182 can include high-K dielectric material, for example, can be one or any combination of lanthanum oxide (La2O3), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), hafnium silicate (HfSiOx) or zirconium oxide (ZrO2).

[0134] In the embodiment of the present disclosure, since the capacitor structure 180 extends along the X-axis direction, that is, the capacitor structure in the embodiment of the present disclosure is horizontally shaped, compared with the vertical capacitor structure with high aspect ratio, the horizontally shaped capacitor structure can reduce the possibility of tilting or breaking, thereby improving the stability of the capacitor structure. In addition, the plurality of horizontally shaped capacitor structures stacked in the Z-axis direction can improve the integration of the semiconductor structure and realize miniaturization.

[0135] It should be noted that, in the embodiment of the present disclosure, the capacitor structure 180 is formed after the selector 170, and in other embodiments, the capacitor structure 180 can also be formed before the selector 170, which is not limited in the present disclosure. In addition, Figure 23 Two storage areas A are shown in FIG. 2.

[0136] In the embodiments of the present disclosure, the dielectric layers 182 in the plurality of capacitor structures 180 arranged along the Y-axis direction are integrally connected; and the second electrode layers 183 in the plurality of capacitor structures 180 arranged along the Y-axis direction are integrally connected.

[0137] In some embodiments, the transistor 140 and the capacitor structure 180 constitute a memory cell, and every two adjacent memory cells along the X-axis direction share the second electrode layer 183. In this way, the further miniaturization of the semiconductor structure 100 can also be facilitated.

[0138] In other embodiments, every two adjacent memory cells along the X-axis direction can also share the bit line structure 130.

[0139] In addition, the embodiments of the present disclosure also provide a semiconductor structure 100, please refer to Figure 23 The semiconductor structure 100 comprises: a substrate (not shown); the substrate comprises a plurality of memory areas A arranged along the X-axis direction; a plurality of transistors 140 arranged along the Y-axis direction and the Z-axis direction on the surface of the memory area A and extending along the X-axis direction; at least one layer of transistors 140 along the Z-axis direction as selection transistors 140a; a first isolation structure 160 located on one side of all the selection transistors 140a and extending along the Y-axis direction; a plurality of selectors 170 arranged along the Y-axis direction in the first isolation structure 160; each selector 170 is connected with the source 1111 of the selection transistor 140a arranged along the Z-axis direction and does not penetrate the first isolation structure 160.

[0140] It should be noted that, Figure 23 Two memory areas A are shown in the above embodiment, and in fact, the number of memory areas A can be set according to actual needs, for example, 2, 4, 6, etc.

[0141] In some embodiments, please continue to refer to Figure 23 The first isolation structure 160 comprises: at least one layer of first sub-isolation structures 161, at least located at the bottom of the selector 170 and extending along the Y-axis direction; and a second sub-isolation structure 162 located between the adjacent selectors 170 along the Y-axis direction and on the side of the selector 170 away from the selection transistor 140a.

[0142] Here, the first sub-isolation structure 161 is also located at the bottom of the second sub-isolation structure 162 and on the side wall not adjacent to the selection transistor 140a.

[0143] In some embodiments, please continue to refer to Figure 23The selector 170 comprises: a first contact structure 171; the first contact structure 171 is connected with the source 1111 of the selection transistor 140a arranged along the Z-axis direction, and the top surface of the first contact structure 171 does not exceed the first isolation structure 160; and a second contact structure 172 located on the surface of the first contact structure 171, and the top surface of the second contact structure 172 is flush with the first isolation structure 160.

[0144] In some embodiments, please continue to refer to Figure 23 The transistor 140 comprises: a semiconductor layer 111 comprising a channel structure 1112 extending along the X-axis direction, and a source 1111 and a drain 1113 located at both ends of the channel structure 1112 along the X-axis direction (the positions can be referred to Figure 8 The gate structure 120 comprises a gate dielectric layer 121 and a gate metal layer 122 sequentially located on the surface of the channel structure 1112; and a plurality of gate metal layers 122 arranged along the Y-axis direction are connected to form a word line structure.

[0145] In some embodiments, please continue to refer to Figure 23 The transistor 140 other than the selection transistor 140a is used as an access transistor 140b, and the semiconductor structure 100 further comprises: a plurality of bit line structures 130 arranged along the Y-axis direction; and each bit line structure 130 is connected with the drain 1113 of all the transistors 140 arranged along the Z-axis direction.

[0146] In some embodiments, please continue to refer to Figure 23 The semiconductor structure 100 further comprises: a capacitor structure 180 connected with the source 1111 of the corresponding access transistor 140b and extending along the X-axis direction; the capacitor structure 180 comprises a first electrode layer 181 connected with the source 1111 of each access transistor 140b and extending along the X-axis direction, and a dielectric layer 182 and a second electrode layer 183 sequentially covering the surface of the first electrode layer 181; and the second electrode layers 183 in the plurality of capacitor structures 180 arranged along the Y-axis direction are integrally connected with each other.

[0147] In some embodiments, please continue to refer to Figure 23 The semiconductor structure 100 further comprises: a seventh isolation structure 131 located between the bit line structures 130 adjacent along the Y-axis direction and between the bit line structures 130 adjacent along the X-axis direction.

[0148] In some embodiments, please continue to refer to Figure 23 The semiconductor structure 100 further comprises: a fourth isolation structure 117 located on the surface of the source 1111; a fifth isolation structure 118 located on the surface of the drain 1113; and a sixth isolation structure 119 located between two transistors 140 adjacent along the Y-axis.

[0149] In some embodiments, please refer to Figure 23 The semiconductor structure 100 also includes a second isolation structure 112b, located between the fourth isolation structure 117 and the capacitor structure 180.

[0150] In this embodiment of the disclosure, since the selector 170 does not penetrate the first isolation structure and is close to the side of the selector transistor 140a, the selector 170 (including the bottom and sidewall) can be isolated from the capacitor structure 180 and from adjacent selectors 170 through the first isolation structure; thus, the coupling between the selector 170 and the capacitor structure 180, and the coupling between the selectors 170 are achieved.

[0151] The semiconductor structure provided in this disclosure is similar to the semiconductor structure formed by the above embodiments. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0152] This disclosure also provides an electronic device. Figure 24 This is a schematic diagram of the structure of an electronic device 200 provided in an embodiment of the present disclosure, as shown below. Figure 24 As shown, the electronic device 200 includes: a processor 210; and a semiconductor structure 100 formed by the method of forming any of the semiconductor structures 100 in the above embodiments, or any of the semiconductor structures 100 in the above embodiments; wherein the memory is coupled to the processor.

[0153] In some embodiments, the electronic device includes, but is not limited to, mobile phones, tablets, smart bracelets, wearable electronic devices, virtual reality devices, augmented reality devices, in-vehicle devices, servers, workstations, etc.

[0154] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0155] The features disclosed in the several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or structural embodiments. The above are merely some implementation methods of this disclosure, but the protection scope of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this disclosure should be included within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the above-described protection scope.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises: providing a substrate; the substrate comprises a plurality of memory areas arranged along a first direction; forming a stack structure on a surface of the memory areas; the stack structure comprises a plurality of transistors arranged in an array along a second direction and a third direction and extending along the first direction; at least one layer of the transistors from top to bottom along the third direction are all select transistors; etching the stack structure to form a first etching trench extending along the second direction; the first etching trench exposes the source of all the select transistors in the stack structure; forming a first isolation structure in the first etching trench and a plurality of selectors arranged along the second direction in the first isolation structure; each of the selectors is connected with the source of the select transistors arranged along the third direction and does not penetrate the first isolation structure; wherein the first direction intersects the second direction and is parallel to the plane on which the substrate lies, and the third direction intersects the plane on which the substrate lies.

2. The method of claim 1, wherein, Forming a first isolation structure in the first etching trench and a plurality of selectors arranged along the second direction in the first isolation structure comprises: forming an initial first isolation structure in the first etching trench; etching the initial first isolation structure to form a plurality of second etching trenches arranged along the second direction; the remaining initial first isolation structure constitutes the first isolation structure, and each of the second etching trenches exposes the source of the select transistors arranged along the third direction and does not penetrate the bottom and the side away from the select transistors of the first isolation structure; forming the selectors in the second etching trenches.

3. The method of claim 2, wherein, Forming an initial first isolation structure in the first etching trench comprises: forming at least one layer of initial first sub-isolation structures on the surface exposed by the first etching trench; forming initial second sub-isolation structures in the remaining first etching trench; the initial first sub-isolation structures and the initial second sub-isolation structures constitute the initial first isolation structure.

4. The method of claim 3, wherein, Etching the initial first isolation structure to form a plurality of second etching trenches arranged along the second direction comprises: etching the sidewall of the initial first sub-isolation structure close to the side of the select transistors and the initial second sub-isolation structure until the bottom surface of the initial first sub-isolation structure is exposed to form a plurality of second etching trenches arranged along the second direction; wherein the remaining initial first sub-isolation structures constitute first sub-isolation structures, and the remaining initial second sub-isolation structures constitute second sub-isolation structures; the first sub-isolation structures and the second sub-isolation structures constitute the first isolation structure.

5. The method of claim 2, wherein, Forming the selectors in the second etching trenches comprises: forming a first contact structure in the second etching trench; the first contact structure is connected with the source of the select transistors arranged along the third direction and the top surface does not exceed the second etching trench; forming a second contact structure in the remaining second etching trench; the first contact structure and the second contact structure constitute the selectors.

6. The method of claim 1, wherein, Forming a stack structure on a surface of the memory region, comprising: Forming an initial stack structure on a surface of the memory region; the initial stack structure comprises initial semiconductor layers arranged in an array along a second direction and a third direction, and extending along a first direction; Etching both sides of the initial semiconductor layers along the first direction, and the remaining initial semiconductor layers form semiconductor layers; the semiconductor layers comprise a channel structure, and the source and drain located at both ends of the channel structure along the first direction; Forming a gate dielectric layer and a gate metal layer on a surface of the channel structure in sequence; the gate dielectric layer and the gate metal layer form a gate structure; Wherein, the semiconductor layers and the gate structure form the transistor; a plurality of the gate metal layers arranged along the second direction are connected to form a word line structure.

7. The method of claim 1, wherein, The method further comprises: Forming a plurality of bit line structures arranged along the second direction; each of the bit line structures is connected to the drain of all the transistors arranged along the third direction.

8. The method of claim 7, wherein, The transistors other than the selection transistor are used as access transistors, and the method further comprises: Forming a first electrode layer connected to the source of the corresponding access transistor and extending along the first direction; Forming a dielectric layer and a second electrode layer on a surface of the first electrode layer in sequence; the first electrode layer, the dielectric layer and the second electrode layer form a capacitor structure; Wherein, the second electrode layers in a plurality of columns of the capacitor structures arranged along the second direction are an integral structure connected to each other.

9. The method of claim 8, wherein: The transistors and the capacitor structures form memory cells, and every adjacent two columns of memory cells share the bit line structure or share the second electrode layer along the first direction.

10. A semiconductor structure, characterized by Comprise: A substrate; the substrate comprises a plurality of memory regions arranged along a first direction; A plurality of transistors arranged in an array along a second direction and a third direction on a surface of the memory region, and extending along the first direction; At least one layer of the transistors along the third direction from top to bottom are used as selection transistors; A first isolation structure located on one side of all the selection transistors and extending along the second direction; A plurality of selectors arranged along the second direction in the first isolation structure; each of the selectors is connected to the source of the selection transistor arranged along the third direction and does not penetrate the first isolation structure; Wherein, the first direction intersects the second direction and is parallel to the plane where the substrate is located, and the third direction intersects the plane where the substrate is located.

11. The semiconductor structure of claim 10, wherein, The first isolation structure comprises: At least one layer of first sub-isolation structures located at least at the bottom of the selector and extending along the second direction; A second sub-isolation structure located between the selectors adjacent along the second direction and on the side of the selector away from the selection transistor.

12. The semiconductor structure of claim 10, wherein, The selector comprises: A first contact structure; the first contact structure is connected to the source of the selection transistor arranged along the third direction, and the top surface does not exceed the first isolation structure; A second contact structure is on the surface of the first contact structure and has a top surface flush with the first isolation structure.

13. The semiconductor structure of claim 10, wherein, The transistor comprises: A semiconductor layer comprising a channel structure extending along the first direction, and the source and drain located at both ends of the channel structure along the first direction; A gate structure comprising a gate dielectric layer and a gate metal layer sequentially on the surface of the channel structure; Wherein, a plurality of the gate metal layers arranged along the second direction are connected to form a word line structure.

14. The semiconductor structure of claim 10, wherein, The transistor other than the selection transistor is used as an access transistor, and the semiconductor structure further comprises: A plurality of bit line structures arranged along the second direction; each of the bit line structures is connected to the drain of all the transistors arranged along the third direction; A capacitor structure connected to the source of the corresponding access transistor and extending along the first direction; the capacitor structure comprises a first electrode layer connected to the source of each of the access transistors and extending along the first direction, and a dielectric layer and a second electrode layer sequentially covering the surface of the first electrode layer; Wherein, the second electrode layers in a plurality of columns of the capacitor structures arranged along the second direction are integrally connected.

15. An electronic device, comprising: A semiconductor structure formed by a method for forming a semiconductor structure according to any one of claims 1 to 9, or comprising a semiconductor structure according to any one of claims 10 to 14. ​

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