Polycrystalline silicon-insulating layer-polycrystalline silicon stacked capacitor structure and manufacturing method thereof

Abstract

The invention discloses a polycrystalline silicon-insulating layer-polycrystalline silicon stacked capacitor structure and a manufacturing method thereof, and belongs to the technical field of semiconductor manufacturing. The structure comprises a semiconductor substrate, a floating gate on the semiconductor substrate, an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. No self-aligned metal silicide is formed on the surface of the predetermined area of the floating gate and contact with the floating gate is formed, and self-aligned metal silicide and corresponding contact are formed on the surfaces of the control gate and the substrate active area. The manufacturing method comprises the steps of forming a floating gate, an inter-gate dielectric layer and a control gate, and is characterized in that when a self-aligned metal silicide forming process is carried out, an SAB mask is used for covering a predetermined region of the floating gate to prevent silicide from being formed at the predetermined region, and silicides are formed on the control gate and an active region at the same time; each contact is then formed. According to the method, silicide is prevented from being formed in the specific region of the floating gate of the PIP capacitor, so that the thickness of the floating gate is effectively maintained, the problem of etching bottom penetration or gate-oxide breakdown of a contact hole is avoided, and the reliability of a device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular to a PIP (Poly-Insulator-Poly) stacked capacitor structure in a memory (e.g. ETOX Nor Flash) and a manufacturing method thereof. BACKGROUND

[0002] In integrated circuit design, especially for flash memory products, a charge pump is usually needed to generate high voltage required for erase and write operations. One of the core components of the charge pump is the pump capacitor. In ETOX (EPROM Tunnel Oxide) structure Nor Flash memory, a Poly-Poly-Sub (poly-silicon-poly-silicon-substrate) stacked structure is usually used, in which the pickup end of the floating gate (FG) is connected as a common connection end, and the capacitance between the control gate (CG) and the floating gate (CG / ONO / FG capacitor, ONO is Oxide-Nitride-Oxide interlayer dielectric) and the capacitance between the floating gate and the substrate deep well (FG / TUNOX / Sub-well capacitor, TUNOX is tunnel oxide layer) are connected in parallel to obtain a larger total capacitance value. This capacitance is usually used as a PIP (Poly-Insulator-Poly) stacked capacitor for the charge pump.

[0003] In a conventional PIP stacked capacitor manufacturing process, the formation of the lower plate (usually the floating gate layer, FGPL) will go through a chemical mechanical polishing (CMP) process. However, the CMP process is sensitive to pattern density and has a "loading effect", which causes the floating gate formed in the isolation area (ISO area, e.g. the area where the PIP capacitor is located) to be thinner than the floating gate formed in the dense area (dense area, e.g. the storage cell array area). In addition, in order to reduce the contact resistance and series resistance of the device, self-aligned metal silicide (Silicide) is usually formed at the source / drain region, poly-silicon gate, etc. However, the formation process of the metal silicide will consume part of the poly-silicon (e.g. FGPL).

[0004] The combined effects of these two factors (CMP loading and metal silicide consumption) can cause the bottom plate of the floating gate in the PIP capacitor region to become too thin at the bottom of the subsequent contact hole (CT). When the floating gate is too thin, it can easily be punched through during contact hole etching. Even if it isn't completely punched through, the excessively thin floating gate can still cause breakdown of the underlying gate oxide (e.g., the tunneling oxide layer, TUNOX) when the device is powered on. These issues can lead to an increased early failure rate (EFR) in devices, and these defects are often difficult to fully screen out during yield testing, impacting product yield and reliability.

[0005] Therefore, how to solve the reliability problem caused by the thinning of the floating gate of the PIP stack capacitor in ETOX Nor Flash due to process factors is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to overcome the reliability problem of the PIP (Poly-Insulator-Poly) stack capacitor in memory devices such as ETOX Nor Flash in the prior art. During the manufacturing process, the floating gate (FG) thickness in the PIP capacitor area (especially the FG pickup) becomes thinner due to the loading effect of chemical mechanical polishing (CMP) and the consumption of floating gate (FG) material by the self-aligned metal silicide (Silicide) process. As a result, the floating gate is easily penetrated during the subsequent formation of contact holes or the gate oxide underneath is broken down during power-on.

[0007] In order to solve the above technical problems, the present invention provides a polysilicon-insulating layer-polysilicon stacked capacitor structure and a manufacturing method thereof.

[0008] According to one aspect of the present invention, a polysilicon-insulating layer-polysilicon stacked capacitor structure is provided, comprising:

[0009] semiconductor substrates;

[0010] a floating gate formed on the semiconductor substrate, the floating gate constituting a lower plate of the PIP stack capacitor;

[0011] an intergate dielectric layer formed on the floating gate;

[0012] a control gate formed on the inter-gate dielectric layer, the control gate constituting an upper plate of the PIP stack capacitor;

[0013] The floating gate includes at least one predetermined region, a surface of which is not formed with self-aligned metal silicide and has a contact with the floating gate; and

[0014] The control gate and the surface of the active region of the semiconductor substrate are formed with self-aligned metal silicide, and contacts to the self-aligned metal silicide on the control gate and the self-aligned metal silicide on the active region of the semiconductor substrate are formed, respectively.

[0015] Preferably, grooves are formed on the shallow trench isolation adjacent to both sides of the gate structure of the floating gate.

[0016] Preferably, a tunneling oxide layer is formed between the semiconductor substrate and the floating gate.

[0017] Preferably, the floating gate comprises polysilicon.

[0018] Preferably, in step two, the inter-gate dielectric layer is an oxide-nitride-oxide stack structure.

[0019] Preferably, a sidewall spacer is formed on the sidewall of the stack gate structure comprising the control gate and the inter-gate dielectric layer.

[0020] According to another aspect of the present application, a method for manufacturing a PIP stack capacitor is provided, comprising the following steps:

[0021] Step one, forming a floating gate (FG), which constitutes the lower plate of the PIP stack capacitor;

[0022] Step two, forming an inter-gate dielectric layer on the floating gate;

[0023] Step three, forming a control gate (CG) on the inter-gate dielectric layer, which constitutes the upper plate of the PIP stack capacitor;

[0024] Step four, performing a self-aligned metal silicide formation process, wherein a self-aligned metal silicide block (SAB) mask is used to cover at least one predetermined region of the floating gate to prevent the formation of self-aligned metal silicide on the predetermined region of the floating gate covered by the SAB mask, and to form self-aligned metal silicide on the control gate and the active region of the semiconductor substrate not covered by the SAB mask; and

[0025] Step five, forming a contact to the floating gate at the predetermined region, and forming contacts to the self-aligned metal silicide on the control gate and the self-aligned metal silicide on the active region of the semiconductor substrate, respectively.

[0026] Preferably, the PIP stack capacitor is used in the manufacturing of a Nor Flash memory with an EPROM tunneling oxide layer structure.

[0027] Preferably, after step one and before step two, further comprising: performing a corner rounding shallow trench etch to form a recess on the shallow trench isolation adjacent to both sides of the gate structure of the floating gate.

[0028] Preferably, in step one, the floating gate is formed on a semiconductor substrate, and a tunneling oxide layer is formed between the semiconductor substrate and the floating gate.

[0029] Preferably, in step one, the forming the floating gate comprises: depositing a floating gate material layer; performing ion implantation on the floating gate material layer; and performing chemical mechanical polishing on the floating gate material layer to achieve planarization, thereby forming the floating gate lower plate.

[0030] Preferably, the floating gate comprises polysilicon.

[0031] Preferably, in step two, the inter-gate dielectric layer is an oxide-nitride-oxide stack structure.

[0032] Preferably, in step two, after the forming the inter-gate dielectric layer, further comprising: removing the inter-gate dielectric layer material outside the floating gate lower plate area by an inter-gate dielectric layer etching process; and removing the inter-gate dielectric layer material on the shallow trench isolation structure by an inter-gate dielectric layer etching process.

[0033] Preferably, in step three, after the forming the control gate, further comprising: removing the control gate material on the shallow trench isolation structure by a control gate etching process.

[0034] Preferably, after step three and before step four, further comprising: patterning etching the control gate and the inter-gate dielectric layer by a gate line etching to form a stacked gate structure comprising the control gate and the inter-gate dielectric layer, the patterning etching defining an upper plate area of the PIP stacked capacitor and exposing a partial area of the floating gate.

[0035] Preferably, after the gate line etching and before step four, further comprising: forming a sidewall spacer on the sidewall of the stacked gate structure.

[0036] Preferably, in step four, the performing a self-aligned metal silicide formation process comprises: removing a surface oxide to expose an active region of the semiconductor substrate and / or a polysilicon region of the control gate in an area not covered by the self-aligned metal silicide block mask; depositing a metal material layer; and performing an annealing process to form a self-aligned metal silicide on a surface of the exposed active region of the semiconductor substrate and / or the polysilicon region of the control gate.

[0037] Preferably, the metal material layer comprises at least one metal selected from nickel (Ni), cobalt (Co), titanium (Ti), platinum (Pt), or an alloy comprising the at least one metal.

[0038] Preferably, the metal material layer comprises a nickel-platinum (NiPt) alloy.

[0039] Preferably, in step five, the forming the contact comprises: simultaneously forming, by a contact hole etching process, a contact to the floating gate at the predetermined region, a contact to self-aligned metal silicide on the control gate, and a contact to self-aligned metal silicide on an active region of the semiconductor substrate.

[0040] As described above, the polycrystalline silicon-insulating layer-polycrystalline silicon stacked capacitor structure and the manufacturing method thereof have the following beneficial effects:

[0041] The polycrystalline silicon-insulating layer-polycrystalline silicon stacked capacitor structure and the manufacturing method thereof provided by the present application effectively maintain the thickness of the floating gate in the specific region by optimizing the self-aligned metal silicide forming process step, in particular, by introducing a SAB mask to prevent the formation of metal silicide in the specific region of the floating gate of the PIP capacitor, avoiding the reliability problems such as contact hole etching through the bottom or gate oxide breakdown caused by the floating gate being too thin, and combining the precise gate stack structure sidewall spacer formation, interlayer dielectric layer deposition and contact hole formation process, and selectively combining the CRS etching step optimizer to optimize the electric field distribution at the edge of the device, improving the long-term stability and working life of the device. At the same time, the method has good process compatibility, low modification cost, and has important industrial application value. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 A process flow diagram of the present application is shown;

[0043] Figure 2 A schematic diagram of depositing a floating gate material layer of the present application is shown;

[0044] Figure 3 A schematic diagram of forming a floating gate lower plate of the present application is shown;

[0045] Figure 4 A schematic diagram of forming an inter-gate dielectric layer of the present application is shown;

[0046] Figure 5 A schematic diagram of defining the coverage of the inter-gate dielectric layer of the present application is shown;

[0047] Figure 6 A schematic diagram of forming a control gate on the inter-gate dielectric layer of the present application is shown;

[0048] Figure 7FIG. 1 shows a schematic diagram of patterning and etching a control gate (CG) and an inter-gate dielectric layer by gate line etching (GPL ET) according to embodiments of the present application;

[0049] Figure 8 FIG. 2 shows a schematic diagram of forming a sidewall spacer on a sidewall of a stacked gate structure according to embodiments of the present application;

[0050] Figure 9 FIG. 3 shows a schematic diagram of forming a self-aligned metal silicide according to embodiments of the present application;

[0051] Figure 10 FIG. 4 shows a schematic diagram of forming a contact according to embodiments of the present application. DETAILED DESCRIPTION

[0052] Other advantages and embodiments of the present application will be described in detail in the following specific examples. The present application can be implemented or applied in other different embodiments, and the details in the present specification can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0053] Reference will now be made to Figure 10 The embodiments of the present application first provide a polysilicon-insulator-polysilicon stacked capacitor structure.

[0054] The polysilicon-insulator-polysilicon stacked capacitor structure includes:

[0055] a semiconductor substrate 101;

[0056] a floating gate 104 (FG) formed on the semiconductor substrate 101, the floating gate 104 constituting a lower plate of the PIP stacked capacitor;

[0057] an inter-gate dielectric layer 105 formed on the floating gate 104, and a control gate 106 (CG) formed on the inter-gate dielectric layer 105, the control gate 106 constituting an upper plate of the PIP stacked capacitor;

[0058] wherein the floating gate 104 includes at least one predetermined region, a surface of the predetermined region is not formed with a self-aligned metal silicide 108, and a contact 110 to the floating gate 104 is formed; and

[0059] a surface of the control gate 106 and an active region of the semiconductor substrate 101 is formed with the self-aligned metal silicide 108, and a contact 110 to the self-aligned metal silicide 108 on the control gate 106 and the self-aligned metal silicide 108 on the active region of the semiconductor substrate 101 is formed, respectively.

[0060] The core of this structure design is that by not forming metal silicide in the key area of the floating gate 104 (FG pickup of PIP capacitor), the original thickness of the floating gate 104 in this area can be effectively maintained, avoiding the thinning of the floating gate 104 due to metal silicide consumption, thereby significantly improving the process window during the subsequent contact hole formation, preventing the contact hole from penetrating the floating gate 104 or damaging the underlying tunneling oxide layer 102, and thus improving the reliability and yield of the PIP capacitor and even the entire device. In other areas that require low resistance, such as the control gate 106 and the active area, metal silicide is still formed to ensure the electrical performance of the device.

[0061] In some embodiments, recesses are formed on the shallow trench isolation 103 (STI) adjacent to both sides of the gate structure of the floating gate 104. These recesses are usually formed by corner rounding shallow trench (CRS) etching, which aims to improve the electric field distribution of the gate edge and reduce the electric field concentration, thereby improving the reliability of the gate oxide layer (such as the interlayer dielectric layer 105 or the tunneling oxide layer 102).

[0062] In some embodiments, a tunneling oxide layer 102 (TUNOX) is formed between the semiconductor substrate 101 and the floating gate 104. The tunneling oxide layer 102 is a key thin film layer in memory devices such as ETOX Nor Flash, which enables charge tunneling for writing and erasing.

[0063] In some embodiments, the floating gate 104 (FG) includes polysilicon. Polysilicon is a widely used gate material in semiconductor manufacturing.

[0064] In some embodiments, the interlayer dielectric layer 105 is an oxide-nitride-oxide (ONO) stack structure. The ONO stack structure is widely used in non-volatile memory due to its excellent charge retention characteristics and high breakdown field strength.

[0065] In some embodiments, a side wall spacer 107 is formed on the sidewall of the stacked gate structure including the control gate 106 and the interlayer dielectric layer 105. The side wall spacer 107 not only protects the sidewall of the stacked gate structure, but also can be used for self-aligned processes, such as as a mask during ion implantation for source / drain formation or subsequent etching steps, to accurately control critical dimensions.

[0066] In some embodiments, an inter-layer dielectric (ILD) 109 is formed over the floating gate 104, the control gate 106, and the semiconductor substrate 101, and the contacts 110 to the floating gate 104, the self-aligned metal silicide 108 on the control gate 106, and the self-aligned metal silicide 108 on the active region of the semiconductor substrate 101 all pass through the inter-layer dielectric 109. The inter-layer dielectric 109 can include a silicon oxide based material, such as silicon oxide (SiO2), fluorine-doped silicon oxide (FSG), carbon-doped silicon oxide (SiCOH), or a low-k material formed by plasma-enhanced chemical vapor deposition (PECVD), etc. The contacts 110 can include a metal material, such as tungsten (W), copper (Cu), aluminum (Al), or alloys thereof, and can include a barrier layer and / or a seed layer, such as titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), tantalum (Ta), etc.

[0067] Embodiments of the present application also provide a method for manufacturing a PIP stacked capacitor, which includes the following steps:

[0068] Step one, forming a floating gate 104 (FG) that constitutes the lower plate of the PIP stacked capacitor. Precise control of the formation of the floating gate 104 lays the foundation for the subsequent construction of high-quality PIP capacitors.

[0069] In some embodiments, in step one, the floating gate 104 is formed on the semiconductor substrate 101, and a tunneling oxide layer 102 (TUNOX) is formed between the semiconductor substrate 101 and the floating gate 104. The tunneling oxide layer 102 is a key structure for realizing charge tunneling writing and erasing in flash memory devices, and its quality directly affects the performance and life of the device.

[0070] In some embodiments, in step one, forming the floating gate 104 (FG) includes: depositing a floating gate material layer to form a structure as shown in FIG. 1B; ion implantation on the floating gate material layer to adjust its conductivity type and conductivity to meet the design requirements of the device; and chemical mechanical polishing (CMP) on the floating gate material layer to achieve planarization, thereby forming the floating gate 104 lower plate to form a structure as shown in FIG. 1C. Figure 2 Figure 3 The CMP planarization step is crucial for the uniform growth and patterning of subsequent thin films, and helps to improve the uniformity and reliability of the device.

[0071] In some embodiments, the floating gate 104 (FG) includes polysilicon. Polysilicon is a commonly used gate material in semiconductor manufacturing, with mature processes and good electrical properties.

[0072] ​In some embodiments, after step 1 and before step 2, the process further includes performing corner-rounded shallow trench (CRS) etching to form recesses in the shallow trench isolation (STI) 103 adjacent to the gate structure on both sides of the floating gate 104. The purpose of the CRS etching step is to improve the electric field distribution at the gate edge and reduce the electric field concentration effect at the gate corner, thereby improving the reliability of the gate oxide layer (such as the subsequently formed inter-gate dielectric layer 105 or tunnel oxide layer 102) and reducing the risk of early breakdown due to electric field concentration. Furthermore, the recesses formed in the STI can affect the step coverage of subsequent thin films and may be used to optimize the isolation performance or stress management of the device.

[0073] Step 2: forming an inter-gate dielectric layer 105 on the floating gate 104. The inter-gate dielectric layer 105 is used to isolate the floating gate 104 and the control gate 106 and store charges. The dielectric constant and thickness of the inter-gate dielectric layer 105 have a significant impact on the capacitance value.

[0074] In some embodiments, in step 2, the inter-gate dielectric layer 105 is an oxide-nitride-oxide (ONO) stacked structure. The ONO structure has good charge retention properties and a high breakdown field strength, which can effectively prevent charge leakage and improve the non-volatility of the memory.

[0075] In some embodiments, in step 2, after forming the inter-gate dielectric layer 105, a Figure 4 The structure shown in FIG. 1 further includes: removing the inter-gate dielectric layer 105 material outside the lower plate region of the floating gate 104 by an inter-gate dielectric layer 105 etching process; and removing the inter-gate dielectric layer 105 material on the shallow trench isolation 103 (STI) structure by an inter-gate dielectric layer 105 etching process, forming the following structure: Figure 5 These etching steps accurately define the coverage of the inter-gate dielectric layer 105, ensuring the correct formation of the PIP capacitor and avoiding adverse effects on other areas.

[0076] Step 3: forming a control gate 106 (CG) on the inter-gate dielectric layer 105. The control gate 106 constitutes the upper plate of the PIP stack capacitor. Figure 6 The control gate 106 is used to apply a voltage to control the charge state in the floating gate 104.

[0077] In some embodiments, after forming the control gate 106 (CG) in step 3, the process further includes removing the control gate 106 material located on the shallow trench isolation (STI) structure 103 by etching the control gate 106. This step ensures the accuracy of the control gate 106 pattern and avoids electrical short circuits between different device units.

[0078] In some embodiments, after step three and before step four, further comprising: patterning and etching the control gate 106 (CG) and the inter-gate dielectric layer 105 by a gate line etch (GPL ET) to form a stack gate structure including the control gate 106 and the inter-gate dielectric layer 105, the patterning and etching defining an upper plate region of the PIP stack capacitor and exposing a portion of the floating gate 104 to form a structure as shown in Figure 7 The GPL ET step precisely defines the overall stack structure of the PIP capacitor upper plate and the inter-gate dielectric layer 105, which is important for precise control of the capacitor value and subsequent process window assurance.

[0079] In some embodiments, after the gate line etch (GPL ET) and before step four, further comprising: forming a sidewall spacer 107 on the sidewalls of the stack gate structure to form a structure as shown in Figure 8 The formation of the sidewall spacer 107 (i.e. part of the SPA ET process) can protect the sidewalls of the stack gate structure from damage in subsequent processes and can be used in subsequent self-aligned etching steps, for example, as a mask to remove the inter-gate dielectric layer 105 between the stack gate structures, thereby precisely exposing the floating gate 104 for contact 110 formation.

[0080] More specifically, the step of forming the sidewall spacer 107 can comprise: first, after the formation of the stack gate structure by the gate line etch (GPL ET), conformally depositing a spacer material layer that uniformly covers the top and sidewalls of the stack gate structure and the exposed floating gate 104 surface. The spacer material can be, for example, silicon nitride (SiN) or silicon oxide (Si02), with silicon nitride often being chosen for its good etch selectivity over oxides and polysilicon commonly used in subsequent etching processes. The deposition method can employ chemical vapor deposition (CVD) such as low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). Subsequently, the deposited spacer material layer is anisotropically etched, for example, by reactive ion etching (RIE). This anisotropic etching process removes the spacer material mainly from the horizontal surfaces (e.g. the top of the stack gate structure and the exposed floating gate 104 surface) while leaving the spacer material on the vertical sidewalls of the stack gate structure, thereby forming the desired sidewall spacer 107. The width of the formed sidewall spacer 107 can be precisely controlled by controlling the thickness of the deposited spacer material layer and the parameters of the anisotropic etching.

[0081] Step four, a self-aligned metal silicide 108 formation process is performed, in which a self-aligned metal silicide 108 block (SAB) mask is used to cover at least one predetermined region of the floating gate 104 to prevent the formation of the self-aligned metal silicide 108 on the covered predetermined region of the floating gate 104, and the self-aligned metal silicide 108 is formed on the control gate 106 and the active area of the semiconductor substrate 101 which are not covered by the self-aligned metal silicide 108 block mask, forming a structure as shown in Figure 9 This step is one of the cores of the present application. By using the SAB mask at the floating gate 104 pickup end of the PIP capacitor region, the formation of metal silicide in this region can be selectively prevented. The metal silicide process is usually used to reduce the contact 110 resistance and sheet resistance of the active area and the polysilicon gate, but the formation process consumes part of the silicon material. For the floating gate 104 of the PIP capacitor region, the thickness of the floating gate 104 in this region may have been thinned due to the CMP load effect, and if it is further consumed by metal silicide, it is extremely easy to be punched during the subsequent contact hole etching, or to cause the underlying tunneling oxide layer 102 to break down during the power-on operation. The present application applies the SAB mask to prevent the formation of metal silicide at the bottom of the floating gate 104 of the PIP capacitor region (i.e. the bottom of the future contact hole), thereby avoiding the consumption of the floating gate 104 material, effectively maintaining the thickness of the floating gate 104 in this region, significantly reducing the risk of contact hole punching or gate oxide breakdown, and improving the reliability and yield of the device. At the same time, metal silicide is still formed in places where resistance reduction is needed, such as the control gate 106 and the active area of the substrate 101, to ensure the overall performance of the device.

[0082] This method only needs to modify the SAB mask layout, with small changes in the process flow and controllable cost increases, good economic benefits and manufacturability.

[0083] In some embodiments, in step four, the self-aligned metal silicide 108 formation process includes: removing the surface oxide to expose the active area (AA) of the semiconductor substrate 101 and / or the polysilicon region of the control gate 106 in the region not covered by the self-aligned metal silicide 108 block (SAB) mask, to ensure that the metal can react well with the exposed silicon surface; depositing a metal material layer; and performing an annealing process to form the self-aligned metal silicide 108 on the surface of the exposed active area of the semiconductor substrate 101 and / or the polysilicon region of the control gate 106.

[0084] In some embodiments, the metal material layer includes at least one metal selected from nickel (Ni), cobalt (Co), titanium (Ti), platinum (Pt), or an alloy containing at least one of the foregoing metals. These metals and their alloys are commonly used in the semiconductor industry to form low-resistance metal silicides.

[0085] In some embodiments, the metal material layer comprises a nickel platinum (NiPt) alloy. Nickel platinum silicide has good thermal stability and low resistivity, and is a commonly used silicide material in advanced process nodes.

[0086] Step five, forming contacts 110 to the predetermined region of the floating gate 104, and separately to the self-aligned metal silicide 108 on the control gate 106 and the self-aligned metal silicide 108 on the active region of the semiconductor substrate 101, forms a structure as shown in FIG. 1C. This step is typically performed after deposition of an interlayer dielectric layer 109 (ILD). Figure 10

[0087] First, one or more layers of interlayer dielectric layer 109, such as silicon oxide (SiO2), fluorine-doped silicon oxide (FSG), carbon-doped silicon oxide (SiCOH), or low-k materials formed by plasma-enhanced chemical vapor deposition (PECVD), are deposited for electrical isolation. Subsequently, a contact hole is formed in the interlayer dielectric layer 109 by a lithography and etching process (e.g., contact etch, CT_ET) to expose the predetermined region of the floating gate 104, the self-aligned metal silicide 108 on the control gate 106, and the self-aligned metal silicide 108 on the active region of the semiconductor substrate 101, respectively. Finally, the contact hole is filled with a conductive material to form the contact 110. The conductive material can include a metal, such as tungsten (W), copper (Cu), aluminum (Al), or alloys thereof, and a barrier layer and / or seed layer, such as titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), tantalum (Ta), etc., can be deposited first to improve adhesion and prevent diffusion of the metal before filling the main metal.

[0088] The step of filling the conductive material to form the contact 110 plug typically includes, after forming the contact hole by etching and exposing the underlying conductive region (i.e., the predetermined region of the floating gate 104, the metal silicide on the control gate 106, and the metal silicide on the active region of the semiconductor substrate 101), depositing one or more layers of liner and / or barrier layer on the inner wall and bottom of the contact hole to ensure good ohmic contact 110 and prevent diffusion of the subsequent filling metal. For example, a layer of titanium (Ti) can be deposited first as an adhesion and improvement layer for the contact 110 by physical vapor deposition (PVD) or atomic layer deposition (ALD), followed by a layer of titanium nitride (TiN) as a barrier layer, forming a Ti / TiN stack structure. Other optional liner / barrier layer materials include tantalum nitride (TaN), tantalum (Ta) / tantalum nitride (Ta / TaN) stack, etc. These liner / barrier layers can effectively prevent the filling metal, such as tungsten, from undesirably reacting with the underlying silicon or silicide (e.g., forming high-resistance tungsten silicide compounds).

[0089] ​After the liner / barrier layer is deposited, the main conductive metal is then filled by a chemical vapor deposition (CVD) process to form the contact plug. Tungsten (W) is a metal material widely used for contact hole filling at present, and a tungsten hexafluoride (WF6) is usually used as a precursor gas for CVD deposition. Tungsten has good step coverage, can effectively fill the contact hole with high aspect ratio, and has low resistivity and good high-temperature resistance.

[0090] After the tungsten or other conductive metal filling is completed, a chemical mechanical polishing (CMP) process is usually used to remove the excess conductive metal on the wafer surface and the excess liner / barrier layer material below, so that the conductive metal is only retained inside the contact hole, and the wafer surface is planarized to facilitate the subsequent interconnection line manufacturing. Thus, the contact plug is formed.

[0091] Since the predetermined region of the floating gate 104 in the PIP capacitor region in step four is not formed with metal silicide, a relatively thick floating gate 104 is retained, so that when the contact 110 to the floating gate 104 is formed, the problem of the contact hole etching punching through the floating gate 104 or damaging the underlying tunneling oxide layer 102 can be effectively avoided. This directly improves the structural integrity and electrical performance stability of the PIP capacitor, thereby improving the reliability of the entire memory device and reducing the early failure rate (EFR).

[0092] Moreover, experimental results show that the formation of no metal silicide on the floating gate 104 has little effect on the capacitance of the ONO capacitor, and the chip pin measurement (CP) and packaging verification results are also good, proving the feasibility and superiority of the technical solution.

[0093] In some embodiments, in step five, the forming of the contact 110 includes: simultaneously forming the contact 110 to the floating gate 104 in the predetermined region, the contact 110 to the self-aligned metal silicide 108 on the control gate 106, and the contact 110 to the self-aligned metal silicide 108 on the active region of the semiconductor substrate 101 by a contact hole etching (CT_ET) process. Using a contact hole etching process to simultaneously form multiple contacts 110 helps to simplify the manufacturing process and improve production efficiency.

[0094] In some embodiments, the PIP stacked capacitor is used for the manufacturing of a Nor Flash memory with an EPROM tunneling oxide layer 102 structure. The PIP stacked capacitor manufacturing method provided by the present application can effectively solve the problem of the PIP capacitor region floating gate 104 being too thin due to the CMP load effect and metal silicide consumption in the ETOX Nor Flash, and when combined with the CRS etching step, the gate edge reliability can be further improved, thereby significantly improving the reliability and yield of the Nor Flash product.

[0095] In summary, the poly-silicon-insulation layer-poly-silicon stacked capacitor structure and the manufacturing method thereof provided by the present application, by optimizing the self-aligned metal silicide 108 forming process step, especially by introducing SAB mask to prevent the formation of metal silicide in the specific area of the floating gate 104 of the PIP capacitor, effectively maintains the thickness of the floating gate 104 in the area, avoids the reliability problems such as contact hole etching through the bottom or gate oxide breakdown caused by the too thin floating gate 104, and combines the precise gate stack structure side wall spacer 107 forming, interlayer dielectric layer 109 deposition and contact hole forming process, and selectively combines the CRS etching step optimizer to optimize the electric field distribution of the device edge, improves the long-term stability and working life of the device, at the same time, the method has good process compatibility, low modification cost, and has important industrial application value.

[0096] It should be noted that the diagrams provided in the embodiments only illustrate the basic concept of the present application in a schematic manner, and only show the components related to the present application in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component may be arbitrarily changed in type, number and proportion, and the component layout pattern may be more complex.

[0097] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A polysilicon-insulating layer-polysilicon stacked capacitor structure, characterized in that: include: semiconductor substrates; a floating gate formed on the semiconductor substrate, the floating gate constituting a lower plate of the polysilicon-insulating layer-polysilicon stack capacitor; an intergate dielectric layer formed on the floating gate; a control gate formed on the inter-gate dielectric layer, the control gate constituting an upper plate of the polysilicon-insulating layer-polysilicon stack capacitor; The floating gate includes at least one predetermined region, a surface of which is not formed with self-aligned metal silicide and has a contact with the floating gate; and Self-aligned metal silicide is formed on the surfaces of the control gate and the active region of the semiconductor substrate, and contacts are formed to the self-aligned metal silicide on the control gate and the self-aligned metal silicide on the active region of the semiconductor substrate, respectively.

2. The polysilicon-insulating layer-polysilicon stacked capacitor structure according to claim 1, wherein: Grooves are formed on the shallow trench isolations adjacent to each other on both sides of the gate structure of the floating gate.

3. The polysilicon-insulating layer-polysilicon stacked capacitor structure according to claim 1, wherein: A tunneling oxide layer is formed between the semiconductor substrate and the floating gate.

4. The polysilicon-insulating layer-polysilicon stacked capacitor structure according to claim 1, wherein: The floating gate includes polysilicon.

5. The polysilicon-insulating layer-polysilicon stacked capacitor structure according to claim 1, wherein: In step 2, the inter-gate dielectric layer is an oxide-nitride-oxide stacked structure.

6. The polysilicon-insulating layer-polysilicon stacked capacitor structure according to claim 1, wherein: Sidewall spacers are formed on the sidewalls of the stacked gate structure including the control gate and the inter-gate dielectric layer.

7. A method for manufacturing a polysilicon-insulating layer-polysilicon stacked capacitor structure, characterized in that: At least: Step 1: forming a floating gate, wherein the floating gate constitutes the lower plate of the polysilicon-insulating layer-polysilicon stack capacitor; Step 2: forming an inter-gate dielectric layer on the floating gate; Step 3: forming a control gate on the inter-gate dielectric layer, wherein the control gate constitutes an upper plate of the polysilicon-insulating layer-polysilicon stack capacitor; Step 4: performing a self-aligned metal silicide formation process, wherein a self-aligned metal silicide blocking mask is used to cover at least one predetermined region of the floating gate to prevent the formation of self-aligned metal silicide on the covered predetermined region of the floating gate, and self-aligned metal silicide is formed on the control gate and the active region of the semiconductor substrate not covered by the self-aligned metal silicide blocking mask; and Step 5: forming a contact to the floating gate located in the predetermined area, and forming contacts to the self-aligned metal silicide on the control gate and the self-aligned metal silicide on the active area of ​​the semiconductor substrate respectively.

8. The method for manufacturing a polysilicon-insulating layer-polysilicon stacked capacitor structure according to claim 7, wherein: The polysilicon-insulating layer-polysilicon stack capacitor is used for manufacturing a Nor Flash memory with an EPROM tunneling oxide layer structure.

9. The method for manufacturing a polysilicon-insulating layer-polysilicon stacked capacitor structure according to claim 7, wherein: After step one and before step two, the method further includes: performing corner rounding shallow trench etching to form grooves on the shallow trench isolations adjacent to the gate structure of the floating gate.

10. The method for manufacturing a polysilicon-insulating layer-polysilicon stacked capacitor structure according to claim 7, wherein: In step 1, the floating gate is formed on a semiconductor substrate, and a tunneling oxide layer is formed between the semiconductor substrate and the floating gate.

11. The method for manufacturing a polysilicon-insulating layer-polysilicon stacked capacitor structure according to claim 7 or 10, wherein: In step 1, forming the floating gate includes: depositing a floating gate material layer; performing ion implantation on the floating gate material layer; and performing chemical mechanical polishing on the floating gate material layer to achieve planarization, thereby forming the floating gate bottom plate.

12. The method for manufacturing a polysilicon-insulating layer-polysilicon stacked capacitor structure according to claim 7, wherein: The floating gate includes polysilicon.

13. The method for manufacturing a polysilicon-insulating layer-polysilicon stacked capacitor structure according to claim 7, wherein: In step 2, the inter-gate dielectric layer is an oxide-nitride-oxide stacked structure.

14. The method for manufacturing a polysilicon-insulating layer-polysilicon stacked capacitor structure according to claim 7, wherein: In step 2, after the inter-gate dielectric layer is formed, it also includes: removing the inter-gate dielectric layer material outside the floating gate lower plate area through an inter-gate dielectric layer etching process; and removing the inter-gate dielectric layer material on the shallow trench isolation structure through an inter-gate dielectric layer etching process.

15. The method for manufacturing a polysilicon-insulating layer-polysilicon stacked capacitor structure according to claim 7, wherein: In step three, after forming the control gate, the method further includes: removing the control gate material located on the shallow trench isolation structure through a control gate etching process.

16. The method for manufacturing a polysilicon-insulating layer-polysilicon stacked capacitor structure according to claim 7, wherein: After step three and before step four, the method further includes: patterning the control gate and the inter-gate dielectric layer by gate line etching to form a stacked gate structure including the control gate and the inter-gate dielectric layer, wherein the patterned etching defines the upper plate area of ​​the polysilicon-insulating layer-polysilicon stack capacitor and exposes a partial area of ​​the floating gate.

17. The method for manufacturing a polysilicon-insulating layer-polysilicon stacked capacitor structure according to claim 16, wherein: After etching the gate connection and before step 4, the method further includes forming sidewall spacers on the sidewalls of the stacked gate structure.

18. The method for manufacturing a polysilicon-insulating layer-polysilicon stacked capacitor structure according to claim 7, wherein: In step four, the self-aligned metal silicide formation process includes: removing the surface oxide in the area not covered by the self-aligned metal silicide blocking mask to expose the active area of ​​the semiconductor substrate and / or the polysilicon area of ​​the control gate; depositing a metal material layer; and performing annealing treatment to form a self-aligned metal silicide on the surface of the exposed active area of ​​the semiconductor substrate and / or the polysilicon area of ​​the control gate.

19. The method for manufacturing a polysilicon-insulating layer-polysilicon stacked capacitor structure according to claim 18, wherein: The metal material layer includes at least one metal selected from nickel (Ni), cobalt (Co), titanium (Ti), platinum (Pt), or an alloy including the foregoing at least one metal.

20. The method for manufacturing a polysilicon-insulating layer-polysilicon stacked capacitor structure according to claim 19, wherein: The metal material layer includes nickel-platinum (NiPt) alloy.

21. The method for manufacturing a polysilicon-insulating layer-polysilicon stacked capacitor structure according to claim 7, wherein: In step five, the forming of the contact includes: forming a contact to the floating gate located in the predetermined area through a contact hole etching process, forming a contact to the self-aligned metal silicide on the control gate, and forming a contact to the self-aligned metal silicide on the active area of ​​the semiconductor substrate.

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