Preparation method of vertical channel transistor and vertical channel transistor structure

Abstract

The invention provides a preparation method of a vertical channel transistor and a vertical channel transistor structure, and the preparation method of the vertical channel transistor comprises the steps: forming a bottom source drain layer, a first extension layer, a channel layer, a second extension layer and a top source drain layer which are sequentially stacked from bottom to top on a substrate, the bottom source-drain layer, the channel layer and the top source-drain layer are made of silicon, the first extension layer and the second extension layer are made of silicon germanium, and P-type ions are doped in the bottom source-drain layer, the first extension layer, the second extension layer and the top source-drain layer. P-type ions are doped in a bottom source-drain layer, a first extension layer, a second extension layer and a top source-drain layer, so that in the process of diffusing the P-type ions to a channel layer, the hindrance suffered by the P-type ions in a first extension region and a second extension region is reduced, namely, the resistance of the first extension region and the second extension region is reduced; therefore, the driving capability of the vertical channel PMOS transistor is improved, and the driving capability performance of the PMOS transistor and the driving capability performance of the NMOS transistor are better matched.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor preparation, and in particular to a preparation method of a vertical channel transistor and a vertical channel transistor structure. BACKGROUND

[0002] At the 3nm node and smaller processes, vertical channel transistors exhibit many advantages compared to horizontal channel transistors. Since the channel of the vertical channel transistor is perpendicular to the substrate surface, more transistors can be integrated in the same chip area, thereby saving chip area. In addition, the vertical structure allows longer channels to be implemented in smaller horizontal areas, so that even at very small process nodes, the gate can still effectively control the channel, thereby improving transistor performance and reducing power consumption.

[0003] However, in the vertical channel transistor, the driving capability performance of the PMOS tube and the NMOS tube does not match, causing the rise time and the fall time of the digital circuit output signal to be asymmetric, thereby causing timing problems. SUMMARY

[0004] The present application provides a preparation method of a vertical channel transistor and a vertical channel transistor structure, which improves the driving capability of the PMOS tube to achieve better matching of the driving capability performance of the PMOS tube and the NMOS tube.

[0005] According to a first aspect of the present application, a preparation method of a vertical channel transistor is provided, comprising: forming, on a substrate, a bottom source-drain layer, a first extension layer, a channel layer, a second extension layer and a top source-drain layer stacked in order from bottom to top, the materials of the bottom source-drain layer, the channel layer and the top source-drain layer being silicon, the materials of the first extension layer and the second extension layer being silicon germanium, and P-type ions being doped in the bottom source-drain layer, the first extension layer, the second extension layer and the top source-drain layer.

[0006] Optionally, the doping concentration of the P-type ions in the first extension layer is the same as that in the bottom source-drain layer, and the doping concentration of the P-type ions in the second extension layer is the same as that in the top source-drain layer.

[0007] Optionally, the method of forming, on a substrate, the bottom source-drain layer, the first extension layer, the channel layer, the second extension layer and the top source-drain layer stacked in order from bottom to top comprises: forming, on a substrate, a bottom source-drain layer, an initial first extension layer, an initial channel layer, an initial second extension layer and a top source-drain layer stacked in order from bottom to top; performing lateral etching on the initial first extension layer to form a first recess with a lateral opening between the bottom source-drain layer and the initial channel layer, and to form a first extension layer; lateral etching the initial second extension layer to form a second recessed groove with a lateral opening between the top source-drain layer and the initial channel layer, and to form a second extension layer; forming a first gate isolation dielectric layer in the first recessed groove; forming a second gate isolation dielectric layer in the second recessed groove; after forming the first gate isolation dielectric layer and the second gate isolation dielectric layer, laterally etching the initial channel layer to form a channel layer, and the sidewall surface of the channel layer is recessed relative to the sidewall surface of the first gate isolation dielectric layer and the sidewall surface of the second gate isolation dielectric layer, so as to form a gate recessed groove with a lateral opening between the first gate isolation dielectric layer and the second gate isolation dielectric layer, and the groove bottom of the gate recessed groove exposes the sidewall surface of the channel layer; forming a gate structure in at least the gate recessed groove.

[0008] Optionally, the method further comprises: in the process of forming the bottom source-drain layer, the initial first extension layer, the initial channel layer, the initial second extension layer and the top source-drain layer stacked in sequence from bottom to top on the substrate, etching the substrate to form an isolation groove in the substrate around the bottom source-drain layer; after forming the bottom source-drain layer, the initial first extension layer, the initial channel layer, the initial second extension layer and the top source-drain layer stacked in sequence from bottom to top on the substrate, forming a first isolation layer in the isolation groove and on the side of the bottom source-drain layer.

[0009] Optionally, before forming the first gate isolation dielectric layer and the second gate isolation dielectric layer, a protection structure is formed on the top surface of the top source-drain layer on the substrate; after forming the first gate isolation dielectric layer and the second gate isolation dielectric layer, and before laterally etching the initial channel layer, the method further comprises: forming a protection sidewall on the surface of the second gate isolation dielectric layer, the side of the top source-drain layer and the surface of the protection structure; and forming a second isolation layer on the side of the first gate isolation dielectric layer.

[0010] Optionally, the method for forming the gate structure comprises: forming a gate dielectric material film on the surface of the second isolation layer, the inner wall surface of the gate recessed groove, the side of the protection sidewall and the surface of the protection structure; etching to remove the gate dielectric material film on part of the surface of the second isolation layer; forming a third isolation layer on the second isolation layer and the gate dielectric material film on the partial surface of the second isolation layer, a top surface of the third isolation layer being flush with a bottom surface of the protective spacer to expose the protective spacer and the protective structure; etching to remove the gate dielectric material film on the surface of the protective spacer and the protective structure to form the gate structure.

[0011] Optionally, after forming the gate structure, the method further comprises: forming a fourth isolation layer on the surface of the third isolation layer and the surface of the top source / drain layer; forming a first electrode in the fourth isolation layer, the first electrode being in contact with the top source / drain layer; forming a second electrode in the third isolation layer and the fourth isolation layer, the second electrode being in contact with the gate dielectric material film on the partial surface of the second isolation layer.

[0012] Optionally, a K value of a material of the first gate isolation dielectric layer is less than a K value of a material of the second isolation layer, and a K value of a material of the second gate isolation dielectric layer is less than a K value of a material of the fourth isolation layer.

[0013] Optionally, a method for forming, from bottom to top, a bottom source / drain layer, an initial first extension layer, an initial channel layer, an initial second extension layer, and a top source / drain layer on a substrate comprises: forming, from bottom to top, a bottom source / drain material layer, a first extension material layer, a channel material layer, a second extension material layer, and a top source / drain material layer on the substrate, and in the process of forming, from bottom to top, a bottom source / drain material layer, a first extension material layer, a channel material layer, a second extension material layer, and a top source / drain material layer on the substrate, performing in-situ doping to P-type ion dope the bottom source / drain layer, the first extension material layer, the second extension material layer, and the top source / drain material layer; after the in-situ doping, forming an initial protective structure on the surface of the top source / drain material layer; performing etching on the first extension material layer, the channel material layer, the second extension material layer, the top source / drain material layer, and the initial protective structure to correspondingly form an initial first extension layer, an initial channel layer, an initial second extension layer, the top source / drain layer, and the protective structure; Etching the substrate and the bottom source-drain material layer to form the bottom source-drain layer and the isolation groove, and a projection area of the protection structure, the top source-drain layer, the initial second extension layer, the initial channel layer and the initial first extension layer on the bottom source-drain layer is less than an area of the bottom source-drain layer.

[0014] Optionally, after the gate structure is formed, the method further comprises: forming a first type of conductive recess in the third isolation layer and the fourth isolation layer, a bottom of the first type of conductive recess exposing the bottom source-drain layer; depositing a third electrode material in the first type of conductive recess to form a first type of third electrode.

[0015] Optionally, a method for forming, from bottom to top, a bottom source-drain layer, a first extension layer, an initial channel layer, a second extension layer and a top source-drain layer on a substrate comprises: forming, from bottom to top, a bottom source-drain material layer, a first extension material layer, a channel material layer, a second extension material layer and a top source-drain material layer on the substrate, and in the process of forming, from bottom to top, the bottom source-drain material layer, the first extension material layer, the channel material layer, the second extension material layer and the top source-drain material layer on the substrate, performing in-situ doping to P-type ion dope the bottom source-drain layer, the first extension material layer, the second extension material layer and the top source-drain material layer; after the in-situ doping, forming an initial protection structure on a surface of the top source-drain material layer; etching the substrate, the bottom source-drain material layer, the first extension material layer, the channel material layer, the second extension material layer, the top source-drain material layer and the initial protection structure to correspondingly form the isolation groove, the bottom source-drain layer, the initial first extension layer, the initial channel layer, the initial second extension layer, the top source-drain layer and the protection structure, and a projection area of the protection structure, the top source-drain layer, the initial second extension layer, the initial channel layer and the initial first extension layer on the bottom source-drain layer is equal to an area of the bottom source-drain layer.

[0016] Optionally, the substrate has opposite two sides, the gate structure is located on one side of the substrate, and after the first electrode and the second electrode are formed, the method further comprises: etching the substrate and the first isolation layer from the other side of the substrate to form a second type of conductive recess in the substrate and the first isolation layer, a groove bottom of the second type of conductive recess exposing the bottom source-drain layer; forming a passivation layer on a sidewall surface of the second type of conductive recess; Depositing a third electrode material in the second type of conductive recess with the passivation layer formed therein to form a second type of third electrode.

[0017] Optionally, the in-situ doping is also used for N-type ion doping of the channel material layer.

[0018] According to a second aspect of the present application, there is provided a vertical channel transistor structure, comprising: a substrate and a bottom source-drain layer, a first extension layer, a channel layer, a second extension layer and a top source-drain layer stacked in sequence from bottom to top on the substrate, the bottom source-drain layer, the channel layer and the top source-drain layer being made of silicon, the first extension layer and the second extension layer being made of silicon germanium, and the bottom source-drain layer, the initial first extension layer, the initial second extension layer and the top source-drain layer being doped with P-type ions.

[0019] Optionally, the bottom source-drain layer exposes a part of a top surface relative to the first extension layer, the top source-drain layer exposes a part of a bottom surface relative to the second extension layer, the channel layer is doped with N-type ions, and the vertical channel transistor structure further comprises: a first gate isolation dielectric layer between a sidewall surface of the first extension layer and a part of the top surface of the bottom source-drain layer exposed relative to the first extension layer; a second gate isolation dielectric layer between a sidewall surface of the second extension layer and a part of the bottom surface of the top source-drain layer exposed relative to the second extension layer, a sidewall surface of the channel layer being recessed relative to sidewall surfaces of the first gate isolation dielectric layer and the second gate isolation dielectric layer to form a gate recess with a lateral opening between the first gate isolation dielectric layer and the second gate isolation dielectric layer, and a sidewall surface of the channel layer being exposed at a bottom of the gate recess; a first isolation layer in an isolation groove in the substrate around the bottom source-drain layer and on a side surface of the bottom source-drain layer; a second isolation layer between a side surface of the first extension layer, a part of the top surface of the bottom source-drain layer exposed relative to the first extension layer and a surface of the first isolation layer; a gate structure comprising a gate dielectric material film on a part of the surface of the second isolation layer and a gate dielectric material film on an inner wall surface of the gate recess; a third isolation layer on the second isolation layer and on the gate dielectric material film on the part of the surface of the second isolation layer; a fourth isolation layer on a surface of the third isolation layer and on a surface of the top source-drain layer; a first electrode in the fourth isolation layer, and the first electrode is in contact with the top source-drain layer; a second electrode in the third and fourth isolation layers, and the second electrode is in contact with the gate dielectric film on the partial surface of the second isolation layer; a first type of third electrode in the third and fourth isolation layers, and the first type of third electrode is in contact with the bottom source-drain layer.

[0020] Optionally, the bottom source-drain layer exposes a partial top surface relative to the first extension layer, the top source-drain layer exposes a partial bottom surface relative to the second extension layer, the channel layer is doped with N-type ions, and the vertical channel transistor structure further comprises: a first gate isolation dielectric layer between the sidewall surface of the first extension layer and the partial top surface of the bottom source-drain layer exposed relative to the first extension layer; a second gate isolation dielectric layer between the sidewall surface of the second extension layer and the partial bottom surface of the top source-drain layer exposed relative to the second extension layer, the sidewall surface of the channel layer is recessed relative to the sidewall surface of the first gate isolation dielectric layer and the sidewall surface of the second gate isolation dielectric layer, so that a gate recess with a horizontal opening is formed between the first gate isolation dielectric layer and the second gate isolation dielectric layer, and the sidewall surface of the channel layer is exposed at the bottom of the gate recess; a first isolation layer in an isolation groove in the substrate around the bottom source-drain layer and on the side surface of the bottom source-drain layer; a second isolation layer between the side surface of the first extension layer, the partial top surface of the bottom source-drain layer exposed relative to the first extension layer, and the surface of the first isolation layer; a gate structure comprising a gate dielectric film on the partial surface of the second isolation layer and a gate dielectric film on the inner wall surface of the gate recess; a third isolation layer on the second isolation layer and on the gate dielectric film on the partial surface of the second isolation layer; a fourth isolation layer on the surface of the third isolation layer and on the surface of the top source-drain layer; a first electrode in the fourth isolation layer, and the first electrode is in contact with the top source-drain layer; a second electrode in the third and fourth isolation layers, and the second electrode is in contact with the gate dielectric film on the partial surface of the second isolation layer; a third electrode material layer in contact with the bottom source-drain layer; a passivation layer between the third electrode material layer and the substrate and the first isolation layer.

[0021] Compared with the prior art, the technical scheme of the present application has the following beneficial effects: In the preparation method of the vertical channel transistor provided by the technical scheme of the present application, the bottom source-drain layer, the first extension layer, the channel layer, the second extension layer and the top source-drain layer are sequentially stacked from bottom to top on the substrate, the materials of the bottom source-drain layer, the channel layer and the top source-drain layer are silicon, the materials of the first extension layer and the second extension layer are silicon germanium, and P-type ions are doped in the bottom source-drain layer, the first extension layer, the second extension layer and the top source-drain layer. Among them, by doping P-type ions in the bottom source-drain layer, the first extension layer, the second extension layer and the top source-drain layer, the resistance of the first extension region and the second extension region is reduced in the process of diffusion of the P-type ions to the channel layer, that is, the resistance of the first extension region and the second extension region is reduced, so that the driving capability of the vertical channel PMOS transistor is improved, and the driving capability of the PMOS tube and the NMOS tube in the vertical channel transistor is reduced, that is, the driving capability of the PMOS tube and the NMOS tube is better matched.

[0022] Further, by performing lateral etching on the initial first extension layer, a first recess with a lateral opening is formed between the bottom source-drain layer and the initial channel layer, and the first extension layer is formed, and by performing lateral etching on the initial second extension layer, a second recess with a lateral opening is formed between the top source-drain layer and the initial channel layer, and the second extension layer is formed, then, the first gate isolation medium layer is formed in the first recess, and the second gate isolation medium layer is formed in the second recess, finally, by performing lateral etching on the initial channel layer, the channel layer is formed, and the gate recess is formed between the first gate isolation medium layer and the second gate isolation medium layer, so that the first gate isolation medium layer can be used to isolate the bottom source-drain layer and the gate recess, and the second gate isolation medium layer can be used to isolate the top source-drain layer and the gate recess. Since the gate recess can be used to form the gate structure of the vertical channel transistor, the parasitic between the gate and the source and the drain in the vertical channel transistor, such as parasitic resistance, parasitic capacitance, etc., can be reduced, and the parasitic of the vertical channel transistor can be reduced, thereby improving the performance of the vertical channel transistor.

[0023] Further, since the K value of the material forming the first gate isolation medium layer is less than the K value of the material of the second isolation layer, the K value of the material forming the second gate isolation medium layer is less than the K value of the material of the fourth isolation layer, so that the first gate isolation medium layer is decoupled from the second isolation layer, and the second gate isolation medium layer is decoupled from the fourth isolation layer, thereby further reducing the parasitic of the vertical channel transistor.

[0024] Further, by etching the initial protection structure, the top source-drain material layer, the second extension material layer, the channel material layer, the first extension material layer, and the bottom source-drain material layer, the protection structure, the top source-drain layer, the initial second extension layer, the initial channel layer, the initial first extension layer, and the bottom source-drain layer are formed correspondingly, and the projection areas of the protection structure, the top source-drain layer, the initial second extension layer, the initial channel layer, the initial first extension layer, and the bottom source-drain layer on the bottom source-drain layer are all equal to the area of the bottom source-drain layer, so that the active area of the vertical channel transistor only needs to be etched once, and since the projection area of the top source-drain layer on the bottom source-drain layer is equal to the area of the bottom source-drain layer, the symmetry of the top source-drain layer and the bottom source-drain layer is achieved, thereby reducing the series resistance between the bottom source-drain layer and the substrate, making the effective voltage applied on both sides of the channel layer larger, and thereby improving the on-state current of the transistor.

[0025] In the vertical channel transistor structure provided in the technical scheme, the P-type ions doped in the bottom source-drain layer, the first extension layer, the second extension layer, and the top source-drain layer reduce the hindrance in the first extension region and the second extension region during the diffusion of the P-type ions to the channel layer, so that the resistance of the first extension region and the second extension region is reduced, thereby improving the driving capability of the vertical channel PMOS transistor, and further reducing the difference between the driving capabilities of the PMOS and NMOS in the vertical channel transistor, that is, achieving better matching of the driving capability performance of the PMOS and NMOS. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figures 1-9 is a device structure cross-sectional schematic diagram corresponding to each step of the preparation method of the vertical channel transistor provided in an embodiment of the present application; Figures 10-18 is a device structure cross-sectional schematic diagram corresponding to each step of the preparation method of the vertical channel transistor provided in another embodiment of the present application; Figure 19 is a schematic diagram of the distribution of P-type ions in the PMOS; Figure 20 is a comparison diagram of the driving current and RC delay of the NMOS and PMOS. DETAILED DESCRIPTION

[0027] As described in the background, in the vertical channel transistor, the driving capability performance of PMOS and NMOS is not matched.

[0028] Specifically, in the vertical channel transistor, the first extension layer of silicon germanium exists between the bottom source-drain layer and the channel layer of silicon, and the second extension layer of silicon germanium exists between the top source-drain layer and the channel layer of silicon. Due to the difference in the solid solubility and the diffusion coefficient of P-type impurities in silicon germanium and silicon, the diffusion of P-type impurities from the bottom source-drain layer to the channel layer through the first extension layer and the diffusion of P-type impurities from the top source-drain layer to the channel layer through the second extension layer are hindered. Therefore, the resistance of the first extension layer and the second extension layer is large, which leads to the decrease of the driving capability of PMOS. On this basis, since the diffusion of N-type ions in silicon germanium is almost not hindered, the driving capability performance of PMOS and NMOS is not matched.

[0029] Therefore, the technical scheme of the present application creatively provides a preparation method of a vertical channel transistor, comprising: forming, on the substrate, a bottom source-drain layer, a first extension layer, a channel layer, a second extension layer and a top source-drain layer stacked in sequence from bottom to top, the materials of the bottom source-drain layer, the channel layer and the top source-drain layer are silicon, the materials of the first extension layer and the second extension layer are silicon germanium, and the bottom source-drain layer, the first extension layer, the second extension layer and the top source-drain layer are doped with P-type ions.

[0030] By doping P-type ions in the bottom source-drain layer, the first extension layer, the second extension layer and the top source-drain layer, the hindrance of the diffusion of P-type ions to the channel layer in the first extension region and the second extension region is reduced, and the resistance of the first extension region and the second extension region is reduced. Therefore, the driving capability of the vertical channel PMOS transistor is improved, and the difference between the driving capability of PMOS and NMOS in the vertical channel transistor is reduced, that is, the driving capability performance of PMOS and NMOS is better matched.

[0031] With reference to the drawings and embodiments of the present application, the embodiments in the present application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work belong to the scope of protection of the present application. The terms "first", "second", "third" and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be exchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0032] Figures 1-9 is a device structure cross-sectional schematic view corresponding to each step of the preparation method of the vertical channel transistor provided by an embodiment of the present application.

[0033] Please refer to Figure 1 A bottom source-drain material layer 202, a first extension material layer 302, a channel material layer 402, a second extension material layer 902 and a top source-drain material layer 502 are sequentially stacked from bottom to top on the substrate 100.

[0034] The substrate 100 is a silicon substrate.

[0035] The process of forming the bottom source-drain material layer 202, the first extension material layer 302, the channel material layer 402, the second extension material layer 902 and the top source-drain material layer 502 is an epitaxial growth process.

[0036] Further, the materials of the bottom source-drain material layer 202, the channel material layer 402 and the top source-drain material layer 502 are silicon, and the silicon layer is doped by in-situ doping during the epitaxial growth process of forming the silicon layer, thereby forming the bottom source-drain material layer 202, the channel material layer 402 and the top source-drain material layer 502.

[0037] In the present embodiment, P-type ions are doped in the bottom source-drain material layer 202 and the top source-drain material layer 502, and N-type ions are doped in the channel material layer 402.

[0038] The material of the first and second extension material layers 302 and 902 can be, for example, silicon germanium, and the silicon germanium layers are doped by in-situ doping during epitaxial growth of the silicon germanium layers, thereby forming the first and second extension material layers 302 and 902.

[0039] In this embodiment, the first and second extension material layers 302 and 902 are doped with P-type ions.

[0040] Preferably, the P-type ion concentration in the first extension material layer 302 is the same as that in the bottom source / drain material layer 202, and the P-type ion concentration in the second extension material layer 902 is the same as that in the top source / drain material layer 502. Generally, to ensure symmetry of the device, current transmission efficiency, stability of threshold voltage, and thermal balance and reliability, the doping ion concentration in the bottom source / drain material layer 202 is the same as that in the top source / drain material layer 502, and thus the doping ion concentration in the bottom source / drain material layer 202, the top source / drain material layer 502, the first extension material layer 302 and the second extension material layer 902 is the same.

[0041] In one embodiment, an initial protection structure 1002 is formed on the surface of the top source / drain material layer 502.

[0042] Further, the material of the initial protection structure 1002 can be silicon nitride.

[0043] Please refer to Figure 2 The initial protection structure 1002, the top source / drain material layer 502, the second extension material layer 902, the channel material layer 402 and the first extension material layer 302 are etched to form the protection structure 1000, the top source / drain layer 500, the initial second extension layer 901, the initial channel layer 401 and the initial first extension layer 301.

[0044] The method for forming the protection structure 1000, the top source-drain layer 500, the initial second extension layer 901, the initial channel layer 401 and the initial first extension layer 301 includes: spin-coating a first photoresist layer on a surface of an initial protection structure 1002; performing exposure and development on the first photoresist layer by using a first mask to realize patterning of the first photoresist layer, thereby forming a patterned first photoresist layer; taking the patterned first photoresist layer as a mask to etch the initial protection structure 1002 until a surface of a top source-drain material layer 502 is exposed, thereby forming the protection structure 1000; after forming the protection structure 1000, continuing to take the patterned first photoresist layer as the mask to etch the top source-drain material layer 502, a second extension material layer 902, a channel material layer 402 and a first extension material layer 302, thereby corresponding to form the top source-drain layer 500, the initial second extension layer 901, the initial channel layer 401 and the initial first extension layer 301.

[0045] In one embodiment, when the material of the protection structure 1000 is silicon nitride, the protection structure 1000 also serves as a hard mask for etching the top source-drain material layer 502, the second extension material layer 902, the channel material layer 402 and the first extension material layer 302.

[0046] In one embodiment, after forming the top source-drain layer 500, the initial second extension layer 901, the initial channel layer 401 and the initial first extension layer 301, the remaining patterned first photoresist layer is removed.

[0047] Please continue to refer to Figure 2 After forming the top source-drain layer 500, the initial second extension layer 901, the initial channel layer 401 and the initial first extension layer 301, the bottom source-drain material layer 202 and the substrate 100 are etched to form a bottom source-drain layer 200 and an isolation groove 12, and the projection area of the protection structure 1000, the top source-drain layer 500, the initial second extension layer 901, the initial channel layer 401 and the initial first extension layer 301 on the bottom source-drain layer 200 is smaller than the area of the bottom source-drain layer 200.

[0048] The etched substrate 100 includes a bottom structure 101 and a fin-type structure 102, the fin-type structure 102 is located above the bottom structure 101, the bottom source-drain layer 200 is located above the fin-type structure 102, and the isolation groove 12 surrounds the bottom source-drain layer 200 and the fin-type structure 102 from the periphery, and the groove bottom of the isolation groove 12 exposes part of the top surface of the bottom structure 101.

[0049] The method for forming the bottom source-drain layer 200 and the isolation groove 12 comprises: spin-coating a second photoresist layer on the exposed surface of the bottom source-drain material layer 202; exposing and developing the second photoresist layer by using a second mask to achieve the patterning of the second photoresist layer, thereby forming a patterned second photoresist layer, wherein the patterned second photoresist layer comprises a pattern of the isolation groove 12; and etching the bottom source-drain material layer 202 and the substrate 100 by using the patterned second photoresist layer as a mask, thereby forming the bottom source-drain layer 200, the isolation groove 12, and the substrate 100 comprising the bottom structure 101 and the fin-type structure 102.

[0050] In one embodiment, after the bottom source-drain layer 200, the isolation groove 12, and the substrate 100 comprising the bottom structure 101 and the fin-type structure 102 are formed, the remaining patterned second photoresist layer is removed.

[0051] Referring to Figure 3 , then, the first isolation material is deposited in the isolation groove 12 to form the first isolation layer 10, and the top surface of the first isolation layer 10 is flush with the top surface of the bottom source-drain layer 200.

[0052] The material of the first isolation layer 10 may, for example, be silicon oxide, and the first isolation layer 10 can be used to isolate the vertical channel transistor from other devices in the vicinity. Of course, there are many materials that can be used as the first isolation layer 10, and the present application does not limit the material.

[0053] Referring to Figure 4 , after the first isolation layer 10 is formed, the initial first extension layer 301 is subjected to lateral etching to form the first recess 601 and the first extension layer 300.

[0054] The lateral etching is isotropic and selective, so the first recess 601 surrounds the first extension layer 300 peripherally, the bottom of the first recess 601 exposes the side surface of the first extension layer 300, and the sidewall surface of the first recess 601 exposes part of the bottom surface of the initial channel layer 401 and part of the top surface of the bottom source-drain layer 200.

[0055] The initial second extension layer 901 is subjected to lateral etching to form the second recess 701 and the second extension layer 900.

[0056] The lateral etching is isotropic and selective, so the second recess 701 surrounds the second extension layer 900 peripherally, the bottom of the second recess 701 exposes the side surface of the second extension layer 900, and the sidewall surface of the second recess 701 exposes part of the top surface of the initial channel layer 401 and part of the bottom surface of the top source-drain layer 500.

[0057] The order of the two steps of etching the initial first extension layer 301 and etching the initial second extension layer 901 is not fixed, for example, the initial first extension layer 301 and the initial second extension layer 901 can be etched at the same time.

[0058] Next, please refer to Figure 5 The first gate isolation dielectric layer 600 and the second gate isolation dielectric layer 700 are formed in the first recess 601 and the second recess 701, respectively.

[0059] In an embodiment, the first gate isolation dielectric layer 600 and the second gate isolation dielectric layer 700 can be the same material, for example, and thus the method of forming the first gate isolation dielectric layer 600 and the second gate isolation dielectric layer 700 in the first recess 601 and the second recess 701, respectively, includes: forming a gate isolation dielectric material layer on the surface of the first isolation layer 10, the exposed surface of the bottom source-drain layer 200, the inner wall surface of the first recess 601, the side surface of the initial channel layer 401, the inner wall surface of the second recess 701, the side surface of the top source-drain layer 500, the side surface and the top surface of the protection structure 1000 by atomic layer deposition; and removing the gate isolation dielectric material layer in the first recess 601 and the second recess 701 by a back etching process to form the first gate isolation dielectric layer 600 and the second gate isolation dielectric layer 700 in the first recess 601 and the second recess 701, respectively.

[0060] Next, please refer to Figure 6 After the first gate isolation dielectric layer 600 and the second gate isolation dielectric layer 700 are formed, and before the initial channel layer 401 is etched, a protection side wall 1100 is formed on the surface of the second gate isolation dielectric layer 700, the side surface of the top source-drain layer 500, and the surface of the protection structure 1000.

[0061] The method of forming the protection side wall 1100 specifically includes: depositing a second isolation material layer on the exposed part of the top surface of the bottom source-drain layer 200 and the first isolation layer 10, the top surface of the second isolation material layer being flush with the top surface of the initial channel layer 400; forming a protection material layer on the surface of the second isolation material layer, the side surface of the top source-drain layer 500, the side surface of the second gate isolation dielectric layer 700, the side surface and the surface of the protection structure 1000 by atomic layer deposition; and removing the protection material layer on the surface of the second isolation material layer and the surface of the protection structure 1000 by a collimated etching process using a plasma etching process to form the protection side wall 1100.

[0062] The material of the protection side wall 1100 can be silicon nitride, for example. Of course, those skilled in the art can realize that there are many materials for forming the protection side wall 1100, and the present application is not limited thereto.

[0063] Then, the second isolation layer 201 is formed on the side of the first gate isolation medium layer 600.

[0064] Specifically, the second isolation material layer is collimated and etched by using a plasma etching process to form the second isolation layer 201, the top surface of the second isolation layer 201 is flush with the top surface of the first gate isolation medium layer 600, and the second isolation layer 201 surrounds the first gate isolation medium layer 600 from the periphery. At this time, the exposed protection structure 1000 is used to protect the top source-drain layer 500 from being etched.

[0065] The material of the second isolation layer 201 may be silicon oxide, for example. Of course, those skilled in the art can realize that there are many materials for forming the second isolation layer 201, and the present application is not limited thereto. In addition, the K value of the material of the second isolation layer 201 is greater than the K value of the material of the first gate isolation medium layer 600, so that the second isolation layer 201 is decoupled from the first gate isolation medium layer 600.

[0066] After the protection side wall 1100 and the second isolation layer 201 are formed, the initial channel layer 401 is laterally etched to form the channel layer 400, and the side wall surface of the channel layer 400 is recessed relative to the side wall surfaces of the first gate isolation medium layer 600 and the second gate isolation medium layer 700, so that the gate recess 802 with a lateral opening is formed between the first gate isolation medium layer 600 and the second gate isolation medium layer 700, and the side wall surface of the channel layer 400 is exposed at the bottom of the gate recess 802. When the initial channel layer 401 is laterally etched, the protection side wall 1100 can protect the top source-drain layer 500 and the second gate medium isolation layer from being etched, and the channel layer 400 formed by etching is relatively thin, which can enhance the gate control and reduce the leakage.

[0067] Please refer to Figure 8 The gate structure 800 is formed at least in the gate recess 802.

[0068] Specifically, please refer to Figure 7 and Figure 8 The method for forming the gate structure 800 includes: Please refer to Figure 7 The gate medium material film 801 is formed on the surface of the second isolation layer 201, the inner wall surface of the gate recess 802, the side surface of the protection side wall 1100, and the surface of the protection structure 1000. Specifically, hafnium oxide and titanium nitride are sequentially deposited on the surface of the second isolation layer 201, the inner wall surface of the gate recess 802, the side surface of the protection side wall 1100, and the surface of the protection structure 1000 by atomic layer deposition to form the gate medium material film 801. Of course, those skilled in the art can realize that there are many materials for forming the gate medium material film 801, and the present application is not limited thereto.

[0069] Please refer toFigure 8 The gate dielectric film 801 on the partial surface of the second isolation layer 201 is etched and removed.

[0070] Then, the third isolation layer 30 is formed on the second isolation layer 201 and the gate dielectric film 801 on the partial surface of the second isolation layer 201, and the top surface of the third isolation layer 30 is flush with the bottom surface of the protection side wall 1100, so as to expose the protection side wall 1100 and the protection structure 1000.

[0071] After the third isolation layer is formed, the gate dielectric film 801 on the surface of the protection side wall 1100 and the protection structure 1000 is etched and removed, so as to form the gate structure 800.

[0072] In this embodiment, please refer to Figure 9 After the gate structure 800 is formed, the fourth isolation layer 40 is formed on the surface of the third isolation layer 30 and the surface of the top source-drain layer 500.

[0073] The material of the second isolation layer 201, the third isolation layer 30 and the fourth isolation layer 40 can be silicon oxide, and the K value of the material of the fourth isolation layer 40 is greater than the K value of the material of the second gate isolation dielectric layer 700, so that the fourth isolation layer 40 is decoupled from the second gate isolation dielectric layer 700.

[0074] Then, the first electrode 11 is formed in the fourth isolation layer 40, and the first electrode 11 is in contact with the top source-drain layer 500. Specifically, the method for forming the first electrode 11 includes: spin-coating a third photoresist layer on the surface of the fourth isolation layer 40; exposing and developing the third photoresist layer by using a third mask, so as to achieve the patterning of the third photoresist layer, and form a patterned third photoresist layer, wherein the patterned third photoresist layer includes a first conductive groove pattern; taking the patterned third photoresist layer as a mask, etching the fourth isolation layer 40, and correspondingly forming a first conductive groove; removing the remaining patterned third photoresist layer; and depositing a first electrode 11 material in the first conductive groove, so as to form the first electrode 11, wherein the first electrode 11 is in contact with the top source-drain layer 500.

[0075] Then, after the fourth isolation layer 40 is formed, the second electrode 21 is formed in the third isolation layer 30 and the fourth isolation layer 40, and the second electrode 21 is in contact with the gate dielectric film 801 on the partial surface of the second isolation layer 201.

[0076] Specifically, the method for forming the second electrode 21 comprises the following steps: spin-coating a fourth photoresist layer on the surface of the fourth isolation layer 40; exposing and developing the fourth photoresist layer by using a fourth mask to realize the patterning of the fourth photoresist layer, thereby forming a patterned fourth photoresist layer, wherein the patterned fourth photoresist layer comprises a second conductive groove pattern; taking the patterned fourth photoresist layer as a mask, etching the third isolation layer 30 and the fourth isolation layer 40 to form a second conductive groove; removing the remaining patterned fourth photoresist layer; and depositing a second electrode 21 material in the second conductive groove to form the second electrode 21, wherein the second electrode 21 is in contact with the gate structure 800 on the second isolation layer 201.

[0077] The first type of third electrode 31 is formed in the second isolation layer 201, the third isolation layer 30 and the fourth isolation layer 40.

[0078] Specifically, the method for forming the first type of third electrode 31 comprises the following steps: The first type of conductive groove is formed in the second isolation layer 201, the third isolation layer 30 and the fourth isolation layer 40, and the bottom of the second conductive groove exposes the bottom source-drain layer 200.

[0079] Specifically, the method for forming the first type of conductive groove in the third isolation layer 30 and the fourth isolation layer 40 comprises the following steps: spin-coating a fifth photoresist layer on the surface of the fourth isolation layer 40; exposing and developing the fifth photoresist layer by using a fifth mask to realize the patterning of the fifth photoresist layer, thereby forming a patterned fifth photoresist layer, wherein the patterned fifth photoresist layer comprises a first type of conductive groove pattern; taking the patterned fifth photoresist layer as a mask, etching the second isolation layer 201, the third isolation layer 30 and the fourth isolation layer 40, and over-etching the bottom source-drain layer 200 to form a second conductive groove; removing the remaining patterned fifth photoresist layer; and depositing a first type of third electrode 31 material in the first type of conductive groove to form the first type of third electrode 31, wherein the first type of third electrode 31 is in contact with the gate structure 800 on the second isolation layer 201. The over-etching of the bottom source-drain layer 200 can reduce the contact resistance between the first type of third electrode and the bottom source-drain layer 200.

[0080] The third electrode material layer is deposited in the first type of conductive groove to form the first type of third electrode 31.

[0081] Specifically, the material of the first type of third electrode 31 can be a metal material such as platinum, silver and copper.

[0082] The manufacturing sequence of the first electrode 11, the second electrode 21 and the first type of third electrode 31 is not fixed, and the manufacturing sequence can be changed according to actual conditions, which is not limited in the present application.

[0083] In one embodiment of the present invention, a bottom source / drain layer 200, an initial first extension layer 301, an initial channel layer 401, an initial second extension layer 901, and a top source / drain layer 500 are stacked sequentially from bottom to top on a substrate 100. The initial first extension layer 301 and the initial second extension layer 901 are then laterally etched to form a first groove 601 and a second groove 701 with laterally openings between the bottom source / drain layer 200 and the initial channel layer 401 and between the top source / drain layer 500 and the initial channel layer 401, respectively. A first gate isolation dielectric layer 600 and a second gate isolation dielectric layer 700 are then formed in the first groove 601 and the second groove 701, respectively. Finally, the initial channel layer 401 is etched to form a first gate isolation dielectric layer 601 and a second gate isolation dielectric layer 701. The channel layer 401 is laterally etched to form a channel layer 400, and a gate groove 802 is formed between the first gate isolation dielectric layer 600 and the second gate isolation dielectric layer 700, so that the first gate isolation dielectric layer 600 can be used to isolate the bottom source and drain layer 200 and the gate groove 802, and the second gate isolation dielectric layer 700 can be used to isolate the top source and drain layer 500 and the gate groove 802. Since the gate groove 802 can be used to form the gate structure 800 of the vertical channel transistor, the parasitics between the gate and the source and drain in the vertical channel transistor, such as parasitic resistance, parasitic capacitance, etc., can be reduced, thereby reducing the parasitics of the vertical channel transistor and improving the performance of the vertical channel transistor.

[0084] Furthermore, since the K value of the material forming the first gate isolation dielectric layer 600 is smaller than the K value of the material of the second isolation layer 201, and the K value of the material forming the second gate isolation dielectric layer 700 is smaller than the K value of the material of the fourth isolation layer 43, the first gate isolation dielectric layer 600 is decoupled from the second isolation layer 201, and the second gate isolation dielectric layer 700 is decoupled from the fourth isolation layer 43, thereby further reducing the parasitics of the vertical channel transistor.

[0085] Accordingly, an embodiment of the present invention further provides a vertical channel transistor structure, please continue to refer to Figure 9 , including a substrate 100 and a bottom source and drain layer 200, a first extension layer 300, a channel layer 400, a second extension layer 900 and a top source and drain layer 500, a first gate isolation dielectric layer 600, a second gate isolation dielectric layer 700 and a gate structure 800 stacked on the substrate 100 from bottom to top.

[0086] The bottom source / drain layer 200 exposes a portion of its top surface relative to the first extension layer 300 , and the top source / drain layer 500 exposes a portion of its bottom surface relative to the second extension layer 900 .

[0087] The projection area of ​​the top source / drain layer 500 on the bottom source / drain layer 200 is smaller than the area of ​​the bottom source / drain layer 200 .

[0088] The first gate isolation medium layer 600 is located between the sidewall of the first extension layer 300 and the part of the top surface of the bottom source-drain layer 200 exposed relative to the first extension layer 300.

[0089] The second gate isolation medium layer 700 is located between the sidewall of the second extension layer 900 and the part of the bottom surface of the top source-drain layer 500 exposed relative to the second extension layer 900, and the sidewall of the channel layer 400 is recessed relative to the sidewall of the first gate isolation medium layer 600 and the sidewall of the second gate isolation medium layer 700, so that a gate recess 802 with a horizontal opening is formed between the first gate isolation medium layer 600 and the second gate isolation medium layer 700, and the sidewall of the channel layer 400 is exposed at the bottom of the gate recess 802.

[0090] The gate structure 800 is located at least in the gate recess 802.

[0091] In this embodiment, the vertical channel transistor further comprises a first isolation layer 10, a second isolation layer 201, a third isolation layer 30, a fourth isolation layer 40, a first electrode 11, a second electrode 21, and a first type of third electrode 31.

[0092] The first isolation layer 10 is located in an isolation groove in the substrate 100 around the bottom source-drain layer 200 and on the side of the bottom source-drain layer 200.

[0093] The second isolation layer 201 is located between the side of the first extension layer 300, the part of the top surface of the bottom source-drain layer 200 exposed relative to the first extension layer 300, and the surface of the first isolation layer 10.

[0094] The third isolation layer 30 is located on the second isolation layer 201 and on the gate dielectric material film 801 on the part of the surface of the second isolation layer 201, and the gate dielectric material film 801 is also located on the inner wall of the gate recess 802, and the gate structure 800 comprises the gate dielectric material film 801 on the part of the surface of the second isolation layer 201 and the gate dielectric material film 801 on the inner wall of the gate recess 802.

[0095] The fourth isolation layer 40 is located on the surface of the third isolation layer 30 and the surface of the top source-drain layer 500.

[0096] The first electrode 11 is located in the fourth isolation layer 40, and the first electrode 11 is in contact with the top source-drain layer 500.

[0097] The second electrode 21 is located in the third isolation layer 30 and the fourth isolation layer 40, and the second electrode 21 is in contact with the gate dielectric material film 801 on the part of the surface of the second isolation layer 201.

[0098] The first type of third electrode 31 is located in the third isolation layer 30 and the fourth isolation layer 40, and the first type of third electrode 31 is in contact with the bottom source-drain layer 200.

[0099] In the embodiment, the details of the features in the embodiment are explained in the above-mentioned method embodiment, and thus the related description of the same features is referred to and not repeated here.

[0100] In an embodiment of the application, the first gate isolation medium layer 600 can be used to isolate the bottom source-drain layer 200 and the gate recess 802, and the second gate isolation medium layer 700 can be used to isolate the top source-drain layer 500 and the gate recess 802, so as to reduce the parasitic between the gate and the source and the drain in the vertical channel transistor, such as parasitic resistance, parasitic capacitance, etc., and further reduce the parasitic of the vertical channel transistor.

[0101] In an embodiment of the application, by doping P-type ions in the first extension layer 300 and the second extension layer 900, the solid solubility or diffusion coefficient difference of the P-type ions in the bottom source-drain layer 200 and the first extension layer 300 and in the top source-drain layer 500 and the second extension layer 900 is reduced, so that the resistance of the first extension layer 300 and the second extension layer 900 is reduced, and the driving capability of the PMOS transistor is improved.

[0102] Specifically, refer to Figure 19 , Figure 19is a schematic diagram of P-type ion distribution in the PMOS tube, wherein the abscissa in the figure is used to represent the depth of the PMOS tube, the ordinate in the figure is used to represent the concentration of P-type ions, the blue line in the figure is used to represent the P-type ion distribution when the first extension layer 300 and the second extension layer 900 are not doped with P-type ions, and the orange line in the figure is used to represent the P-type ion distribution when the first extension layer 300 and the second extension layer 900 are doped with P-type ions, the second extension layer 900 is located between the depth of 40 nanometers to 45 nanometers, the first extension layer 300 is located between the depth of 75 nanometers to 80 nanometers, and the channel layer 400 is located between the depth of 45 nanometers to 75 nanometers. By comparing the blue line and the orange line, it can be concluded that when the first extension layer 300 and the second extension layer 900 are not doped with P-type ions, the concentration of P-type ions in the first extension layer 300 and the second extension layer 900 decreases sharply as the distance from the channel layer 400 decreases, which indicates that when the first extension layer 300 and the second extension layer 900 are not doped with P-type ions, the P-type ions are hindered in the process of diffusing from the first extension layer 300 and the second extension layer 900 to the channel layer 400, that is, the resistance formed in the first extension layer 300 and the second extension layer 900 is large, which degrades the driving ability of the PMOS tube; when the first extension layer 300 and the second extension layer 900 are doped with P-type ions, the concentration of P-type ions in the first extension layer 300 and the second extension layer 900 first increases slightly and then decreases slightly as the distance from the channel layer 400 decreases, which indicates that the P-type ions are less hindered in the process of diffusing from the first extension layer 300 and the second extension layer 900 to the channel layer 400, that is, the resistance formed in the first extension layer 300 and the second extension layer 900 is small, therefore, this further indicates that doping P-type ions in the first extension layer 300 and the second extension layer 900 can improve the driving ability of the PMOS tube.

[0103] Further, as an example, please refer to Figure 20 , Figure 20 for the comparison of the driving current and RC delay of the NMOS tube and the PMOS tube, wherein the structure of the NMOS tube and the PMOS tube is the same (please refer to Figure 9 or Figure 18 ), and the doping ion concentration of the bottom source-drain layer 200 and the top source-drain layer 500 in the NMOS tube and the PMOS tube is 3.0×10 20 cm -3, the first extension layer 300 and the second extension layer 900 in the NMOS tube are not ion doped. The abscissa in the figure is used to represent the concentration of P-type ions doped in the first extension layer 300 and the second extension layer 900, and the ordinate in the figure is a normalized coordinate. The figure includes a first group of column charts, a second group of column charts, a third group of column charts, a fourth group of column charts and a fifth group of column charts from left to right, the first group of column charts is used to represent the drive current and RC delay when the NMOS tube is not doped with P-type ions in the first extension layer 300 and the second extension layer 900, the second group of column charts is used to represent the drive current and RC delay when the PMOS tube is not doped with P-type ions in the first extension layer 300 and the second extension layer 900, and the third group of column charts, the fourth group of column charts and the fifth group of column charts are used to represent the drive current and RC delay when the PMOS tube is doped with P-type ions with concentrations of 1.5×10 20 cm -3 , 3.0×10 20 cm -3 and 4.5×10 20 cm -3 in the first extension layer 300 and the second extension layer 900 respectively. Therefore, according to Figure 20 , by adjusting the P-type ion doping concentration in the first extension layer 300 and the second extension layer 900, the drive current of the PMOS tube is increased by 23% at most, the drive current ratio of the NMOS tube to the PMOS tube is increased from 1:0.74 to 1:0.91, the RC delay ratio of the NMOS tube to the PMOS tube is optimized from 1:1.31 to 1:1.16, and the symmetry of the drive capability of the NMOS tube and the PMOS tube is improved. Moreover, after the P-type ions are doped in the first extension layer 300 and the second extension layer 900 to improve the drive capability of the PMOS tube, the drive capability of the PMOS tube can be more matched with the drive capability of the NMOS tube, thereby reducing the timing problems in the digital circuit caused by the asymmetry of the rise time and the fall time of the output signals of the NMOS tube and the PMOS tube.

[0104] Figures 10-18 is a device structure cross-sectional schematic diagram corresponding to each step of the preparation method of the vertical channel transistor provided by another embodiment of the present application.

[0105] First, a bottom source-drain layer 210, a first extension layer 310, an initial channel layer 411, a second extension layer 910 and a top source-drain layer 510 are sequentially stacked from bottom to top on a substrate 110.

[0106] The method for forming the bottom source-drain layer 210, the first extension layer 310, the initial channel layer 411, the second extension layer 910 and the top source-drain layer 510 includes: Please refer to Figure 10A bottom source-drain material layer 212, a first extension material layer 312, a channel material layer 412, a second extension material layer 912 and a top source-drain material layer 512 are sequentially stacked from bottom to top on the substrate 110.

[0107] Next, an initial protection structure 1012 is formed on the surface of the top source-drain material layer 512.

[0108] Referring to Figure 11 The initial protection structure 1012, the top source-drain material layer 512, the second extension material layer 912, the channel material layer 412, the first extension material layer 312, the bottom source-drain material layer 212 and the substrate 110 are etched to form a protection structure 1010, a top source-drain layer 510, an initial second extension layer 910, an initial channel layer 411, an initial first extension layer 310, a bottom source-drain layer 210 and an isolation groove 13. At this time, the projection area of the protection structure 1010, the top source-drain layer 510, the initial second extension layer 910, the initial channel layer 411 and the initial first extension layer 310 on the bottom source-drain layer 210 is equal to the area of the bottom source-drain layer 210.

[0109] Next, referring to Figure 12 A first isolation material is deposited in the isolation groove 13 to form a first isolation layer 14, and the top surface of the first isolation layer 14 is flush with the top surface of the bottom source-drain layer 210.

[0110] Referring to Figure 13 The initial first extension layer 310 is laterally etched to form a first recess 611 and a first extension layer 310.

[0111] The initial second extension layer 910 is laterally etched to form a second recess 711 and a second extension layer 910.

[0112] Next, referring to Figure 14 The first gate isolation medium layer 610 and the second gate isolation medium layer 710 are formed in the first recess 611 and the second recess 711, respectively.

[0113] Referring to Figure 15 After the first gate isolation medium layer 610 and the second gate isolation medium layer 710 are formed, and before the initial channel layer 411 is laterally etched, a protection side wall 1110 is formed on the surface of the second gate isolation medium layer 710, the side surface of the top source-drain layer 510 and the protection structure 1010.

[0114] Next, a second isolation layer 211 is formed on the side surface of the first gate isolation medium layer 610.

[0115] After the protective side wall 1110 and the second isolation layer 211 are formed, the initial channel layer 411 is laterally etched to form the channel layer 400, and the side wall surface of the channel layer 400 is recessed relative to the side wall surface of the first gate isolation medium layer 610 and the side wall surface of the second gate isolation medium layer 710, so that the gate recess 812 with a lateral opening is formed between the first gate isolation medium layer 610 and the second gate isolation medium layer 710, and the groove bottom of the gate recess 812 exposes the side wall surface of the channel layer 400.

[0116] Please refer to Figure 17 The gate structure 810 is formed at least in the gate recess 812.

[0117] Specifically, please refer to Figure 16 and Figure 17 The forming method of the gate structure 810 includes: Please refer to Figure 16 The gate medium material film 811 is formed on the surface of the second isolation layer 211, the inner wall surface of the gate recess 812, the side surface of the protective side wall 1110, and the surface of the protective structure 1010. Specifically, hafnium oxide and titanium nitride are sequentially deposited on the surface of the second isolation layer 211, the inner wall surface of the gate recess 812, the side surface of the protective side wall 1110, and the surface of the protective structure 1010 by atomic layer deposition to form the gate medium material film 811. Of course, those skilled in the art can realize that there are many materials for forming the gate medium material film 811, and the present application is not limited thereto.

[0118] The gate medium material film 811 on the part of the surface of the second isolation layer 211 is etched and removed.

[0119] Next, please refer to Figure 17 The third isolation layer 33 is formed on the second isolation layer 211 and the gate medium material film 811 on the part of the surface of the second isolation layer 211, and the top surface of the third isolation layer 33 is flush with the bottom surface of the protective side wall 1110 to expose the protective side wall 1110 and the protective structure 1010.

[0120] The gate medium material film 811 on the side surface of the protective side wall 1110 and the surface of the protective structure 1010 is etched and removed to form the gate structure 810.

[0121] Please refer to Figure 18 After the gate structure 810 is formed, the fourth isolation layer 43 is formed on the surface of the third isolation layer 33 and the surface of the top layer source-drain layer 510.

[0122] The first electrode 15 is formed in the fourth isolation layer 43.

[0123] After the fourth isolation layer 43 is formed, the second electrode 25 is formed in the third isolation layer 33 and the fourth isolation layer 43.

[0124] The order of forming the first electrode 15 and the second electrode 25 is not fixed, and needs to be arranged by the person skilled in the art according to the actual situation.

[0125] After the first electrode 15 and the second electrode 25 are formed, the method for forming the second third electrode 32 comprises: The substrate 110 and the first isolation layer 14 are etched from the side of the substrate 110 away from the gate structure, so as to form a second conductive groove in the substrate 110 and the first isolation layer 14, and the bottom of the second conductive groove exposes the bottom source-drain layer 210.

[0126] The method for forming the second conductive groove comprises: after the first electrode 15 and the second electrode 25 are formed, the substrate 110 is flipped, and the fourth isolation layer 43 is bonded with a carrier; the bottom structure 111 of the substrate 110 is thinned from the other side of the substrate 110; the second conductive groove is formed, which penetrates the bottom structure 111 and the fin structure 112 of the substrate 110, and the bottom of the second conductive groove exposes the bottom source-drain layer 210.

[0127] A passivation layer 33 is formed on the sidewall of the second conductive groove.

[0128] The third electrode material is deposited in the second conductive groove with the passivation layer 33, so as to form the second third electrode 32.

[0129] In another embodiment of the present application, by etching the initial protection structure 1012, the top source-drain material layer 512, the second extension material layer 912, the channel material layer 412, the first extension material layer 312 and the bottom source-drain material layer 212, the protection structure 1010, the top source-drain layer 510, the initial second extension layer 911, the initial channel layer 411, the initial first extension layer 311 and the bottom source-drain layer 210 are formed correspondingly, and the projection area of the protection structure 1010, the top source-drain layer 510, the initial second extension layer 911, the initial channel layer 411, the initial first extension layer 311 and the bottom source-drain layer 210 on the bottom source-drain layer 210 is equal to the area of the bottom source-drain layer 210, so that the active area of the vertical channel transistor only needs to be etched once, and since the projection area of the top source-drain layer 510 on the bottom source-drain layer 210 is equal to the area of the bottom source-drain layer 210, the symmetry of the top source-drain layer 510 and the bottom source-drain layer 210 is realized, so that the series resistance between the bottom source-drain layer 210 and the substrate 110 can be reduced, the effective voltage applied on both sides of the channel layer 410 is larger, and the on-state current of the transistor can be improved.

[0130] Correspondingly, another embodiment of the present application also provides a vertical channel transistor structure, which will be described below.Figure 18 , including: a substrate 110 and a bottom source and drain layer 210, a first extension layer 310, a channel layer 410, a second extension layer 910 and a top source and drain layer 510, a first gate isolation dielectric layer 610, a second gate isolation dielectric layer 710 and a gate structure 810 stacked on the substrate 110 from bottom to top.

[0131] The bottom source / drain layer 210 exposes a portion of its top surface relative to the first extension layer 310 , and the top source / drain layer 510 exposes a portion of its bottom surface relative to the second extension layer 910 .

[0132] Among them, the projected area of ​​the top source and drain layer 510 on the bottom source and drain layer 210 is equal to the area of ​​the bottom source and drain layer 210, so that the symmetry between the top source and drain layer 510 and the bottom source and drain layer 210 is achieved, thereby reducing the series resistance between the bottom source and drain layer 210 and the substrate 110, making the effective voltage applied on both sides of the channel layer 410 larger, thereby increasing the on-state current of the transistor.

[0133] The first gate isolation dielectric layer 610 is located between the sidewall surface of the first extension layer 310 and a portion of the top surface of the underlying source / drain layer 210 exposed relative to the first extension layer 310 .

[0134] The second gate isolation dielectric layer 710 is located between the sidewall surface of the second extension layer 910 and the portion of the bottom surface of the top source and drain layer 510 exposed relative to the second extension layer 910. The sidewall surface of the channel layer 410 is recessed relative to the sidewall surface of the first gate isolation dielectric layer 610 and the sidewall surface of the second gate isolation dielectric layer 710, so that a laterally open gate groove 812 is formed between the first gate isolation dielectric layer 610 and the second gate isolation dielectric layer 710, and the bottom of the gate groove 812 exposes the sidewall surface of the channel layer 410.

[0135] The gate structure 810 is at least located in the gate groove 812 .

[0136] In another embodiment, the vertical channel transistor structure further includes a first isolation layer 14 , a second isolation layer 211 , a third isolation layer 33 , a fourth isolation layer 43 , a first electrode 15 , a second electrode 25 , a second-type third electrode 32 , and a passivation layer 33 .

[0137] The first isolation layer 14 is located in the isolation trench 13 in the substrate around the bottom source / drain layer 210 and on the side of the bottom source / drain layer 210 .

[0138] The second isolation layer 211 is located between the side surfaces of the first expansion layer 310 and the first isolation layer 211 .

[0139] The third isolation layer 33 is located on the second isolation layer 211 and on the gate dielectric material film 811 on the partial surface of the second isolation layer 211, and the gate dielectric material film 811 is also located on the inner wall surface of the gate recess 812, and the gate structure 810 includes the gate dielectric material film on the partial surface of the second isolation layer 211 and the gate dielectric material film on the inner wall surface of the gate recess 812.

[0140] The fourth isolation layer 43 is located on the surface of the third isolation layer 33 and the surface of the top source-drain layer 510.

[0141] The first electrode 15 is located in the fourth isolation layer 43, and the first electrode 15 is in contact with the top source-drain layer 510.

[0142] The second electrode 25 is located in the third isolation layer 33 and the fourth isolation layer 43, and the second electrode 25 is in contact with the gate dielectric material film on the partial surface of the second isolation layer 211.

[0143] The third electrode 32 of the second type is in contact with the bottom source-drain layer 33.

[0144] The passivation layer 33 is located between the third electrode 32 of the second type and the substrate 110 and the first isolation layer 14.

[0145] In the embodiment, the detailed explanation of each feature is as follows. Please refer to the related description of the same feature in the above method embodiment, and no further description is given here.

[0146] Although the present application has been disclosed as above, the present application is not limited to this. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, and therefore the protection scope of the present application should be subject to the range defined by the claims.

Claims

1. A method for preparing a vertical channel transistor, characterized in that: include: A bottom source and drain layer, a first extension layer, a channel layer, a second extension layer, and a top source and drain layer are stacked in sequence from bottom to top on a substrate. The bottom source and drain layer, the channel layer, and the top source and drain layer are made of silicon, the first extension layer and the second extension layer are made of silicon germanium, and the bottom source and drain layer, the first extension layer, the second extension layer, and the top source and drain layer are doped with P-type ions.

2. The method for preparing a vertical channel transistor according to claim 1, wherein: The doping concentration of P-type ions in the first extension layer is the same as that in the bottom source / drain layer, and the doping concentration of P-type ions in the second extension layer is the same as that in the top source / drain layer.

3. The method for preparing a vertical channel transistor according to claim 1, wherein: The method of forming the bottom source and drain layer, the first extension layer, the channel layer, the second extension layer and the top source and drain layer stacked sequentially from bottom to top on a substrate includes: Forming a bottom source-drain layer, an initial first extension layer, an initial channel layer, an initial second extension layer and a top source-drain layer stacked sequentially from bottom to top on the substrate; performing transverse etching on the initial first extension layer to form a first groove with a transverse opening between the underlying source and drain layer and the initial channel layer, and forming a first extension layer; performing transverse etching on the initial second extension layer to form a second groove with a transverse opening between the top source / drain layer and the initial channel layer, and forming a second extension layer; forming a first gate isolation dielectric layer in the first groove; forming a second gate isolation dielectric layer in the second groove; After forming the first gate isolation dielectric layer and the second gate isolation dielectric layer, the initial channel layer is laterally etched to form a channel layer, wherein the sidewall surface of the channel layer is recessed relative to the sidewall surface of the first gate isolation dielectric layer and the sidewall surface of the second gate isolation dielectric layer, so that a gate groove with a laterally open opening is formed between the first gate isolation dielectric layer and the second gate isolation dielectric layer, and the bottom of the gate groove exposes the sidewall surface of the channel layer; A gate structure is formed at least in the gate groove.

4. The method for preparing a vertical channel transistor according to claim 3, wherein: Also includes: During the process of forming the bottom source and drain layer, the initial first extension layer, the initial channel layer, the initial second extension layer and the top source and drain layer stacked sequentially from bottom to top on the substrate, etching the substrate to form an isolation trench in the substrate around the bottom source and drain layer; After forming the bottom source and drain layer, the initial first extension layer, the initial channel layer, the initial second extension layer and the top source and drain layer stacked in sequence from bottom to top on the substrate, a first isolation layer is formed in the isolation trench and on the side of the bottom source and drain layer.

5. The method for preparing a vertical channel transistor according to claim 4, wherein: Before forming the first gate isolation dielectric layer and the second gate isolation dielectric layer, forming a protection structure on the substrate and located on the top surface of the top source and drain layer; After forming the first gate isolation dielectric layer and the second gate isolation dielectric layer, and before laterally etching the initial channel layer, the method further includes: forming protective sidewalls on the second gate isolation dielectric layer, the side surfaces of the top source and drain layer, and the surface of the protective structure; A second isolation layer is formed on the side of the first gate isolation dielectric layer.

6. The method for preparing a vertical channel transistor according to claim 5, wherein: The method for forming the gate structure includes: forming a gate dielectric material film on the surface of the second isolation layer, the inner wall surface of the gate groove, the side surface of the protection sidewall, and the surface of the protection structure; Etching and removing the gate dielectric material film on a portion of the surface of the second isolation layer; forming a third isolation layer on the second isolation layer and the gate dielectric material film on a portion of the surface of the second isolation layer, wherein a top surface of the third isolation layer is flush with a bottom surface of the protection sidewall to expose the protection sidewall and the protection structure; The protection sidewalls and the gate dielectric material film on the sides of the protection sidewalls and the surface of the protection structure are removed by etching to form the gate structure.

7. The method for preparing a vertical channel transistor according to claim 6, wherein: After forming the gate structure, the method further includes: forming a fourth isolation layer on the surface of the third isolation layer and the surface of the top source and drain layer; forming a first electrode, wherein the first electrode is located in the fourth isolation layer and contacts the top source / drain layer; A second electrode is formed, wherein the second electrode is located in the third isolation layer and the fourth isolation layer, and the second electrode is in contact with the gate dielectric material film located on a surface of a portion of the second isolation layer.

8. The method for preparing a vertical channel transistor according to claim 7, wherein: The K value of the material of the first gate isolation dielectric layer is smaller than the K value of the material of the second isolation layer; and the K value of the material of the second gate isolation dielectric layer is smaller than the K value of the material of the fourth isolation layer.

9. The method for preparing a vertical channel transistor according to claim 7, wherein: The method of forming a bottom source-drain layer, an initial first extension layer, an initial channel layer, an initial second extension layer, and a top source-drain layer stacked sequentially from bottom to top on a substrate includes: forming a bottom source-drain material layer, a first extension material layer, a channel material layer, a second extension material layer, and a top source-drain material layer stacked sequentially from bottom to top on the substrate, and performing in-situ doping in the process of forming the bottom source-drain material layer, the first extension material layer, the channel material layer, the second extension material layer, and the top source-drain material layer stacked sequentially from bottom to top on the substrate, so as to perform P-type ion doping on the bottom source-drain material layer, the first extension material layer, the second extension material layer, and the top source-drain material layer; After in-situ doping, an initial protection structure is formed on the surface of the top source / drain material layer; Etching the first extension material layer, the channel material layer, the second extension material layer, the top source and drain material layer, and the initial protection structure to correspondingly form an initial first extension layer, an initial channel layer, an initial second extension layer, the top source and drain layer, and the protection structure; The bottom source and drain material layer and the substrate are etched to form the bottom source and drain layer and the isolation groove, and the projection area of ​​the protection structure, the top source and drain layer, the initial second extension layer, the initial channel layer and the initial first extension layer on the bottom source and drain layer is smaller than the area of ​​the bottom source and drain layer.

10. The method for preparing a vertical channel transistor according to claim 9, wherein: After forming the gate structure, the method further includes: forming a first type of conductive groove in the third isolation layer and the fourth isolation layer, wherein the bottom of the first type of conductive groove exposes the underlying source and drain layer; A third electrode material is deposited in the first-type conductive grooves to form a first-type third electrode.

11. The method for preparing a vertical channel transistor according to claim 7, wherein: The method of forming a bottom source-drain layer, a first extension layer, an initial channel layer, a second extension layer, and a top source-drain layer stacked sequentially from bottom to top on a substrate includes: forming a bottom source-drain material layer, a first extension material layer, a channel material layer, a second extension material layer, and a top source-drain material layer stacked sequentially from bottom to top on the substrate, and performing in-situ doping in the process of forming the bottom source-drain material layer, the first extension material layer, the channel material layer, the second extension material layer, and the top source-drain material layer stacked sequentially from bottom to top on the substrate, so as to perform P-type ion doping on the bottom source-drain material layer, the first extension material layer, the second extension material layer, and the top source-drain material layer; After in-situ doping, an initial protection structure is formed on the surface of the top source / drain material layer; The substrate, the bottom source and drain material layer, the first extension material layer, the channel material layer, the second extension material layer, the top source and drain material layer and the initial protection structure are etched to correspondingly form the isolation groove, the bottom source and drain layer, the initial first extension layer, the initial channel layer, the initial second extension layer, the top source and drain layer and the protection structure, wherein the projection area of ​​the protection structure, the top source and drain layer, the initial second extension layer, the initial channel layer and the initial first extension layer on the bottom source and drain layer is equal to the area of ​​the bottom source and drain layer.

12. The method for preparing a vertical channel transistor according to claim 11, wherein: The substrate has two opposite sides, the gate structure is located on one side of the substrate, and after forming the first electrode and the second electrode, the method further includes: Etching the substrate and the first isolation layer from the other side of the substrate to form a second type of conductive groove in the substrate and the first isolation layer, wherein the bottom of the second type of conductive groove exposes the underlying source and drain layer; forming a passivation layer on the sidewall surface of the second-type conductive groove; A third electrode material is deposited in the second-type conductive groove where the passivation layer is formed to form a second-type third electrode.

13. The method for preparing a vertical channel transistor according to claim 9 or 11, wherein: The in-situ doping is also used to perform N-type ion doping on the channel material layer.

14. A vertical channel transistor structure, characterized in that: include: A substrate and a bottom source and drain layer, a first extension layer, a channel layer, a second extension layer and a top source and drain layer stacked sequentially from bottom to top on the substrate, wherein the bottom source and drain layer, the channel layer and the top source and drain layer are made of silicon, the first extension layer and the second extension layer are made of silicon germanium, and the bottom source and drain layer, the initial first extension layer, the initial second extension layer and the top source and drain layer are doped with P-type ions.

15. The vertical channel transistor structure according to claim 14, wherein: The bottom source and drain layer exposes a portion of its top surface relative to the first extension layer, the top source and drain layer exposes a portion of its bottom surface relative to the second extension layer, the channel layer is doped with N-type ions, and the vertical channel transistor structure further includes: a first gate isolation dielectric layer, the first gate isolation dielectric layer being located between a sidewall surface of the first extension layer and a portion of a top surface of the underlying source / drain layer exposed relative to the first extension layer; a second gate isolation dielectric layer, the second gate isolation dielectric layer being located between sidewall surfaces of the second extension layer and a portion of the bottom surface of the top source / drain layer exposed relative to the second extension layer, the sidewall surfaces of the channel layer being recessed relative to the sidewall surfaces of the first gate isolation dielectric layer and the sidewall surfaces of the second gate isolation dielectric layer, so that a gate groove with a transverse opening is formed between the first gate isolation dielectric layer and the second gate isolation dielectric layer, and the bottom of the gate groove exposes the sidewall surfaces of the channel layer; a first isolation layer, the first isolation layer being located in an isolation trench in the substrate surrounding the bottom source / drain layer and on a side surface of the bottom source / drain layer; a second isolation layer, the second isolation layer being located between a side surface of the first extension layer, a portion of the top surface of the underlying source / drain layer exposed relative to the first extension layer, and a surface of the first isolation layer; a gate structure comprising a gate dielectric material film located on a surface of a portion of the second isolation layer and a gate dielectric material film located on an inner wall surface of the gate groove; a third isolation layer, the third isolation layer being located on the second isolation layer and on the gate dielectric material film located on a portion of the surface of the second isolation layer; a fourth isolation layer, the fourth isolation layer being located on a surface of the third isolation layer and a surface of the top source / drain layer; a first electrode, wherein the first electrode is located in the fourth isolation layer and contacts the top source / drain layer; a second electrode, the second electrode being located in the third isolation layer and the fourth isolation layer, and the second electrode being in contact with the gate dielectric material film located on a surface of a portion of the second isolation layer; A first type of third electrode is located in the third isolation layer and the fourth isolation layer, and the first type of third electrode is in contact with the bottom source and drain layer.

16. The vertical channel transistor structure according to claim 14, wherein: The bottom source and drain layer exposes a portion of its top surface relative to the first extension layer, the top source and drain layer exposes a portion of its bottom surface relative to the second extension layer, the channel layer is doped with N-type ions, and the vertical channel transistor structure further includes: a first gate isolation dielectric layer, the first gate isolation dielectric layer being located between a sidewall surface of the first extension layer and a portion of a top surface of the underlying source / drain layer exposed relative to the first extension layer; a second gate isolation dielectric layer, the second gate isolation dielectric layer being located between sidewall surfaces of the second extension layer and a portion of the bottom surface of the top source / drain layer exposed relative to the second extension layer, the sidewall surfaces of the channel layer being recessed relative to the sidewall surfaces of the first gate isolation dielectric layer and the sidewall surfaces of the second gate isolation dielectric layer, so that a gate groove with a transverse opening is formed between the first gate isolation dielectric layer and the second gate isolation dielectric layer, and the bottom of the gate groove exposes the sidewall surfaces of the channel layer; a first isolation layer, the first isolation layer being located in an isolation trench in the substrate surrounding the bottom source / drain layer and on a side surface of the bottom source / drain layer; a second isolation layer, the second isolation layer being located between a side surface of the first extension layer, a portion of the top surface of the underlying source / drain layer exposed relative to the first extension layer, and a surface of the first isolation layer; a gate structure comprising a gate dielectric material film located on a surface of a portion of the second isolation layer and a gate dielectric material film located on an inner wall surface of the gate groove; a third isolation layer, the third isolation layer being located on the second isolation layer and on the gate dielectric material film located on a portion of the surface of the second isolation layer; a fourth isolation layer, the fourth isolation layer being located on a surface of the third isolation layer and a surface of the top source / drain layer; a first electrode, wherein the first electrode is located in the fourth isolation layer and contacts the top source / drain layer; a second electrode, the second electrode being located in the third isolation layer and the fourth isolation layer, and the second electrode being in contact with the gate dielectric material film located on a surface of a portion of the second isolation layer; A second type of third electrode, wherein the third electrode material layer is in contact with the underlying source and drain layer; A passivation layer is located between the second-type third electrode, the substrate, and the first isolation layer.

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