Semiconductor chip with integrated capacitor and preparation method thereof
By integrating capacitor components in the dielectric layer of the semiconductor chip, the problems of complex packaging and difficulty in miniaturization in the prior art are solved, and more efficient space utilization and process simplification are achieved.
Patent Information
- Application Number
- CN202510746021.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-05
- Publication Date
- 2025-10-17
AI Technical Summary
In the prior art, capacitance compensation solutions for depletion-mode gallium nitride semiconductor devices require independent parallel capacitor plates, which results in complex packaging and is not conducive to miniaturization design.
The capacitor components are integrated into the dielectric layer of the semiconductor chip, and the capacitor plates and electrodes are arranged on the outer edge of the chip body to achieve the capacitor compensation function. The three-dimensional space of the dielectric layer is utilized to avoid the use of independent capacitor plates.
It realizes the miniaturization design of semiconductor chips, reduces packaging complexity and process difficulty, and improves space utilization efficiency.
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Figure CN120813033A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure belongs to the technical field of semiconductor technology, and particularly relates to a semiconductor chip with integrated capacitor and a preparation method thereof. BACKGROUND
[0002] A semiconductor device is an electronic device that uses the special electrical characteristics of semiconductor materials to complete a specific function, and a semiconductor chip is an important component of a semiconductor device.
[0003] In the related art, there is a depletion-mode gallium nitride semiconductor device which is connected in parallel with a capacitor to achieve the purpose of capacitor compensation. The capacitor is a parallel capacitor plate chip independent of the semiconductor chip. During packaging, the capacitor and the semiconductor chip are connected together through wire bonding and are packaged together into a packaging frame.
[0004] However, the above packaging process is complex and requires a large space, which is not conducive to miniaturization design. SUMMARY
[0005] The present disclosure provides a semiconductor chip with integrated capacitor and a preparation method thereof, which can reduce the preparation difficulty and is conducive to miniaturization design. The technical solution is as follows:
[0006] In one aspect, the present disclosure provides a semiconductor chip with integrated capacitor, comprising: a chip body and a capacitor part.
[0007] The capacitor part is located at the outer edge of the chip body.
[0008] The capacitor part comprises a first capacitor electrode plate, a second capacitor electrode plate, a first electrode and a second electrode. The first capacitor electrode plate and the second capacitor electrode plate are both located in the dielectric layer of the chip body and are arranged in opposite directions. The first electrode and the second electrode are both located outside the dielectric layer and are arranged in opposite directions. The first electrode is electrically connected to the first capacitor electrode plate, the second electrode is electrically connected to the second capacitor electrode plate, and the first electrode and the second electrode are connected in parallel between the gate and the source of the chip body.
[0009] In one implementation of the present disclosure, the first capacitor electrode plate comprises a first U-shaped segment.
[0010] The length direction of the first U-shaped segment is consistent with the epitaxial growth direction of the chip body. The first U-shaped segment has an open end and a closed end at both ends of the length direction.
[0011] In one implementation of the present disclosure, the first capacitor electrode plate comprises a first connection segment and at least two first U-shaped segments.
[0012] The first connecting section is located between the open ends of two adjacent first U-shaped sections, and one end of the first connecting section is connected to the open end of one first U-shaped section, and the other end of the first connecting section is connected to the open end of another first U-shaped section.
[0013] In an implementation form of the present disclosure, the open ends of the first U-shaped sections are located on a same plane perpendicular to the epitaxial layer growth direction, and the closed ends of the first U-shaped sections are located on a same plane perpendicular to the epitaxial layer growth direction.
[0014] In an implementation form of the present disclosure, the second capacitor plate includes a second U-shaped section.
[0015] The second U-shaped section is located at the open end and the closed end at the two ends in the length direction, and the length direction of the second U-shaped section is consistent with the epitaxial growth direction of the chip body.
[0016] In an implementation form of the present disclosure, the second capacitor plate includes a second U-shaped section.
[0017] The second connecting section is located between the open ends of two adjacent second U-shaped sections, and one end of the second connecting section is connected to the open end of one second U-shaped section, and the other end of the second connecting section is connected to the open end of another second U-shaped section.
[0018] In an implementation form of the present disclosure, the open ends of the second U-shaped sections are located on a same plane perpendicular to the epitaxial layer growth direction, and the closed ends of the second U-shaped sections are located on a same plane perpendicular to the epitaxial layer growth direction.
[0019] In an implementation form of the present disclosure, the first capacitor plate and the second capacitor plate have an inter-plate medium therebetween.
[0020] The inter-plate medium is filled between the first capacitor plate and the second capacitor plate, and the inter-plate medium is an insulating member.
[0021] In an implementation form of the present disclosure, the capacitor part is arranged around the outer edge of the chip body.
[0022] Alternatively, the capacitor part is located on one side of the chip body.
[0023] In another aspect, the embodiments of the present disclosure provide a preparation method of a semiconductor chip, the preparation method being used for preparing the semiconductor chip of the previous aspect, and the preparation method comprising:
[0024] Preparation of a chip body;
[0025] etching a groove at the outer edge of the dielectric layer of the chip body;
[0026] depositing a first capacitor plate at the groove;
[0027] depositing an inter-plate dielectric at the first capacitor plate;
[0028] depositing a second capacitor plate on the side of the inter-plate dielectric opposite to the first capacitor plate;
[0029] depositing a first electrode and a second electrode on the side of the second capacitor plate opposite to the first capacitor plate, so that the first electrode is electrically connected to the first capacitor plate and the source of the chip body respectively, and the second electrode is electrically connected to the second capacitor plate and the gate of the chip body respectively.
[0030] The technical scheme provided by the embodiments of the present disclosure has the following beneficial effects:
[0031] The semiconductor chip provided by the embodiments of the present disclosure includes a chip body and a capacitor part, wherein the chip body serves to realize a specific function by utilizing the special electrical characteristics of the semiconductor material itself, and the capacitor part serves to compensate the capacitance. The capacitor part is located at the outer edge of the chip body, so as not to affect the functionality of the chip body. The capacitor part includes a first capacitor plate, a second capacitor plate, a first electrode and a second electrode, wherein the first capacitor plate and the second capacitor plate are both arranged in the dielectric layer of the chip body, so as to effectively utilize the space in the three-dimensional direction of the dielectric layer. The first electrode plate and the second electrode plate are arranged outside the dielectric layer, so as to facilitate the connection of the source and the gate of the chip body, thereby achieving the purpose of capacitance compensation.
[0032] That is, the semiconductor chip provided by the embodiments of the present disclosure can effectively utilize the space in the three-dimensional direction of the dielectric layer by integrating the capacitor part in the dielectric layer of the chip body, so as to realize the miniaturization design of the semiconductor chip. In addition, since the capacitor and the semiconductor chip are integrated together, it is not necessary to connect them by wire bonding, thereby effectively reducing the process difficulty. BRIEF DESCRIPTION OF DRAWINGS
[0033] In order to more clearly illustrate the technical scheme in the embodiments of the present disclosure, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without creative labor.
[0034] Figure 1 is a structural schematic diagram of the semiconductor chip provided by the embodiments of the present disclosure;
[0035] Figure 2 is provided by embodiments of the present disclosure Figure 1 is a sectional view along A-A direction of the
[0036] Figure 3 is a flow chart of a preparation method of a semiconductor chip provided by embodiments of the present disclosure
[0037] Figure 4 is a flow chart of another preparation method of a semiconductor chip provided by embodiments of the present disclosure
[0038] Figure 5 is a step schematic diagram of the preparation method provided by embodiments of the present disclosure
[0039] Figure 6 is a step schematic diagram of the preparation method provided by embodiments of the present disclosure
[0040] Figure 7 is a step schematic diagram of the preparation method provided by embodiments of the present disclosure
[0041] Figure 8 is a step schematic diagram of the preparation method provided by embodiments of the present disclosure
[0042] Figure 9 is a step schematic diagram of the preparation method provided by embodiments of the present disclosure
[0043] The meanings of the symbols in the figures are as follows:
[0044] 10, chip body
[0045] 110, dielectric layer; 120, interboard dielectric; 130, groove; 140, first hole groove; 150, second hole groove
[0046] 20, capacitor part
[0047] 210, first capacitor plate; 211, first connecting section; 212, first U-shaped section; 213, first vertical section; 214, first horizontal section; 215, second vertical section
[0048] 220, second capacitor plate; 221, second connecting section; 222, second U-shaped section; 223, third vertical section; 224, second horizontal section; 225, fourth vertical section
[0049] 230, first electrode
[0050] 240, second electrode
[0051] The specific embodiments of the present disclosure have been shown in the above drawings, and will be described in more detail hereinafter. These drawings and detailed description are not intended to limit the scope of the present disclosure in any way, but to illustrate the concept of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION
[0052] In order to make the purposes, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in further detail below with reference to the drawings.
[0053] The embodiments of the present disclosure provide a semiconductor chip with integrated capacitor, Figure 1 For the structural schematic diagram of the semiconductor chip, refer to Figure 1 In the present embodiment, the semiconductor chip comprises a chip body 10 and a capacitor part 20, and the capacitor part 20 is located at the outer edge of the chip body 10.
[0054] Figure 2 For the A-A direction sectional view of Figure 1 , combined with Figure 2 In the present embodiment, the capacitor part 20 comprises a first capacitor plate 210, a second capacitor plate 220, a first electrode 230 and a second electrode 240, the first capacitor plate 210 and the second capacitor plate 220 are both located in the dielectric layer 110 of the chip body 10 and are arranged in opposite directions, the first electrode 230 and the second electrode 240 are both located outside the dielectric layer 110 and are arranged in opposite directions, the first electrode 230 is electrically connected with the first capacitor plate 210, the second electrode 240 is electrically connected with the second capacitor plate 220, and the first electrode 230 and the second electrode 240 are connected in parallel between the gate and the source of the chip body 10.
[0055] The semiconductor chip provided by the embodiments of the present disclosure comprises a chip body 10 and a capacitor part 20, wherein the chip body 10 plays a role of realizing specific functions by utilizing the special electrical characteristics of its own semiconductor material, and the capacitor part 20 plays a role of capacitor compensation. The capacitor part 20 is located at the outer edge of the chip body 10, so as not to affect the functionality of the chip body 10. The capacitor part 20 comprises a first capacitor plate 210, a second capacitor plate 220, a first electrode 230 and a second electrode 240, wherein the first capacitor plate 210 and the second capacitor plate 220 are both arranged in the dielectric layer 110 of the chip body 10, so as to effectively utilize the space in the three-dimensional direction of the dielectric layer 110. The first electrode 230 and the second electrode 240 are arranged outside the dielectric layer 110, so as to facilitate the connection of the source and the gate of the chip body 10, thereby achieving the purpose of capacitor compensation.
[0056] That is, the semiconductor chip provided by the embodiment of the present disclosure can effectively utilize the space of the dielectric layer 110 in the three-dimensional direction to realize the miniaturization design of the semiconductor chip by integrating the capacitor part 20 in the dielectric layer 110 of the chip body 10. In addition, since the capacitor and the semiconductor chip are integrated together, there is no need to be connected by wire bonding, which effectively reduces the process difficulty.
[0057] It is worth noting that the three-dimensional direction of the dielectric layer 110 refers to the three directions of X, Y, and Z in Figure 1 and Figure 2 , wherein the Z direction is the epitaxial growth direction of the chip body 10, the X direction and the Y direction are perpendicular to each other and perpendicular to the Z direction.
[0058] In addition, the first electrode 230 and the second electrode 240 are connected in parallel between the gate and the source of the chip body 10, which means that the first electrode 230 is electrically connected to one of the gate and the source, and the second electrode 240 is electrically connected to the other of the gate and the source.
[0059] In the embodiment, the capacitor part 20 is arranged around the outer edge of the chip body 10.
[0060] In this way, the total area of the capacitor part 20 can be increased as much as possible to ensure the functionality of the capacitor part 20 without affecting the functionality of the chip body 10.
[0061] For example, the capacitor part 20 is located in the region between the main chip and the seal ring (SealRing) of the chip body 10.
[0062] In other embodiments, the capacitor part 20 is located on one side of the chip body 10.
[0063] That is, the capacitor part 20 can be located in the blank area of the chip body 10 to ensure that the capacitor part 20 does not affect the normal function of the chip body 10.
[0064] In the embodiment, the first capacitor plate 210 and the second capacitor plate 220 are aluminum structural members or aluminum alloy structural members.
[0065] Of course, in other embodiments, the first capacitor plate 210 and the second capacitor plate 220 can also be other conductive metal structural members, which are not limited by the present disclosure.
[0066] Continuing to refer to Figure 2 In the embodiment, the first capacitor plate 210 includes a first U-shaped section 212. The length direction of the first U-shaped section 212 is consistent with the epitaxial growth direction of the chip body 10, and the first U-shaped section 212 is located at the open end and the closed end at the two ends of the length direction.
[0067] In the embodiment, the first capacitor plate 210 includes a first connecting segment 211 and at least two first U-shaped segments 212.
[0068] The first connecting segment 211 is located between the open ends of two adjacent first U-shaped segments 212, and one end of the first connecting segment 211 is connected to the open end of one first U-shaped segment 212, and the other end of the first connecting segment 211 is connected to the open end of the other first U-shaped segment 212.
[0069] In the above implementation, the length direction of the first U-shaped segment 212 extends along the epitaxial growth direction of the chip body 10, so that the Z direction in the dielectric layer 110 can be effectively utilized. In this way, compared with parallel capacitor plates, the occupation of space can be effectively reduced. The first connecting segment 211 is used to connect two adjacent first U-shaped segments 212 together to realize electrical connection, so that each first connecting segment 211 and each first U-shaped segment 212 become a conductive whole.
[0070] For example, the first U-shaped segment 212 includes a first vertical segment 213, a first horizontal segment 214 and a second vertical segment 215 connected in sequence, wherein the length direction of the first vertical segment 213 and the second vertical segment 215 are consistent with the Z direction, and the first horizontal segment 214 is located between the first vertical segment 213 and the second vertical segment 215 and is perpendicular to the Z direction. In this way, the shape of the first U-shaped segment 212 is relatively neat, which is conducive to being opposite to the second U-shaped segment 222 to ensure its function of capacitive compensation.
[0071] Of course, in other embodiments, the connection between the first vertical segment 213 and the first horizontal segment 214, and the connection between the second vertical segment 215 and the first horizontal segment 214 can also be arc-shaped or other shapes, which are not limited by the present disclosure.
[0072] In the embodiment, the open ends of each first U-shaped segment 212 are located on the same plane perpendicular to the epitaxial growth direction, and the closed ends of the first U-shaped segment 212 are located on the same plane perpendicular to the epitaxial growth direction.
[0073] In the above implementation, the open ends and the closed ends of the first U-shaped segment 212 are arranged in this way, on the one hand, the connecting segment can be used to connect two adjacent first U-shaped segments 212 together to realize electrical connection, and on the other hand, the shape of the first U-shaped segment 212 is relatively neat, which is conducive to being opposite to the second U-shaped segment 222.
[0074] Continuing to refer to Figure 2In the embodiment, the second capacitor plate 220 comprises a second U-shaped segment 222. The length direction of the second U-shaped segment 222 is consistent with the epitaxial growth direction of the chip body 10, and the second U-shaped segment 222 is located at the length direction ends of the open end and the closed end.
[0075] In the embodiment, the second capacitor plate 220 comprises a second connection segment 221 and at least two second U-shaped segments 222.
[0076] The second connection segment 221 is located between the open ends of the two adjacent second U-shaped segments 222, and one end of the second connection segment 221 is connected with the open end of one second U-shaped segment 222, and the other end of the second connection segment 221 is connected with the open end of another second U-shaped segment 222.
[0077] In the above implementation, the length direction of the second U-shaped segment 222 is along the epitaxial growth direction of the chip body 10, so that the Z direction in the dielectric layer 110 can be effectively utilized. In this way, compared with the parallel capacitor plate, the occupation of the space can be effectively reduced. The second connection segment 221 is used to connect the two adjacent second U-shaped segments 222 together to realize electrical connection, so that each second connection segment 221 and each second U-shaped segment 222 become a conductive whole.
[0078] Exemplarily, the second U-shaped segment 222 comprises a third vertical segment 223, a second horizontal segment 224 and a fourth vertical segment 225 connected in sequence, wherein the length direction of the third vertical segment 223 and the fourth vertical segment 225 is consistent with the Z direction, and the second horizontal segment 224 is located between the third vertical segment 223 and the fourth vertical segment 225 and is perpendicular to the Z direction. In this way, the shape of the second U-shaped segment 222 is more regular, which can be beneficial to the relative position with the first U-shaped segment 212 to ensure its function of capacitor compensation.
[0079] Of course, in other embodiments, the connection between the third vertical segment 223 and the second horizontal segment 224, and the connection between the fourth vertical segment 225 and the second horizontal segment 224 can also be arc-shaped or other shapes, which are not limited in the present disclosure.
[0080] In the embodiment, the open ends of each second U-shaped segment 222 are located on the same plane perpendicular to the epitaxial layer growth direction, and the closed ends of the second U-shaped segments 222 are located on the same plane perpendicular to the epitaxial layer growth direction.
[0081] In the above implementation, the opening end and the closed end of the second U-shaped section 222 are arranged in this way, on the one hand, it is convenient to connect the two adjacent second U-shaped sections 222 together by the connecting section to realize electrical connection, on the other hand, it can make the shape of the second U-shaped section 222 more regular, which is conducive to the relative arrangement with the first U-shaped section 212.
[0082] In the embodiment, the second capacitor plate 220 is closer to the top surface of the chip body 10 than the first capacitor plate 210, and the size of the second U-shaped section 222 is slightly smaller than the size of the first U-shaped section 212, so that the second U-shaped section 222 can be located in the recess of the first U-shaped section 212, and the first vertical section 213 and the third vertical section 223 are parallel and opposite, the second vertical section 215 and the fourth vertical section 225 are parallel and opposite, and the first horizontal section 214 and the second horizontal section 224 are parallel and opposite.
[0083] Continuing to refer to Figure 2 In the embodiment, the inter-plate medium 120 is filled between the first capacitor plate 210 and the second capacitor plate 220, and the inter-plate medium 120 is an insulating piece.
[0084] For example, the inter-plate medium 120 is an insulating material, such as silicon dioxide or silicon nitride.
[0085] The thickness of the inter-plate medium 120 can be determined according to the actual capacitance size and the required capacitance withstand voltage, and for example, the thickness of the inter-plate medium 120 is less than 10 μm.
[0086] Figure 3 A flowchart of a preparation method of a semiconductor chip provided by the embodiment of the present disclosure is combined with Figure 3 In the embodiment, the preparation method comprises:
[0087] Step 301: preparing a chip body 10.
[0088] Step 302: etching a groove 130 at the outer edge of the medium layer 110 of the chip body 10.
[0089] Step 303: depositing a first capacitor plate 210 at the groove 130.
[0090] Step 304: depositing an inter-plate medium 120 at the first capacitor plate 210.
[0091] Step 305: depositing a second capacitor plate 220 on the side of the inter-plate medium 120 away from the first capacitor plate 210.
[0092] Step 306: Deposit a first electrode 230 and a second electrode 240 on the side of the second capacitor plate 220 facing away from the first capacitor plate 210, so that the first electrode 230 is electrically connected to the first capacitor plate 210 and the source of the chip body 10, respectively, and the second electrode 240 is electrically connected to the second capacitor plate 220 and the gate of the chip body 10, respectively.
[0093] The semiconductor chip produced by the method provided in the embodiments of the present disclosure integrates the capacitor portion 20 within the dielectric layer 110 of the chip body 10, effectively utilizing the three-dimensional space of the dielectric layer 110 to achieve a miniaturized design of the semiconductor chip. Furthermore, since the capacitor and semiconductor chip are integrated together, there is no need for wire bonding to connect them, effectively reducing the complexity of the process.
[0094] Figure 4 A flowchart of another method for preparing a semiconductor chip provided in an embodiment of the present disclosure, combined with Figure 4 In this embodiment, the preparation method includes:
[0095] Step 401: Prepare the chip body 10.
[0096] In this embodiment, the chip body 10 includes a substrate, an epitaxial layer, a dielectric layer 110 , a source electrode, a gate electrode, a drain electrode and other structures.
[0097] Step 402: Etch a groove 130 at the outer edge of the dielectric layer 110 of the chip body 10 (see Figure 5 ).
[0098] In step 402 , a groove 130 is etched at the outer edge of the dielectric layer 110 by photolithography.
[0099] Exemplarily, there are two grooves 130 , and one groove 130 surrounds the other groove 130 to form a U-shaped structure.
[0100] Step 403 : depositing the first capacitor plate 210 in the groove 130 .
[0101] Illustratively, the first capacitor plate 210 is deposited in the groove 130 by physical vapor deposition (PVD).
[0102] Step 404: Etch the first capacitor plate 210 to remove excess metal deposits (see Figure 6 ).
[0103] In step 404 , the first capacitor plate 210 is etched by a photolithography process.
[0104] Step 405: depositing the inter-plate medium 120 at the first capacitor plate 210 (see Figure 7 ).
[0105] The inter-plate medium 120 is exemplarily deposited at the first capacitor plate 210 by way of Chemical Vapor Deposition (CVD).
[0106] The inter-plate medium 120 is exemplarily silicon dioxide or silicon nitride.
[0107] Step 406: depositing the second capacitor plate 220 at the side of the inter-plate medium 120 opposite to the first capacitor plate 210.
[0108] The deposition of step 406 is substantially the same as that of step 403, and thus is not described herein again.
[0109] Step 407: etching the second capacitor plate 220 to remove the excess metal deposit (see Figure 8 ).
[0110] The etching of step 407 is substantially the same as that of step 404, and thus is not described herein again.
[0111] Step 408: depositing a passivation layer at the side of the second capacitor plate 220 opposite to the first capacitor plate 210, and etching the passivation layer to form the first via 140 and the second via 150 (see Figure 9 ).
[0112] Step 409: depositing the first electrode 230 in the first via 140 and the second electrode 240 in the second via 150, such that the first electrode 230 is electrically connected to the first capacitor plate 210 and the source of the chip body 10 respectively, and the second electrode 240 is electrically connected to the second capacitor plate 220 and the gate of the chip body 10 respectively.
[0113] Unless otherwise defined, technical terms or scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", "third" and similar terms used herein do not denote any order, quantity, or importance, but are used to distinguish one element from another, and the terms "one", "another", "an" and "a" are defined as including one or more of the referenced elements. The terms "including" and "comprising" and similar terms are used herein to mean that the referenced elements are included or comprised, but not to the exclusion of other elements. The term "connected" or "coupled" and similar terms are used herein to mean either a direct connection or coupling between the connected or coupled elements, or an indirect connection or coupling between the connected or coupled elements through one or more additional elements. The terms "upper", "lower", "left", "right", and similar terms are used herein only to denote relative positions for ease of description, and can change accordingly when the absolute positions of the described objects are changed.
[0114] The above description is merely illustrative of the exemplary embodiments of this disclosure, and does not limit the scope of the disclosure. Any modification, equivalent replacement, improvement, and the like made within the spirit and principle of this disclosure shall be included in the scope of the disclosure.
Claims
1. A semiconductor chip with an integrated capacitor, characterized in that: It comprises: a chip body (10) and a capacitor part (20); The capacitor portion (20) is located at the outer edge of the chip body (10); The capacitor portion (20) includes a first capacitor plate (210), a second capacitor plate (220), a first electrode (230) and a second electrode (240); the first capacitor plate (210) and the second capacitor plate (220) are both located in the dielectric layer (110) of the chip body (10) and are arranged with a relative interval; the first electrode (230) and the second electrode (240) are both located outside the dielectric layer (110) and are arranged with a relative interval; the first electrode (230) is electrically connected to the first capacitor plate (210); the second electrode (240) is electrically connected to the second capacitor plate (220); and the first electrode (230) and the second electrode (240) are connected in parallel between the gate and the source of the chip body (10).
2. The semiconductor chip according to claim 1, wherein The first capacitor plate (210) includes a first U-shaped section (212); The length direction of the first U-shaped segment (212) is consistent with the epitaxial growth direction of the chip body (10), and the first U-shaped segment (212) has an open end and a closed end at both ends in the length direction.
3. The semiconductor chip according to claim 2, wherein: The first capacitor plate (210) comprises a first connecting section (211) and at least two first U-shaped sections (212); The first connecting section (211) is located between the open ends of two adjacent first U-shaped sections (212), and one end of the first connecting section (211) is connected to the open end of one first U-shaped section (212), and the other end of the first connecting section (211) is connected to the open end of another first U-shaped section (212).
4. The semiconductor chip according to claim 3, wherein: The open ends of each first U-shaped segment (212) are located on a same plane perpendicular to the growth direction of the epitaxial layer, and the closed ends of each first U-shaped segment (212) are located on another same plane perpendicular to the growth direction of the epitaxial layer.
5. The semiconductor chip according to claim 1, wherein The second capacitor plate (220) includes a second U-shaped section (222); The length direction of the second U-shaped segment (222) is consistent with the epitaxial growth direction of the chip body (10), and the second U-shaped segment (222) is located at two ends in the length direction, namely an open end and a closed end.
6. The semiconductor chip according to claim 5, wherein: The second capacitor plate (220) comprises a second connecting section (221) and at least two second U-shaped sections (222); The second connecting section (221) is located between the open ends of two adjacent second U-shaped sections (222), and one end of the second connecting section (221) is connected to the open end of one second U-shaped section (222), and the other end of the second connecting section (221) is connected to the open end of another second U-shaped section (222).
7. The semiconductor chip according to claim 6, wherein: The open ends of each second U-shaped segment (222) are located on a plane perpendicular to the growth direction of the epitaxial layer, and the closed ends of each second U-shaped segment (222) are located on another plane perpendicular to the growth direction of the epitaxial layer.
8. The semiconductor chip according to any one of claims 1 to 7, wherein: There is an inter-plate dielectric (120) between the first capacitor plate (210) and the second capacitor plate (220); The inter-plate dielectric (120) is filled between the first capacitor plate (210) and the second capacitor plate (220), and the inter-plate dielectric (120) is an insulating member.
9. The semiconductor chip according to any one of claims 1 to 7, characterized in that The capacitor portion (20) is arranged around the outer edge of the chip body (10); Alternatively, the capacitor portion (20) is located on one side of the chip body (10).
10. A method for preparing a semiconductor chip, characterized in that: The preparation method is used to prepare the semiconductor chip according to any one of claims 1 to 9, and the preparation method comprises: preparing a chip body (10); Etching a groove (130) at the outer edge of the dielectric layer (110) of the chip body (10); depositing a first capacitor plate (210) at the groove (130); Depositing an inter-plate dielectric (120) on the first capacitor plate (210); Depositing a second capacitor plate (220) on a side of the inter-plate dielectric (120) facing away from the first capacitor plate (210); A first electrode (230) and a second electrode (240) are deposited on a side of the second capacitor plate (220) facing away from the first capacitor plate (210), so that the first electrode (230) is electrically connected to the first capacitor plate (210) and the source of the chip body (10), respectively, and the second electrode (240) is electrically connected to the second capacitor plate (220) and the gate of the chip body (10), respectively.