System and method for detecting index change of chip after reflow soldering and surface mounting, and medium

Abstract

The invention discloses a system and a method for detecting the index change of a chip after reflow soldering and surface mounting, and a medium. The system comprises a programmable reflow soldering machine, a programmable testing machine and a testing PC (Personal Computer), the programmable reflow soldering machine comprises a chip soldering plate and a console; the chip welding plate is used for placing a to-be-tested chip; the console is used for receiving the control instruction for reflow soldering control; the programmable testing machine is used for carrying out index testing on the to-be-tested chip on the programmable reflow soldering machine according to the control instruction after reflow soldering of the to-be-tested chip is completed, and chip testing data are formed; the test PC is used for sending a control instruction to the programmable reflow soldering machine and the programmable test machine so as to carry out chip performance test, and receiving chip test data returned by the programmable test machine. According to the invention, the integrated design of the reflow soldering process and the chip performance index test is realized, the direct electrical test after soldering is supported, the chip test data is compared with the stored historical test data, and the visual chip index change data is quickly formed.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a system, method and medium for detecting changes in chip indicators after reflow soldering. Background Art

[0002] During the reflow process, thermal stress and temperature can cause chip performance indicators (such as electrical characteristics) to shift. If this shift exceeds the normal range, it can negatively impact the overall chip performance, such as reduced reliability or functional abnormalities.

[0003] Currently, the industry primarily indirectly ensures chip parameter stability through process monitoring and optimization, encompassing three key dimensions: process monitoring (such as temperature profile monitoring and defect detection), performance testing (covering electrical, thermal, and mechanical properties), and reliability verification (such as environmental stress testing and life testing). These methods collectively assess changes in key chip indicators after chip placement to optimize the production process.

[0004] However, in the surface mount technology (SMT) process, there is currently a lack of a solution to directly detect changes in chip performance after reflow soldering. This makes it impossible to accurately identify whether the chip performance changes are caused by the reflow soldering process, thereby limiting the efficiency of chip defect diagnosis and process improvement. Summary of the Invention

[0005] In view of this, the embodiment of the present invention provides a detection system, method and medium for detecting chip index changes after reflow soldering.

[0006] On one hand, the present invention provides a system for detecting changes in chip indicators after reflow soldering, comprising a programmable reflow soldering machine, a programmable test machine and a test PC;

[0007] The programmable reflow soldering machine includes a chip soldering plate and a control console; the chip soldering plate is used to place the chip to be tested; the control console is used to receive control instructions to perform reflow soldering control;

[0008] The programmable tester is used to perform an index test on the chip to be tested on the programmable reflow soldering machine according to the control instruction after the chip to be tested completes reflow soldering, thereby generating chip test data;

[0009] The test PC is used to send control instructions to the programmable reflow machine and the programmable test machine to perform chip performance testing, and receive chip test data returned by the programmable test machine.

[0010] Furthermore, the control instructions sent by the test PC to the programmable reflow soldering machine are used to control the temperature test environment of the chip to be tested; the control instructions sent by the test PC to the programmable test machine are used to instruct the programmable test machine to send test signals corresponding to chip indicators to the chip to be tested, and receive test data corresponding to indicators returned by the chip to be tested.

[0011] Furthermore, the programmable test machine is composed of an MCU chip and an FPGA array; the FPGA array stores multiple chip index test programs; the MCU chip is used to decode the control instructions sent by the test PC and call the target chip index test program stored in the FPGA array to perform index testing on the chip.

[0012] Furthermore, the chip indicators include frequency accuracy indicator, temperature drift indicator, zero offset indicator, linearity indicator, gain error indicator and offset error indicator.

[0013] Furthermore, the test PC stores historical test data of the same chip as the chip to be tested; the test data is also used to compare the chip test data of the chip to be tested with the historical test data to form a chip test result.

[0014] Furthermore, a plurality of chips to be tested are placed on the chip welding board, and the programmable test machine includes a plurality of test paths, each of which is connected to a chip to be tested in the programmable reflow machine to perform index tests on the chip to be tested.

[0015] Furthermore, the test PC is a host computer, and the host computer is connected to the programmable test machine and the reflow soldering machine console via an RS485 / RS422 bus.

[0016] Another aspect of the present invention provides a method for testing the performance indicators of a TCXO clock chip, which is implemented based on the above-mentioned detection system for chip indicator changes after reflow soldering and includes the following steps:

[0017] Place the TCXO clock chip as the chip to be tested on the chip welding board and perform reflow soldering on the chip to be tested;

[0018] After the chip under test is left to cool for a preset time, the test PC sends control instructions to the programmable reflow machine to keep the chip under test in the target temperature environment;

[0019] The test PC sends control instructions to the programmable tester, which supplies power to the chip under test, collects the clock frequency output by the chip under test, and generates chip test data in the programmable tester.

[0020] After the chip test data is obtained from the programmable test machine through the test PC, the frequency deviation rate of the chip test data is compared with the stored historical test data to form a temperature-frequency comparison curve of the TCXO clock chip.

[0021] Another aspect of the present invention provides a method for testing ADC / DAC chip performance indicators, which is based on the above-mentioned detection system for chip indicator changes after reflow soldering and includes the following steps:

[0022] Place the ADC / DAC chip as the chip to be tested on the chip soldering board and perform reflow soldering on the chip to be tested;

[0023] After the chip under test is left to cool for a preset time, the test PC sends control instructions to the programmable reflow machine to keep the chip under test in the target temperature environment;

[0024] The test PC sends control instructions to the programmable tester, which supplies power to the chip under test and sends test instructions, collects the analog voltage output by the chip under test, and forms chip test data in the programmable tester;

[0025] After the chip test data is obtained from the programmable test machine through the test PC, the linearity error and zero offset of the chip test data are compared with the stored historical test data to form a temperature-voltage comparison curve of the ADC / DAC chip.

[0026] Another aspect of the present invention provides a computer-readable storage medium storing a program, wherein the program is executed by a processor to implement the test PC function in the above-mentioned system for detecting chip indicator changes after reflow soldering.

[0027] The embodiments of the present invention have the following beneficial effects: The present invention provides a system, method, and medium for detecting changes in chip indicators after reflow soldering and surface mounting, realizing an integrated design of the reflow soldering process and chip performance indicator testing, integrating a programmable reflow soldering machine with a programmable test machine, and supporting direct electrical testing after soldering. After the test is completed, the test PC directly retrieves the stored historical test data and compares it with the chip test data to quickly generate intuitive chip indicator change data. Compared with the traditional process that requires the transfer of the chip to be tested between different devices, the present invention can avoid the errors caused by chip transfer and is widely used in the test process of chip performance indicators.

[0028] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0030] Figure 1 The present invention is a schematic structural diagram of a detection system for chip indicator changes after reflow soldering.

[0031] Figure 2 It is a schematic diagram of the actual assembly of the system of the present invention.

[0032] Figure 3 It is a schematic diagram of the test results of the TCXO clock chip performance index testing method of the present invention.

[0033] Figure 4 It is a schematic diagram of the test results of the ADC / DAC chip performance index testing method of the present invention.

[0034] Figure 5 It is a schematic diagram of the structure of a computer-readable storage medium of the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0036] After the reflow process, some chip performance indicators may change, primarily including the frequency accuracy of clock chips, the gain and offset errors of ADC / DAC chips, and the linearity and zero-point offset of thermal and piezoelectric sensors. These chip indicators are easily affected by SMT, leading to deterioration, and this has an unavoidable and negligible impact on the application of these chips in these areas. If the post-surface mounting performance of the tested chip exceeds the qualified range specified in the product manual, or deviates from the historical FT test quantity by more than the empirical value (for example, clock chips will tighten the specifications by 20% to ensure frequency accuracy after board mounting), it indicates that the chip has obvious defects or problems at the relevant design or manufacturing nodes.

[0037] like Figure 1 As shown, the first embodiment of the present invention provides a system for detecting changes in chip indicators after reflow soldering, including a programmable reflow soldering machine, a programmable test machine and a test PC.

[0038] The programmable reflow machine includes a chip soldering plate and a control console; the chip soldering plate is used to place the chip to be tested; and the control console is used to receive control instructions for reflow control. In the embodiment of the present invention, the chip soldering plate adopts a modular design and is fixed in the reflow machine through a card slot. A solder paste pad is pre-set on its surface to carry the chip to be tested, and each card slot is used as the minimum unit for chip index testing. The console receives instructions from the test PC through the RS485 / RS422 bus, dynamically adjusts the temperature curve from 25°C to 500°C, accurately simulates the actual SMT reflow process environment (such as automotive-grade high-temperature scenarios, etc.), and provides various temperature environments for chip index testing.

[0039] The programmable test machine is used to perform index tests on the chip to be tested on the programmable reflow machine according to control instructions after the chip to be tested completes reflow soldering, thereby generating chip test data.

[0040] In an embodiment of the present invention, a programmable tester is composed of an MCU chip and an FPGA array. The MCU chip serves as the instruction parsing center, receiving control instructions from the test PC via the RS485 / RS422 bus, identifying the target test type through instruction decoding, and then activating the corresponding pre-stored test program in the FPGA array. The FPGA array serves as a hardware acceleration module, and internally incorporates specialized test algorithms for different chip categories—for example, a ppm-level frequency deviation detection program for clock chips, a linearity scanning algorithm for ADC / DAC chips, and a zero-drift compensation test process for sensors.

[0041] For example, during implementation, the FPGA array directly drives the chip's test path: it outputs a 0-12V chip operating voltage via a programmable power pin, captures chip output signals using a high-speed acquisition channel (500MHz bandwidth), and configures the chip's internal registers via the IIC / SPI communication interface. Test data returned by the chip is pre-processed by the FPGA and then transmitted to the MCU, ultimately forming a structured test data packet containing the original waveform, calculated metrics, and timestamps, which serves as the chip test data.

[0042] In some embodiments, for multi-chip parallel testing scenarios, the chip bonding board adopts a modular design, and each chip bonding pad is independently connected to one of the multiple test paths of the test machine.

[0043] For example, when multiple chips are placed on a soldering plate (e.g., a 4×4 array), the tester dynamically allocates 16 physical paths to each chip via a multiplexer. The MCU dispatches FPGA resources based on these instructions: It can perform the same test on all chips (e.g., random inspection during mass production) or assign different test procedures to different chips (e.g., comparing multiple packaging solutions during R&D).

[0044] In these embodiments, the independent design of test paths ensures that each path has independent power supply, signal isolation, and data caching capabilities, ensuring that parallel testing does not cause signal crosstalk. Test results are automatically associated with chip location coordinates, making it easier to locate specific failed chips.

[0045] The test PC is used to send control commands to the programmable reflow machine and programmable tester to perform chip performance testing, and receives chip test data returned by the programmable tester. In this embodiment of the present invention, the test PC uses host computer software to achieve full process automation management, integrating traditional discrete process simulation, parameter testing, and data analysis processes into an integrated solution.

[0046] The control commands sent by the test PC to the programmable reflow oven control the temperature test environment of the chip under test, accurately simulating the actual working conditions of the SMT production line. For example, in the automotive-grade chip testing scenario, the test PC can program a multi-stage temperature control curve from 25°C to 500°C (including preheating zone, reflow zone, and cooling zone) and monitor the thermal stress application process in real time.

[0047] The control instructions sent by the test PC to the programmable tester can instruct the programmable tester to send test signals corresponding to chip indicators to the chip under test and receive test data corresponding to the indicators returned by the chip under test.

[0048] After the test PC receives the chip test data sent back by the programmable test machine, it retrieves the historical test data of the same chip stored in the host computer, compares the current chip test data with the historical test data, and generates intuitive chip test results to prompt developers of the impact of the reflow soldering process on chip performance indicators.

[0049] The actual assembly effect of the present invention is as follows Figure 2 As shown. The present invention uses a programmable reflow soldering machine to accurately reproduce the temperature curve of the user's SMT production line, applying a thermal stress environment on the chip soldering board that is completely consistent with the actual patch, eliminating the interference of environmental variables in traditional indirect testing. At the same time, the test algorithms for chip performance indicators such as frequency accuracy index, temperature drift index, zero offset index, linearity index, gain error index and offset error index are solidified in the FPGA array. After the chip completes the reflow soldering process, it is directly tested in situ to ensure that the electrical parameters are directly obtained within the critical time window after the reflow soldering is completed, avoiding performance degradation after the chip leaves the test environment.

[0050] A second embodiment of the present invention provides a method for testing the performance indicators of a TCXO clock chip, which is based on the detection system for chip indicator changes after reflow soldering in the first embodiment and includes the following steps:

[0051] S201. Place the TCXO clock chip as the chip to be tested on the chip soldering board and perform a reflow soldering operation on the chip to be tested;

[0052] S202. After the chip under test is allowed to cool for a preset time, a control command is sent to the programmable reflow machine through the test PC so that the chip under test is in the target temperature environment;

[0053] S203 sends control instructions to the programmable tester through the test PC, the programmable tester supplies power to the chip under test, collects the clock frequency output by the chip under test, and forms chip test data in the programmable tester;

[0054] S204. After obtaining chip test data from the programmable tester through the test PC, the frequency offset rate of the chip test data is compared with the stored historical test data to form a temperature-frequency comparison curve of the TCXO clock chip.

[0055] The TCXO clock chip performance index testing method provided by the embodiment of the present invention realizes accurate quantitative evaluation of the impact of the reflow soldering process on the clock frequency through a closed-loop test system. First, the TCXO chip to be tested is placed on the dedicated pad of the chip soldering board, and precise temperature curve control is performed through a programmable reflow soldering machine: the system dynamically adjusts the temperature in the preheating zone, reflow zone, and cooling zone according to the preset SMT process parameters (such as automotive-grade 260°C peak temperature / 90 seconds dwell time), so that the chip experiences a thermal stress environment that is completely consistent with the actual patch. After the soldering is completed, it is left to stand for a preset cooling time (such as 5 minutes) to eliminate the interference of transient thermal effects on the crystal structure.

[0056] Next, the temperature-frequency characteristics test phase begins: the test PC issues a target temperature command (e.g., a temperature step scan from 25°C to 85°C) to the reflow soldering machine, subjecting the chip to a specific temperature environment. Simultaneously, the programmable tester provides a 3.3V operating voltage to the chip and configures internal registers via the SPI interface to activate the clock output. The FPGA array then activates its 500MHz high-speed acquisition channel, capturing the clock signal in real time at a resolution of 0.1ppm. This is then combined with the temperature sensor data to generate a raw frequency-temperature dataset.

[0057] Finally, the test PC automatically retrieves the stored historical frequency-temperature data of the same chip package test (FT) phase and finally generates the following Figure 3 The temperature-frequency comparison graph shown. Figure 3 The pattern track is used to intuitively present the differences before and after SMT. The dots represent the data after reflow soldering, and the grid points represent the historical data, realizing the visual traceability of process impact.

[0058] A third embodiment of the present invention provides a method for testing ADC / DAC chip performance indicators, which is based on the detection system for chip indicator changes after reflow soldering in the first embodiment and includes the following steps:

[0059] S301. Place the ADC / DAC chip as the chip to be tested on the chip soldering board and perform a reflow soldering operation on the chip to be tested;

[0060] S302. After the chip under test is allowed to cool for a preset time, a control command is sent to the programmable reflow machine through the test PC so that the chip under test is in the target temperature environment;

[0061] S303 sends control instructions to the programmable tester through the test PC, the programmable tester supplies power to the chip under test and sends test instructions, collects the analog voltage output by the chip under test, and forms chip test data in the programmable tester;

[0062] S304. After obtaining chip test data from the programmable test machine through the test PC, the linearity error and zero offset of the chip test data are compared with the stored historical test data to form a temperature-voltage comparison curve of the ADC / DAC chip.

[0063] The ADC / DAC chip performance index testing method provided by the embodiments of the present invention implements a quantitative evaluation of the analog conversion accuracy of the reflow soldering process through an integrated system. First, the ADC / DAC chip to be tested is placed on a dedicated pad on the chip soldering board. A programmable reflow soldering machine performs precise temperature curve control: the system dynamically adjusts the temperature in the preheating zone, reflow zone, and cooling zone according to preset SMT process parameters, subjecting the chip to a thermal stress environment identical to that of an actual chip. After soldering is completed, the chip is allowed to cool for a preset period of time (e.g., 3 minutes) to eliminate the effects of residual soldering stress on the internal thin-film resistor network.

[0064] During the chip testing phase, the test PC drives the programmable tester to perform three operations: 1) output the chip's operating voltage (e.g., 3.3V) through a programmable power pin; 2) configure the ADC and DAC internal registers using the IIC / SPI interface to set the sampling rate and range; and 3) send a sequence of digital input code values ​​to the DAC chip. The programmable tester captures the analog voltage output from the ADC / DAC and combines it with temperature control data to generate a raw temperature-voltage data set.

[0065] Finally, the test PC automatically retrieves the stored historical temperature-voltage data of the same chip package test (FT) phase and finally generates the following Figure 4 The temperature-voltage comparison graph is shown. Figure 3Different color trajectories are used to intuitively present the differences before and after SMT. The blue line represents the data after reflow soldering, and the orange line represents the historical data, realizing the visual traceability of process impact.

[0066] For other types of chips, this can also be achieved by pre-loading the corresponding chip test program into the programmable tester FPGA. For example, for high-density packaged chips (BGA, CSP), after the design is completed and preliminary samples are available, multiple rounds of reflow soldering are required before communication and functional testing to expose whether there are design flaws or chip malfunction caused by SMT. At this point, the testing process can be simplified, and the verification cycle can be further shortened due to the simple design of the chip soldering board. The external tester FPGA has a high degree of programmability and can be used with different board materials and verification environments with different temperature curves. It provides multiple test items such as communication verification, analog voltage measurement, frequency measurement, and more to improve test details.

[0067] On the other hand, for chips that experience functional abnormalities after reflow due to reduced internal circuit conductivity and / or process changes, such as reduced silver paste usage, longer bonding distances, or other inadequately addressed details, the present invention can collaborate with the chip fabrication department to conduct rapid SMT+functional verification and provide recommendations on usage and process changes.

[0068] The embodiments of the present invention can be applied to various signal analyses after evaluating chip SMT, for example:

[0069] 1. High-frequency chips, such as clock chips, experience stress in the internal crystals after SMT due to high and low temperature fluctuations during soldering, causing the output frequency to shift and requiring a specific amount of time to recover. The frequency measurement function of the FPGA in this invention can be used to test the chip's final frequency deviation.

[0070] 2. High-density packaged chips, such as BGA and CSP, face the risk of short circuits or cold solder joints after specific soldering curves due to different pad designs, leading to functional failure. In this case, the present invention can be used with PCBs of different materials and chip soldering boards with different pad packages to test the set functional items of the chip after surface mounting.

[0071] 3. Sensor chips, such as ADC / DAC chips, need to be evaluated for their ability to accurately detect or output signals after a specific welding profile. In this case, the system dynamically configures the ADC / DAC chip operating mode via the IIC / SPI interface, with the FPGA driving a precision voltage source to generate a ramp input signal and synchronously acquiring the output response.

[0072] In addition, the system of the present invention can also evaluate how long the static time is required to eliminate the impact of stress on the key parts of the chip after the SMT is completed, and output the reference value of the process requirements; and after evaluating the chip design, it can quickly verify the impact of the production and dosage of the process that is easily affected by SMT surface mounting on the function, etc., and has a wide range of applications.

[0073] In summary, the embodiment of the present invention greatly simplifies the chip performance index test process through a closed-loop system design. The operator only needs to place a certain number of chips to be tested in the test environment, set the test process and test indicators, and then an evaluation report on the parameter changes after SMT can be output. Whether it is used for reliability assessment before the product is put on the market, or for random inspection after mass production, it can reduce the possibility of chip defects after SMT due to adverse effects caused by process flow or material changes, or even production process control, etc., which can be achieved through the embodiment of the present invention.

[0074] Figure 5 Schematic diagram of the structure of the computer-readable storage medium of the fourth embodiment of the present invention. The computer-readable storage medium of the fourth embodiment of the present invention stores program instructions for testing the PC function in the detection system for the change of chip indicators after the above-mentioned reflow soldering surface mounting, wherein the program instructions can be stored in the above-mentioned storage medium in the form of a software product, including a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the methods of various embodiments of the present invention. The aforementioned computer-readable storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, or terminal devices such as a computer, a server, a mobile phone, and a tablet.

[0075] The contents of the system in the first embodiment of the present invention are all applicable to this computer-readable storage medium embodiment. The functions specifically implemented by this computer-readable storage medium embodiment are the same as those of the above-mentioned system embodiment, and the beneficial effects achieved are also the same as those achieved by the above-mentioned system.

[0076] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of the present invention are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0077] Those skilled in the art will appreciate that the modules in the devices in the embodiments of the present invention can be adaptively changed and set in one or more devices different from the embodiments. The modules or units or components in the embodiments of the present invention can be combined into one module or unit or component, and in addition they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, all features disclosed in this specification (including corresponding claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner can be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including corresponding claims, abstracts and drawings) can be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0078] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0079] In addition, each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. In particular, for embodiments such as devices and equipment, since they are basically similar to the method embodiments, the relevant parts can be referred to the partial description of the method embodiments. The embodiments of the devices and equipment described above are merely schematic, wherein the modules, units, etc. described as separate components may or may not be physically separated, that is, they may be located in one place, or they may be distributed to multiple places, such as nodes in a system network. Specifically, some or all of the modules and units may be selected according to actual needs to achieve the purpose of the above-mentioned embodiment scheme. Those skilled in the art can understand and implement it without paying any creative work.

[0080] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0081] In addition, the terms "first" and "second" used in the embodiments of the present invention are only used for descriptive purposes and should not be understood as indicating or implying relative importance, or implicitly indicating the number of technical features indicated in this embodiment. Therefore, the features defined by the terms "first" and "second" in the embodiments of the present invention can explicitly or implicitly indicate that the embodiment includes at least one of such features. In the description of the present invention, the word "plurality" means at least two or two or more, such as two, three, four, etc., unless otherwise clearly and specifically defined in the embodiments.

[0082] In the embodiments of the present invention, the terms "comprises", "includes" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or apparatus. In the absence of further restrictions, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or apparatus comprising the element. In addition, components, features, and elements with the same name in different embodiments of the present invention may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0083] Although embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention, and those of ordinary skill in the art may change, modify, replace, and modify the above embodiments within the scope of the present invention. Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the present invention. This application is intended to cover any variations, uses, or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art that are not disclosed in the present invention. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present invention are indicated by the claims below.

Claims

1. A system for detecting changes in chip indicators after reflow soldering, characterized in that: Including programmable reflow machine, programmable test machine and test PC; The programmable reflow soldering machine includes a chip soldering plate and a control console; the chip soldering plate is used to place the chip to be tested; the control console is used to receive control instructions to perform reflow soldering control; The programmable tester is used to perform an index test on the chip to be tested on the programmable reflow soldering machine according to the control instruction after the chip to be tested completes reflow soldering, thereby generating chip test data; The test PC is used to send control instructions to the programmable reflow machine and the programmable test machine to perform chip performance testing, and receive chip test data returned by the programmable test machine.

2. The method for detecting chip index changes after reflow soldering according to claim 1, characterized in that: The control instructions sent by the test PC to the programmable reflow soldering machine are used to control the temperature test environment of the chip to be tested; The control instruction sent by the test PC to the programmable test machine is used to instruct the programmable test machine to send a test signal corresponding to the chip index to the chip under test, and receive test data corresponding to the index returned by the chip under test.

3. The method for detecting chip index changes after reflow soldering according to claim 1, characterized in that: The programmable tester consists of an MCU chip and an FPGA array; the FPGA array stores multiple chip index test programs; the MCU chip is used to decode the control instructions sent by the test PC and call the target chip index test program stored in the FPGA array to perform index testing on the chip.

4. The system for detecting chip index changes after reflow soldering according to claim 3, characterized in that: The chip indicators include frequency accuracy indicator, temperature drift indicator, zero offset indicator, linearity indicator, gain error indicator and offset error indicator.

5. The system for detecting chip index changes after reflow soldering according to claim 1, characterized in that: The test PC stores historical test data of the same chip as the chip to be tested; the test data is also used to compare the chip test data of the chip to be tested with the historical test data to form a chip test result.

6. The system for detecting chip index changes after reflow soldering according to claim 1, characterized in that: A plurality of chips to be tested are placed on the chip welding board, and the programmable test machine includes a plurality of test paths, each of which is connected to a chip to be tested in the programmable reflow soldering machine to perform index tests on the chip to be tested.

7. The system for detecting chip index changes after reflow soldering according to claim 1, characterized in that: The test PC is a host computer, which is connected to the programmable test machine and the reflow soldering machine console via RS485 / RS422 bus.

8. A method for testing the performance index of a TCXO clock chip, implemented based on the detection system for chip index changes after reflow soldering according to any one of claims 1 to 7, characterized in that: The following steps are involved: Place the TCXO clock chip as the chip to be tested on the chip welding board and perform reflow soldering on the chip to be tested; After the chip under test is left to cool for a preset time, the test PC sends control instructions to the programmable reflow machine to keep the chip under test in the target temperature environment; The test PC sends control instructions to the programmable tester, which supplies power to the chip under test, collects the clock frequency output by the chip under test, and generates chip test data in the programmable tester. After the chip test data is obtained from the programmable test machine through the test PC, the frequency deviation rate of the chip test data is compared with the stored historical test data to form a temperature-frequency comparison curve of the TCXO clock chip.

9. A method for testing ADC / DAC chip performance indicators, implemented based on the detection system for chip indicator changes after reflow soldering according to any one of claims 1 to 7, characterized in that: The following steps are involved: Place the ADC / DAC chip as the chip to be tested on the chip soldering board and perform reflow soldering on the chip to be tested; After the chip under test is left to cool for a preset time, the test PC sends control instructions to the programmable reflow machine to keep the chip under test in the target temperature environment; The test PC sends control instructions to the programmable tester, which supplies power to the chip under test and sends test instructions, collects the analog voltage output by the chip under test, and forms chip test data in the programmable tester; After the chip test data is obtained from the programmable test machine through the test PC, the linearity error and zero offset of the chip test data are compared with the stored historical test data to form a temperature-voltage comparison curve of the ADC / DAC chip.

10. A computer-readable storage medium, characterized in that The storage medium stores a program, and the program is executed by the processor to implement the test PC function in the detection system for chip indicator changes after reflow soldering according to any one of claims 1 to 7.

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