Integrated circuit quality testing method and system

Abstract

The application relates to the technical field of integrated circuit quality testing, in particular to an integrated circuit quality testing method and system, which comprises the following steps: executing a preset test instruction set to perform electrical parameter testing on an integrated circuit chip; when any electrical parameter value of the chip deviates from a preset range, recording the initial electrical parameter measurement value when the electrical parameter deviates from the preset range, the identification of the test instruction sequence and the chip pin number where the abnormality occurs; repeatedly executing the test instruction sequence according to the recorded identification of the test instruction sequence and the chip pin number, and adjusting the test conditions to change the electrical margin of the chip when the test instruction sequence is repeatedly executed, so as to obtain secondary verification electrical parameter measurement values; through the introduction of the secondary verification and electrical margin adjustment mechanism, the false electrical parameter abnormality caused by signal coupling noise can be effectively distinguished from the real physical defects of the chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit quality testing, and in particular to an integrated circuit quality testing method and system. BACKGROUND

[0002] In the production and quality verification of integrated circuits, functional testing is an indispensable link. This test relies on a pre-determined test vector file, which specifies the input signals that the chip should receive at each timing node and the expected output results. This file is the core basis for verifying the correctness of the chip function, and its development and verification usually consumes a large amount of resources. Once put into use, it is considered as a stable and reliable test reference. In order to continuously reduce manufacturing costs and improve product competitiveness, enterprises often migrate mature mass-produced chips from the original process node to a more advanced process node. This process upgrade aims to achieve higher performance, lower power consumption and more optimal cost structure through smaller feature size, which is a common business strategy in the semiconductor industry.

[0003] However, process migration may bring about unintended physical effects. The reduction of circuit size and wire spacing in the new process leads to a significant increase in parasitic capacitance between adjacent signal lines, making it easier to induce signal coupling noise. For example, a level transition on a signal line may induce unintended voltage fluctuations on its adjacent signal lines, affecting signal integrity. If the test vectors developed based on the old process are continued to be used, the coupling noise problem may be exposed in the new process, and some specific signal combinations in the original test sequence may induce strong coupling noise, causing abnormal fluctuations in the otherwise stable signals. This noise is a manifestation of physical effects under specific logic excitation, rather than a chip design or functional defect.

[0004] In electrical parameter testing, coupling noise further erodes the parameter safety margin originally set based on the old process. Due to unavoidable minor differences in the manufacturing process, the noise impact on different chips is statistically distributed, resulting in some chips having measured parameters outside the original tolerance range.

[0005] As a result, a batch of chips that can normally work in actual application are misjudged as unqualified due to coupling noise leading to test parameter over-limit. This not only causes yield loss and economic loss, but also increases the difficulty of diagnosis as the problem cannot be classified as a clear hardware defect. This phenomenon has systematic and statistical characteristics, posing a continuous challenge to production quality and cost control.

[0006] The existing test method is insufficient in the face of signal integrity problems caused by process migration, and there is an urgent need for a test strategy that can identify and avoid misjudgment caused by coupling noise. SUMMARY

[0007] The application aims to solve the problems in the prior art and provides an integrated circuit quality testing method and system.

[0008] In a first aspect, the application provides an integrated circuit quality testing method, which comprises the following steps:

[0009] Performing a preset test instruction set to test the electrical parameters of the integrated circuit chip;

[0010] When detecting that any electrical parameter value of the chip deviates from a preset range, recording the initial electrical parameter measurement value when the electrical parameter deviates from the preset range, the identification of the test instruction sequence, and the chip pin number where the abnormality occurs;

[0011] Repeating the execution of the test instruction sequence according to the recorded identification of the test instruction sequence and the chip pin number, and adjusting the test conditions to change the electrical margin of the chip when repeating the execution of the test instruction sequence to obtain secondary verification electrical parameter measurement values;

[0012] According to the relationship between the initial electrical parameter measurement value and the secondary verification electrical parameter measurement value, determining whether the electrical parameter abnormality is caused by signal coupling noise or by a real physical defect of the chip to obtain a determination result;

[0013] According to the determination result, performing classification processing on the chip.

[0014] In a second aspect, an integrated circuit quality testing system is provided, which comprises:

[0015] An initial test module for performing a preset test instruction set to test the electrical parameters of the integrated circuit chip, and when detecting that any electrical parameter value of the chip deviates from a preset range, not immediately determining that the chip is unqualified, and recording the initial electrical parameter measurement value when the electrical parameter deviates from the preset range, the identification of the test instruction sequence, and the chip pin number where the abnormality occurs;

[0016] A repeating execution module for repeating the execution of the test instruction sequence according to the recorded identification of the test instruction sequence and the chip pin number;

[0017] A condition adjustment module for adjusting the test conditions to change the electrical margin of the chip when repeating the execution of the test instruction sequence;

[0018] A secondary measurement module for measuring the electrical parameters of the chip again under the adjusted test conditions to obtain secondary verification electrical parameter measurement values;

[0019] a judging module, configured to judge whether the electrical parameter abnormality is caused by signal coupling noise or by a real physical defect of the chip according to a relationship between the initial electrical parameter measurement value and the secondary verification electrical parameter measurement value, to obtain a judging result;

[0020] a classification processing module, configured to perform classification processing on the chip according to the judging result.

[0021] Compared with the prior art, the present application has the following beneficial effects:

[0022] By introducing the secondary verification and electrical margin adjustment mechanism, the false electrical parameter abnormality caused by signal coupling noise can be effectively distinguished from the real physical defect of the chip. Specifically, when the electrical parameter of the chip appears abnormal, the method does not immediately determine it as a defective product, but records the relevant information, and repeatedly executes the test instruction sequence and adjusts the test conditions to change the electrical margin of the chip, so as to obtain the secondary verification electrical parameter measurement value. By comparing the relationship between the initial measurement value and the secondary verification measurement value, the root cause of the abnormality can be accurately judged. This innovative method overcomes the problem that a large number of functional chips are misjudged as defective products due to signal coupling noise caused by process migration in the prior art, significantly improves the accuracy of the test and the production yield, and avoids unnecessary production loss and diagnosis trouble. Accordingly, the present application can effectively solve the problems of yield reduction and difficult troubleshooting in the prior art, and provides a more reliable solution for quality control of integrated circuits. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The method flowchart of the present application.

[0024] Figure 2 The system structure schematic diagram of the present application.

[0025] In the figure: 201, initial test module; 202, repeated execution module; 203, condition adjustment module; 204, secondary measurement module; 205, judging module; 206, classification processing module. DETAILED DESCRIPTION

[0026] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as a limitation of the present application.

[0027] The terms "first", "second", "third", etc. are used only for descriptive purposes and are not to be construed as indicating or implying relative importance or an ordered ranking of the indicated technical features. Thus, features defined with "first", "second" or "third" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly specified otherwise.

[0028] In the production and quality verification of integrated circuits, functional testing is an indispensable part, which relies on a set of predetermined test instruction sets that specify the input signals that the chip should receive at a specific time and the output results that the chip should produce. However, with the continuous advancement of semiconductor manufacturing technology, chip design often moves from mature production processes to more advanced and precise process nodes. This upgrade in process, although aimed at improving performance and reducing costs, can have unexpected effects at the physical level. Specifically, smaller circuit sizes and closer wire spacings under new processes can make it easier for adjacent signal lines to interact with each other, resulting in a phenomenon known as "signal coupling noise". When the test instruction set designed for the old process is used, some specific signal combinations may induce significant signal coupling noise under the new process, causing abnormal fluctuations in the electrical parameters of the chip during testing. This anomaly is not a real defect of the chip itself, but a false problem caused by the interaction of the test instruction with the physical characteristics of the new process, which often leads to the false determination of good chips as defective products, resulting in unnecessary production losses and diagnostic difficulties.

[0029] To this end, the present application provides an integrated circuit quality testing method as shown in Figure 1 The method comprises the following steps:

[0030] S101, performing a preset test instruction set to test the electrical parameters of the integrated circuit chip;

[0031] This step can be completed by loading the pre-designed test instruction sequence into an automatic test equipment (ATE) and applying excitation signals to the chip under test by the ATE while measuring the response signals of the chip. For example, the test instruction set can include a series of test vectors for verifying the functions of chip logic gates, memory cells, or interface circuits. During testing, the ATE will monitor various electrical parameters of the chip in real time, such as output voltage, input current, propagation delay, etc., and compare them with the preset acceptable range.

[0032] S102, when any electrical parameter value of the chip deviates from the preset range, recording the initial electrical parameter measurement value when the electrical parameter deviates from the preset range, the identification of the test instruction sequence, and the pin number of the chip where the anomaly occurs;

[0033] When the ATE detects that a certain electrical parameter value exceeds its preset upper limit or lower limit, the system does not immediately determine that the chip is unqualified. On the contrary, the system accurately records the specific electrical parameter measurement value at the time of this anomaly, which is the initial electrical parameter measurement value. At the same time, in order to subsequent trace and analysis, the system also records the unique identification of the test instruction sequence that caused the anomaly, and the specific number of the chip pin where the anomaly occurred. For example, if the output voltage of a certain output pin of the chip is lower than the preset minimum qualified voltage when executing a specific test instruction sequence, the output voltage value, the identification of the test instruction sequence and the number of the output pin will be recorded.

[0034] S103, for the recorded identification of the test instruction sequence and the chip pin number, repeat executing the test instruction sequence, and adjust the test conditions to change the electrical margin of the chip when repeating the test instruction sequence to measure the secondary verification electrical parameter measurement value;

[0035] After recording the initial abnormal information, the test system will specifically and repeatedly execute the test instruction sequence that caused the anomaly. In the process of repeating the sequence, the test conditions will be adjusted purposefully to change the electrical margin of the chip. For example, the electrical margin can be changed by slightly raising or lowering the test voltage, or changing the frequency of the test signal, or adjusting the test environment temperature, etc. Under these adjusted test conditions, the electrical parameters of the chip will be measured again to obtain the secondary verification electrical parameter measurement value. For example, if the initial anomaly is due to the low output voltage, then in the secondary verification, the output voltage can be measured again under the condition of slightly increasing the supply voltage.

[0036] S104, according to the relationship between the initial electrical parameter measurement value and the secondary verification electrical parameter measurement value, determine whether the electrical parameter anomaly is caused by signal coupling noise or by real physical defects of the chip to obtain a judgment result;

[0037] After obtaining the initial electrical parameter measurement and the secondary verification electrical parameter measurement, the system analyzes the relationship between the two. If the abnormality of the electrical parameter is caused by signal coupling noise, the influence of the noise can be weakened or strengthened by adjusting the test conditions (e.g., changing the electrical margin), resulting in a significant change trend between the secondary verification electrical parameter measurement and the initial value. For example, if increasing the supply voltage can restore the low output voltage to the normal range, it is likely that the abnormality is caused by signal coupling noise. Conversely, if the abnormality of the electrical parameter is caused by the real physical defects of the chip (such as short circuit, open circuit, transistor failure, etc.), the influence of the defect usually does not change significantly even if the test conditions are adjusted, and the secondary verification electrical parameter measurement and the initial value can change little or remain abnormal. Through this comparison and analysis, the system can distinguish the root cause of the abnormality, thereby obtaining a clear judgment result.

[0038] S105, according to the judgment result, the chip is classified.

[0039] Based on the above judgment result, the chip will be subjected to corresponding classification processing. If the judgment result shows that the abnormality is caused by signal coupling noise and the chip itself is functional, the chip can be judged as a qualified product or a qualified product of a specific level, thereby avoiding unnecessary scrapping. If the judgment result shows that the abnormality is caused by the real physical defects of the chip, the chip will be judged as a unqualified product and can be sent to the failure analysis department for further diagnosis to find out the specific defect type and location. This classification processing mechanism ensures the accuracy of the test result and improves the production yield.

[0040] The integrated circuit quality test method of the present application can effectively distinguish whether the abnormal electrical parameter in the integrated circuit test is caused by signal coupling noise or real physical defects by introducing an innovative secondary verification mechanism. In the traditional existing test method, when the electrical parameter deviates from the preset range, the chip is often directly judged as unqualified, which leads to a large number of chips with good functions but affected by signal coupling noise being misjudged and scrapped, causing significant production loss. The present application does not immediately judge the chip as unqualified after detecting the abnormality, but records the initial abnormal information and repeatedly executes the test instruction sequence, while adjusting the test conditions to change the electrical margin of the chip, so as to obtain the secondary verification electrical parameter measurement value. By comparing the relationship between the initial measurement value and the secondary verification measurement value, the present application can accurately judge the root cause of the abnormality. For example, if the abnormality can be alleviated or eliminated by adjusting the electrical margin, it is likely caused by signal coupling noise; otherwise, if the abnormality persists, it is more likely a real physical defect. This method avoids the misjudgment caused by signal coupling noise in the traditional test, significantly improves the accuracy of the test and the production yield, and provides a more delicate and efficient solution for the quality control of integrated circuits.

[0041] As an embodiment of the present application, when the chip is classified as unqualified, the method further comprises the following steps:

[0042] adjusting the test conditions to a preset limit margin state to change the electrical margin of the chip;

[0043] measuring the electrical parameter of the chip again under the adjusted test conditions to obtain a limit recovery value;

[0044] The limit recovery value refers to the electrical parameter value measured under the limit margin state, which can more truly reflect the performance of the chip under extreme conditions, and is helpful to strip noise interference and reveal the physical properties of the chip itself.

[0045] Further, according to the initial electrical parameter measurement value, the limit recovery value and the ideal design specification value of the chip, the residual deviation and the noise deviation of the chip are calculated;

[0046] The initial electrical parameter measurement value is the measurement value when the abnormality is first detected under the normal test conditions; the limit recovery value is the electrical parameter value measured under the limit margin state; and the ideal design specification value is the standard value of the electrical parameter that the chip should reach under the ideal working state. The residual deviation can be understood as the inherent deviation between the electrical parameter of the chip after excluding the noise influence and the ideal design specification value, mainly reflecting the degree of physical defects of the chip. The noise deviation can be understood as the deviation of the electrical parameter caused by signal coupling noise or other environmental factors, which reflects the sensitivity of the chip to noise or the performance fluctuation under non-ideal conditions.

[0047] Thus, according to the residual deviation and the noise deviation, the failure component of the chip is quantitatively judged;

[0048] Quantitative judgment refers to evaluating the proportion or severity of physical defects and noise effects in chip failure through numerical methods. For example, different thresholds or judgment rules can be set to divide the failure components of the chip into categories such as "mainly caused by physical defects", "mainly caused by noise", "physical defects and noise jointly acting", etc.

[0049] Finally, according to the quantitative judgment result, the chip is processed by fine classification.

[0050] Fine classification processing refers to further subdividing the unqualified chip into different subcategories according to the quantitative judgment result of the failure component, such as "hard failure (physical defect is serious)", "soft failure (noise sensitive)", "edge failure (physical defect is slight but easy to be affected by noise)", etc. This fine classification helps to provide more accurate basis for subsequent chip disposal (such as scrapping, downgrading, repair or further analysis).

[0051] Specifically, when the chip is initially judged as unqualified, the basic scheme can only provide a macroscopic judgment result. However, by adjusting the test condition to the limit margin state, the electrical margin of the chip changes, so that the inherent physical defects of the chip can be more thoroughly exposed, and the influence of noise can be weakened or amplified. Thus, the limit recovery value obtained under the limit margin state, combined with the initial electrical parameter measurement value and the ideal design specification value, can accurately separate the residual deviation and the noise deviation of the chip. The residual deviation directly reflects the degree of physical defects of the chip itself, while the noise deviation quantifies the influence of external interference on the performance of the chip. It is through this quantitative analysis of the failure component that the present scheme can reveal the root cause of chip failure in depth, so as to realize more accurate quantitative judgment of the failure component of the unqualified chip, and on this basis, fine classification processing.

[0052] By the technical solution, the fine level of integrated circuit quality testing can be improved. Compared with only preliminary judgment of noise or physical defects, the scheme introduces limit margin testing and quantitative calculation of residual deviation and noise deviation, so that the failure cause analysis of unqualified chip is more in-depth and accurate. This not only helps to more accurately identify the real physical defect degree and noise sensitivity of the chip, but also provides more instructive data for defect tracing and process optimization in the production process. In addition, through quantitative judgment and fine classification processing of the failure components, differential treatment of different types of unqualified chips can be realized. For example, for "soft failure" chips mainly caused by noise, they can be restored by adjusting the system environment or software parameters; and for "hard failure" chips, they can be directly scrapped or repaired, thereby effectively reducing the misjudgment rate, improving resource utilization efficiency, and ultimately improving the overall production yield and product quality.

[0053] As an embodiment of the present application, the step of quantitatively judging the failure components of the chip according to the residual deviation and the noise deviation includes:

[0054] First, the residual deviation and noise deviation data of the reference sample of the current batch of chips are obtained;

[0055] The reference sample can be a part of chips randomly selected from the same production batch, or chip data with known quality status (for example, qualified products, unqualified products with specific failure modes) accumulated in the production process. The residual deviation and noise deviation data are calculated according to the above method, and are used to represent the deviation of the electrical parameters of the chip from the ideal design specification value and the degree of influence by noise.

[0056] Second, the residual deviation and noise deviation data of the reference sample are statistically analyzed;

[0057] The statistical analysis can include calculating statistical quantities such as mean, standard deviation, median, percentile, and performing distribution fitting (for example, normal distribution, Weibull distribution, etc.) or cluster analysis. Through statistical analysis of a large amount of reference sample data, the distribution characteristics and rules of residual deviation and noise deviation in chips of different quality states can be revealed, thereby providing data support for subsequent quantitative judgment.

[0058] Further, according to the statistical analysis result, a threshold for quantitative judgment is determined;

[0059] The threshold value is a boundary value for distinguishing different failure components or different quality levels. For example, the threshold value can be set according to a certain percentile (such as a 95% or 99% percentile) of a statistical distribution, or determined according to a multiple of a standard deviation. These threshold values are intended to divide the residual deviation and noise deviation of the chip into different regions, each corresponding to a quantitative judgment result of one or more failure components.

[0060] Finally, using the determined threshold value, the failure components of the chip are quantitatively judged according to the residual deviation and the noise deviation.

[0061] Specifically, the residual deviation and the noise deviation of the chip to be tested are compared with the preset threshold value. According to the region it falls into, it can be judged whether the abnormality of the electrical parameter of the chip is mainly caused by a real physical defect (corresponding to a larger residual deviation), or by signal coupling noise (corresponding to a larger noise deviation), or both, and the failure components are quantitatively evaluated.

[0062] The scheme of the present application can establish a set of objective, data-driven quantitative judgment criteria by introducing statistical analysis of reference samples. Through in-depth statistical analysis of residual deviation and noise deviation data, the internal characteristics of different failure modes can be more accurately captured, and more representative and discriminative judgment threshold values can be determined. Thus, when quantitatively judging the failure components of the chip, subjective speculation can be avoided, and the accuracy and reliability of the judgment can be improved.

[0063] Through the above technical scheme, fine quantitative judgment of the failure components of the integrated circuit chip can be realized. Compared with the method of relying only on a single measurement value or a simple threshold value, the present scheme can more clearly identify whether the chip abnormality is dominated by a physical defect or noise interference by combining the statistical characteristics of the residual deviation and the noise deviation, thereby providing a more accurate basis for subsequent fine classification processing and failure analysis. This helps to optimize the production process, improve product yield, and effectively reduce resource waste caused by misjudgment.

[0064] As an embodiment of the present application, the steps of calculating the residual deviation and the noise deviation of the chip according to the initial electrical parameter measurement value, the limit recovery value and the ideal design specification value of the chip include:

[0065] When the electrical parameter value deviating from the preset range involves multiple electrical parameter types or multiple chip pins, the residual deviation and the noise deviation of each abnormal electrical parameter are calculated according to the initial electrical parameter measurement value, the limit recovery value and the ideal design specification value of the chip, respectively, for the abnormalities of multiple electrical parameter types or multiple chip pins.

[0066] Specifically, when the electrical parameter values deviating from the preset range involve multiple electrical parameter types or multiple chip pins, it means that during the electrical parameter testing of the integrated circuit chip, the abnormal electrical parameters of the chip are not single, but deviate from the preset qualified range at the same time in multiple different electrical parameter types (for example, voltage, current, frequency, timing, etc.) or in multiple different pins of the chip. For the abnormalities of multiple electrical parameter types or multiple chip pins, the residual deviation and noise deviation of each abnormal electrical parameter are calculated according to the initial electrical parameter measurement value, the limit recovery value and the ideal design specification value of the chip, which means that for each detected abnormal electrical parameter, whether it belongs to different electrical parameter types or is located in different chip pins, the residual deviation and noise deviation are calculated independently. The initial electrical parameter measurement value refers to the measurement value when the electrical parameter abnormality is first detected; the limit recovery value is the value obtained by measuring the electrical parameter again after adjusting the test conditions to the preset limit margin state; and the ideal design specification value of the chip is the ideal or target value of the electrical parameter specified during the design of the chip. These values are used to calculate the residual deviation and noise deviation of each individual abnormality.

[0067] Further, according to the type of each abnormal electrical parameter or the preset influence factor of its corresponding chip pin, the residual deviation and noise deviation of each electrical parameter value deviating from the preset range are assigned weights;

[0068] In practical applications, the influence of different types of electrical parameters or different chip pin abnormalities on the overall function, performance and reliability of the integrated circuit chip may differ significantly. For example, voltage abnormality of a power pin may have a global impact on the entire chip, while a slight signal delay abnormality of a non-critical data pin may only affect local functions. Therefore, a "influence factor" can be preset, which reflects the importance of a specific electrical parameter type or chip pin, or the severity of its abnormality. These preset influence factors are used as weights and assigned to each individually calculated residual deviation and noise deviation to reflect their relative importance in overall evaluation.

[0069] Thus, the weighted residual deviation and noise deviation assigned with weights are aggregated to obtain the comprehensive residual deviation and comprehensive noise deviation of the chip.

[0070] After assigning the corresponding weights to each individual residual deviation and noise deviation, these discrete deviation values with different importance weights are combined into a "comprehensive residual deviation" and a "comprehensive noise deviation" representing the overall state of the chip by weighted averaging or other appropriate weighted aggregation methods. This aggregation method can more comprehensively and accurately reflect the real physical defect components and signal coupling noise components of the chip under multiple abnormal conditions.

[0071] The scheme of the present application can more accurately evaluate the failure components of the integrated circuit chip by fine processing of the electrical parameters under multiple abnormal conditions. The traditional method may not effectively distinguish the importance of different abnormalities or simply treat all abnormalities equally when facing multiple electrical parameters or multiple pins with abnormality, resulting in inaccurate judgment of the real physical defects and signal coupling noise of the chip. The present scheme ensures in-depth analysis of each specific abnormality by "calculating the residual deviation and noise deviation of each abnormal electrical parameter respectively". At the same time, the step of "allocating weights according to the preset influence factor" enables different importance of abnormalities to be treated differently, for example, the abnormality of a key parameter or pin that has a greater impact on the function of the chip will be given a higher weight, so as to occupy a more important position in the final comprehensive deviation. Finally, "weighting and aggregating the deviation with allocated weights" integrates these discrete deviations with different importance weights to form a comprehensive index that can fully reflect the overall quality of the chip. This enables the quantitative judgment of the failure components of the chip to be based on a more representative and accurate data, thereby avoiding the problem of misjudgment or insufficient evaluation caused by multiple abnormalities.

[0072] Through the above technical scheme, the present application can effectively solve the problem of inaccurate evaluation caused by traditional single or simple cumulative calculation method when multiple or multiple types of electrical parameters of the integrated circuit chip are abnormal. The scheme calculates each abnormality independently and allocates weights according to its importance, and finally aggregates into a comprehensive deviation, so that the quantitative judgment of the residual deviation (real physical defect) and noise deviation (signal coupling noise) of the chip is more accurate and comprehensive. Thus, the root cause of chip failure can be more accurately identified, the accuracy and efficiency of chip classification processing can be improved, especially in complex failure modes, accidental abnormalities caused by noise can be avoided from being misjudged as physical defects, or vice versa, thereby optimizing the quality control and yield management of integrated circuits and improving product reliability.

[0073] As an embodiment of the present application, the step of determining the threshold value for quantitative judgment according to the statistical analysis result includes:

[0074] In the production process, the residual deviation and noise deviation data of the chips are continuously monitored; specifically, in the entire production cycle of the integrated circuit chips, after the residual deviation and noise deviation of each batch or each individual chip are calculated, the data are collected and stored in real time or quasi-real time. These data can include residual deviation values, noise deviation values, test times, batch information, production line information, etc., for subsequent statistical analysis. Among them, the residual deviation refers to the inherent deviation between the actual electrical parameters of the chip and the ideal design specification value, while the noise deviation reflects the fluctuation of the electrical parameters caused by signal coupling noise and other non-physical defect factors.

[0075] The residual deviation and noise deviation data are periodically or when a change in chip batch characteristics is detected, and statistical analysis is performed to obtain updated statistical analysis results; specifically, the collected residual deviation and noise deviation data are periodically (e.g., daily, weekly, or at the end of each batch) or statistically processed when a specific event triggers (e.g., when the production line is adjusted, the raw materials are replaced, or the quality control chart shows an abnormal trend). Statistical analysis can include calculating the mean, median, standard deviation, percentile, distribution shape, etc., to fully understand the distribution characteristics of the residual deviation and noise deviation of the chips under the current production state. Thus, the latest statistical analysis results reflecting the current production status can be obtained.

[0076] According to the updated statistical analysis results, the threshold value for quantitative judgment is determined; specifically, the latest statistical analysis results are used to recalculate or adjust the judgment threshold for distinguishing the failure components of the chips (e.g., distinguishing physical defects and noise effects). For example, a new control limit can be set according to the updated mean and standard deviation, or the pass / fail limit can be determined according to a specific percentile. In this way, the threshold value for quantitative judgment can dynamically adapt to the actual changes in the production process, thereby improving the accuracy and robustness of the judgment.

[0077] The scheme of the present application effectively solves the problem that the threshold value cannot adapt to the changes in the production process due to the fixed threshold value in the traditional method. When the production batch characteristics drift, for example, due to equipment wear, process parameter fluctuations, or raw material batch differences, the distribution of the residual deviation and noise deviation of the chips may change. Through periodic or event-driven statistical analysis, these changes can be captured in time, and the judgment threshold is updated accordingly, so that the threshold value can always accurately reflect the characteristics of the chips under the current production state. Thus, the quantitative judgment of the failure components of the chips is always based on the latest and most accurate data, thereby improving the accuracy of the judgment.

[0078] By the technical solution, the accuracy and reliability of the failure component quantification judgment in the integrated circuit chip quality test can be significantly improved. Since the threshold value can dynamically adapt to the batch characteristic changes in the production process, the failure caused by the real physical defects and the abnormality caused by the signal coupling noise can be more accurately identified, and misjudgment or omission is avoided. This not only helps to more effectively perform fine classification processing of the chips, for example, sending the physical defect chips to failure analysis, performing specific optimization or degraded use of the noise sensitive chips, but also provides more accurate feedback for improvement of the production process, thereby improving the overall production quality and efficiency.

[0079] As an embodiment of the present application, according to the updated statistical analysis result, the step of determining the threshold value for quantification judgment comprises:

[0080] According to the updated statistical analysis result, the specific percentile or standard deviation multiple of the statistical distribution of the residual deviation and the noise deviation is calculated; specifically, after statistical analysis of the residual deviation and the noise deviation data, statistical methods can be used to quantify the distribution characteristics. Specifically, the specific percentile can be, for example, the 95th percentile, the 99th percentile, etc., which can reflect the position of a certain percentage of data points in the data set. For example, the 99th percentile indicates that 99% of the data points are less than or equal to the value. The standard deviation multiple can be, for example, one, two or three standard deviations from the mean, etc., which is commonly used for normally distributed data to define the degree of deviation of data points from the mean. By calculating these statistics, data-driven boundaries can be provided for subsequent quantification judgment.

[0081] According to the specific percentile or standard deviation multiple, the threshold value for quantification judgment is determined; specifically, the specific percentile or standard deviation multiple calculated above is directly or after appropriate adjustment as the judgment threshold for distinguishing the failure components of the chips. For example, the 99th percentile of the residual deviation can be set as the threshold value for judging whether the chip has a real physical defect, or the mean value plus or minus two standard deviations of the noise deviation can be set as the threshold value for judging whether the chip has signal coupling noise. This threshold value determination method based on the statistical distribution characteristics can make the judgment threshold more objective and adaptive.

[0082] The scheme of the present application calculates the specific percentile or standard deviation multiple of the statistical distribution of the residual deviation and the noise deviation according to the updated statistical analysis result, and determines the threshold value for quantification judgment based thereon, so that the setting of the threshold value is no longer a fixed empirical value, but can be dynamically adjusted according to the characteristic changes of the chip batches in the actual production process. This method can more accurately capture the actual distribution of the residual deviation and the noise deviation, thereby providing more accurate basis for subsequent failure component quantification judgment.

[0083] By the technical solution, the threshold value for quantitative judgment can reflect the actual quality distribution of the current batch of chips in real time, thereby improving the accuracy and reliability of the chip failure component judgment. This helps to more effectively identify abnormalities caused by signal coupling noise and abnormalities caused by real physical defects of the chip, thereby realizing more refined chip classification processing, avoiding misjudgment, and improving overall test efficiency and product quality.

[0084] As an embodiment of the present application, the step of detecting that the chip batch characteristics change includes:

[0085] statistical process control analysis is performed on the residual deviation and noise deviation data;

[0086] According to the statistical process control analysis result, when the residual deviation and noise deviation data exceed the preset statistical control limit or present a preset trend, it is judged that the chip batch characteristics change.

[0087] The statistical process control analysis refers to monitoring and analyzing the production process through statistical methods to identify abnormal variations in the process. The purpose is to ensure the stability and consistency of product quality. The statistical control limit is the upper and lower limit determined according to historical data or theoretical models, which is used to judge whether the process is in a statistical controlled state. The preset trend can be understood as the data points showing a non-random specific pattern on the control chart, such as a continuous upward or downward trend, a continuous multi-point on one side of the center line, etc. These trends usually indicate that the process may have systematic problems or is about to be out of control.

[0088] The scheme of the present application can monitor the quality characteristics of the chip batch in real time or quasi-real time by performing statistical process control analysis on the residual deviation and noise deviation data. When these key deviation data exceed the preset statistical control limit or present a specific preset trend, it indicates that the production process of the chip batch may have non-random, systematic changes, such as raw material batch differences, production equipment wear, process parameter drift, etc. Therefore, statistical analysis of the residual deviation and noise deviation data can be updated in time, thereby ensuring that the threshold value used for quantitative judgment can accurately reflect the real quality distribution of the current batch, avoiding misjudgment caused by using outdated or inaccurate threshold values.

[0089] By the technical solution, sensitive and accurate detection of integrated circuit chip batch characteristic changes can be achieved. This helps to timely discover abnormalities in the production process and avoid the flow of products with potential defects or quality fluctuations into subsequent links, thereby improving the timeliness and effectiveness of product quality control. In addition, by dynamically adjusting the threshold value, the natural fluctuations in the production process and the differences between batches can be better adapted, making the quantitative judgment of failure components more accurate, and ultimately improving the overall reliability and efficiency of integrated circuit quality testing.

[0090] As an embodiment of the present application, the step of performing statistical process control analysis on the residual deviation and noise deviation data comprises:

[0091] performing statistical process control analysis on the residual deviation and noise deviation data using X-bar and R control charts or I-MR control charts.

[0092] Among them, X-bar control chart and R control chart are two commonly used control charts in statistical process control. X-bar control chart is mainly used to monitor the change of process mean, while R control chart is used to monitor the change of process variability. When residual deviation and noise deviation data can be reasonably grouped, for example, a fixed number of chips are extracted for measurement in each test batch, these control charts can effectively reveal whether the process is in a state of statistical control. I-MR control chart, i.e. individual value and moving range control chart, is suitable for cases where reasonable grouping cannot be performed or each sample has only one observation value, for example, continuous monitoring of residual deviation and noise deviation of a single chip. By drawing these control charts, the trend of residual deviation and noise deviation data over time can be observed intuitively, as well as whether there are abnormal points that exceed the control limit or show non-random patterns.

[0093] The scheme of the present application can present residual deviation and noise deviation data in a graphical manner by using X-bar and R control charts or I-MR control charts, and real-time monitoring in combination with preset statistical control limits. When the data points exceed the control limits, it indicates that the process may have abnormalities; when the data points show a specific non-random pattern (such as continuous rising or falling trend, periodic fluctuation, etc.), it also indicates that the process may change. Thus, whether the characteristics of the chip batch have deviated or abnormal can be found in time, thereby providing accurate judgment basis for subsequent fine classification processing.

[0094] As an embodiment of the present application, the step of quantitatively judging the failure components of the chip according to the residual deviation and noise deviation comprises:

[0095] comparing the residual deviation and noise deviation with a plurality of preset judgment thresholds;

[0096] quantitatively judging the failure components of the chip according to the comparison result.

[0097] The preset multiple judgment thresholds can be determined according to historical test data, chip design specifications, known failure mode analysis results, or statistical process control (SPC) analysis results. These thresholds can be set as boundaries to distinguish different failure levels or failure types. For example, a first set of thresholds can be set to distinguish slight electrical parameter deviations, a second set of thresholds can be set to distinguish moderate deviations, and a third set of thresholds can be set to distinguish severe electrical parameter deviations. The residual deviation and the noise deviation can be compared with the respective threshold set respectively, or combined to compare with a multi-dimensional threshold space. Through such comparison, a quantitative judgment result can be obtained, which can indicate the degree of chip failure or the type of main failure component. For example, when the residual deviation exceeds a certain threshold and the noise deviation does not exceed, it can indicate a physical defect dominant failure; on the contrary, it can indicate a signal coupling noise dominant failure; if both exceed different thresholds, it can indicate a mixed failure of physical defect and signal coupling noise.

[0098] The scheme of the present application can make more fine and quantitative judgments on the failure components of the chip by comparing the residual deviation and the noise deviation with the preset multiple judgment thresholds. Traditional failure judgment can be limited to binary classification of qualified and unqualified, or rough distinction between physical defects and noise effects. However, by introducing multiple judgment thresholds, the failure components can be divided into different levels or categories according to the degree and type of deviation. For example, according to the numerical range of the residual deviation and the noise deviation, the failure components of the chip can be subdivided into slight physical defects, severe physical defects, slight noise sensitivity, severe noise sensitivity, and physical defect and noise coupling. Such multi-threshold comparison mechanism makes the judgment of failure components no longer a simple "yes" or "no", but can provide more rich failure information, thereby providing more accurate basis for subsequent fine classification processing.

[0099] As shown in a kind of integrated circuit quality test system shown in Figure 2 System includes:

[0100] Initial test module 201, for executing preset test instruction set, carries out electrical parameter test to integrated circuit chip, when detecting that any electrical parameter value of chip deviates from preset range, not immediately determine that chip is unqualified product, and record initial electrical parameter measured value when electrical parameter deviates from preset range, the identification of test instruction sequence and the pin number of chip that occurs abnormality;

[0101] Repeated execution module 202, for the identification of test instruction sequence recorded and chip pin number, repeatedly executes test instruction sequence;

[0102] The conditional adjustment module 203 is configured to adjust the test condition to change the electrical margin of the chip when repeatedly executing the test instruction sequence.

[0103] The secondary measurement module 204 is configured to measure the electrical parameter of the chip again under the adjusted test condition to obtain a secondary verification electrical parameter measurement value.

[0104] The judgment module 205 is configured to judge whether the electrical parameter abnormality is caused by the signal coupling noise or the real physical defect of the chip according to the relationship between the initial electrical parameter measurement value and the secondary verification electrical parameter measurement value to obtain a judgment result.

[0105] The classification processing module 206 is configured to perform classification processing on the chip according to the judgment result.

[0106] The basic principle, main features and advantages of the present application are shown and described above. It should be understood by those skilled in the art that the present application is not limited to the above-mentioned embodiments, and the above-mentioned embodiments and descriptions in the specification are only the principles of the present application. Without departing from the spirit and scope of the present application, various changes and improvements can be made to the present application, and these changes and improvements all fall within the scope of the claimed present application.

Claims

1. An integrated circuit quality test method, characterized by, The method comprises the following steps: performing a preset test instruction set to test the electrical parameters of the integrated circuit chip; when any electrical parameter value of the chip deviates from the preset range, recording the initial electrical parameter measurement value when the electrical parameter deviates from the preset range, the identification of the test instruction sequence, and the pin number of the chip where the anomaly occurs; for the recorded identification of the test instruction sequence and the pin number of the chip, repeating the execution of the test instruction sequence, and adjusting the test conditions to change the electrical margin of the chip when repeating the execution of the test instruction sequence to measure the secondary verification electrical parameter measurement value; determining whether the electrical parameter anomaly is caused by signal coupling noise or by a real physical defect of the chip according to the relationship between the initial electrical parameter measurement value and the secondary verification electrical parameter measurement value to obtain a determination result; according to the determination result, classifying the chip; when the chip is classified as a non-conforming product, the method further comprises the following steps: adjusting the test conditions to a preset limit margin state to change the electrical margin of the chip; measuring the electrical parameters of the chip again under the adjusted test conditions to obtain a limit recovery value; calculating the residual deviation and noise deviation of the chip according to the initial electrical parameter measurement value, the limit recovery value, and the ideal design specification value of the chip; quantitatively judging the failure components of the chip according to the residual deviation and the noise deviation; according to the quantitative judgment result, performing fine classification processing on the chip.

2. The integrated circuit quality test method of claim 1, wherein, The step of quantitatively judging the failure components of the chip according to the residual deviation and the noise deviation comprises: obtaining the residual deviation and noise deviation data of the reference sample of the current batch of chips; statistically analyzing the residual deviation and noise deviation data of the reference sample; determining the threshold value for the quantitative judgment according to the statistical analysis result; using the determined threshold value, quantitatively judging the failure components of the chip according to the residual deviation and the noise deviation.

3. The integrated circuit quality test method of claim 1, wherein, The step of calculating the residual deviation and noise deviation of the chip according to the initial electrical parameter measurement value, the limit recovery value, and the ideal design specification value of the chip comprises: when the electrical parameter value deviating from the preset range involves multiple electrical parameter types or multiple chip pins, for the anomalies of the multiple electrical parameter types or multiple chip pins, respectively calculating the residual deviation and noise deviation of each abnormal electrical parameter according to the initial electrical parameter measurement value, the limit recovery value, and the ideal design specification value of the chip; according to the type of each abnormal electrical parameter or the preset influence factor of its corresponding chip pin, assigning weights to the residual deviation and noise deviation of each electrical parameter value deviating from the preset range; weighting and aggregating the residual deviation and noise deviation with assigned weights to obtain the comprehensive residual deviation and comprehensive noise deviation of the chip.

4. The integrated circuit quality test method of claim 2, wherein, The step of determining the threshold value for the quantitative judgment according to the statistical analysis result comprises: continuously monitoring the residual deviation and noise deviation data of the chip during the production process; periodically or upon detecting a change in the chip lot characteristics, performing statistical analysis on the residual bias and noise bias data to obtain updated statistical analysis results; determining a threshold value for the quantification judgment according to the updated statistical analysis results.

5. The integrated circuit quality test method of claim 4, wherein, The step of determining a threshold value for the quantification judgment according to the updated statistical analysis results comprises: calculating a specific percentile or a standard deviation multiple of the statistical distribution of the residual bias and the noise bias according to the updated statistical analysis results; determining a threshold value for the quantification judgment according to the specific percentile or the standard deviation multiple.

6. The integrated circuit quality test method of claim 4, wherein, The step of detecting a change in the chip lot characteristics comprises: performing statistical process control analysis on the residual bias and noise bias data; judging that the chip lot characteristics have changed when the residual bias and noise bias data exceed a preset statistical control limit or exhibit a preset trend according to the statistical process control analysis results.

7. The integrated circuit quality test method of claim 6, wherein, The step of performing statistical process control analysis on the residual bias and noise bias data comprises: performing statistical process control analysis on the residual bias and noise bias data using X-bar and R control charts or I-MR control charts.

8. The method of claim 1, wherein the integrated circuit is a memory device. The step of quantitatively judging the failure components of the chip according to the residual bias and the noise bias comprises: comparing the residual bias and the noise bias with a plurality of preset judgment threshold values; quantitatively judging the failure components of the chip according to the comparison results.

9. An integrated circuit quality test system for performing an integrated circuit quality test method as claimed in any one of claims 1-8, characterized in that The system comprises: an initial test module configured to execute a preset test instruction set to perform electrical parameter testing on an integrated circuit chip, and configured not to immediately determine the chip as a non-conforming product when detecting that any electrical parameter value of the chip deviates from a preset range, and configured to record an initial electrical parameter measurement value, an identification of a test instruction sequence, and a chip pin number at which the electrical parameter deviates from the preset range; a repeated execution module configured to repeatedly execute the test instruction sequence for the recorded identification of the test instruction sequence and the chip pin number; a condition adjustment module configured to adjust a test condition to change an electrical margin of the chip when repeatedly executing the test instruction sequence; a secondary measurement module configured to measure the electrical parameter of the chip again under the adjusted test condition to obtain a secondary verification electrical parameter measurement value; a judgment module configured to judge whether the electrical parameter abnormality is caused by signal coupling noise or by a real physical defect of the chip according to a relationship between the initial electrical parameter measurement value and the secondary verification electrical parameter measurement value to obtain a judgment result; a classification processing module configured to perform classification processing on the chip according to the judgment result.

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