Clamping voltage generating circuit

Abstract

The invention discloses a clamping voltage generating circuit which comprises an operational amplifier, a PMOS (P-channel Metal Oxide Semiconductor) tube M20, a PMOS tube M21, an NMOS (N-channel Metal Oxide Semiconductor) tube M22, an NMOS tube M23 and a constant current source, the source end of the PMOS tube M20 and the source end of the PMOS tube M21 are connected with working voltage; the gate end of the PMOS tube M20 is connected with the output end of the operational amplifier; the drain end of the PMOS tube M20 is connected with a first output node; the grid end of the NMOS tube M22 and the grid end and the drain end of the NMOS tube M23 are in short circuit connection with a first output node. The source end of the NMOS tube M23 is grounded; the grid end and the drain end of the PMOS tube M21 are connected with the drain end of the NMOS tube M22; the source end of the NMOS tube M22 is connected with the negative input end of the operational amplifier; the positive input end of the operational amplifier is connected with reference voltage; and the constant current source is connected between the source end of the NMOS tube M22 and the ground. The clamping voltage generating circuit can output stable clamping voltage, and the clamping voltage is established quickly.

Description

Technical Field

[0001] The present invention relates to semiconductor circuit technology, and in particular to a clamping voltage generating circuit. Background Art

[0002] Sense amplifiers are mainly used in non-volatile memory to distinguish the data "0" and "1" by comparing the current of the read memory cell with the reference current.

[0003] The read operation of nonvolatile memory is performed by measuring the current in a selected memory cell. Given a known wordline voltage, a preset voltage is applied to the bitline of the selected memory cell to read the current. The read current is then compared with a reference current to determine the phase state of the memory cell. The sense amplifier is a key module in the readout circuit, and read speed is a key performance indicator of the readout circuit.

[0004] There are two types of bit line voltage clamping methods used in Nor flash (flash memory) sense amplifiers: voltage clamping and current clamping. Voltage clamping determines the bit line voltage by controlling the gate terminal of the NMOS switch tube, while current clamping determines the bit line voltage by using the current passing through the NMOS switch tube.

[0005] A common sensitive amplifier is Figure 1 As shown, one input terminal is used to receive the clamping voltage Vout, one input terminal is used to receive the read current Icell of the memory cell, and one input terminal is used to receive the reference current Iref.

[0006] The clamping voltage generating circuit is used to generate a clamping voltage Vout and output it to the clamping voltage input terminal of the sense amplifier.

[0007] A common clamping voltage generating circuit is Figure 2 As shown in the figure, due to the influence of the process, there is a deviation in the resistance, and the current deviation of the main branch of the op amp is large. Through traditional Miller compensation, the zero point compensation pole is inserted. After superimposing the process deviation, the stability deviation of the wide voltage working loop is large, and it also affects the establishment speed of the clamping voltage to a certain extent.

[0008] The existing tail current generating circuit of the clamping voltage generating circuit is as follows Figure 3 As shown, the self-biased current mirror is mainly achieved by bringing the NMOS transistor M10 into the saturation region and modifying the size of the NMOS transistor M10 to generate a bias current of appropriate size. The bias current is then mirrored to the operational amplifier control terminal of the clamping voltage generation circuit through the current mirror as the input tail current of the operational amplifier. Usually, the NMOS transistor M10 needs to be of a longer length (3-5 times or more of the minimum process length) to reduce the influence of the channel length modulation effect on the branch circuit of the NMOS transistor M10.

[0009] The bias current deviation generated by the wide-voltage tail current generation circuit is primarily due to variations in the drain-source voltage VDS of NMOS transistor M10. During wide-voltage operation, the significant difference in the drain-source voltage VDS of NMOS transistor M10 leads to significant tail current deviation at the control terminal of the op amp in the clamp voltage generation circuit. When the enable signal EN = 1, the circuit is inactive. When the enable signal (EN) is switched, the first bias voltage node bgbiasn builds downward from the operating voltage VDD. The tail current of op amp A1 in the clamp voltage generation circuit builds upward from a low to a high level. This slow settling time affects the overall settling time of the op amp in the clamp voltage generation circuit. Summary of the Invention

[0010] The technical problem to be solved by the present invention is to provide a clamping voltage generating circuit which can output a stable clamping voltage.

[0011] To solve the above technical problems, the present invention provides a clamping voltage generating circuit, which includes an operational amplifier A1, a PMOS transistor M20, a PMOS transistor M21, an NMOS transistor M22, an NMOS transistor M23 and a constant current source;

[0012] The source terminals of the PMOS transistor M20 and the PMOS transistor M21 are connected to the operating voltage VDD;

[0013] The gate terminal of the PMOS tube M20 is connected to the output terminal of the operational amplifier A1;

[0014] The drain terminal of the PMOS tube M20 is connected to the first output node Vout1;

[0015] The gate terminal of the NMOS transistor M22 and the gate terminal and the drain terminal of the NMOS transistor M23 are all short-circuited to the first output node Vout1;

[0016] The source end of the NMOS tube M23 is grounded;

[0017] The gate terminal and the drain terminal of the PMOS tube M21 are connected to the drain terminal of the NMOS tube M22;

[0018] The source terminal of the NMOS transistor M22 is connected to the negative input terminal of the operational amplifier A1;

[0019] The positive input terminal of the operational amplifier A1 is used to connect to the reference voltage Vref;

[0020] The constant current source is connected between the source terminal of the NMOS transistor M22 and the ground.

[0021] Preferably, the clamping voltage generating circuit serves as a bit line voltage clamping circuit of the sense amplifier, and is used to generate a clamping voltage and output it to a clamping voltage input terminal of the sense amplifier;

[0022] Preferably, the sense amplifier is a sense amplifier applied to Nor flash;

[0023] The sense amplifier has one input terminal for receiving a clamping voltage, one input terminal for receiving a read current Icell of a memory cell, and one input terminal for receiving a reference current Iref.

[0024] Preferably, the clamping voltage generating circuit further includes an NMOS transistor M25;

[0025] The source terminal of the NMOS transistor M23 is connected to the drain terminal of the NMOS transistor M25;

[0026] The gate terminal of the NMOS transistor M25 is connected to the first output node Vout1 , and the source terminal thereof is grounded.

[0027] Preferably, the clamping voltage generating circuit further includes a resistor R1, a capacitor C1 and a capacitor C2;

[0028] The resistor R1 and the capacitor C1 are connected in series between the output terminal of the operational amplifier A1 and the ground;

[0029] The capacitor C2 is connected between the first output node Vout1 and the negative input terminal of the operational amplifier A1.

[0030] Preferably, the clamping voltage generating circuit further includes an NMOS transistor M24;

[0031] The drain terminal of the NMOS transistor M24 is short-connected to the first output node Vout1 , the source terminal thereof is grounded, and the gate terminal thereof is connected to the negative input terminal of the operational amplifier A1 .

[0032] Preferably, the width-to-length ratio of the NMOS transistor M24 is less than 5.

[0033] Preferably, the threshold voltage Vth of the NMOS tube M22 decreases as the temperature increases, and the constant current source current Ir decreases as the temperature increases.

[0034] Preferably, the clamping voltage generating circuit further includes a PMOS transistor M30, a PMOS transistor M31, a PMOS transistor M41, an NMOS transistor M32, an NMOS transistor M33, an NMOS transistor M36, an NMOS transistor M42 and an NMOS transistor M43;

[0035] The source terminals of the PMOS transistors M30, M31 and M41 are connected to the operating voltage VDD;

[0036] The gate terminal of the PMOS transistor M31 is connected to the gate terminal of the PMOS transistor M21, and the drain terminal of the PMOS transistor M31 is connected to the drain terminal of the NMOS transistor M32;

[0037] The NMOS transistor M32 has a gate terminal connected to the first output node Vout1 and a source terminal connected to the drain terminal of the NMOS transistor M36;

[0038] The PMOS transistor M30 has a gate terminal connected to the output terminal of the operational amplifier A1 and a drain terminal connected to the second output node Vout2;

[0039] The gate and drain terminals of the NMOS transistor M33 and the gate terminal of the NMOS transistor M42 are short-circuited to the second output node Vout2;

[0040] The gate terminal and the drain terminal of the PMOS tube M41 are connected to the drain terminal of the NMOS tube M42;

[0041] The source terminal of the NMOS tube M42 is connected to the drain terminal of the NMOS tube M43;

[0042] The gate terminal of the NMOS transistor M43 is connected to the gate terminal of the NMOS transistor M36 and the drain terminal of the NMOS transistor M32;

[0043] The source terminals of the NMOS transistor M36 , the NMOS transistor M33 , and the NMOS transistor M43 are grounded.

[0044] Preferably, the clamping voltage generating circuit further includes an NMOS transistor M35;

[0045] The drain terminal of the NMOS transistor M35 is connected to the source terminal of the NMOS transistor M33 , the gate terminal of the NMOS transistor M35 is connected to the second output node Vout2 , and the source terminal of the NMOS transistor M35 is grounded.

[0046] Preferably, the clamping voltage generating circuit further includes an NMOS transistor M34;

[0047] The source terminal of the NMOS transistor M34 is grounded, the drain terminal thereof is short-circuited with the second output node Vout2 , and the gate terminal thereof is connected to the source terminal of the NMOS transistor M42 .

[0048] Preferably, the control terminal of the operational amplifier A1 is externally connected to a tail current generating circuit;

[0049] The tail current generating circuit includes a PMOS transistor M12, a PMOS transistor M13, a PMOS transistor M14, a PMOS transistor M15, an NMOS transistor M10, an NMOS transistor M11, an NMOS transistor M16, an NMOS transistor M17 and an NMOS transistor M18;

[0050] The source terminals of the PMOS transistor M13 and the PMOS transistor M14 are connected to the operating voltage VDD;

[0051] The gate terminal of the PMOS transistor M13, the gate terminal of the PMOS transistor M14, the drain terminal of the PMOS transistor M12, the drain terminal of the NMOS transistor M11, and the drain terminal of the NMOS transistor M16 are all connected to the first bias voltage node bgbiasn;

[0052] The drain terminal of the PMOS tube M13 is connected to the source terminal of the PMOS tube M12;

[0053] The source terminal of the NMOS tube M11 is connected to the drain terminal of the NMOS tube M10;

[0054] The drain terminal of the PMOS tube M14 is connected to the source terminal of the PMOS tube M15;

[0055] The source terminal of the PMOS transistor M15, the drain terminal and the gate terminal of the NMOS transistor M17, and the drain terminal of the NMOS transistor M18 are all connected to the second bias voltage node nbias;

[0056] The source terminals of the NMOS transistors M10, M16, M17 and M18 are grounded;

[0057] The gate terminals of the NMOS transistor M16, the PMOS transistor M12, the PMOS transistor M15 and the NMOS transistor M18 are all used to receive an enable signal EN;

[0058] The gate terminals of the NMOS transistor M10 and the NMOS transistor M11 are used to connect to a reference voltage Vref;

[0059] The threshold voltage VthM11 of the NMOS transistor M11 is 0-0.1V.

[0060] Preferably, the tail current generating circuit further includes a coupling capacitor C3;

[0061] The coupling capacitor C3 is connected between the first bias voltage node bgbiasn and the second bias voltage node nbias.

[0062] The clamping voltage generating circuit of the present invention uses a first output node Vout1 as a clamping voltage output terminal and includes three operational amplifier stages. Operational amplifier A1 serves as the first stage, which is a common-source single-stage amplifier (high gain) with a constant current source Ir as a load. PMOS transistor M20 and NMOS transistor M23 constitute the second stage, which is a common-source single-stage amplifier (high output impedance) with a diode as a load. MOS resistors can be superimposed on this stage to increase the output impedance and obtain greater gain. NMOS transistor M22 and PMOS transistor M21 constitute the third stage, which is a common-drain (source follower) single-stage amplifier (low output impedance, gain = 1). From the perspective of a single-stage amplifier, the third-stage source-follower amplifier uses the negative input signal fdbk of the operational amplifier A1 as its input and the first output node Vout1 of the second-stage amplifier as its output. The third-stage source-follower amplifier also provides the voltage at the first output node Vout1 as a bias voltage to the diode load (NMOS transistors M23 and M25) in the second-stage amplifier. The second-stage amplifier can also be considered a unipolar amplifier with a constant current source as its load. The NMOS transistor M22 of the third-stage amplifier uses the voltage at the first output node Vout1 as its bias voltage. Vout1 = Vref + VGSM22. Since Vref is a stable reference voltage unaffected by power supply or temperature, Vout1 is only affected by the gate-source voltage VGSM22 of NMOS transistor M22. Vout1 is relatively stable, thus enabling the output of a stable clamping voltage. Furthermore, this clamping voltage generation circuit has very small load capacitance and parasitic capacitance within the operational amplifier, resulting in a fast clamping voltage buildup. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0064] Figure 1 This is a circuit diagram of a common sensitive amplifier;

[0065] Figure 2 A circuit diagram of an existing clamping voltage generating circuit;

[0066] Figure 3 The present invention is a circuit diagram of an existing tail current generating circuit;

[0067] Figure 4 1 is a circuit diagram of an embodiment of a clamping voltage generating circuit of the present invention;

[0068] Figure 5 1 is a three-stage amplifier circuit diagram of an embodiment of a clamping voltage generating circuit of the present invention;

[0069] Figure 6 This is an external tail current generating circuit of an embodiment of the clamping voltage generating circuit of the present invention. DETAILED DESCRIPTION

[0070] The following is a clear and complete description of the technical solutions of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0071] Example 1

[0072] like Figure 4 As shown, the clamping voltage generating circuit includes an operational amplifier A1, a PMOS transistor M20, a PMOS transistor M21, an NMOS transistor M22, an NMOS transistor M23 and a constant current source;

[0073] The source terminals of the PMOS transistor M20 and the PMOS transistor M21 are connected to the operating voltage VDD;

[0074] The gate terminal of the PMOS tube M20 is connected to the output terminal of the operational amplifier A1;

[0075] The drain terminal of the PMOS tube M20 is connected to the first output node Vout1;

[0076] The gate terminal of the NMOS transistor M22 and the gate terminal and the drain terminal of the NMOS transistor M23 are all short-circuited to the first output node Vout1;

[0077] The source end of the NMOS tube M23 is grounded;

[0078] The gate terminal and the drain terminal of the PMOS tube M21 are connected to the drain terminal of the NMOS tube M22;

[0079] The source terminal of the NMOS transistor M22 is connected to the negative input terminal of the operational amplifier A1;

[0080] The positive input terminal of the operational amplifier A1 is used to connect to the reference voltage Vref;

[0081] The constant current source is connected between the source terminal of the NMOS transistor M22 and the ground.

[0082] Preferably, the clamping voltage generating circuit serves as a bit line voltage clamping circuit of the sense amplifier, and is used to generate a clamping voltage and output it to a clamping voltage input terminal of the sense amplifier;

[0083] Preferably, the sense amplifier is a sense amplifier applied to Nor flash;

[0084] The sense amplifier has one input terminal for receiving a clamping voltage, one input terminal for receiving a read current Icell of a memory cell, and one input terminal for receiving a reference current Iref. Figure 1 shown.

[0085] The clamping voltage generating circuit of the first embodiment uses the first output node Vout1 as the clamping voltage output terminal and includes a three-stage operational amplifier, such as Figure 5 As shown, operational amplifier A1, as the first stage, is a common-source single-stage amplifier (high gain) with a constant current source Ir as a load. PMOS transistor M20 and NMOS transistor M23 form the second stage, a common-source single-stage amplifier (high output impedance) with a diode as a load. MOS resistors can be added to this stage to increase the output impedance and achieve greater gain. NMOS transistor M22 and PMOS transistor M21 form the third stage, a common-drain (source-follower) single-stage amplifier (low output impedance, gain = 1). Analyzed from the perspective of a single-stage amplifier, the third-stage source-follower amplifier takes the negative input signal fdbk of operational amplifier A1 as its input and the first output node Vout1 of the second-stage amplifier as its output. The third-stage source-follower amplifier also provides the voltage of the first output node Vout1 as a bias voltage to the diode load (NMOS transistors M23 and M25) in the second-stage amplifier. The second-stage amplifier can also be considered a single-stage amplifier with a constant current source as its load. The NMOS transistor M22 of the third-stage amplifier uses the voltage of the first output node Vout1 as its bias voltage. Vout1 = Vref + VGSM22. Since Vref is a stable reference voltage unaffected by power supply or temperature, Vout1 is only affected by the gate-source voltage VGSM22 of NMOS transistor M22. Vout1 is relatively stable, thus outputting a stable clamping voltage. Furthermore, this clamping voltage generation circuit has minimal load capacitance and parasitic capacitance on the op amp itself, allowing for rapid clamping voltage development.

[0086] The clamping voltage generating circuit of the present invention can output a stable clamping voltage and is not affected by power supply voltage or temperature changes. When applied to a sense amplifier of a NOR flash, it can solve the problem that the voltage-clamped sense amplifier structure affects the reading speed due to the slow clamping voltage establishment under wide voltage operation.

[0087] Example 2

[0088] Based on the first embodiment, the clamping voltage generating circuit further includes an NMOS transistor M25;

[0089] The source terminal of the NMOS transistor M23 is connected to the drain terminal of the NMOS transistor M25;

[0090] The gate terminal of the NMOS transistor M25 is connected to the first output node Vout1 , and the source terminal thereof is grounded.

[0091] The clamping voltage generation circuit of Embodiment 2, wherein the source terminal of the NMOS transistor M23 is grounded through the NMOS transistor M25.

[0092] Embodiment 3

[0093] Based on Embodiment 1, the clamping voltage generation circuit further includes a resistor R1, a capacitor C1 and a capacitor C2;

[0094] The resistor R1 and the capacitor C1 are connected in series between the output terminal of the operational amplifier A1 and the ground;

[0095] The capacitor C2 is connected between the first output node Vout1 and the negative input terminal of the operational amplifier A1.

[0096] The clamping voltage generation circuit of Embodiment 3, two zero-compensating poles are inserted in the three-stage amplification, which are the resistor R1, the capacitor C1 (the first stage to the ground) and the capacitor C2 (the third stage is cross-connected), respectively compensating the main pole and the high-frequency pole to ensure that the phase margin PM > 70°; the resistor R1 and the capacitor C1 of the first zero are connected on the path from the output of the operational amplifier to the ground, the current deviation of the main branch of the operational amplifier is small, and the loop stability deviation is small; in addition to ensuring sufficient loop stability, from the perspective of transient establishment analysis, it can also reduce the jitter of the output of the first-stage amplification caused by the influence of the tail current establishment speed on the operational amplifier A1, further improving the overall speed of the three-stage amplification from establishment to stability and accelerating the establishment of the clamping voltage.

[0097] Embodiment 4

[0098] Based on Embodiment 1, the clamping voltage generation circuit further includes an NMOS transistor M24;

[0099] For the NMOS transistor M24, its drain terminal is short-circuited to the first output node Vout1, its source terminal is grounded, and its gate terminal is connected to the negative input terminal of the operational amplifier A1.

[0100] Preferably, the aspect ratio of the NMOS transistor M24 is less than 5. During the establishment of the operational amplifier, the feedback voltage fdbk at the negative input terminal of the operational amplifier A1 will have a certain degree of overshoot. Affected by the source follower, Vout1 = fdbk + VthM22. When fdbk > VthM24, the NMOS transistor M24 conducts. VthM24 is the threshold voltage of the NMOS transistor M24. At this time, the NMOS transistor M24 will slowly discharge the overshoot charge of the first output node Vout1 until fdbk < VthM24. Here, the NMOS transistor M24 needs to be sized with an inverted ratio (width < 5 times length or more, that is, the aspect ratio is less than 5) to avoid remaining at VthM24 < fdbk all the time and avoid making the NMOS transistor M24 always conduct, which has an adverse effect on the stability of the operational amplifier.

[0101] In the clamping voltage generating circuit of the fourth embodiment, when the voltage fdbk at the negative input terminal of the operational amplifier A1 overshoots, the NMOS transistor M24 turns on to discharge the charge of the first output node Vout1, thereby accelerating the stabilization of the output clamping voltage. Under extreme conditions (such as high temperature and low power supply voltage), the clamping voltage establishment time can be reduced to within 40ns, and the static power consumption problem of traditional clamping diodes can be avoided.

[0102] Example 5

[0103] Based on the clamping voltage generating circuit of the fourth embodiment, the threshold voltage Vth of the NMOS transistor M22 decreases as the temperature increases, and the constant current source current Ir decreases as the temperature increases.

[0104] The threshold voltage Vth of the NMOS transistor M22 is affected by temperature. As the temperature increases, Vth decreases. The constant current source current Ir varies with temperature. As the temperature increases, the current decreases. This variation trend can be used to compensate for deviations in the gate-source voltage VGSM22 of the NMOS transistor M22 caused by the temperature influence on the threshold voltage VthM22 of the NMOS transistor M22. Based on the MOS transistor saturation region current formula, the gate-source voltage VGSM22 of the NMOS transistor M22 is ensured to be unaffected by temperature.

[0105] The clamping voltage generating circuit of the fifth embodiment adopts a temperature-current synergistic compensation mechanism. It uses a temperature-sensitive constant current source Ir (temperature↑→Ir↓) to offset the temperature drift of the threshold voltage VthM22 of the NMOS transistor M22 (temperature↑→Vth↓), so that the gate-source voltage VGSM22 of the NMOS transistor M22 remains constant. The temperature stability of Vout1=Vref+VGSM22 is less than ±1%.

[0106] Example 6

[0107] Based on the first embodiment, the clamping voltage generating circuit further includes a PMOS transistor M30, a PMOS transistor M31, a PMOS transistor M41, an NMOS transistor M32, an NMOS transistor M33, an NMOS transistor M36, an NMOS transistor M42, and an NMOS transistor M43;

[0108] The source terminals of the PMOS transistors M30, M31 and M41 are connected to the operating voltage VDD;

[0109] The gate terminal of the PMOS transistor M31 is connected to the gate terminal of the PMOS transistor M21, and the drain terminal of the PMOS transistor M31 is connected to the drain terminal of the NMOS transistor M32;

[0110] The NMOS transistor M32 has a gate terminal connected to the first output node Vout1 and a source terminal connected to the drain terminal of the NMOS transistor M36;

[0111] The PMOS transistor M30 has a gate terminal connected to the output terminal of the operational amplifier A1 and a drain terminal connected to the second output node Vout2;

[0112] The gate and drain terminals of the NMOS transistor M33 and the gate terminal of the NMOS transistor M42 are short-circuited to the second output node Vout2;

[0113] The gate terminal and the drain terminal of the PMOS tube M41 are connected to the drain terminal of the NMOS tube M42;

[0114] The source terminal of the NMOS tube M42 is connected to the drain terminal of the NMOS tube M43;

[0115] The gate terminal of the NMOS transistor M43 is connected to the gate terminal of the NMOS transistor M36 and the drain terminal of the NMOS transistor M32;

[0116] The source terminals of the NMOS transistor M36 , the NMOS transistor M33 , and the NMOS transistor M43 are grounded.

[0117] Preferably, the clamping voltage generating circuit further includes an NMOS transistor M35;

[0118] The drain terminal of the NMOS transistor M35 is connected to the source terminal of the NMOS transistor M33 , the gate terminal of the NMOS transistor M35 is connected to the second output node Vout2 , and the source terminal of the NMOS transistor M35 is grounded.

[0119] Preferably, the clamping voltage generating circuit further includes an NMOS transistor M34;

[0120] The source terminal of the NMOS transistor M34 is grounded, the drain terminal thereof is short-circuited with the second output node Vout2 , and the gate terminal thereof is connected to the source terminal of the NMOS transistor M42 .

[0121] The clamping voltage generating circuit of Example 6 uses a current mirror method and an additional independent mirror branch (PMOS transistor M30, NMOS transistor M33, etc.) to transmit the clamping voltage to the load with the second output node Vout2 as the clamping voltage output terminal of the clamping voltage generating circuit. There is no direct connection between the main op amp and the second output node Vout2, isolating the load's influence on the main op amp. Changes in load capacitance (such as 1pF-10pF) do not affect the stability of the main loop, avoiding the deterioration of the phase margin introduced by the load in the traditional solution. The PMOS transistor M30, NMOS transistor M33, NMOS transistor M34, and NMOS transistor M42 in the mirror branch are independent paths and can be regarded as two additional unipolar amplifiers, but they are not closed-loop applications, so loop stability does not need to be considered. The stable voltages of the second output node Vout2 and the first output node Vout1 differ only in the settling time. After reaching the static operating point, the voltages of the second output node Vout2 and the first output node Vout1 are exactly the same. By modifying the aspect ratio of the PMOS tube M20 and the PMOS tube M30 (the lengths of the two tubes are the same, and only the widths of the two tubes are modified proportionally, such as 1:2, 1:3, 1:4, etc.), the current mirror ratio is adjusted to adapt to loads of different sizes, ensuring that the clamping voltage generation circuit is more flexible in application.

[0122] The clamping voltage generation circuit of Example 6 features a mirror branch isolation design that allows for independent optimization of the clamping voltage circuit and flexible adaptation to multiple loads (different numbers of sense amplifiers SA), expanding its application scenarios. Multiple loads can refer to different numbers of sense amplifiers SA. The more sense amplifiers SA there are, the more transistors connected to the second output node Vout2, resulting in a slower settling time. Therefore, it is necessary to adjust the current mirror ratio between the PMOS transistors M20 and M30. By increasing the current, the settling speed is improved and the settling time is reduced.

[0123] Example 7

[0124] Based on the clamping voltage generating circuit of the first embodiment, the control terminal of the operational amplifier A1 is externally connected to a tail current generating circuit;

[0125] like Figure 6 As shown, the control terminal of the operational amplifier A1 is externally connected to a tail current generating circuit;

[0126] The tail current generating circuit includes a PMOS transistor M12, a PMOS transistor M13, a PMOS transistor M14, a PMOS transistor M15, an NMOS transistor M10, an NMOS transistor M11, an NMOS transistor M16, an NMOS transistor M17 and an NMOS transistor M18;

[0127] The source terminals of the PMOS transistor M13 and the PMOS transistor M14 are connected to the operating voltage VDD;

[0128] The gate terminal of the PMOS transistor M13, the gate terminal of the PMOS transistor M14, the drain terminal of the PMOS transistor M12, the drain terminal of the NMOS transistor M11, and the drain terminal of the NMOS transistor M16 are all connected to the first bias voltage node bgbiasn;

[0129] The drain terminal of the PMOS tube M13 is connected to the source terminal of the PMOS tube M12;

[0130] The source terminal of the NMOS tube M11 is connected to the drain terminal of the NMOS tube M10;

[0131] The drain terminal of the PMOS tube M14 is connected to the source terminal of the PMOS tube M15;

[0132] The source terminal of the PMOS transistor M15, the drain terminal and the gate terminal of the NMOS transistor M17, and the drain terminal of the NMOS transistor M18 are all connected to the second bias voltage node nbias;

[0133] The source terminals of the NMOS transistors M10, M16, M17 and M18 are grounded;

[0134] The gate terminals of the NMOS transistor M16, the PMOS transistor M12, the PMOS transistor M15 and the NMOS transistor M18 are all used to receive an enable signal EN;

[0135] The gate terminals of the NMOS transistor M10 and the NMOS transistor M11 are used to connect to a reference voltage Vref;

[0136] The threshold voltage VthM11 of the NMOS transistor M11 is extremely small and close to 0 (0V-0.1V).

[0137] In the clamping voltage generating circuit of the seventh embodiment, an NMOS transistor M11 (ZVT transistor) is added to the tail current generating circuit. When operating in a wide voltage range (e.g., 1.5V-3.8V), the NMOS transistor M11 is a switch controlled by a reference voltage Vref. The maximum voltage that can be transmitted is Vref-VthM11 (the drain-source voltage VDSM10 of the NMOS transistor M10 is not dynamically adjusted here; the drain-source voltage VDSM10 of the NMOS transistor M10 is always equal to Vref-VthM11). The drain-source voltage VDSM10 of the NMOS transistor M10 is constant, which can greatly reduce the difference in the drain-source voltage VDSM10 of the NMOS transistor M10 under wide voltage operation, eliminate the output current deviation of the tail current generating circuit caused by the channel length modulation effect (CLM), save area, and eliminate the need for complex feedback control.

[0138] Example 8

[0139] Based on the clamping voltage generating circuit of embodiment 7, the tail current generating circuit further includes a coupling capacitor C3;

[0140] The coupling capacitor C3 is connected between the first bias voltage node bgbiasn and the second bias voltage node nbias.

[0141] In the clamping voltage generating circuit of Example 8, a newly added coupling capacitor C3 is connected between the first bias voltage node bgbiasn and the second bias voltage node nbias of the tail current generating circuit. The voltages of both the first bias voltage node bgbiasn and the second bias voltage node nbias need to be built up from 0 to a stable state. When the enable signal EN=0, the tail current generating circuit does not operate. When the NMOS transistor M11 is turned on as a switch, the instantaneous currents in the two branches are large, and the voltage of the second bias voltage node nbias rises rapidly. The coupling capacitor C3 quickly reflects the change in the voltage of the second bias voltage node nbias to the first bias voltage node bgbiasn, causing the voltage of the first bias voltage node bgbiasn to rise rapidly, accelerating the development of the voltage of the first bias voltage node bgbiasn. When the enable (EN) signal is switched, the coupling capacitor C3 can suppress the tail current overshoot of the op amp caused by the voltage of the first bias voltage node bgbiasn building up from 0, thereby accelerating the development of the tail current of the op amp to a stable state.

[0142] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A clamping voltage generating circuit, characterized in that: It includes an operational amplifier (A1), a PMOS tube M20, a PMOS tube M21, an NMOS tube M22, an NMOS tube M23 and a constant current source; The source terminal operating voltage (VDD) of the PMOS transistor M20 and the PMOS transistor M21; The gate terminal of the PMOS tube M20 is connected to the output terminal of the operational amplifier (A1); The drain terminal of the PMOS tube M20 is connected to the first output node (Vout1); The gate terminal of the NMOS transistor M22 and the gate terminal and the drain terminal of the NMOS transistor M23 are all short-circuited to the first output node (Vout1); The source end of the NMOS tube M23 is grounded; The gate terminal and the drain terminal of the PMOS tube M21 are connected to the drain terminal of the NMOS tube M22; The source terminal of the NMOS transistor M22 is connected to the negative input terminal of the operational amplifier (A1); The positive input terminal of the operational amplifier (A1) is used to connect to a reference voltage (Vref); The constant current source is connected between the source terminal of the NMOS transistor M22 and the ground.

2. The clamping voltage generating circuit according to claim 1, wherein: The clamping voltage generating circuit serves as a bit line voltage clamping circuit of the sense amplifier, and is used to generate a clamping voltage and output it to the clamping voltage input terminal of the sense amplifier; 3. The clamping voltage generating circuit according to claim 1, wherein: The sensitive amplifier is a sensitive amplifier applied to Nor flash; The sense amplifier has one input terminal for receiving a clamping voltage, one input terminal for receiving a read current (Icell) of a storage cell, and one input terminal for receiving a reference current (Iref).

4. The clamping voltage generating circuit according to claim 1, wherein: The clamping voltage generating circuit further includes an NMOS tube M25; The source terminal of the NMOS transistor M23 is connected to the drain terminal of the NMOS transistor M25; The gate terminal of the NMOS transistor M25 is connected to the first output node (Vout1), and the source terminal thereof is grounded.

5. The clamping voltage generating circuit according to claim 1, wherein: The clamping voltage generating circuit further includes a resistor R1, a capacitor C1 and a capacitor C2; The resistor R1 and the capacitor C1 are connected in series between the output terminal of the operational amplifier (A1) and the ground; The capacitor C2 is connected between the first output node (Vout1) and the negative input terminal of the operational amplifier (A1).

6. The clamping voltage generating circuit according to claim 1, wherein: The clamping voltage generating circuit further includes an NMOS tube M24; The drain end of the NMOS transistor M24 is short-circuited with the first output node (Vout1), the source end thereof is grounded, and the gate end thereof is connected to the negative input end of the operational amplifier (A1).

7. The clamping voltage generating circuit according to claim 6, wherein: The width-to-length ratio of the NMOS transistor M24 is less than 5.

8. The clamping voltage generating circuit according to claim 1, wherein: The threshold voltage Vth of the NMOS transistor M22 decreases as the temperature increases, and the constant current source current Ir decreases as the temperature increases.

9. The clamping voltage generating circuit according to claim 1, wherein: The clamping voltage generating circuit further includes a PMOS transistor M30, a PMOS transistor M31, a PMOS transistor M41, an NMOS transistor M32, an NMOS transistor M33, an NMOS transistor M36, an NMOS transistor M42 and an NMOS transistor M43; The source terminal operating voltage (VDD) of the PMOS transistor M30, the PMOS transistor M31, and the PMOS transistor M41; The gate terminal of the PMOS transistor M31 is connected to the gate terminal of the PMOS transistor M21, and the drain terminal of the PMOS transistor M31 is connected to the drain terminal of the NMOS transistor M32; The NMOS transistor M32 has a gate terminal connected to the first output node (Vout1) and a source terminal connected to the drain terminal of the NMOS transistor M36; The PMOS transistor M30 has a gate terminal connected to the output terminal of the operational amplifier (A1) and a drain terminal connected to the second output node (Vout2); The gate and drain terminals of the NMOS transistor M33 and the gate terminal of the NMOS transistor M42 are all short-circuited to the second output node (Vout2); The gate terminal and the drain terminal of the PMOS tube M41 are connected to the drain terminal of the NMOS tube M42; The source terminal of the NMOS tube M42 is connected to the drain terminal of the NMOS tube M43; The gate terminal of the NMOS transistor M43 is connected to the gate terminal of the NMOS transistor M36 and the drain terminal of the NMOS transistor M32; The source terminals of the NMOS transistor M36 , the NMOS transistor M33 , and the NMOS transistor M43 are grounded.

10. The clamping voltage generating circuit according to claim 9, wherein: The clamping voltage generating circuit further includes an NMOS tube M35; The drain terminal of the NMOS transistor M35 is connected to the source terminal of the NMOS transistor M33 , the gate terminal of the NMOS transistor M35 is connected to the second output node ( Vout2 ), and the source terminal of the NMOS transistor M35 is grounded.

11. The clamping voltage generating circuit according to claim 9, wherein: The clamping voltage generating circuit further includes an NMOS tube M34; The source terminal of the NMOS transistor M34 is grounded, the drain terminal thereof is short-circuited to the second output node ( Vout2 ), and the gate terminal thereof is connected to the source terminal of the NMOS transistor M42 .

12. The clamping voltage generating circuit according to claim 1, wherein: The control terminal of the operational amplifier (A1) is externally connected to a tail current generating circuit; The tail current generating circuit includes a PMOS transistor M12, a PMOS transistor M13, a PMOS transistor M14, a PMOS transistor M15, an NMOS transistor M10, an NMOS transistor M11, an NMOS transistor M16, an NMOS transistor M17 and an NMOS transistor M18; The source terminal operating voltage (VDD) of the PMOS transistor M13 and the PMOS transistor M14; The gate terminal of the PMOS transistor M13, the gate terminal of the PMOS transistor M14, the drain terminal of the PMOS transistor M12, the drain terminal of the NMOS transistor M11, and the drain terminal of the NMOS transistor M16 are all connected to a first bias voltage node (bgbiasn); The drain terminal of the PMOS tube M13 is connected to the source terminal of the PMOS tube M12; The source terminal of the NMOS tube M11 is connected to the drain terminal of the NMOS tube M10; The drain terminal of the PMOS tube M14 is connected to the source terminal of the PMOS tube M15; The source terminal of the PMOS transistor M15, the drain terminal and the gate terminal of the NMOS transistor M17, and the drain terminal of the NMOS transistor M18 are all connected to a second bias voltage node (nbias); The source terminals of the NMOS transistors M10, M16, M17 and M18 are grounded; The gate terminals of the NMOS transistor M16, the PMOS transistor M12, the PMOS transistor M15, and the NMOS transistor M18 are all used to receive an enable signal (EN); The gate terminals of the NMOS transistor M10 and the NMOS transistor M11 are used to connect to a reference voltage (Vref); The threshold voltage VthM11 of the NMOS transistor M11 is 0V to 0.1V.

13. The clamping voltage generating circuit according to claim 1, wherein: The tail current generating circuit further includes a coupling capacitor C3; The coupling capacitor C3 is connected between a first bias voltage node (bgbiasn) and a second bias voltage node (nbias).

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