Method, apparatus, device, medium and program product for optimizing combinational logic circuits

Abstract

The application relates to a combinational logic circuit optimization method, device, equipment, medium and program product. The method comprises the following steps: obtaining a combinational logic circuit expression to be optimized; performing symmetric logic identification on the combinational logic circuit expression to determine symmetric logic in the combinational logic circuit expression; generating a transposition gate structure based on variables related to the symmetric logic; and optimizing the combinational logic circuit expression based on the transposition gate structure. The method can improve processing efficiency.

Description

Technical Field

[0001] This application relates to the fields of digital integrated circuit design and electronic design automation (EDA) technology, and in particular to a method, apparatus, device, medium and program product for optimizing combinational logic circuits. Background Technology

[0002] Logic synthesis is an important step in EDA. Traditional synthesis methods based on global heuristic algorithms often yield suboptimal solutions. Furthermore, as the complexity of computational tasks increases, the need to optimize circuit area and power consumption becomes increasingly urgent.

[0003] In modern integrated circuit design, combinational logic optimization is one of the key technologies for improving circuit performance and silicon wafer area utilization. Current mainstream logic optimization techniques, such as Boolean algebra rewriting, lookup table (LUT) mapping, and subgraph reconstruction, all focus on gate-level optimization in the later synthesis stage. However, these methods often rely on complex graph search algorithms, which are extremely inefficient. Summary of the Invention

[0004] Therefore, it is necessary to provide a method, apparatus, device, medium, and program product for optimizing combinational logic circuits that can improve processing efficiency in response to the above-mentioned technical problems.

[0005] In a first aspect, this application provides a method for optimizing combinational logic circuits, the method comprising:

[0006] Obtain the combinational logic circuit expression to be optimized;

[0007] Perform symmetric logic identification on the combinational logic circuit expression to determine the symmetric logic in the combinational logic circuit expression;

[0008] The transpose gate structure is generated based on the variables involved in the symmetric logic.

[0009] The combinational logic circuit expression is optimized based on the transposed gate structure.

[0010] In some optional embodiments, the step of performing symmetric logic identification on the combinational logic circuit expression to determine the symmetric logic in the combinational logic circuit expression includes:

[0011] Determine the variables involved in the combinational logic circuit expression and the number of times the variables appear in the combinational logic circuit expression;

[0012] If the number of occurrences exceeds a threshold, the common factor in the combinational logic circuit expression is extracted based on the variable whose number of occurrences exceeds the threshold.

[0013] Based on the variables involved in the common factor, the symmetric logic in the combinational logic circuit expression is obtained.

[0014] In some optional embodiments, extracting the common factor from the combinational logic circuit expression based on the variables whose occurrence frequency is greater than a threshold includes:

[0015] If the combinational logic circuit expression is a completely symmetrical logic, then the combinational logic circuit expression is subjected to like terms extraction to obtain the common factor.

[0016] In some optional embodiments, extracting the common factor from the combinational logic circuit expression based on the variables whose occurrence frequency is greater than a threshold includes:

[0017] If the combinational logic circuit expression is partially symmetric logic, the combinational logic circuit expression is factored based on the variables that appear more than a threshold number of times to obtain a common factor.

[0018] In some alternative embodiments, the generation of transpose gate structures based on the variables involved in the symmetric logic includes:

[0019] Based on the variables involved in the symmetric logic, the symmetric logic is decomposed into at least one AND gate and / or at least one OR gate;

[0020] Based on at least one AND gate and / or at least one OR gate obtained from the split, a transposed gate structure is generated.

[0021] In some optional embodiments, optimizing the combinational logic circuit expression based on the transposed gate structure includes:

[0022] Determine the target position in the combinational logic circuit expression where the variables involved in the symmetric logic first participate in the operation together;

[0023] Insert the transposed gate structure into the target position, and change the expression in the combinational logic circuit expression that involves the transposed gate structure to reference the transposed gate structure.

[0024] Secondly, this application also provides a combinational logic circuit optimization device, the device comprising:

[0025] The expression acquisition module is used to acquire the combinational logic circuit expression to be optimized;

[0026] A symmetric logic identification module is used to perform symmetric logic identification on the combinational logic circuit expression and determine the symmetric logic in the combinational logic circuit expression.

[0027] A transpose gate structure generation module is used to generate transpose gate structures based on the variables involved in the symmetric logic;

[0028] An optimization module is used to optimize the combinational logic circuit expression based on the transposed gate structure.

[0029] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described in any of the above embodiments.

[0030] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method described in any of the above embodiments.

[0031] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method described in any of the above embodiments.

[0032] The aforementioned combinational logic circuit optimization method, apparatus, device, medium, and program product obtain a combinational logic circuit expression to be optimized; perform symmetric logic identification on the combinational logic circuit expression to determine the symmetric logic in the combinational logic circuit expression; generate transposed gate structures based on the variables involved in the symmetric logic; and optimize the combinational logic circuit expression based on the transposed gate structures. Thus, by performing symmetric logic identification on the combinational logic circuit expression and generating transposed gate structures from the variables involved in the symmetric logic, these transposed gate structures can be reused, improving optimization efficiency. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a flowchart illustrating a combinational logic circuit optimization method in one embodiment;

[0035] Figure 2 This is a flowchart of the symmetric logic identification steps in one embodiment;

[0036] Figure 3 Here is a flowchart of the symmetric logic identification steps in another embodiment;

[0037] Figure 4A block diagram of a combinational logic circuit optimization device in one embodiment;

[0038] Figure 5 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0040] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0041] In one embodiment, such as Figure 1 As shown, a method for optimizing combinational logic circuits is provided. This embodiment illustrates the application of this method to a terminal. It is understood that this method can also be applied to a server, and further to a system including both a terminal and a server, and implemented through interaction between the terminal and the server. In this embodiment, the method includes the following steps:

[0042] S102: Obtain the combinational logic circuit expression to be optimized.

[0043] The combinational logic circuit expression to be optimized is obtained in the RTL structure generation process. For example, the RTL structure can be visualized through a graphical interface, which receives the combinational logic circuit expression of the circuit input by the user or drawn by the user.

[0044] S104: Perform symmetric logic identification on the combinational logic circuit expression to determine the symmetric logic in the combinational logic circuit expression.

[0045] Symmetric logic includes variables in a combinational logic circuit expression that satisfy a symmetry relationship. Symmetry means that the output of the combinational logic circuit expression remains unchanged after the positions of the variables are interchanged. Specifically, it automatically detects the symmetry relationship between input variables: if a variable pair (A, B) satisfies the condition that the output of the function remains unchanged after swapping inputs A and B, then (A, B) is said to be symmetric. In other embodiments, the number of input variables can include not only two, but also three, four, etc., and no specific limitation is made here.

[0046] The identification process can be carried out by combining structural analysis and simulation, which can efficiently discover symmetric logic.

[0047] Optionally, after the RTL code is completed, a shell script for symmetry identification is used to analyze the RTL code and detect all symmetric variables as symmetric logic.

[0048] S106: Generate transpose gate structure based on variables involved in symmetric logic.

[0049] A transpose gate is a special type of combinational logic module. Its principle lies in utilizing the symmetry of the input variable set to combine multiple logical operations into a single AND gate and an OR gate. For example, for a pair of symmetrical inputs (A, B), a 2-input AND gate and a 2-input OR gate can be introduced to compute A∧B and A∨B respectively. Since symmetric logic only cares about the number and distribution of inputs, these two outputs (A∧B and A∨B) become the basic building blocks for constructing symmetric logic.

[0050] For larger symmetric groups, multiple AND / OR gates (or multi-input AND / OR gates) can be used to simultaneously compute at least one of the logical AND and logical OR results of the variables throughout the symmetric logic. These logical AND and logical OR results are then presented as transpose gate structures.

[0051] S108: Optimize combinational logic circuit expressions based on transpose gate structure.

[0052] In this application, expressions involving the logical AND and logical OR of transposed gate structures in combinational logic circuit expressions are replaced with logical AND and logical OR of transposed gate structures. This achieves the reuse of transposed gate structures and also optimizes the combinational logic circuit expressions.

[0053] In some optional embodiments, the transpose gate structure of this application is implemented using Verilog code and integrated into the RTL generator as a reusable module. This reusable module takes one or more pairs of symmetrical signals as input and outputs the corresponding AND and OR operation results. The design reuses these result signals as much as possible, thereby achieving the original function with fewer gates and reducing area. Similarly, decomposing Boolean functions into a network of symmetrical functions and implementing them using special logic units can achieve higher area efficiency. By analyzing the symmetrical relationships of the input variables in the logical expression, reconstructing the logical structure, and inserting reusable intermediate computation nodes (i.e., transpose gates), redundancy of logic gates is reduced, and hardware resource utilization is improved.

[0054] The above-described combinational logic circuit optimization method obtains the combinational logic circuit expression to be optimized; performs symmetric logic identification on the combinational logic circuit expression to determine the symmetric logic in the combinational logic circuit expression; generates transposed gate structures based on the variables involved in the symmetric logic; and optimizes the combinational logic circuit expression based on the transposed gate structures. In this way, by performing symmetric logic identification on the combinational logic circuit expression and generating transposed gate structures from the variables involved in the symmetric logic, these transposed gate structures can be reused, thereby improving optimization efficiency.

[0055] In some of these alternative embodiments, combined with Figure 2 As shown, Figure 2 This is a flowchart of a symmetric logic identification step in one embodiment. In this embodiment, the symmetric logic identification step, namely, performing symmetric logic identification on the combinational logic circuit expression to determine the symmetric logic in the combinational logic circuit expression, includes:

[0056] S202: Determine the variables involved in the combinational logic circuit expression and the number of times each variable appears in the combinational logic circuit expression.

[0057] In this embodiment, the variables involved in the combinational logic circuit expression are first obtained. For example, if the combinational logic circuit expression is F=(A AND B)OR(A OR B)AND C, the variables involved include A, B and C. The number of times each variable appears is counted. For example, the number of times variable A appears is 2, the number of times variable B appears is 2, and the number of times variable C appears is 1.

[0058] S204: When the number of occurrences exceeds a threshold, extract the common factor from the combinational logic circuit expression based on the variable whose number of occurrences exceeds the threshold.

[0059] S206: Based on the variables involved in the common factor, obtain the symmetric logic in the combinational logic circuit expression.

[0060] The threshold is preset. For example, the threshold can be 1. If the number of times a variable appears is greater than 1, it is considered that it may be redundant and can therefore be optimized.

[0061] The common factor in a combinational logic circuit expression can be obtained by logical analysis or extraction of like terms. That is, the combinational logic circuit expression is factored and reconstructed, repeating paths are logically factored, and the common factor is extracted.

[0062] The variables involved in the common factor are used to obtain the symmetric logic in the combinational logic circuit expression. For example, F=(A ANDB)OR(A OR B)AND C, whose common factor includes (A AND B), (A OR B) and C. Therefore, changing the order of A and B will not change the value of F, so A and B satisfy the symmetry rule.

[0063] Subsequently, transpose gate structures can be generated based on A and B, i.e., T1=A AND B, T2=A OR B. Finally, F is rewritten as F=(T1)OR(T2 AND C). The original RTL code is used in conjunction with a shell script to generate the final RTL code, completing the automatic output of RTL and outputting the rewritten Verilog code structure, which is convenient for subsequent hardware synthesis.

[0064] In the above embodiments, based on the symmetry identification between variables in Boolean functions, transposed gate structures oriented towards shared computation are inserted before RTL generation or synthesis. Expressions are pre-reconstructed into synthesizable hardware structural units through logical factorization, eliminating the need to traverse and merge existing netlists. This method leverages symmetry to pre-release shared intermediate nodes, reducing gate-level redundancy and directly generating synthesizable Verilog / hardware structures. Furthermore, semantic layer optimization is more efficient: it does not rely on netlist traversal or hash comparisons, but instead identifies the equivalence relationships between variable pairs for direct structural optimization. The structural implementation is simpler: shared intermediate nodes are implemented by inserting logical transposed gate modules, avoiding the complex control judgments of traditional merging processes. The hardware generation path is more direct: the optimized RTL can be synthesized into a gate-level network without further folding by subsequent software or tools. Therefore, this embodiment can significantly improve area and power efficiency in symmetric logic scenarios, possessing technical advantages such as simplicity, efficiency, and hardware friendliness.

[0065] In some optional embodiments, common factors are extracted from combinational logic circuit expressions based on variables that appear more than a threshold, including: if the combinational logic circuit expression is a completely symmetrical logic, then like terms are extracted from the combinational logic circuit expression to obtain common factors.

[0066] In some optional embodiments, common factors are extracted from combinational logic circuit expressions based on variables that appear more than a threshold, including: when the combinational logic circuit expression is partially symmetric logic, factoring the combinational logic circuit expression based on variables that appear more than a threshold to obtain common factors.

[0067] Among them, combined Figure 3 As shown, Figure 3 The flowchart below shows a symmetric logic identification step in another embodiment, in which the symmetric logic identification step can be divided into a fully symmetric logic processing step and a partially symmetric logic processing step.

[0068] For the expression that completes symmetric logic and combinational logic circuits, i.e., code 1: F=(a&b)|(a&c), in this expression, variables b and c are respectively ANDed with a, and then ORed. According to Boolean algebra expansion and merging rules, this expression can be rewritten as: F=a&(b|c).

[0069] This rewriting method has higher sharing and gate-level compression in terms of logic structure. In particular, when 'a' is used as a control condition signal, it can effectively avoid redundant 'a' signals driving multiple AND gates multiple times.

[0070] The optimized structure consists of three parts: OR gate T1: implements (b|c), corresponding to assignT1=b|c in RTL; AND gate T2: ANDs a with T1 to obtain the final output F=a&T1; the output signal F is the result of the rewritten structure, which is functionally equivalent to the original logic.

[0071] Taking RTL construction as an example, the following diagram illustrates the process:

[0072] module logic_opt_example (

[0073] input wire a,

[0074] input wire b,

[0075] input wire c,

[0076] output wire F );

[0078] wire T1;

[0079] assign T1 = b | c;

[0080] assign F = a&T1;

[0081] endmodule

[0082] For partially symmetric logic, the expression for combinational logic circuits, i.e., code 2: F=(a&b)|(a|b)&c, will be expanded into multiple basic gate circuits during actual hardware synthesis. Traditional logic synthesis methods cannot recognize the symmetric structure between A and B in this formula, leading to redundant and repeated calculations. For example, "a&b" and "a|b" may each generate independent gate-level paths in the hardware, resulting in wasted logic area.

[0083] This application automatically identifies symmetric variable pairs in the input logic function during the pre-generation stage of RTL or logic synthesis. In this example, the variable pair (A, B) satisfies input symmetry: swapping A and B does not change the value of the output logic F. This symmetry can be automatically identified through Boolean function analysis (such as BDD structure judgment, symbolic equivalence detection, etc.).

[0084] Then, the transpose gate insertion and structure rewriting are performed. After identifying the symmetric variable pair (A,B), this application automatically introduces transpose gate units into the logic and rewrites the original logic expression in a structured way as: T1=a&b, T2=a|b, F=T1|(T2&C).

[0085] In other words, both T1 and T2 only need to be calculated once and reused by downstream logic. This results in higher gate-level resource utilization in the hardware implementation and avoids duplicate paths generated after the original expression is expanded.

[0086] Taking RTL construction as an example, the following diagram illustrates the process:

[0087] module logic_opt (

[0088] input wires A, B, C,

[0089] output wire F );

[0091] wires T1 and T2;

[0092] assign T1 = A&B;

[0093] assign T2 = A | B;

[0094] assign F = T1 | (T2&C);

[0095] endmodule

[0096] This RTL structure is more hierarchical than the traditional approach, which facilitates logic reuse and subsequent optimization of EDA tools.

[0097] The above embodiments only illustrate symmetric logic with two variables, but it can be extended to multi-input symmetric logic with n variables. For example, for the function F=Majority(A, B, C, D), this application can identify the complete symmetry among all input variables and reconstruct it into optimized RTL logic based on a shared counter or tree structure.

[0098] In the above embodiments, if there exists a logic function F whose input variables, such as A and B, satisfy symmetry (meaning that changing them does not affect the output), then these combinations of variables exhibit similar logical behavior in the Boolean function space. This invention introduces a structural factorization operation into this type of combinational logic, constructing common sub-expressions as intermediate nodes (such as A AND B, A OR B), and replacing repeated paths in the original expression, thereby achieving logical convergence and reuse.

[0099] Furthermore, this method does not rely on user-specified templates. Instead, it automatically identifies, rewrites, and generates optimized RTL structures through formalized symmetry criteria and Boolean algebra transformation rules. Compared to the gate-level compression strategies of traditional synthesis tools, this application optimizes the logic structure at the semantic level, combining scalability and interpretability. It is particularly suitable for area optimization and low-power design of large-scale combinational logic modules.

[0100] In some optional embodiments, generating a transposed gate structure based on the variables involved in the symmetric logic includes: splitting the symmetric logic into at least one AND gate and / or at least one OR gate based on the variables involved in the symmetric logic; and generating a transposed gate structure based on the at least one AND gate and / or at least one OR gate obtained from the splitting.

[0101] A transpose gate is a special type of combinational logic module. Its principle lies in utilizing the symmetry of the input variable set to combine multiple logical operations into a single AND gate and an OR gate. For example, for a pair of symmetrical inputs (A, B), a 2-input AND gate and a 2-input OR gate can be introduced to compute A∧B and A∨B respectively. Since symmetric logic only cares about the number and distribution of inputs, these two outputs (A∧B and A∨B) become the basic building blocks for constructing symmetric logic.

[0102] In some optional embodiments, the combinational logic circuit expression is optimized based on the transposed gate structure, including: determining the target position in the combinational logic circuit expression where the variables involved in the symmetric logic first participate in the operation; inserting the transposed gate structure at the target position; and changing the expression in the combinational logic circuit expression that involves the transposed gate structure to a reference to the transposed gate structure.

[0103] The target position is the location where the transpose gate is inserted. Generally, the transpose gate is inserted when the symmetric variables first participate in the operation together, and adjacent symmetric groups are merged as much as possible. Therefore, it is necessary to first determine the target position where the variables involved in the symmetric logic first participate in the operation together in the combinational logic circuit expression.

[0104] Subsequently, transpose gate instances are inserted at the target location in the data stream, and the corresponding subexpressions in the original logic are changed to reference the transpose gate output. For example, if the original logic has F=(A AND B)OR(A OR B)AND C and (A,B) is determined to be symmetric, then a set of transpose gates can be inserted to obtain T1=A AND B, T2=A OR B, and F is rewritten as F=(T1) OR (T2 ANDC). The original RTL code, together with a shell script, generates the final RTL code, completing the automatic output of the RTL.

[0105] In the above embodiments, area and power efficiency can be significantly improved in symmetric logic scenarios, offering advantages such as simplicity, high efficiency, and hardware friendliness. The method of this application can be integrated into existing EDA toolchains or preceding them to automatically perform symmetric optimization of circuit structures during RTL generation or logic synthesis stages, thereby effectively improving logic cell reuse, reducing gate-level redundancy, and ultimately enhancing integrated circuit area utilization and power efficiency. The method of this application is applicable to automated modeling and optimization of standard cell design flows, FPGA synthesis flows, and custom logic modules.

[0106] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0107] Based on the same inventive concept, this application also provides a combinational logic circuit optimization apparatus for implementing the combinational logic circuit optimization method described above. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more examples of the combinational logic circuit optimization apparatus provided below can be found in the limitations of the combinational logic circuit optimization method described above, and will not be repeated here.

[0108] In one exemplary embodiment, such as Figure 4As shown, a combinational logic circuit optimization device is provided, comprising: an expression acquisition module 401, a symmetric logic recognition module 402, a transpose gate structure generation module 403, and an optimization module 404, wherein:

[0109] Expression acquisition module 401 is used to acquire the combinational logic circuit expression to be optimized;

[0110] The symmetric logic identification module 402 is used to identify symmetric logic in combinational logic circuit expressions and determine the symmetric logic in the combinational logic circuit expressions.

[0111] Transposed gate structure generation module 403 is used to generate transposed gate structures based on the variables involved in symmetric logic;

[0112] Optimization module 404 is used to optimize the expression of combinational logic circuits based on the transposed gate structure.

[0113] In one optional embodiment, the symmetric logic identification module 402 is further configured to determine the variables involved in the combinational logic circuit expression and the number of times the variables appear in the combinational logic circuit expression; if the number of occurrences is greater than a threshold, extract the common factor in the combinational logic circuit expression based on the variables whose number of occurrences is greater than the threshold; and obtain the symmetric logic in the combinational logic circuit expression based on the variables involved in the common factor.

[0114] In one optional embodiment, the symmetric logic identification module 402 is further configured to extract like terms from the combinational logic circuit expression to obtain the common factor if the combinational logic circuit expression is completely symmetric logic.

[0115] In one optional embodiment, the symmetric logic identification module 402 is further configured to factorize the combinational logic circuit expression, which is partially symmetric logic, based on variables whose occurrence frequency is greater than a threshold, to obtain a common factor.

[0116] In one optional embodiment, the transpose gate structure generation module 403 is further configured to split the symmetric logic into at least one AND gate and / or at least one OR gate based on the variables involved in the symmetric logic; and generate a transpose gate structure based on the at least one AND gate and / or at least one OR gate obtained from the split.

[0117] In one optional embodiment, the optimization module 404 is further configured to determine the target position in the combinational logic circuit expression where the variables involved in the symmetric logic first participate in the operation; insert the transposed gate structure into the target position; and change the expression in the combinational logic circuit expression that involves the transposed gate structure to a reference to the transposed gate structure.

[0118] Each module in the aforementioned combinational logic circuit optimization device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in a computer device, or stored in software within the memory of the computer device, so that the processor can invoke and execute the operations corresponding to each module.

[0119] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 5 As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a combinational logic circuit optimization method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0120] Those skilled in the art will understand that Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0121] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0122] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0123] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0124] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0125] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0126] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for optimizing combinational logic circuits, characterized in that, The method includes: Obtain the combinational logic circuit expression to be optimized; Perform symmetric logic identification on the combinational logic circuit expression to determine the symmetric logic in the combinational logic circuit expression; The transpose gate structure is generated based on the variables involved in the symmetric logic. The combinational logic circuit expression is optimized based on the transposed gate structure. The step of performing symmetric logic identification on the combinational logic circuit expression to determine the symmetric logic in the combinational logic circuit expression includes: Determine the variables involved in the combinational logic circuit expression and the number of times the variables appear in the combinational logic circuit expression; If the number of occurrences exceeds a threshold, the common factor in the combinational logic circuit expression is extracted based on the variable whose number of occurrences exceeds the threshold. Based on the variables involved in the common factor, the symmetric logic in the combinational logic circuit expression is obtained.

2. The method according to claim 1, characterized in that, The step of extracting the common factor from the combinational logic circuit expression based on the variables whose occurrence frequency is greater than a threshold includes: If the combinational logic circuit expression is a completely symmetrical logic, then the combinational logic circuit expression is subjected to like terms extraction to obtain the common factor.

3. The method according to claim 1, characterized in that, The step of extracting the common factor from the combinational logic circuit expression based on the variables whose occurrence frequency is greater than a threshold includes: If the combinational logic circuit expression is partially symmetric logic, the combinational logic circuit expression is factored based on the variables that appear more than a threshold number of times to obtain a common factor.

4. The method according to any one of claims 1 to 3, characterized in that, The variable generation transpose gate structure based on the symmetric logic includes: Based on the variables involved in the symmetric logic, the symmetric logic is decomposed into at least one AND gate and / or at least one OR gate; Based on at least one AND gate and / or at least one OR gate obtained from the split, a transposed gate structure is generated.

5. The method according to any one of claims 1 to 3, characterized in that, The optimization of the combinational logic circuit expression based on the transposed gate structure includes: Determine the target position in the combinational logic circuit expression where the variables involved in the symmetric logic first participate in the operation together; Insert the transposed gate structure into the target position, and change the expression in the combinational logic circuit expression that involves the transposed gate structure to reference the transposed gate structure.

6. A combinational logic circuit optimization device, characterized in that, The device includes: The expression acquisition module is used to acquire the combinational logic circuit expression to be optimized; A symmetric logic identification module is used to perform symmetric logic identification on the combinational logic circuit expression and determine the symmetric logic in the combinational logic circuit expression. A transpose gate structure generation module is used to generate transpose gate structures based on the variables involved in the symmetric logic; An optimization module is used to optimize the combinational logic circuit expression based on the transposed gate structure; The symmetric logic identification module is specifically used to determine the variables involved in the combinational logic circuit expression and the number of times the variables appear in the combinational logic circuit expression; if the number of occurrences is greater than a threshold, the module extracts the common factor in the combinational logic circuit expression based on the variables whose number of occurrences is greater than the threshold; and obtains the symmetric logic in the combinational logic circuit expression based on the variables involved in the common factor.

7. The apparatus according to claim 6, characterized in that, The symmetric logic identification module is specifically used to extract like terms from the combinational logic circuit expression if the combinational logic circuit expression is completely symmetric logic, thereby obtaining the common factor.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 5.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.

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