Stage circuit

Abstract

The invention relates to a stage circuit. The stage circuit includes: a first transistor coupled between the first input terminal and the fourth node, where a gate electrode of the first transistor is coupled to the second input terminal; a tenth transistor coupled between the output terminal and a second power supply line, in which a gate electrode of the tenth transistor is coupled to the second node; a third capacitor coupled between the second node and a seventh node; a third transistor coupled between the seventh node and a third input terminal, in which a gate electrode of the third transistor is coupled to the second node; and a second transistor coupled between the seventh node and the first power supply line, in which a gate electrode of the second transistor is coupled to the third node, in which a first conductor including a first electrode of the third capacitor, a gate electrode of the third transistor, and a gate electrode of the tenth transistor is disposed in a first conductive layer, and in which a second conductor including a second electrode of the tenth transistor is disposed in a second conductive layer. The first conductor forms a second node.

Description

[0001] This application is a divisional application of the invention patent application with the application date of March 17, 2020, application number 202010186275.4, and invention name “Level circuit and emission control driver with the stage circuit”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0030721, filed on March 18, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0004] Exemplary embodiments of the present disclosure generally relate to a stage circuit (stage) and an emission control driver having the stage circuit (stage). Background Art

[0005] An organic light emitting display (OLED) has advantages over other types of displays in that a response speed of the organic light emitting display (OLED) is high and the organic light emitting display (OLED) has low power consumption.

[0006] An emission control driver provided in an OLED can control the emission time of a pixel by supplying an emission control signal to an emission control line. For this operation, the emission control driver includes multiple stages coupled to respective emission control lines. Each of the stages may include multiple transistors and capacitors.

[0007] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute the prior art. Summary of the Invention

[0008] Exemplary embodiments of the present disclosure provide a stage circuit capable of stably maintaining a voltage of a node for controlling output of an emission control signal at a high voltage while maintaining the emission control signal at a low voltage, and an emission control driver having the same.

[0009] Exemplary embodiments of the present disclosure also provide a stage circuit configured such that a capacitor provided in the stage circuit can be prevented from being charged or discharged while maintaining an emission control signal at a low voltage, and an emission control driver having the stage circuit.

[0010] Additional features of the present inventive concept will be set forth in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the present inventive concept.

[0011] An exemplary embodiment of the present disclosure provides a stage circuit, the stage circuit comprising: an output circuit configured to supply a voltage of a first power supply or a second power supply to an output terminal in response to a voltage of a first node and a voltage of a second node; an input circuit configured to control the voltage of the second node and the voltage of a third node in response to respective signals supplied to a first input terminal and a second input terminal; a first signal processor configured to control the voltage of the first node in response to the voltage of the second node; a second signal processor coupled between the first node and the third node and configured to control the voltage of the first node in response to an output voltage of the third signal processor and a signal supplied to a third input terminal; and a third signal processor configured to control the voltage of the second node in response to a signal supplied to the first input terminal. The third signal processor comprises: a third capacitor coupled between the first power supply and the second node; and a third transistor coupled between the first power supply and the third input terminal and including a gate electrode coupled to the second node.

[0012] When the voltage of the first power source is supplied to the output terminal in response to the voltage of the second node, the third transistor may be turned off so as to block a path of current flowing from the second input terminal to the second node.

[0013] While the voltage of the first power source is supplied to the output terminal in response to the voltage of the second node, a potential difference between opposite ends of the third capacitor may be maintained constant.

[0014] The third signal processor may further include a second transistor coupled between the first power supply and a common node between the third capacitor and the third transistor, the second transistor including a gate electrode coupled to the third node. When the voltage of the first power supply is supplied to the output terminal in response to the voltage of the second node, the voltage of the first power supply may be applied to the second node via the second transistor and the third capacitor.

[0015] The second input terminal may be supplied with a first clock signal, the third input terminal may be supplied with a second clock signal, and the first clock signal and the second clock signal may have the same waveform with a phase difference of half a cycle or more.

[0016] A gate-on voltage portion of the signal supplied to the first input terminal may overlap a gate-on voltage portion of the first clock signal at least once.

[0017] The third signal processor may further include: a fourth transistor coupled between the third node and the second input terminal and including a gate electrode coupled to the second node; and a fifth transistor coupled between the third node and the second power supply and including a gate electrode coupled to the second input terminal.

[0018] The fourth transistor may include a plurality of sub-transistors coupled in series between the third node and the second input terminal. Gate electrodes of the plurality of sub-transistors may be coupled to the second node.

[0019] The third signal processor may include: a thirteenth transistor coupled between the first power supply and the eighth node and including a gate electrode coupled to the third node; and a fourteenth transistor coupled between the eighth node and the second node and including a gate electrode coupled to the third input terminal.

[0020] The input circuit may include a first transistor coupled between the first input terminal and the second node, the first transistor including a gate electrode coupled to the second input terminal.

[0021] The second signal processor may include: a second capacitor coupled between the third node and a sixth node; a sixth transistor coupled between the sixth node and the third input terminal and including a gate electrode coupled to the third node; and a seventh transistor coupled between the first node and the sixth node and including a gate electrode coupled to the third input terminal.

[0022] The first signal processor may include a first capacitor coupled between the first power supply and the first node; and an eighth transistor coupled between the first power supply and the first node and including a gate electrode coupled to the second node.

[0023] The output circuit may include: a ninth transistor coupled between the first power supply and the output terminal and including a gate electrode coupled to the first node; and a tenth transistor coupled between the output terminal and the second power supply and including a gate electrode coupled to the second node.

[0024] The stage circuit may further include a first stabilizer coupled between the second signal processor and the third signal processor and configured to control a voltage drop width of the third node.

[0025] The stage circuit may further include a second stabilizer coupled between the second node and a fourth node coupled to the first input terminal, the second stabilizer configured to control a voltage drop width of the second node.

[0026] The stage circuit may further include: a first gate insulating layer configured to cover a source electrode and a drain electrode of at least one transistor; a second gate insulating layer configured to cover a gate electrode of the at least one transistor and a first electrode of at least one capacitor; and an interlayer insulating layer configured to cover a second electrode of the at least one capacitor. The second gate insulating layer may cover a line extending from the gate electrode of the third transistor to the second node. The line may be arranged so as not to overlap with the source electrode and the drain electrode covered by the first gate insulating layer, or not to overlap with the second electrode covered by the interlayer insulating layer.

[0027] Another exemplary embodiment of the present disclosure provides an emission control driver, comprising a plurality of stage circuits configured to supply emission signals to emission control lines. Each of the plurality of stage circuits may include: an output circuit configured to supply a voltage of a first power supply or a second power supply to an output terminal in response to a voltage of a first node and a voltage of a second node; an input circuit configured to control the voltage of the second node and the voltage of a third node in response to respective signals supplied to a first input terminal and a second input terminal; a first signal processor configured to control the voltage of the first node in response to the voltage of the second node; a second signal processor connected between the first node and the third node and configured to control the voltage of the first node in response to a signal supplied to the second input terminal and a signal supplied to the third input terminal; and a third signal processor configured to control the voltage of the second node in response to a signal supplied to the first input terminal. The third signal processor may include: a third capacitor coupled between the first power supply and the second node; and a third transistor coupled between the first power supply and the third input terminal and including a gate electrode coupled to the second node.

[0028] When the voltage of the first power source is supplied to the output terminal in response to the voltage of the second node, the third transistor may be turned off so as to block a path of current flowing from the second input terminal to the second node.

[0029] While the voltage of the first power source is supplied to the output terminal in response to the voltage of the second node, a potential difference between opposite ends of the third capacitor may be maintained constant.

[0030] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and together with the description serve to explain the inventive concept.

[0032] Figure 1 is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0033] Figure 2 It is schematically shown Figure 1 The diagram of the emission control driver is shown in .

[0034] Figure 3 According to the first exemplary embodiment of the present disclosure Figure 2 The circuit diagram of the stage is shown in .

[0035] Figure 4 According to the second exemplary embodiment of the present disclosure Figure 2 The circuit diagram of the stage is shown in .

[0036] Figure 5 It shows Figure 3 The waveform diagram of the operation of the stage is shown in FIG.

[0037] Figure 6 According to the third exemplary embodiment of the present disclosure Figure 2 The circuit diagram of the stage is shown in .

[0038] Figure 7 According to the fourth exemplary embodiment of the present disclosure Figure 2 The circuit diagram of the stage is shown in .

[0039] Figure 8 It shows Figure 7 The waveform diagram of the operation of the stage is shown in FIG.

[0040] Figure 9 is a plan view illustrating a layout of stages according to an exemplary embodiment of the present disclosure.

[0041] Figure 10 It is along Figure 9 A cross-sectional view taken along line II'. DETAILED DESCRIPTION

[0042] In the following description, for the purpose of illustration, many specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments of the present disclosure. As used herein, an "embodiment" is a non-limiting example of a device or method using one or more inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other examples, well-known structures and devices are shown in block diagram form to avoid unnecessary confusion of various exemplary embodiments. In addition, various exemplary embodiments may be different, but are not necessarily exclusive. For example, without departing from the present invention, the specific shape, configuration and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment.

[0043] Unless otherwise indicated, the exemplary embodiments shown are to be understood as providing exemplary features of variable detail of some ways in which the inventive concept may be implemented in practice. Therefore, unless otherwise indicated, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0044] Cross hatching and / or shading are generally provided in the drawings to illustrate the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material properties, dimensions, proportions, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0045] When an element such as a layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, the element may be directly on, directly connected to or directly coupled to the other element or layer, or there may be an intermediate element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intermediate elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection and / or a fluid connection with or without intermediate elements. In addition, the D1 axis, the D2 axis and the D3 axis are not limited to the three axes of a rectangular coordinate system such as the x-axis, the y-axis and the z-axis, and may be interpreted in a broader sense. For example, the D1 axis, the D2 axis and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0046] Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0047] For descriptive purposes, spatially relative terms such as "under," "beneath," "beneath," "down," "above," "upper," "above," "higher," and "side" (e.g., as in "sidewall") may be used herein to describe the relationship of one element(s) to another element(s) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features. Thus, the exemplary term "under" can encompass both the orientations "above" and "under." Furthermore, the device can be oriented in other ways (e.g., rotated 90 degrees or at other orientations), and therefore, the spatially relative descriptors used herein are interpreted accordingly.

[0048] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "one", "a kind of" and "said (the)" are also intended to include plural forms. In addition, when used in this specification, the terms "comprise", "include", "contain" and / or "have" illustrate the presence of stated features, integral bodies, steps, operations, elements, components and / or their groups, but do not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or their groups. It is also noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms rather than degree terms, therefore, for illustrating the inherent deviation of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0049] Various exemplary embodiments are described herein with reference to cross-sectional and / or exploded views that are idealized exemplary embodiments and / or intermediate structures. As such, variations from the shapes of the illustrations due, for example, to manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments disclosed herein should not be necessarily construed as limited to the shapes of the specifically illustrated regions, but are to include deviations in shape that result, for example, from manufacturing. In this manner, the regions illustrated in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of regions of a device and, therefore, are not necessarily intended to be limiting.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. Unless explicitly defined as such herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0051] Figure 1 is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0052] Reference Figure 1 , a display device according to an exemplary embodiment of the present disclosure may include a pixel unit 10 , a scan driver 20 , a data driver 30 , an emission control driver 40 , and a timing controller 50 .

[0053] The pixel unit 10 may include a plurality of pixels PX, which are coupled to scan lines S1 to Sn, data lines D1 to Dm, and emission control lines E1 to En and arranged in a matrix. The pixels PX may receive scan signals via the scan lines S1 to Sn, may receive data signals via the data lines D1 to Dm, and may receive emission control signals via the emission control lines E1 to En. When scan signals are supplied from the scan lines S1 to Sn to the pixels PX, the pixels PX may emit light at a brightness level corresponding to the data signals supplied from the data lines D1 to Dm.

[0054] The scan driver 20 may be coupled to a plurality of scan lines S1 to Sn, generate scan signals in response to scan drive control signals SCS from the timing controller 50, and output the generated scan signals to the scan lines S1 to Sn. The scan driver 20 may be formed of a plurality of stage circuits. When the scan signals are sequentially supplied to the scan lines S1 to Sn, the pixels PX may be selected on a horizontal line basis.

[0055] The data driver 30 may be coupled to a plurality of data lines D1 to Dm, generate data signals based on image data DATA' and a data drive control signal DCS from the timing controller 50, and output the generated data signals to the data lines D1 to Dm. Each time a scan signal is supplied, the data signals supplied to the data lines D1 to Dm may be supplied to the pixels PX selected by the scan signal. The pixels PX may then be charged with a voltage corresponding to the data signal.

[0056] The emission control driver 40 may be coupled to the emission control lines E1 to En, generate emission control signals in response to the emission drive control signals ECS of the timing controller 50, and output the generated emission control signals to the emission control lines E1 to En. The emission control driver 40 may be formed of a plurality of stage circuits and controls the emission period of the pixel PX by supplying the emission control signals to the emission control lines E1 to En.

[0057] The timing controller 50 can receive image data DATA as well as synchronization signals Hsync and Vsync, a clock signal CLK, and the like to control the display of an image corresponding to the image data DATA. The timing controller 50 can perform image processing on the input image data DATA, generate compensated image data DATA' suitable for image display of the pixel unit 10, and output the image data DATA' to the data driver 30. The timing controller 50 can generate drive control signals SCS, DCS, and ECS to control the operation of the scan driver 20, the data driver 30, and the emission control driver 40 based on the synchronization signals Hsync and Vsync and the clock signal CLK. In detail, the timing controller 50 can generate a scan drive control signal SCS and supply the scan drive control signal SCS to the scan driver 20, generate a data drive control signal DCS and supply the data drive control signal DCS to the data driver 30, and generate an emission drive control signal ECS and supply the emission drive control signal ECS to the emission control driver 40.

[0058] Figure 2 It is schematically shown Figure 1 FIG. 4 is a diagram of the emission control driver 40 shown in FIG.

[0059] Common Reference Figure 1 and Figure 2 The emission control driver 40 according to an exemplary embodiment of the present disclosure may include a plurality of stages 401, 402, 403, ... to supply emission control signals to the emission control lines E1 to En. In this exemplary embodiment, for illustration, only three stages 401, 402, and 403 are shown.

[0060] Stages 401, 402, and 403 may be driven by a start signal FLM and first and second clock signals CLK1 and CLK2 and output emission control signals EM1, EM2, and EM3, respectively. The start signal FLM and first and second clock signals CLK1 and CLK2 may be received via an emission drive control signal ECS provided from a timing controller 50.

[0061] In an exemplary embodiment of the present disclosure, stages 401 , 402 , and 403 may be formed of the same or different circuits.

[0062] Each of the stages 401 , 402 , 403 , . . . may include a first input terminal 101 , a second input terminal 102 , a third input terminal 103 and an output terminal 104 .

[0063] The first input terminal 101 may be supplied with a start signal FLM or an emission control signal EM1, EM2, EM3, ... of a previous stage. The second input terminal 102 and the third input terminal 103 may be supplied with any one of a first clock signal CLK1 and a second clock signal CLK2. The signal output to the output terminal 104 may be used as the emission control signal EM1, EM2, EM3, ...

[0064] In an exemplary embodiment, each of the first clock signal CLK1 and the second clock signal CLK2 can be set to a square wave signal having a logic high level and a logic low level formed repeatedly. The first clock signal CLK1 and the second clock signal CLK2 can be signals having the same waveform with two horizontal periods 2H per cycle. In an exemplary embodiment, the first clock signal CLK1 and the second clock signal CLK2 can be set so that the gate-on voltage periods of the first clock signal CLK1 and the second clock signal CLK2 do not overlap with each other and have a phase difference of half a cycle or greater. However, this is for illustrative purposes only, and the waveform relationship between the first clock signal CLK1 and the second clock signal CLK2 is not limited to this.

[0065] The first stage 401 of the stages 401 , 402 , 403 , . . . may receive the start signal FLM, and each of the stages 402 , 403 , . . . excluding the first stage 401 may receive the emission control signal EM1 , EM2 , EM3 , . . . of the previous stage.

[0066] In an exemplary embodiment, the first stage 401 can directly receive the first clock signal CLK1 and the second clock signal CLK2, and each of the stages 402, 403, ... except the first stage 401 can receive any one of the first clock signal CLK1 and the second clock signal CLK2 from the previous stage. In detail, each of the odd-numbered stages 403, ... except the first stage 401 can receive the first clock signal CLK1 from the previous stage and directly receive the second clock signal CLK2. Each of the even-numbered stages 402, ... can directly receive the first clock signal CLK1 and receive the second clock signal CLK2 from the previous stage. However, the present invention is not limited to this, and all stages 401, 402, 403, ... can directly receive the first clock signal CLK1 and the second clock signal CLK2.

[0067] exist Figure 2In an exemplary embodiment of the present invention, the first stage 401 may output a first emission control signal EM1 in response to a start signal FLM and a first clock signal CLK1 and a second clock signal CLK2, and transmit the second clock signal CLK2 and the first emission control signal EM1 to the second stage 402. The second stage 402 may output a second emission control signal EM2 in response to the first clock signal CLK1 and the second clock signal CLK2 and the first emission control signal EM1 transmitted from the first stage 401, and transmit the first clock signal CLK1 and the second emission control signal EM2 to the third stage 403. The third stage 403 may output a third emission control signal EM3 in response to the second clock signal CLK2 and the first clock signal CLK1 and the second emission control signal EM2 transmitted from the second stage 402, and transmit the second clock signal CLK2 and the third emission control signal EM3 to a fourth stage (not shown).

[0068] Figure 3 According to the first exemplary embodiment Figure 2 The circuit diagram of the stage shown in the Figure 4 According to the second exemplary embodiment Figure 2 Although for illustration purposes, Figure 3 and Figure 4 Only level i is shown, but Figure 2 The stage shown in may have the same structure as that of the i-th stage to be described below.

[0069] Reference Figures 1 to 3 , the stage 400 according to the first exemplary embodiment of the present disclosure may include an input circuit 410 , an output circuit 420 , a first signal processor 430 , a second signal processor 440 , a third signal processor 450 , a first stabilizer 461 , and a second stabilizer 462 .

[0070] The output circuit 420 may supply the voltage of the first power supply VDD or the second power supply VSS to the output terminal 104 in response to the voltages of the first and second nodes N1 and N2. To this end, the output circuit 420 may include a ninth transistor M9 and a tenth transistor M10.

[0071] The ninth transistor M9 is coupled between the first power supply VDD and the output terminal 104. The gate electrode of the ninth transistor M9 can be coupled to the first node N1. The ninth transistor M9 can be turned on or off according to the voltage of the first node N1. Here, when the ninth transistor M9 is turned on, the voltage of the first power supply VDD supplied to the output terminal 104 can be supplied to the i-th emission control line Ei and can be used as the emission control signal EM[i] with a gate-on level.

[0072] The tenth transistor M10 is coupled between the output terminal 104 and the second power supply VSS. The gate electrode of the tenth transistor M10 is coupled to the second node N2. The tenth transistor M10 can be turned on or off according to the voltage of the second node N2. Here, when the tenth transistor M10 is turned on, the voltage of the second power supply VSS supplied to the output terminal 104 can be supplied to the i-th emission control line Ei and can be used as the emission control signal EM[i] having a gate-off level. In an exemplary embodiment, when the emission control signal EM[i] has a gate-off level, it is understood that the emission control signal EM[i] is not supplied.

[0073] The input circuit 410 may control voltages of the second node N2 and the fourth node N4 in response to signals supplied to the first input terminal 101 and the second input terminal 102. To this end, the input circuit 410 may include a first transistor M1.

[0074] The first transistor M1 is coupled between the first input terminal 101 and the fourth node N4. The gate electrode of the first transistor M1 is coupled to the second input terminal 102. When the first clock signal CLK1 is supplied to the second input terminal 102, the first transistor M1 may be turned on to electrically couple the first input terminal 101 to the fourth node N4.

[0075] The first signal processor 430 may control the voltage of the first node N1 in response to the voltages of the second node N2 and the fourth node N4. To this end, the first signal processor 430 may include an eighth transistor M8 and a first capacitor C1.

[0076] The eighth transistor M8 is coupled between the first power supply VDD and the first node N1. The gate electrode of the eighth transistor M8 can be coupled to the fourth node N4. The eighth transistor M8 can be turned on or off according to the voltage of the fourth node N4. Here, when the eighth transistor M8 is turned on, the voltage of the first power supply VDD can be supplied to the first node N1.

[0077] The first capacitor C1 is coupled between the first power source VDD and the first node N1. The first capacitor C1 can charge a voltage to be applied to the first node N1. In addition, the first capacitor C1 can stably maintain the voltage of the first node N1.

[0078] The second signal processor 440 is coupled to the fifth node N5 and may control the voltage of the first node N1 in response to a signal input to the third input terminal 103. To this end, the second signal processor 440 may include a sixth transistor M6, a seventh transistor M7, and a second capacitor C2.

[0079] A first terminal of the second capacitor C2 is coupled to the fifth node N5 , and a second terminal of the second capacitor C2 is coupled to a sixth node N6 , which is a common node between the sixth transistor M6 and the seventh transistor M7 .

[0080] The sixth transistor M6 is coupled between the sixth node N6 and the third input terminal 103. A gate electrode of the sixth transistor M6 is coupled to the fifth node N5. The sixth transistor M6 may be turned on according to the voltage of the fifth node N5 so that a voltage corresponding to the second clock signal CLK2 supplied to the third input terminal 103 may be applied to the sixth node N6.

[0081] The seventh transistor M7 is coupled between the first power supply VDD and the sixth node N6. A gate electrode of the seventh transistor M7 is coupled to the third input terminal 103. The seventh transistor M7 can be turned on in response to the second clock signal CLK2 supplied to the third input terminal 103, thereby applying the voltage of the first power supply VDD to the sixth node N6.

[0082] The third signal processor 450 may control the voltage of the third node N3. To this end, the third signal processor 450 may include a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a third capacitor C3.

[0083] A first electrode of the third capacitor C3 is coupled to the second node N2 , and a second electrode of the third capacitor C3 is coupled to a seventh node N7 , which is a common node between the second transistor M2 and the third transistor M3 .

[0084] The second transistor M2 is coupled between the first power source VDD and the seventh node N7. A gate electrode of the second transistor M2 is coupled to the third node N3. The second transistor M2 can be turned on or off according to the voltage of the third node N3.

[0085] The third transistor M3 is coupled between the seventh node N7 and the third input terminal 103. A gate electrode of the third transistor M3 is coupled to the second node N2. The third transistor M3 may be turned on or off according to a voltage of the second node N2.

[0086] The fourth transistor M4 is coupled between the third node N3 and the second input terminal 102. The gate electrode of the fourth transistor M4 is coupled to the fourth node N4. Figure 4As shown in FIG, the fourth transistor M4 may include a 4-1st sub-transistor M4-1 and a 4-2nd sub-transistor M4-2 coupled in series between the third node N3 and the second input terminal 102. In this exemplary embodiment, the gate electrode of each of the 4-1st sub-transistor M4-1 and the 4-2nd sub-transistor M4-2 is coupled to the fourth node N4. If the fourth transistor M4 is formed by a plurality of sub-transistors M4-1 and M4-2, even when there is a large potential difference between the third node N3 and the fourth node N4, a current path can be reliably formed between the third node N3 and the second input terminal 102 in response to the potential difference between the third node N3 and the fourth node N4.

[0087] The fifth transistor M5 is coupled between the third node N3 and the second power supply VSS. A gate electrode of the fifth transistor M5 is coupled to the second input terminal 102. When the first clock signal CLK1 is supplied to the second input terminal 102, the fifth transistor M5 is turned on, so that the voltage of the second power supply VSS can be supplied to the third node N3.

[0088] The first stabilizer 461 is coupled between the second signal processor 440 and the third signal processor 450. The first stabilizer 461 may limit the voltage drop width of the third node N3. To this end, the first stabilizer 461 may include an eleventh transistor M11.

[0089] The eleventh transistor M11 is coupled between the third node N3 and the fifth node N5. The gate electrode of the eleventh transistor M11 is coupled to the second power supply VSS. Since the second power supply VSS has a gate-on level voltage, the eleventh transistor M11 can always remain on. Therefore, the third node N3 and the fifth node N5 can be maintained at the same voltage and operate as substantially the same node.

[0090] The second stabilizer 462 is coupled between the second node N2 and the fourth node N4. The second stabilizer 462 can limit the voltage drop width of the second node N2. To this end, the second stabilizer 462 can include a twelfth transistor M12.

[0091] The twelfth transistor M12 is coupled between the second node N2 and the fourth node N4. The gate electrode of the twelfth transistor M12 is coupled to the second power supply VSS. Since the second power supply VSS has a gate-off level voltage, the twelfth transistor M12 can always remain on. Therefore, the second node N2 and the fourth node N4 can be maintained at the same voltage and operate as substantially the same node.

[0092] In exemplary embodiments of the present disclosure, each of the first to twelfth transistors M1 to M12 may be formed of a p-type transistor. In these exemplary embodiments, the gate-on voltage of the first to twelfth transistors M1 to M12 may be set to a low level, and the gate-off voltage of the first to twelfth transistors M1 to M12 may be set to a high level.

[0093] Figure 5 It shows Figure 3 For illustration purposes, Figure 5 Only the operation of the i-th stage is shown.

[0094] Reference Figure 5 , the first clock signal CLK1 and the second clock signal CLK2 may each have a period of two horizontal periods (2H) and have a gate-on level during different horizontal periods. In other words, the second clock signal CLK2 may be set to a signal that is offset from the first clock signal CLK1 by half a period (i.e., one horizontal period (1H)).

[0095] When the clock signals CLK1 and CLK2 are supplied, the second input terminal 102 and the third input terminal 103 can be set to a low level, that is, the voltage of the second power supply VSS. When the clock signals CLK1 and CLK2 are not supplied, the second input terminal 102 and the third input terminal 103 can be set to a high level, that is, the voltage of the first power supply VDD.

[0096] When the start signal FLM or the emission control signal EM[i-1] of the previous stage is supplied, the first input terminal 101 can be set to a high level, that is, the voltage of the first power supply VDD. When the start signal FLM or the emission control signal EM[i-1] of the previous stage is not supplied, the first input terminal 101 can be set to a low level, that is, the voltage of the second power supply VSS.

[0097] In addition, the start signal FLM to be supplied to the first input terminal 101 or the emission control signal EM[i-1] of the previous stage can be set to overlap at least once with the first clock signal CLK1 to be supplied to the second input terminal 102. To this end, the start signal FLM (or the emission control signal EM[i-1] of the previous stage) can have a width greater than the width of the first clock signal CLK1. For example, the start signal FLM (or the emission control signal EM[i-1] of the previous stage) can be supplied during four horizontal periods (4H). In this case, the first emission control signal to be supplied to the first input terminal 101 of the next stage can also overlap at least once with the second clock signal CLK2 to be supplied to the second input terminal 102 of the next stage.

[0098] The operation process will be described below. First, during a first period t1, the first clock signal CLK1 may be supplied to the second input terminal 102. As a result, the first transistor M1 and the fifth transistor M5 may be turned on. In addition, during the first period t1, the second clock signal CLK2 may not be supplied to the third input terminal 103. Therefore, the seventh transistor M7 may be turned off.

[0099] When the first transistor M1 is turned on, the first input terminal 101 and the fourth node N4 may be electrically coupled to each other. Since the twelfth transistor M12 remains turned on, the first input terminal 101 may also be electrically coupled to the second node N2 via the fourth node N4.

[0100] Since the start signal FLM to be supplied to the first input terminal 101 or the emission control signal EM[i-1] of the previous stage has a low level during the first period t1, a low level (e.g., the voltage of the second power supply VSS) may be applied to the fourth node N4 and the second node N2. When the fourth node N4 and the second node N2 are set to a low voltage, the third transistor M3, the fourth transistor M4, the eighth transistor M8, and the tenth transistor M10 may be turned on.

[0101] When the third transistor M3 is turned on, the third input terminal 103 and the seventh node N7 can be electrically coupled to each other. Since the second clock signal CLK2 is not supplied to the third input terminal 103 during the first period t1, a high voltage can be supplied to the seventh node N7. However, the third capacitor C3 can be charged with a voltage corresponding to the on-state of the third transistor M3.

[0102] When the fourth transistor M4 is turned on, the fifth transistor M5 can be connected in a diode-like manner between the third node N3 and the second power supply VSS. Therefore, even when the fifth transistor M5 is turned on during the first period t1, the voltage of the second power supply VSS is not transmitted to the third node N3, and the voltage of the third node N3 can be maintained at the voltage of the previous state, for example, a high voltage. Since the eleventh transistor M11 remains turned on, the high voltage of the third node N3 can be applied to the fifth node N5, and the fifth node N5 can be set to a high voltage. As a result, the second transistor M2 and the sixth transistor M6 can be turned off.

[0103] When the eighth transistor M8 is turned on, the voltage of the first power source VDD may be supplied to the first node N1. Therefore, the ninth transistor M9 may be turned off.

[0104] When the tenth transistor M10 is turned on, the voltage of the second power source VSS may be supplied to the output terminal 104. Therefore, during the first period t1, the emission control signal EM[i] may not be supplied to the emission control line Ei.

[0105] During the second period t2, the supply of the first clock signal CLK1 to the second input terminal 102 may be interrupted. When the supply of the first clock signal CLK1 is interrupted, the first transistor M1 and the fifth transistor M5 may be turned off. Here, the first node N1 and the second node N2 may maintain the voltage of the previous period via the first capacitor C1 and the third capacitor C3. Since the first node N1 remains in a high voltage state, the ninth transistor M9 may remain turned off. Since the second node N2 remains in a low voltage state, the third transistor M3, the fourth transistor M4, the eighth transistor M8, and the tenth transistor M10 may remain turned on.

[0106] During the second period t2, the second clock signal CLK2 may be supplied to the third input terminal 103. The seventh transistor M7 may be turned on by the second clock signal CLK2 supplied to the third input terminal 103. When the seventh transistor M7 is turned on, the first node N1 and the sixth node N6 may be electrically coupled to each other. Therefore, the sixth node N6 may be set to a high voltage.

[0107] During the second period t2, the second clock signal CLK2 may be supplied to the seventh node N7 via the turned-on third transistor M3. Thus, a low voltage is supplied to the seventh node N7. Then, through the coupling of the third capacitor C3, the voltage of the second node N2 may be maintained at a voltage lower than the voltage of the second power supply VSS (two-level low voltage).

[0108] During the third period t3, the supply of the second clock signal CLK2 to the third input terminal 103 may be interrupted. If the supply of the second clock signal CLK2 is interrupted, the seventh transistor M7 may be turned off.

[0109] During the third period t3, the start signal FLM or the emission control signal EM[i-1] of the previous stage may be supplied to the first input terminal 101, and the first clock signal CLK1 may be supplied to the second input terminal 102. When the first clock signal CLK1 is supplied to the second input terminal 102, the first transistor M1 and the fifth transistor M5 may be turned on.

[0110] When the first transistor M1 is turned on, the first input terminal 101 and the fourth node N4 can be electrically coupled to each other. Since the twelfth transistor M12 remains turned on, the first input terminal 101 can also be electrically coupled to the second node N2 via the fourth node N4. Then, the fourth node N4 and the second node N2 can be set to a high voltage by the start signal FLM supplied to the first input terminal 101 or the emission control signal EM[i-1] of the previous stage. When the fourth node N4 and the second node N2 are set to a high voltage, the third transistor M3, the fourth transistor M4, the eighth transistor M8, and the tenth transistor M10 can be turned off.

[0111] If the fifth transistor M5 is turned on, the low voltage of the second power source VSS may be applied to the third node N3, so that the third node N3 and the fifth node N5 are set to a low voltage. Thus, the second transistor M2 and the sixth transistor M6 may be turned on.

[0112] If the second transistor M2 is turned on, the voltage of the first power supply VDD can be applied to the seventh node N7. Therefore, the seventh node N7 can be maintained at a high voltage. Here, because the third transistor M3 remains off, the voltage of the second clock signal CLK2 to be applied to the third input terminal 103 can not be transmitted to the seventh node N7. In addition, because the seventh node N7 and the second node N2, which are opposite ends of the third capacitor C3, are both maintained at a high voltage, the third capacitor C3 can not be charged or discharged. Here, a current path can be formed from the first power supply VDD to the second node N2 via the second transistor M2, and the high voltage of the first power supply VDD can be transmitted to the second node N2. Therefore, the voltage of the second node N2 can be stably maintained at a high level.

[0113] If the sixth transistor M6 is turned on, the third input terminal 103 and the sixth node N6 can be electrically coupled to each other. Since the second clock signal CLK2 is not supplied to the third input terminal 103 during the third period t3, the sixth node N6 can be maintained at a high voltage. Here, since the seventh transistor M7 remains off, the voltage of the sixth node N6 may not affect the voltage of the first node N1. The second capacitor C2 can store a voltage corresponding to the on-level of the sixth transistor M6.

[0114] During the fourth period t4, the second clock signal CLK2 may be supplied to the third input terminal 103. If the second clock signal CLK2 is supplied to the third input terminal 103, the seventh transistor M7 may be turned on.

[0115] If the seventh transistor M7 is turned on, the first node N1 and the sixth node N6 can be electrically coupled to each other. Here, the low voltage of the second clock signal CLK2 supplied to the third input terminal 103 via the sixth transistor M6 that remains turned on can be supplied to the sixth node N6 and the first node N1. When the low voltage is supplied to the first node N1, the ninth transistor M9 can be turned on.

[0116] If the ninth transistor M9 is turned on, the voltage of the first power supply VDD may be supplied to the output terminal 104. The voltage of the first power supply VDD supplied to the output terminal 104 may be supplied to the i-th emission control line Ei as the emission control signal EM[i].

[0117] During the fifth period t5, the supply of the second clock signal CLK2 to the third input terminal 103 may be interrupted. If the supply of the second clock signal CLK2 is interrupted, the seventh transistor M7 may be turned off. Here, the first node N1 may be stably maintained at a high voltage by the first capacitor C1. As a result, the ninth transistor M9 may remain turned on, and the voltage of the first power supply VDD may be supplied to the i-th emission control line Ei as the emission control signal EM[i].

[0118] Although the supply of the second clock signal CLK2 is interrupted during the fifth period t5 , the third transistor M3 remains turned off, and thus, the voltage of the second clock signal CLK2 may not be supplied to the seventh node N7 and may not affect the voltage of the second node N2 .

[0119] As described above, in an exemplary embodiment of the present disclosure, during the supply of the emission control signal EM[i], the third transistor M3, which remains off, can prevent changes in the voltage of the second clock signal CLK2 from affecting the second node N2, thereby allowing the second node N2 to be stably maintained at a high voltage. Furthermore, in an exemplary embodiment of the present disclosure, during the supply of the emission control signal EM[i], the third capacitor C3 can be prevented from charging or discharging. In other words, the third capacitor C3 can not perform a charging or discharging operation at any time except when the voltage of the second node N2 is set to a low level through the coupling of the third capacitor C3. Therefore, in an exemplary embodiment of the present disclosure, during the supply of the emission control signal EM[i], the third capacitor C3 can not act as a load. Therefore, power consumption can be reduced, and reliable output of the emission control signal EM[i] can be ensured.

[0120] Figure 6 According to the third exemplary embodiment of the present disclosure Figure 2 The circuit diagram of the stage is shown in . Figure 6 In the drawings, the same reference numerals are used to denote Figure 3 The components are the same as those of , and their detailed description will be omitted.

[0121] Reference Figure 6 , the stage 400 - 1 according to the third exemplary embodiment of the present disclosure may include an input circuit 410 , an output circuit 420 , a first signal processor 430 , a second signal processor 440 , and a third signal processor 450 .

[0122] The stage 400-1 according to the third exemplary embodiment has the same structure as the first stabilizer 461 and the second stabilizer 462 except that the first stabilizer 461 and the second stabilizer 462 are omitted. Figure 3 Therefore, a detailed description of the operation process will be omitted.

[0123] exist Figure 3In the exemplary embodiment shown in FIG, each of the first stabilizer 461 and the second stabilizer 462 may include a transistor that is always kept on. The transistors of the first stabilizer 461 and the second stabilizer 462 may be provided to reliably control Figure 3 The voltage drop width of the third node N3 and the second node N2 shown in FIG is substantially not affected by the operation of the circuit. Therefore, even if the first stabilizer 461 and the second stabilizer 462 are omitted, Figure 5 The operation process of the circuit shown in still remains unchanged, but the second node N2 and the fourth node N4 may be substantially the same node, and the third node N3 and the fifth node N5 may be substantially the same node.

[0124] although Figure 6 An example is shown in which both the first stabilizer 461 and the second stabilizer 462 are omitted, but the present inventive concept is not limited thereto. In other words, in an exemplary embodiment of the present disclosure, the stage 400 - 1 may be configured such that only the first stabilizer 461 or the second stabilizer 462 is omitted.

[0125] Figure 7 According to the fourth exemplary embodiment of the present disclosure Figure 2 The circuit diagram of the stage is shown in . Although Figure 7 Only the i-th level is shown, but the other levels described below may have the same Figure 2 The structure of the i-th level is the same as that shown in .

[0126] Reference Figure 1 、 Figure 2 and Figure 7 , the stage 400 - 2 according to the fourth embodiment of the present disclosure may include an input circuit 410 , an output circuit 420 , a first signal processor 430 , a second signal processor 440 , a third signal processor 450 - 1 , a first stabilizer 461 , and a second stabilizer 462 .

[0127] The configuration of the stage 400-2 according to the fourth exemplary embodiment is the same as that of the stage 400-2 except that the third signal processor 450-1 further includes a thirteenth transistor M13 and a fourteenth transistor M14. Figure 3 Therefore, detailed description of other components will be omitted.

[0128] The thirteenth transistor M13 is coupled between the first power supply VDD and the eighth node N8. The gate electrode of the thirteenth transistor M13 is coupled to the third node N3. The thirteenth transistor M13 can be turned on in response to the voltage of the fifth node N5 so that the voltage of the first power supply VDD can be supplied to the eighth node N8.

[0129] The fourteenth transistor M14 is coupled between the eighth node N8 and the fourth node N4. A gate electrode of the fourteenth transistor M14 is coupled to the third input terminal 103. When the second clock signal CLK2 is supplied to the third input terminal 103, the fourteenth transistor M14 may be turned on to electrically couple the eighth node N8 and the fourth node N4.

[0130] In exemplary embodiments of the present disclosure, each of the thirteenth transistor M13 and the fourteenth transistor M14 may be formed of a p-type transistor. In these exemplary embodiments, the gate-on voltage of the thirteenth transistor M13 and the fourteenth transistor M14 may be set to a low level, and the gate-off voltage of the thirteenth transistor M13 and the fourteenth transistor M14 may be set to a high level.

[0131] Figure 8 It shows Figure 7 For illustration purposes, Figure 8 Only the operation of the i-th stage is shown.

[0132] The operation process will be described. First, during the first period t1, the first clock signal CLK1 may be supplied to the second input terminal 102. As a result, the first transistor M1 and the fifth transistor M5 may be turned on. In addition, during the first period t1, the second clock signal CLK2 may not be supplied to the third input terminal 103. As a result, the seventh transistor M7 and the fourteenth transistor M14 may be turned off.

[0133] When the first transistor M1 is turned on, the first input terminal 101 and the fourth node N4 may be electrically coupled to each other. Since the twelfth transistor M12 remains turned on, the first input terminal 101 may also be electrically coupled to the second node N2 via the fourth node N4.

[0134] Since the start signal FLM to be supplied to the first input terminal 101 or the emission control signal EM[i-1] of the previous stage has a low level during the first period t1, a low voltage (e.g., the voltage of the second power supply VSS) may be applied to the fourth node N4 and the second node N2. When the fourth node N4 and the second node N2 are set to a low voltage, the third transistor M3, the fourth transistor M4, the eighth transistor M8, and the tenth transistor M10 may be turned on.

[0135] When the third transistor M3 is turned on, the third input terminal 103 and the seventh node N7 can be electrically coupled to each other. Since the second clock signal CLK2 is not supplied to the third input terminal 103 during the first period t1, a high voltage can be supplied to the seventh node N7. Here, the third capacitor C3 can be charged with a voltage corresponding to the on-state of the third transistor M3.

[0136] When the fourth transistor M4 is turned on, the fifth transistor M5 can be connected in the form of a diode between the third node N3 and the second power supply VSS. Therefore, even when the fifth transistor M5 is turned on during the first period t1, the voltage of the second power supply VSS is not transmitted to the third node N3, and the voltage of the third node N3 can be maintained at the voltage of the previous state, for example, a high voltage. Since the eleventh transistor M11 remains turned on, the high voltage of the third node N3 can be applied to the fifth node N5, and the fifth node N5 can be set to a high voltage. As a result, the second transistor M2, the sixth transistor M6, and the thirteenth transistor M13 can be turned off.

[0137] When the eighth transistor M8 is turned on, the voltage of the first power source VDD may be supplied to the first node N1. Therefore, the ninth transistor M9 may be turned off.

[0138] When the tenth transistor M10 is turned on, the voltage of the second power source VSS may be supplied to the output terminal 104. Therefore, during the first period t1, the emission control signal EM[i] may not be supplied to the emission control line Ei.

[0139] During the second period t2, the supply of the first clock signal CLK1 to the second input terminal 102 may be interrupted. When the supply of the first clock signal CLK1 is interrupted, the first transistor M1 and the fifth transistor M5 may be turned off. Here, the first node N1 and the second node N2 may maintain the voltage of the previous period via the first capacitor C1 and the third capacitor C3. Since the first node N1 remains in a high voltage state, the ninth transistor M9 may remain turned off. Since the second node N2 remains in a low voltage state, the third transistor M3, the fourth transistor M4, the eighth transistor M8, and the tenth transistor M10 may remain turned on.

[0140] During the second period t2, the second clock signal CLK2 may be supplied to the third input terminal 103. The seventh transistor M7 and the fourteenth transistor M14 may be turned on by the second clock signal CLK2 supplied to the third input terminal 103. If the seventh transistor M7 is turned on, the first node N1 and the sixth node N6 may be electrically coupled to each other. Since the eighth transistor M8 remains turned on, the voltage of the first node N1 may be maintained at a high level, and the sixth node N6 coupled to the first node N1 through the seventh transistor M7 may be maintained at a high voltage.

[0141] When the fourteenth transistor M14 is turned on, the fourth node N4 and the eighth node N8 may be electrically connected to each other, and the eighth node N8 may be set to a low voltage.

[0142] During the second period t2, the second clock signal CLK2 may be supplied to the seventh node N7 via the turned-on third transistor M3. Thus, a low voltage is supplied to the seventh node N7. Then, through the coupling of the third capacitor C3, the voltage of the second node N2 may be maintained at a voltage lower than the voltage of the second power supply VSS (two-level low voltage).

[0143] During the third period t3, the supply of the second clock signal CLK2 to the third input terminal 103 may be interrupted. When the supply of the second clock signal CLK2 is interrupted, the seventh transistor M7 and the fourteenth transistor M14 may be turned off.

[0144] During the third period t3, the start signal FLM or the emission control signal EM[i-1] of the previous stage may be supplied to the first input terminal 101, and the first clock signal CLK1 may be supplied to the second input terminal 102. When the first clock signal CLK1 is supplied to the second input terminal 102, the first transistor M1 and the fifth transistor M5 may be turned on.

[0145] When the first transistor M1 is turned on, the first input terminal 101 and the fourth node N4 can be electrically coupled to each other. Since the twelfth transistor M12 remains turned on, the first input terminal 101 can also be electrically coupled to the second node N2 via the fourth node N4. Then, the fourth node N4 and the second node N2 can be set to a high voltage by the start signal FLM supplied to the first input terminal 101 or the emission control signal EM[i-1] of the previous stage. When the fourth node N4 and the second node N2 are set to a high voltage, the third transistor M3, the fourth transistor M4, the eighth transistor M8, and the tenth transistor M10 can be turned off.

[0146] If the fifth transistor M5 is turned on, the low voltage of the second power source VSS may be applied to the third node N3, so that the third node N3 and the fifth node N5 are set to a low voltage. Thus, the second transistor M2, the sixth transistor M6 and the thirteenth transistor M13 may be turned on.

[0147] If the second transistor M2 is turned on, the voltage of the first power supply VDD can be applied to the seventh node N7. Therefore, the seventh node N7 can be maintained at a high voltage. Here, because the third transistor M3 remains off, the voltage of the second clock signal CLK2 to be applied to the third input terminal 103 can not be transmitted to the seventh node N7. In addition, because the seventh node N7 and the second node N2, which are opposite ends of the third capacitor C3, are both maintained at a high voltage, the third capacitor C3 can not be charged or discharged. Here, a current path can be formed from the first power supply VDD to the second node N2 via the second transistor M2, and the high voltage of the first power supply VDD can be transmitted to the second node N2. Therefore, the voltage of the second node N2 can be stably maintained at a high level.

[0148] If the sixth transistor M6 is turned on, the third input terminal 103 and the sixth node N6 can be electrically coupled to each other. Since the second clock signal CLK2 is not supplied to the third input terminal 103 during the third period t3, the sixth node N6 can be maintained at a high voltage. Here, since the seventh transistor M7 remains off, the voltage of the sixth node N6 may not affect the voltage of the first node N1. The second capacitor C2 can store a voltage corresponding to the on-level of the sixth transistor M6.

[0149] If the thirteenth transistor M13 is turned on, the voltage of the first power source VDD may be applied to the eighth node N8. Therefore, the eighth node N8 may be set to a high voltage.

[0150] During the fourth period t4, the second clock signal CLK2 may be supplied to the third input terminal 103. When the second clock signal CLK2 is supplied to the third input terminal 103, the seventh transistor M7 and the fourteenth transistor M14 may be turned on.

[0151] If the seventh transistor M7 is turned on, the first node N1 and the sixth node N6 can be electrically coupled to each other. Here, the low voltage of the second clock signal CLK2 supplied to the third input terminal 103 via the sixth transistor M6 that remains turned on can be supplied to the sixth node N6 and the first node N1. When the low voltage is supplied to the first node N1, the ninth transistor M9 can be turned on.

[0152] If the ninth transistor M9 is turned on, the voltage of the first power supply VDD may be supplied to the output terminal 104. The voltage of the first power supply VDD supplied to the output terminal 104 may be supplied to the i-th emission control line Ei as the emission control signal EM[i].

[0153] When the fourteenth transistor M14 is turned on, a current path can be formed from the first power supply VDD to the second node N2 via the thirteenth transistor M13 and the fourteenth transistor M14, and the high voltage of the first power supply VDD can be transmitted to the second node N2. Therefore, the voltage of the second node N2 can be more stably maintained at a high level.

[0154] As described above, in an exemplary embodiment of the present disclosure, during the supply of the emission control signal EM[i], the third transistor M3, which remains off, can prevent changes in the voltage of the second clock signal CLK2 from affecting the second node N2, thereby stably maintaining the second node N2 at a high voltage. Furthermore, in an exemplary embodiment of the present disclosure, during the supply of the emission control signal EM[i], the third capacitor C3 can be prevented from charging or discharging. In other words, the third capacitor C3 can be prevented from charging or discharging at any time except when the voltage of the second node N2 is set to a low level through coupling of the third capacitor C3. Therefore, in an exemplary embodiment of the present disclosure, during the supply of the emission control signal EM[i], the third capacitor C3 can be prevented from acting as a load. Therefore, power consumption can be reduced, and reliable output of the emission control signal EM[i] can be ensured.

[0155] Figure 9 is a plan view illustrating an example of a layout of stages according to an exemplary embodiment of the present disclosure. Figure 10 It is a cross-sectional view taken along line II'. Specifically, Figure 9 and Figure 10 Shown Figure 4 The layout of the levels is shown in .

[0156] Reference Figure 4 、 Figure 9 and Figure 10 The substrate SUB may be formed of a rigid substrate or a flexible substrate. Examples of the rigid substrate may include a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate.

[0157] Examples of flexible substrates may include film substrates and plastic substrates, each of which includes a polymer organic material. For example, the flexible substrate may include one of polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC), and cellulose acetate propionate (CAP). In addition, the flexible substrate may include fiberglass reinforced plastic (FRP).

[0158] The buffer layer BUF may cover the substrate SUB. The buffer layer BUF may prevent impurities from diffusing from the substrate SUB to the active layer ACT. The buffer layer BUF may be an inorganic insulating layer. For example, the buffer layer BUF may be made of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) or a combination thereof. Depending on the material and processing conditions of the substrate SUB, the buffer layer BUF may be omitted.

[0159] An active layer ACT may be provided on the buffer layer BUF. The active layer ACT is formed of a semiconductor material. For example, the active layer ACT may be formed of a material such as polycrystalline silicon, amorphous silicon, or an oxide semiconductor. The undoped portion of the active layer ACT may form the channels (e.g., CH10) of the transistors M1 to M12. The impurity-doped portion of the active layer ACT may form the electrodes SE1 to SE12 and DE1 to DE12 or lines. The impurities may be p-type impurities. In some exemplary embodiments, the impurities may include at least one of p-type impurities, n-type impurities, and other metals.

[0160] The first gate insulating layer GI1 may cover the active layer ACT. The first gate insulating layer GI1 may cover the source electrodes SE1 to SE12, the drain electrodes DE1 to DE12, and the channel (for example, CH10) of the transistors M1 to M12. The first gate insulating layer GI1 may be an inorganic insulating layer. For example, the first gate insulating layer GI1 may be made of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) or a combination thereof.

[0161] The gate electrodes GE1 to GE12 of the transistors M1 to M12 and the first electrodes LE1 to LE3 of the storage capacitors C1 to C3 may be disposed on the first gate insulating layer GI1. The electrodes disposed on the first gate insulating layer GI1 may be formed of the same conductive material. For example, the electrodes disposed on the first gate insulating layer GI1 may be made of molybdenum (Mo), titanium (Ti), aluminum (Al), silver (Ag), gold (Au), copper (Cu), or a combination thereof.

[0162] The second gate insulating layer GI2 may cover the first gate insulating layer GI1, the gate electrodes GE1 to GE12 of the transistors M1 to M12, and the first electrodes LE1 to LE3 of the storage capacitors C1 to C3. The second gate insulating layer GI2 may be an inorganic insulating layer. For example, the second gate insulating layer GI2 may be made of silicon nitride (SiN x ), silicon oxide (SiO x), silicon oxynitride (SiO x N y ) or a combination thereof.

[0163] The second electrodes VE1 to VE3 of the storage capacitors C1 to C3 and the emission control line Ei may be disposed on the second gate insulating layer GI2. The electrodes and lines disposed on the second gate insulating layer GI2 may be formed of the same conductive material. For example, the electrodes and lines disposed on the second gate insulating layer GI2 may be made of molybdenum (Mo), titanium (Ti), aluminum (Al), silver (Ag), gold (Au), copper (Cu), or a combination thereof.

[0164] The interlayer insulating layer ILD may cover the second gate insulating layer GI2, the second electrodes VE1 to VE3 of the storage capacitors C1 to C3, and the emission control line Ei. The interlayer insulating layer ILD may be an inorganic insulating layer. For example, the interlayer insulating layer ILD may be made of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) or a combination thereof.

[0165] The first power supply VDD, the second power supply VSS, and the power supply lines for the first clock signal CLK1 and the second clock signal CLK2 can be provided on the interlayer insulating layer ILD. The lines provided on the interlayer insulating layer ILD can be made of the same conductive material. For example, the lines provided on the first gate insulating layer GI1 can be made of molybdenum (Mo), titanium (Ti), aluminum (Al), silver (Ag), gold (Au), copper (Cu), or a combination thereof.

[0166] The via layer VIA may cover the interlayer insulating layer ILD. The via layer VIA may be an organic insulating layer. For example, the via layer VIA may include at least one of polystyrene, polymethyl methacrylate (PMMA), polyacrylonitrile (PAN), polyamide (PA), polyimide (PI), polyarylene ether (PAE), a heterocyclic polymer, parylene, epoxy resin, benzocyclobutene (BCB), a siloxane-based resin, and a silane-based resin. In an exemplary embodiment, the via layer VIA may be an inorganic insulating layer, or may have a multilayer structure formed by alternately stacking organic insulating layers and inorganic insulating layers.

[0167] In an exemplary embodiment of the present disclosure, other electrodes or lines may not be provided above or below the line extending from one electrode LE3 of the third capacitor C3 to the second node N2. Therefore, the second node N2 can be protected from field effects caused by electrodes and / or lines that may be provided above or below the second node N2. Due to the above structure, the voltage of the second node N2 can be reliably maintained at the voltage to be controlled by the transistors M1 to M12.

[0168] In the stage and the emission control driver having the stage according to the exemplary embodiment of the present disclosure, when the emission control signal is maintained at a low voltage, the voltage of the node for controlling the output of the emission control signal can be stably maintained at a high voltage. Therefore, the flicker phenomenon of the display device caused by an abnormal emission control signal can be prevented.

[0169] In addition, in the stage and the emission control driver having the same according to the exemplary embodiment of the present disclosure, the capacitor provided in the stage can be prevented from being charged or discharged while the emission control signal is maintained at a low voltage, thereby reducing power consumption regardless of the non-emission section ratio (referred to as an off ratio) in a frame period.

[0170] The present disclosure should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the inventive concept to those skilled in the art.

[0171] Although certain exemplary embodiments have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but rather to the broader scope of this disclosure and various obvious modifications and equivalent arrangements as will be apparent to those skilled in the art.

Claims

1. A stage circuit, wherein: The stage circuit comprises: a first transistor coupled between the first input terminal and the fourth node, wherein a gate electrode of the first transistor is coupled to the second input terminal; a tenth transistor coupled between the output terminal and the second power line, wherein a gate electrode of the tenth transistor is coupled to the second node; a third capacitor coupled between the second node and a seventh node; a third transistor coupled between the seventh node and a third input terminal, wherein a gate electrode of the third transistor is coupled to the second node; and a second transistor coupled between the seventh node and the first power line, wherein a gate electrode of the second transistor is coupled to the third node; The first electrode of the third capacitor coupled to the second node, the gate electrode of the third transistor, and the gate electrode of the tenth transistor are provided in a first conductive layer as first conductors.

2. The stage circuit according to claim 1, wherein: The source electrode and the drain electrode of the first transistor, the source electrode and the drain electrode of the third transistor, and the source electrode and the drain electrode of the second transistor are provided in an active layer, A 1-1 conductor portion of the first conductor extending from the gate electrode of the third transistor to the gate electrode of the tenth transistor does not overlap with the first power line and the second power line.

3. The stage circuit according to claim 1, wherein: The source electrode and the drain electrode of the first transistor, the source electrode and the drain electrode of the third transistor, and the source electrode and the drain electrode of the second transistor are provided below the first conductive layer as an active layer; A first insulating layer is provided between the active layer and the first conductive layer; A second insulating layer is provided on the first conductive layer; The second electrode of the third capacitor is provided on the second insulating layer as a second conductive layer; and The third insulating layer is disposed on the second conductive layer.

4. The stage circuit according to claim 1, wherein: At least one of the source electrode and the drain electrode of the second transistor is directly coupled to at least one of the source electrode and the drain electrode of the third transistor.

5. The stage circuit according to claim 1, wherein: The stage circuit further includes: A fourth transistor is coupled between the second input terminal and the third node, wherein a gate electrode of the fourth transistor is coupled to the fourth node.

6. The stage circuit according to claim 5, wherein: The fourth transistor includes: A plurality of sub-transistors are coupled in series between the third node and the second input terminal, and a plurality of gate electrodes of the plurality of sub-transistors are coupled to the fourth node.

7. The stage circuit according to claim 1, wherein: The stage circuit further includes: a fifth transistor coupled between the second power line and the third node, wherein a gate electrode of the fifth transistor is coupled to the second input terminal.

8. The stage circuit according to claim 1, wherein: The stage circuit further includes: A twelfth transistor is coupled between the fourth node and the gate electrode of the tenth transistor, wherein the gate electrode of the twelfth transistor is coupled to the second power line.

9. The stage circuit according to claim 1, wherein: The stage circuit further includes: a ninth transistor coupled between the first power line and the output terminal, wherein a gate electrode of the ninth transistor is coupled to the first node; a seventh transistor coupled between the first node and a sixth node, wherein a gate electrode of the seventh transistor is coupled to the third input terminal; and a second capacitor coupled between the sixth node and the fifth node, wherein: The gate electrode of the ninth transistor and the first electrode of the third capacitor are provided in the same layer; and The first electrode of the second capacitor is provided in the same layer as the first electrode of the third capacitor.

10. The stage circuit according to claim 9, wherein: The stage circuit further includes: a sixth transistor coupled between the sixth node and the third input terminal, wherein a gate electrode of the sixth transistor is coupled to the fifth node.

11. The stage circuit according to claim 8, wherein: The stage circuit further includes: an eleventh transistor coupled between the fifth node and the gate electrode of the second transistor, wherein the gate electrode of the eleventh transistor is coupled to the second power line.

12. The stage circuit according to claim 9, wherein: The stage circuit further includes: a first capacitor coupled between the first power line and the first node, The first electrode of the first capacitor and the first electrode of the third capacitor are arranged in the same layer.

13. The stage circuit according to claim 9, wherein: The stage circuit further includes: an eighth transistor coupled between the first power line and the first node, wherein a gate electrode of the eighth transistor is coupled to the fourth node.

14. The stage circuit according to claim 1, in, The first input terminal is coupled to an output terminal of a previous stage.

15. The stage circuit according to claim 1, in, The second input terminal is supplied with a first clock signal, the third input terminal is supplied with a second clock signal, and the first clock signal and the second clock signal have the same waveform with a phase difference of half a cycle or more.

16. The stage circuit according to claim 1, in, The first transistor, the second transistor, the third transistor, and the tenth transistor are each a p-type transistor.

17. The stage circuit according to claim 1, wherein: The stage circuit further includes: A thirteenth transistor and a fourteenth transistor are coupled in series between the first power line and the fourth node, wherein the gate electrode of the thirteenth transistor is coupled to the third node, and The gate electrode of the fourteenth transistor is coupled to the third input terminal.

18. A stage circuit, wherein: The stage circuit comprises: a first transistor coupled between the first input terminal and the fourth node, wherein a gate electrode of the first transistor is coupled to the second input terminal; a ninth transistor coupled between the first power source and the output terminal, wherein a gate electrode of the ninth transistor is coupled to the first node; a tenth transistor coupled between the output terminal and a second power source, wherein a gate electrode of the tenth transistor is coupled to a second node; a twelfth transistor coupled between the second node and the fourth node, wherein a gate electrode of the twelfth transistor is coupled to the second power supply; an eighth transistor coupled between the first power source and the first node, wherein a gate electrode of the eighth transistor is coupled to the fourth node; a third capacitor coupled between the second node and a seventh node; a third transistor coupled between the seventh node and a third input terminal, wherein a gate electrode of the third transistor is coupled to the second node; a second transistor coupled between the seventh node and the first power source, wherein a gate electrode of the second transistor is coupled to a third node; and An eleventh transistor is coupled between the fifth node and the third node, wherein a gate electrode of the eleventh transistor is coupled to the second power supply.

19. The stage circuit according to claim 18, wherein: The stage circuit further includes: a fourth transistor coupled between the second input terminal and the third node, The gate electrode of the fourth transistor is coupled to the fourth node.

20. The stage circuit of claim 19, wherein: the fourth transistor includes a plurality of sub-transistors coupled in series between the third node and the second input terminal; and Gate electrodes of the sub-transistors are coupled to the fourth node.

21. The stage circuit according to claim 18, wherein: The stage circuit further includes: a fifth transistor coupled between the second power supply and the third node, The gate electrode of the fifth transistor is coupled to the second input terminal.

22. The stage circuit according to claim 18, wherein The stage circuit further includes: The second capacitor is coupled between the fifth node and the sixth node.

23. The stage circuit according to claim 22, wherein: The stage circuit further includes a seventh transistor coupled between the first node and the sixth node, wherein a gate electrode of the seventh transistor is coupled to the third input terminal.

24. The stage circuit according to claim 23, wherein: The stage circuit further includes a sixth transistor coupled between the sixth node and the third input terminal, wherein a gate electrode of the sixth transistor is coupled to the fifth node.

25. The stage circuit according to claim 18, wherein The stage circuit further includes a first capacitor coupled between the first power source and the first node.

26. The stage circuit according to claim 18, wherein: The first input terminal is coupled to an output terminal of a previous stage.

27. The stage circuit according to claim 18, wherein: The second input terminal is supplied with a first clock signal, the third input terminal is supplied with a second clock signal, and the first clock signal and the second clock signal have the same waveform with a phase difference of half a cycle or more.

28. The stage circuit according to claim 18, wherein: The first transistor, the second transistor, the third transistor, and the tenth transistor are each a p-type transistor.

29. The stage circuit according to claim 18, wherein The stage circuit further includes: A thirteenth transistor and a fourteenth transistor are coupled in series between the first power source and the fourth node, in: a gate electrode of the thirteenth transistor coupled to the third node; and A gate electrode of the fourteenth transistor is coupled to the third input terminal.

30. The stage circuit of claim 25, wherein: The stage circuit further includes: a first gate insulating layer configured to cover a source electrode and a drain electrode of at least one transistor; a second gate insulating layer configured to cover the gate electrode of the at least one transistor and the first electrode of the at least one capacitor; and an interlayer insulating layer configured to cover the second electrode of the at least one capacitor, in: The second gate insulating layer covers a pattern extending from the gate electrode of the third transistor to the gate electrode of the tenth transistor; and The pattern is provided so as not to overlap with the source electrode and the drain electrode covered by the first gate insulating layer.

31. A stage circuit, wherein: The stage circuit comprises: a first transistor coupled between the first input terminal and the fourth node, wherein a gate electrode of the first transistor is coupled to the second input terminal; a ninth transistor coupled between the first power source and the output terminal, wherein a gate electrode of the ninth transistor is coupled to the first node; a tenth transistor coupled between the output terminal and a second power source, wherein a gate electrode of the tenth transistor is coupled to a second node; a twelfth transistor coupled between the second node and the fourth node, wherein a gate electrode of the twelfth transistor is coupled to the second power supply; an eighth transistor coupled between the first power source and the first node, wherein a gate electrode of the eighth transistor is coupled to the fourth node; a third capacitor coupled between the second node and a seventh node; a third transistor coupled between the seventh node and a third input terminal, wherein a gate electrode of the third transistor is coupled to the second node; a first capacitor coupled between the first power source and the first node; a first gate insulating layer configured to cover a source electrode and a drain electrode of at least one transistor; a second gate insulating layer configured to cover the gate electrode of the at least one transistor and the first electrode of the at least one capacitor; and an interlayer insulating layer configured to cover the second electrode of the at least one capacitor, in: The second gate insulating layer covers a pattern extending from the gate electrode of the third transistor to the gate electrode of the tenth transistor; and The pattern is provided so as not to overlap with the source electrode and the drain electrode covered by the first gate insulating layer.

32. The stage circuit according to claim 31, wherein The stage circuit further includes: a second transistor coupled between the seventh node and the first power source, wherein a gate electrode of the second transistor is coupled to a third node; and An eleventh transistor is coupled between the fifth node and the third node, wherein a gate electrode of the eleventh transistor is coupled to the second power supply.

33. The stage circuit according to claim 32, wherein: The stage circuit further includes: a fourth transistor coupled between the second input terminal and the third node, The gate electrode of the fourth transistor is coupled to the fourth node.

34. The stage circuit of claim 33, wherein: the fourth transistor includes a plurality of sub-transistors coupled in series between the third node and the second input terminal; and Gate electrodes of the sub-transistors are coupled to the fourth node.

35. The stage circuit of claim 32, wherein: The stage circuit further includes: a fifth transistor coupled between the second power supply and the third node, The gate electrode of the fifth transistor is coupled to the second input terminal.

36. The stage circuit of claim 32, wherein: The stage circuit further includes: The second capacitor is coupled between the fifth node and the sixth node.

37. The stage circuit of claim 36, wherein: The stage circuit further includes: a seventh transistor coupled between the first node and the sixth node, wherein a gate electrode of the seventh transistor is coupled to the third input terminal; and a sixth transistor coupled between the sixth node and the third input terminal, wherein a gate electrode of the sixth transistor is coupled to the fifth node.

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