Semiconductor package with ultra-thin

Abstract

A semiconductor package includes a semiconductor substrate, a plurality of contact pads, a seed layer, a metal support, and a molded package. The thickness of the semiconductor substrate is 15 microns to 35 microns. The thickness of the metal support body is at least 30 microns. A method comprising the steps of: providing a device wafer; a connection carrier; applying a thinning process; forming a seed layer; forming a plurality of metal support bodies; molding packaging is formed; and a cutting process is applied. The molded package is in direct contact with the plurality of side surfaces and the rear surface of the metal support to facilitate efficient saw blade cutting.

Description

Technical Field

[0001] The present invention generally relates to a semiconductor package having a semiconductor substrate thinner than 50 microns and a method of manufacturing a plurality of semiconductor packages. More particularly, the present invention relates to a semiconductor package that operates within a sufficient safety margin and has a semiconductor substrate having a thickness in the range of 15 to 35 microns. Background Art

[0002] Mobile phone manufacturers and consumers continue to demand higher charging currents, which requires ultra-low resistance products, including ultra-low resistance wafer-level chip scale package (WL-CSP) power chips to improve battery performance. Generally speaking, the silicon layer (semiconductor silicon substrate) of the WL-CSP power chip produces most of the conduction impedance and direct current (DC) resistance. The most effective way is to reduce the thickness of the semiconductor silicon substrate and increase the thickness of the metal support of the WL-CSP power chip to reduce the conduction impedance. Conventional common-drain metal oxide semiconductor field effect transistor (MOSFET) CSP for battery protection applications typically includes a semiconductor silicon substrate with a thickness of 75 microns or more. Reducing the thickness of the semiconductor silicon substrate to 35 microns or less is conducive to reducing DC resistance and improving electrical performance.

[0003] Wang et al., U.S. Patent No. 10,991,660 and U.S. Patent Application Publication No. 2019 / 0189569, disclose a semiconductor package having a semiconductor substrate thickness of 50 microns or less. Lu et al., U.S. Patent No. 11,495,548 and U.S. Patent Application Publication No. 2021 / 0125940, disclose a semiconductor package having a semiconductor substrate thickness of 75 microns or less. Lu et al., U.S. Patent No. 11,784,141 and U.S. Patent Application Publication No. 2023 / 0021687, disclose a semiconductor package having a semiconductor substrate thickness of 75 microns or less.

[0004] When the semiconductor substrate thickness is reduced from 50 microns to 25 microns, on-resistance can be reduced by 24%. However, as the semiconductor substrate thickness decreases, the mechanical strength of the semiconductor package decreases. In the examples disclosed herein, a metal support thickness of at least 30 microns helps the semiconductor package regain mechanical strength, thereby maintaining low warpage, minimal delamination, low cost, and efficient saw blade cutting. Summary of the Invention

[0005] A semiconductor package includes a semiconductor substrate, a plurality of contact pads, a seed layer, a metal support, and a molded package. The semiconductor substrate has a thickness of less than 50 microns, preferably 15 to 35 microns. The metal support has a thickness of at least 30 microns.

[0006] The present invention discloses a method for manufacturing multiple semiconductor packages. The method comprises the following steps: providing a device wafer; attaching a carrier; applying a thinning process; forming a seed layer; forming multiple metal supports; forming a molded package; and applying a singulation process. The molded package directly contacts multiple side surfaces and the rear surface of the metal supports to facilitate efficient saw blade cutting. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A cross-sectional view of a semiconductor package in an example of the present disclosure is shown.

[0008] Figure 2 is a flow chart of a process for developing multiple semiconductor packages in an example of the present disclosure.

[0009] Figure 3A 、 3B 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K and 3L show the embodiment of the present disclosure. Figure 2 Cross-sections of the corresponding steps of the process are shown. DETAILED DESCRIPTION

[0010] Figure 1 FIG1 shows a cross-sectional view of a semiconductor package 100 in an example of the present disclosure. The semiconductor package 100 includes a semiconductor substrate 120, a plurality of contact pads 130, a seed layer 160, a metal support 180, and a molded package 190. In an example of the present disclosure, all edges of the support metal support 180 are recessed from corresponding edges of the seed layer 160.

[0011] The semiconductor substrate 120 has a front surface 122 and a rear surface 124 opposite the front surface 122 of the semiconductor substrate 120. A plurality of contact pads 130 are attached to the front surface 122 of the semiconductor substrate 120. The seed layer 160 has a front surface 162 and a rear surface 164 opposite the front surface 162 of the seed layer 160. The front surface 162 of the seed layer 160 is directly attached to the rear surface 124 of the semiconductor substrate 120. All edges of the seed layer 160 are aligned with corresponding edges of the semiconductor substrate 120.

[0012] The metal support 180 has a plurality of side surfaces 181, a front surface 182, and a rear surface 184 opposite to the front surface 182 of the metal support 180. The front surface 182 of the metal support 180 is directly attached to the rear surface 164 of the support seed layer 160. The plurality of side surfaces 181 of the metal support 180 define a plurality of edges of the metal support 180. All edges of the metal support 180 are recessed from the corresponding edges of the seed layer 160 by a range of 5 to 50 microns. The molded package 190 directly contacts the plurality of side surfaces 181 and the rear surface 184 of the metal support 180. The edges of the molded package 190 are aligned with the corresponding edges of the seed layer 160 and the corresponding edges of the semiconductor substrate 120. In an example of the present disclosure, the molded package 190 directly contacts the rear surface 164 of the seed layer 160 in the area not covered by the metal support 180.

[0013] In the example of the present disclosure, the thickness of the semiconductor substrate 120 is less than 50 micrometers, preferably the thickness of the semiconductor substrate is in the range of 15 micrometers to 35 micrometers. The thickness of the metal support 180 is at least 30 micrometers.

[0014] In an example of the present disclosure, the composition of the seed layer 160 includes titanium formed by sputtering. The thickness of the seed layer 160 is in the range of 0.4 microns to 1.3 microns. The metal support 180 is made of copper (Cu), silver (Ag), solder (SnAg) or tin (Sn). In one example, the metal support 180 is composed of copper, and the seed layer 160 includes TiCu, wherein the thickness of the Ti formed by sputtering is in the range of 0.1 microns to 0.3 microns, and the thickness of the Cu formed by sputtering is 0.3 microns to 1 micron. In another example, the metal support 180 is composed of silver, and the seed layer 160 includes TiNi, wherein the thickness of the Ti formed by sputtering is in the range of 0.1 microns to 0.3 microns, and the thickness of the Ni formed by sputtering is 0.3 microns to 1 micron. Each of the plurality of contact pads 130 contains nickel and gold.

[0015] In an example of the present disclosure, semiconductor package 100 is a common-drain metal oxide semiconductor field effect transistor (MOSFET) chip-scale package (CSP) for battery protection applications. Two gates and multiple sources are located on the front surface of the common-drain MOSFET CSP. The common drain is located on the back surface of the common-drain MOSFET CSP.

[0016] Figure 2 is a flow chart of a process 200 of forming a plurality of semiconductor packages in an example of the present disclosure. Figure 3A 、 3B , 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K and 3L show examples of the present disclosure. Figure 2Cross-sections of corresponding steps of process 200 are shown. Process 200 may begin at step 202.

[0017] In step 202, now refer to Figure 3A , providing a device wafer 302. The device wafer 302 includes a semiconductor substrate 320 on which a plurality of semiconductor devices are formed. Each semiconductor device may have one or more contact pads 330 for providing connections to electrodes of the semiconductor device. Similar to U.S. Patent Application Publication No. 2019 / 0189569 Figure 3A Each of the plurality of contact pads 330 may include an aluminum layer and a nickel-gold layer. The semiconductor substrate 320 has a front surface 322 and a rear surface 324 opposite the front surface 322 of the semiconductor substrate 320. The plurality of contact pads 330 are attached to the front surface 322 of the semiconductor substrate 320. Slice lines (not shown) provided on the front surface of the device wafer 302 separate adjacent devices on the device wafer 302. Step 202 may be followed by step 204.

[0018] In step 204, if Figure 3B As shown, carrier 340 is attached to the plurality of contact pads 330 of device wafer 302. In an example of the present disclosure, attachment is achieved via adhesive layer 309. Adhesive layer 309 is transparent. Adhesive layer 309 surrounds and protects the plurality of contact pads 330. In one example, carrier 340 is composed of a metal material. In another example, carrier 340 is composed of a glass material. Attachment of carrier 340 increases the strength of device wafer 302, thereby reducing warping during subsequent processing steps. Step 204 may be followed by step 206.

[0019] In step 206, refer to Figure 3C A thinning process is applied to the back surface 324 of the semiconductor substrate 320 to form a thinned semiconductor substrate 321. In the example of the present disclosure, the thickness of the thinned semiconductor substrate 321 is in the range of 15 microns to 35 microns. The thinning process may include back grinding and back etching. Step 206 may be followed by step 208.

[0020] In step 208, refer to Figure 3D A seed layer 360 is formed on the thinned semiconductor substrate 321. The seed layer 360 can be formed by sputtering. In one example, the seed layer 360 comprises titanium. The thickness of the seed layer 360 ranges from 0.4 microns to 1.3 microns. The seed layer 360 covers the entire backside of the wafer. Step 208 may be followed by step 210.

[0021] In step 210, refer to Figure 3E , a photoresist coating 370 is formed on the seed layer 360. Step 210 may be followed by step 212.

[0022] In step 212, refer to Figure 3F , etching the photoresist coating 370 to form a patterned photoresist coating 372 including a plurality of grooves 376. The seed layer 360 is exposed from the plurality of grooves 376. The remaining patterned photoresist coating is aligned with and wider than the scribe lines set on the front surface of the device wafer 302. The etching of the photoresist coating may include photolithographic exposure and development. Step 212 may be followed by step 214.

[0023] In step 214, if Figure 3G As shown, a plurality of metal supports 380 are formed in a plurality of recesses 376 of a patterned photoresist coating 372. In an example of the present disclosure, each back surface of the plurality of metal supports 380 and each back surface layer 372 of the patterned photoresist coating are coplanar. In an example of the present disclosure, each of the plurality of metal supports 380 has a thickness of at least 30 microns. In one example, the plurality of metal supports 380 comprises copper formed by electrochemical plating. In another example, the plurality of metal supports 380 comprises silver or solder formed by electrochemical plating. Step 214 may be followed by step 216.

[0024] In step 216, if Figure 3H As shown, the patterned photoresist coating 372 is removed to expose the side surfaces 381 of the plurality of metal supports 380. In one example, the step of removing the patterned photoresist coating 372 includes stripping. Step 216 may be followed by step 218.

[0025] In step 218, refer to Figure 3I , forming a molded package 390. The molded package 390 directly contacts the side surfaces 381 of the plurality of metal supports 380 and the rear surfaces 383 of the plurality of metal supports 380. The molded package 390 prevents oxidation of the rear surfaces 383 of the plurality of metal supports 380. Step 218 may be followed by step 220.

[0026] In step 220, refer to Figure 3J A polishing process is applied to the rear surface of the molded package 390 to form a polished molded package 391. The thickness of the molded package 390 is greater than the thickness of the polished molded package 391. Step 222 may follow.

[0027] In step 222, refer to Figure 3K , removing the carrier 340. The carrier 340 may be removed by a separation process. The top surfaces 331 of the plurality of contact pads 330 are exposed. Step 222 may be followed by step 224.

[0028] In step 224, refer to Figure 3L, a cutting process along cutting lines 398 is provided to cut through the semiconductor substrate, the seed layer and the molded package in each region between adjacent metal supports, thereby forming a plurality of semiconductor packages 399 . Figure 3I The molded package 390 directly contacts the side surfaces 381 and rear surface 383 of the metal supports 380 to facilitate efficient saw blade cutting (at the scribe line, the cut is through the molded package 390 rather than through the metal supports 380). Figure 3L The cross-sectional view of FIG. 1 shows five semiconductor packages, but the present invention is not limited thereto. Figure 3L As shown, the number of semiconductor packages can vary. Figure 3L In the cross-sectional view of each semiconductor package, one contact pad is shown, but the present invention is not limited thereto, and the number of contact pads may vary. For example, Figure 1 A semiconductor package 100 is provided. Figure 1 Includes a cross-sectional view of five contact pads. In one example, the singulation process is a laser cutting process (more expensive, melts metal fragments around the scribe line sidewalls, which may cause reliability testing failures). In another example, the singulation process is a saw blade cutting process (cheaper and more reliable).

[0029] In an example of the present disclosure, each of the plurality of semiconductor packages 399 is a common-drain metal oxide semiconductor field effect transistor (MOSFET) chip-scale package (CSP) for battery protection applications. In an example of the present disclosure, two gates and multiple sources are located on the front surface of the common-drain MOSFET CSP. The common drain is located on the back surface of the common-drain MOSFET CSP.

[0030] Those skilled in the art will recognize that modifications to the embodiments disclosed herein are possible. For example, the total number of contact pads 330 may vary. Other modifications may occur to those skilled in the art, and all such modifications are considered to fall within the scope of the present invention as defined in the claims.

Claims

1. A semiconductor package comprising: a semiconductor substrate having a front surface and a rear surface opposite the front surface of the semiconductor substrate; a plurality of contact pads attached to the front surface of the semiconductor substrate; a seed layer having a front surface and a back surface opposite the front surface of the seed layer, the front surface of the seed layer being directly attached to the back surface of the semiconductor substrate; a metal support having a plurality of side surfaces, a front surface, and a rear surface opposite the front surface of the metal support, the front surface of the metal support being directly attached to the rear surface of the seed layer; and A molded package body directly contacts the side surfaces and back surface of the metal support body; wherein the thickness of the semiconductor substrate is less than 50 microns; and The thickness of the metal support is at least 30 microns. 2 . The semiconductor package according to claim 1 , wherein a thickness of the semiconductor substrate is in a range of 15 μm to 35 μm. 3 . The semiconductor package according to claim 1 , wherein an edge of the molded package is aligned with an edge of the seed layer and an edge of the semiconductor substrate. The semiconductor package according to claim 1 , wherein the seed layer comprises titanium. The semiconductor package according to claim 1 , wherein the metal support is composed of copper or silver. 6 . The semiconductor package of claim 1 , wherein the semiconductor package is a common-drain metal-oxide-semiconductor field-effect transistor (MOSFET) chip scale package (CSP) for battery protection applications. in, Two gates and multiple sources are located on the front surface of the common-drain MOSFET CSP; and The common drain is located on the back side of the common drain MOSFET CSP.

7. A method for manufacturing a plurality of semiconductor packages, the method comprising the steps of: Provide device wafers, including a semiconductor substrate having a front surface and a rear surface opposite the front surface of the semiconductor substrate; and a plurality of contact pads attached to the front surface of the semiconductor substrate; attaching a carrier to a plurality of contact pads of the device wafer; performing a thinning process on the back side of the semiconductor substrate to form a thinned semiconductor substrate; forming a seed layer on the thinned semiconductor substrate; forming a photoresist coating on the seed layer; The photoresist coating is etched to form a patterned photoresist coating including a plurality of recesses exposing regions of the seed layer. A plurality of metal supports are formed to cover the exposed areas of the seed layer in the plurality of recesses of the patterned photoresist coating. removing the patterned photoresist coating to expose side surfaces of the plurality of metal supports; forming a molded package body that directly contacts the side surfaces of the plurality of metal supports and the back surfaces of the plurality of metal supports; Remove the carrier; and Apply segmentation technology; The semiconductor substrate after thinning has a thickness of 15 microns to 35 microns; and Each of the plurality of metal supports has a thickness of at least 30 micrometers.

8. The method according to claim 7, wherein the step of forming the molded package directly contacting the side surfaces of the plurality of metal support bodies and the rear surfaces of the plurality of metal support bodies further comprises the step of performing a polishing process on the molded package to form a polished molded package. The method according to claim 7 , wherein the thinning process comprises grinding and etching. 10 . The method of claim 7 , wherein the seed layer comprises titanium formed by sputtering, wherein a thickness of the seed layer is in a range of 0.4 μm to 1.3 μm. The method according to claim 7 , wherein the plurality of metal supports comprise copper or silver formed by electroplating. Support body. 12 . The method of claim 7 , wherein applying the singulation process comprises sawing through the semiconductor substrate, the seed layer, and the molded package in areas between adjacent metal supports.

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