Low power consumption fast start-up oscillator circuit and control method thereof

Abstract

The application discloses a low-power-consumption fast-starting oscillator circuit and a control method thereof, which comprises a starting circuit, a bias current generating circuit and an oscillation circuit, the input end of the starting circuit is connected with a starting current I_Start, the first output end of the starting circuit is connected with the first input end of the bias current generating circuit, the second output end of the starting circuit is connected with the second input end of the bias current generating circuit, and the oscillation circuit mirrors the current of the bias current generating circuit and alternately charges and discharges two capacitors to generate an OSC signal. The application generates charging and discharging currents in the circuit, does not adopt a comparator circuit, greatly reduces the requirements and power consumption of external circuits, can perform frequency selection switching, synchronously switches the starting circuit, and improves the starting time of the circuit.

Description

Technical Field

[0001] This invention relates to an oscillator circuit and its control method, particularly a low-power, fast-start oscillator circuit and its control method, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] In electronic systems, oscillators are crucial components, providing clock drive for chip circuits. Their proper functioning plays a decisive role in the performance requirements of electronic systems. With advancements in semiconductor technology and the rapid development of fields such as the Internet of Things (IoT) and sensors, there is a growing trend towards lower power consumption. The booming development of wearable devices, biomedical implantable devices, and wireless sensors necessitates that these applications typically utilize small batteries for power, and that these devices rely on precise clock frequencies to achieve basic functions such as timing, wake-up, synchronization, and communication. Therefore, there is an urgent need to design low-power, small-size, and easily integrated high-precision clock source signals.

[0003] Common analog modules used to generate clock frequencies include crystal oscillators, ring oscillators, LC oscillators, and RC oscillators. Crystal oscillators offer high precision but require an external quartz crystal, making them inconvenient to integrate into a chip and resulting in higher area and cost. Ring oscillators have a smaller area and lower cost, but their output frequency is susceptible to temperature and power supply voltage fluctuations, leading to lower frequency stability. LC oscillators are difficult to integrate due to the difficulty in integrating the inductor (L) and the large area of ​​the capacitor (C), resulting in higher chip costs. RC oscillators have both a smaller area and lower cost and can be integrated into a chip.

[0004] Figure 6 The circuit, based on a traditional oscillator structure, mainly consists of switches S1, S2, S3, and S4, capacitors C1 and C2, a comparator, and an RS flip-flop. Two RC charging and discharging circuits alternately charge the oscillator. When switch S1 is closed, S2 is open, charging capacitor C1. When the voltage across C1 exceeds Vref, the comparator output changes state, generating the CLK clock signal after passing through the RS flip-flop. The clock period is determined by R and C. This traditional structure requires two comparators, resulting in a complex design, high power consumption, and large area. The comparator current source is externally provided, and the oscillator output frequency is singular and cannot be selected or varied. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a low-power, fast-start oscillator circuit and its control method, which has a small area, low power consumption and frequency selection switching capability.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0007] A low-power, fast-start oscillator circuit includes a startup circuit, a bias current generation circuit, and an oscillation circuit. The input terminal of the startup circuit is connected to the startup current I_Start. The first output terminal of the startup circuit is connected to the first input terminal of the bias current generation circuit. The second output terminal of the startup circuit is connected to the second input terminal of the bias current generation circuit. The oscillation circuit mirrors the current of the bias current generation circuit and alternately charges and discharges two capacitors to generate an OSC signal.

[0008] Further, the startup circuit includes PMOS transistors PM3, PM6, PM7, PM8, and PM9, and switch S2. The sources of PMOS transistors PM3, PM6, PM7, PM8, and PM9, and the first selection terminal of switch S2 are connected to the power supply VDD. The gate of PMOS transistor PM3 is connected to the gates of PMOS transistors PM6, PM7, PM7, PM8, and PM9, and serves as the input terminal of the startup circuit. The drain of PMOS transistor PM3 serves as the first output terminal of the startup circuit, and the drain of PMOS transistor PM6 serves as the second output terminal of the startup circuit. The gate of PMOS transistor PM8 is connected to the second selection terminal of switch S2 and is connected to the bias voltage VBP. The gate of PMOS transistor PM9 is connected to the fixed terminal of switch S2.

[0009] Furthermore, the PMOS transistors PM3, PM6, and PM7 constitute the first PMOS current mirror.

[0010] Further, the bias current generating circuit includes PMOS transistors PM1, PM2, PM4, PM5, NMOS transistors NM1, NM2, NM3, NM4, and NM5, a switch S1, resistors R1 and R2. The sources of PMOS transistors PM1, PM2, PM4, and PM5 are connected to the power supply VDD. The gates of PMOS transistors PM1, PM2, PM4, and PM5 are connected to the gates of PMOS transistors PM2, PM4, and PM5, and the drains of PMOS transistors PM1 and NM5 are connected to the bias voltage VBP. The gate of NMOS transistor NM5 is connected to the bias voltage VBN. The source of NMOS transistor NM5 is connected to the NM5 gate. The drain of MOSFET NM4 is connected. The drain of PMOS transistor PM2 is connected to the drains of NMOS transistors NM2 and NM3, the gate of NMOS transistor NM3, and the gate of NMOS transistor NM4, and serves as the first input terminal of the bias current generation circuit. The drain of PMOS transistor PM4 is connected to one end of resistor R2 and the gate of NMOS transistor NM2. The other end of resistor R2 is connected to one end of resistor R1 and one end of switch S1 at node X. The drain of PMOS transistor PM5, the drain of NMOS transistor NM1, and the gate of NMOS transistor NM1 are connected to the bias voltage VBN and serve as the second input terminal of the bias current generation circuit. The source of NMOS transistor NM1, the other end of switch S1, the other end of resistor R1, the source of NMOS transistor NM2, the source of NMOS transistor NM3, and the source of NMOS transistor NM4 are grounded.

[0011] Further, the oscillation circuit includes PMOS transistors PM10, PM11, PM12, NMOS transistors NM7, NM9, NM6, and NM8, switches S3 and S4, capacitors C1 and C2, an RS flip-flop, and an inverter INV1. The sources of PMOS transistors PM10, PM11, and PM12 are connected to the power supply VDD. The gates of PMOS transistors PM10, PM11, and PM12 are connected to the bias voltage VBP. The drain of PMOS transistor PM10 is connected to one end of switch S3 and one end of switch S4. The other end of switch S3 is connected to one end of capacitor C1 and the gate of NMOS transistor NM6. The terminals are connected as follows: the other end of switch S4 is connected to one end of capacitor C2 and the gate of NMOS transistor NM8; the drain of PMOS transistor PM11 is connected to the drain of NMOS transistor NM7 and the S terminal of RS flip-flop; the drain of PMOS transistor PM12 is connected to the drain of NMOS transistor NM9 and the R terminal of RS flip-flop; the gates of NMOS transistor NM7 and NMOS transistor NM9 are connected to the bias voltage VBN; the source of NMOS transistor NM7 is connected to the drain of NMOS transistor NM6; the source of NMOS transistor NM9 is connected to the drain of NMOS transistor NM8; the Q terminal of RS flip-flop is connected to the input terminal of inverter INV1 and the control terminal of switch S4; the Q' terminal of RS flip-flop is connected to the control terminal of switch S3; and the output terminal of inverter INV1 generates an oscillation signal CLK.

[0012] Furthermore, the PMOS transistors PM1, PM2, PM4, PM5, PM8, PM10, PM11, and PM12 constitute a second PMOS current mirror.

[0013] A control method for a low-power, fast-start oscillator circuit includes the following steps:

[0014] When the circuit is not working, there is no current in the circuit, the bias voltage VBP of the gate of PMOS transistor PM1 is high, and the gate of NMOS transistor NM3 is low. At this time, the circuit starts working, and the start-up current I_Strat flows into PMOS transistor PM7, pulling the gate voltage of PMOS transistor PM7 low. At the same time, PMOS transistors PM3 and PM6 generate current and inject the current into the gates of NMOS transistors NM3 and NMOS transistor NM1 respectively, pulling the gate voltages of NMOS transistors NM3 and NMOS transistor NM1 high. The gate voltages of NMOS transistors NM4 and NMOS transistor NM5 are pulled high and turned on, pulling the gate voltage of PMOS transistor PM1 low, and the circuit generates current.

[0015] PMOS transistors PM2, PM4, PM5, and PM8 generate current. When the current of PMOS transistor PM8 is greater than the startup current I_Strat, the gate voltage of PMOS transistor PM7 is pulled high, and PMOS transistors PM3, PM6, and PM7 are turned off. The startup circuit is turned off, and the circuit works normally.

[0016] When switch S1 is open, the total resistance R = R1 + R2. The total resistance is large, and the current generated is small. Since the starting current I_Strat itself is small, the size ratio between PMOS transistor PM8 and PMOS transistor PM1 does not need to be large to turn off the starting circuit.

[0017] When switch S1 is closed, the total resistance R = R2. The smaller the total resistance, the larger the current generated. If PMOS transistors PM8 and PM1 control the startup circuit in the same ratio, the circuit will be shut down before it is fully started. At this time, the gate voltages of PMOS transistors PM3 and NMOS transistor NM1 will take a long time to reach a stable state due to the lack of startup current, resulting in a long startup time. If the ratio of PMOS transistors PM8 to PM1 is smaller, the circuit can start up and shut down quickly when switch S1 is closed and the total resistance is small. However, when switch S1 is open and the total resistance is large, the current generated by PMOS transistor PM8 will be small, which will not be able to completely shut down PMOS transistor PM7, and the startup circuit will still be working.

[0018] When switch S1 is closed and the total resistance is low, switch S2 switches to the power supply VDD, PMOS transistor PM9 is turned off, and only PMOS transistor PM8 is used to shut down the startup circuit. When switch S1 is open and the total resistance is high, switch S2 switches to the bias voltage VBP, PMOS transistor PM9 works, and PMOS transistors PM8 and PM9 work together to shut down the startup circuit, improving the startup time of the circuit.

[0019] The oscillation circuit controls switches S3 and S4 through the two opposite outputs Q and Q' of the RS flip-flop, causing capacitors C1 and C2 to charge and discharge alternately. When the voltage of capacitors C1 and C2 is higher than the threshold voltage of NMOS transistors NM6 and NM8, the input voltage of the RS flip-flop is pulled low, and the state changes of outputs Q and Q' generate an oscillation signal.

[0020] Compared with the prior art, the present invention has the following advantages and effects:

[0021] 1. This invention provides a low-power, fast-start oscillator circuit with a simple circuit structure and selectable, flexible output frequency.

[0022] 2. The bias current of this invention is not provided by an external source, which simplifies the circuit, reduces the burden on the external circuit, stabilizes the charging current, and ensures that the oscillation frequency is related to the resistor and the charging capacitor, thus maintaining a stable frequency.

[0023] 3. This invention improves the startup time and reduces power consumption by using different startup circuits for different frequencies;

[0024] 4. This invention eliminates the comparator and control logic in traditional circuits and uses an RS flip-flop, which occupies a small chip area. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of a low-power, fast-start oscillator circuit according to the present invention.

[0026] Figure 2 This is a circuit diagram of a low-power, fast-start oscillator circuit according to the present invention.

[0027] Figure 3 This is a circuit diagram of the startup circuit of the present invention.

[0028] Figure 4 This is a circuit diagram of the bias current generating circuit of the present invention.

[0029] Figure 5 This is a circuit diagram of the oscillation circuit of the present invention.

[0030] Figure 6 This is a circuit diagram of a traditional oscillator. Detailed Implementation

[0031] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0032] like Figure 1 and Figure 2 As shown, a low-power fast-start oscillator circuit of the present invention includes a startup circuit, a bias current generating circuit, and an oscillation circuit. The input terminal of the startup circuit is connected to the startup current I_Start, the first output terminal of the startup circuit is connected to the first input terminal of the bias current generating circuit, and the second output terminal of the startup circuit is connected to the second input terminal of the bias current generating circuit. The oscillation circuit mirrors the current of the bias current generating circuit and alternately charges and discharges two capacitors to generate an OSC signal.

[0033] This invention provides a low-power, fast-start oscillator circuit. The circuit generates charging and discharging current internally, eliminating the need for a comparator circuit. This significantly reduces the requirements and power consumption for external circuits. It allows for frequency selection and switching, synchronously switching the startup circuit, and improving the circuit's startup time.

[0034] like Figure 3 As shown, the startup circuit includes PMOS transistors PM3, PM6, PM7, PM8, and PM9, and switch S2. The sources of PMOS transistors PM3, PM6, PM7, PM8, and PM9, and the first selection terminal of switch S2 are connected to the power supply VDD. The gate of PMOS transistor PM3 is connected to the gates of PMOS transistors PM6, PM7, PM7, PM8, and PM9, and serves as the input terminal of the startup circuit. The drain of PMOS transistor PM3 serves as the first output terminal of the startup circuit, and the drain of PMOS transistor PM6 serves as the second output terminal of the startup circuit. The gate of PMOS transistor PM8 is connected to the second selection terminal of switch S2 and is connected to the bias voltage VBP. The gate of PMOS transistor PM9 is connected to the fixed terminal of switch S2.

[0035] Among them, PMOS transistors PM3, PM6, and PM7 constitute the first PMOS current mirror.

[0036] The startup module is responsible for starting the circuit to a normal state. When the circuit is not working, the startup circuit is working, and after the circuit enters the normal working state, the startup circuit is turned off.

[0037] like Figure 4As shown, the bias current generating circuit includes PMOS transistors PM1, PM2, PM4, PM5, NMOS transistors NM1, NM2, NM3, NM4, and NM5, a switch S1, resistors R1 and R2. The sources of PMOS transistors PM1, PM2, PM4, and PM5 are connected to the power supply VDD. The gates of PMOS transistors PM1, PM2, PM4, and PM5 are connected to the gates of PMOS transistors PM2, PM4, and PM5, and the drains of PMOS transistors PM1 and NM5 are connected to the bias voltage VBP. The gate of NMOS transistor NM5 is connected to the bias voltage VBN. The source of NMOS transistor NM5 is connected to the NMOS transistor NM5. The drain of S-channel transistor NM4 is connected. The drain of PMOS transistor PM2 is connected to the drains of NMOS transistors NM2 and NM3, the gate of NMOS transistor NM3, and the gate of NMOS transistor NM4, and serves as the first input terminal of the bias current generation circuit. The drain of PMOS transistor PM4 is connected to one end of resistor R2 and the gate of NMOS transistor NM2. The other end of resistor R2 is connected to one end of resistor R1 and one end of switch S1 at node X. The drain of PMOS transistor PM5, the drain of NMOS transistor NM1, and the gate of NMOS transistor NM1 are connected to the bias voltage VBN and serve as the second input terminal of the bias current generation circuit. The source of NMOS transistor NM1, the other end of switch S1, the other end of resistor R1, the source of NMOS transistor NM2, the source of NMOS transistor NM3, and the source of NMOS transistor NM4 are grounded.

[0038] The bias current generation circuit generates a stable current through a loop. The current is related to resistors R1 and R2 and the threshold voltage of NMOS transistor NM2. The gate resistance of NMOS transistor NM2 is related to the frequency of OSC. By controlling the switch S1 to adjust the total resistance, the frequency can be switched, thus switching between low-power mode and normal operation.

[0039] like Figure 5As shown, the oscillation circuit includes PMOS transistors PM10, PM11, PM12, NMOS transistors NM7, NM9, NM6, and NM8, switches S3 and S4, capacitors C1 and C2, an RS flip-flop, and an inverter INV1. The sources of PMOS transistors PM10, PM11, and PM12 are connected to the power supply VDD. The gates of PMOS transistors PM10, PM11, and PM12 are connected to the bias voltage VBP. The drain of PMOS transistor PM10 is connected to one end of switch S3 and one end of switch S4. The other end of switch S3 is connected to one end of capacitor C1 and the gate of NMOS transistor NM6. The other end of switch S4 is connected to one end of capacitor C2 and the gate of NMOS transistor NM8. The drain of PMOS transistor PM11 is connected to the drain of NMOS transistor NM7 and the S terminal of RS flip-flop. The drain of PMOS transistor PM12 is connected to the drain of NMOS transistor NM9 and the R terminal of RS flip-flop. The gates of NMOS transistor NM7 and NMOS transistor NM9 are connected to the bias voltage VBN. The source of NMOS transistor NM7 is connected to the drain of NMOS transistor NM6. The source of NMOS transistor NM9 is connected to the drain of NMOS transistor NM8. The Q terminal of RS flip-flop is connected to the input terminal of inverter INV1 and the control terminal of switch S4. The Q' terminal of RS flip-flop is connected to the control terminal of switch S3. The output terminal of inverter INV1 generates an oscillation signal CLK.

[0040] The core of the oscillation circuit is to generate oscillation by continuously charging and discharging the capacitor. The two opposite outputs Q and Q' of the RS flip-flop control the switches S1 and S2, so that the capacitors C1 and C2 are charged and discharged alternately. When the capacitor voltage is higher than the threshold voltage of the NMOS transistors NM6 and NM8, the input of the RS flip-flop is pulled low, and the state change of the outputs Q and Q' generates the OSC signal.

[0041] PMOS transistors PM1, PM2, PM4, PM5, PM8, PM10, PM11, and PM12 constitute the second PMOS current mirror.

[0042] A control method for a low-power, fast-start oscillator circuit includes the following steps:

[0043] When the circuit is not working, there is no current in the circuit, the bias voltage VBP of the gate of PMOS transistor PM1 is high, and the gate of NMOS transistor NM3 is low. At this time, the circuit starts working, and the starting current I_Strat flows into PMOS transistor PM7, pulling the gate voltage of PMOS transistor PM7 low. At the same time, PMOS transistors PM3 and PM6 generate current and inject the current into the gates of NMOS transistors NM3 and NMOS transistor NM1 respectively, pulling the gate voltages of NMOS transistors NM3 and NMOS transistor NM1 high. The gate voltages of NMOS transistors NM4 and NMOS transistor NM5 are pulled high and turned on, pulling the gate voltage of PMOS transistor PM1 low, and the circuit generates current.

[0044] PMOS transistors PM2, PM4, PM5, and PM8 generate current. When the current of PMOS transistor PM8 is greater than the startup current I_Strat, the gate voltage of PMOS transistor PM7 is pulled high, and PMOS transistors PM3, PM6, and PM7 are turned off. The startup circuit is shut down, and the circuit works normally.

[0045] Because the total resistance R varies, the current generated in the circuit also varies.

[0046] When switch S1 is open, the total resistance R = R1 + R2. The total resistance is relatively large, and the current generated is relatively small. Since the starting current I_Strat itself is small, the size ratio between PMOS transistor PM8 and PMOS transistor PM1 does not need to be too large to turn off the starting circuit.

[0047] When switch S1 is closed, the total resistance R = R2, which is relatively small, resulting in a larger current. If PMOS transistors PM8 and PM1 control the startup circuit in the same ratio, the circuit will be shut down before it is fully started. At this time, the gate voltages of PMOS transistors PM3 and NMOS transistor NM1 will take a longer time to reach a stable state due to the lack of startup current, leading to a longer startup time. If the ratio of PMOS transistors PM8 to PM1 is smaller, the circuit can start and shut down faster when switch S1 is closed and the total resistance is smaller. However, when switch S1 is open and the total resistance is larger, the current generated by PMOS transistor PM8 may be too small to completely shut down PMOS transistor PM7, and the startup circuit will continue to operate.

[0048] When the total resistance is small when switch S1 is closed, switch S2 switches to the power supply VDD, PMOS transistor PM9 is turned off, and only PMOS transistor PM8 is used to shut down the startup circuit. When the total resistance is large when switch S1 is open, switch S2 switches to the bias voltage VBP, PMOS transistor PM9 works, and PMOS transistors PM8 and PM9 work together to shut down the startup circuit, improving the startup time of the circuit.

[0049] The oscillation circuit controls switches S3 and S4 through the two opposite outputs Q and Q' of the RS flip-flop, causing capacitors C1 and C2 to charge and discharge alternately. When the voltage of capacitors C1 and C2 is higher than the threshold voltage of NMOS transistors NM6 and NM8, the input voltage of the RS flip-flop is pulled low, and the state changes of outputs Q and Q' generate an oscillation signal.

[0050] The clock frequency is related to resistors R1 and R2, and capacitors C1 and C2. Resistors R1 and R2 are used to adjust the OSC's output frequency, and C1 = C2 = C. The charging and discharging current I of the capacitor is provided by PMOS transistor PM10, and its magnitude is I = VTH / R, where R is the total resistance and R = R2 or R = R1 + R2, and VTH is the threshold voltage of the transistor. When the charging voltage reaches the threshold voltage VTH of NMOS transistors NM6 and NM8, the output flips, i.e., the charging time of the capacitor t = C * VTH / I, from which the OSC's output frequency F = 1 / RC can be obtained.

[0051] This invention provides a low-power, fast-start oscillator circuit with a simple structure, selectable and flexible output frequency. The bias current is not externally supplied, simplifying the circuit and reducing the burden on external circuitry. The charging current is stable, and the oscillation frequency is related to the resistor and charging capacitor, ensuring frequency stability. The invention improves the circuit startup time and reduces power consumption by using different startup circuits for different frequencies. Furthermore, this invention eliminates the comparator and control logic found in traditional circuits, employing an RS flip-flop, resulting in a smaller chip footprint.

[0052] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A low power fast start-up oscillator circuit characterized by: The application relates to a starting circuit, a bias current generating circuit and an oscillation circuit, the input end of the starting circuit is connected with a starting current I_Start, the first output end of the starting circuit is connected with the first input end of the bias current generating circuit, the second output end of the starting circuit is connected with the second input end of the bias current generating circuit, the oscillation circuit mirrors the current of the bias current generating circuit and alternately charges and discharges two capacitors to generate an OSC signal; the bias current generating circuit comprises PMOS tubes PM1, PM2, PM4, PM5, NMOS tubes NM1, NM2, NM3, NM4, NM5, a switch S1, a resistor R1 and a resistor R2, the source of the PMOS tube PM1, the source of the PMOS tube PM2, the source of the PMOS tube PM4 and the source of the PMOS tube PM5 are connected with a power supply VDD, the gate of the PMOS tube PM1 is connected with the gate of the PMOS tube PM2, the gate of the PMOS tube PM4, the gate of the PMOS tube PM5, the drain of the PMOS tube PM1 and the drain of the NMOS tube NM5 and is connected with a bias voltage VBP, the gate of the NMOS tube NM5 is connected with a bias voltage VBN, the source of the NMOS tube NM5 is connected with the drain of the NMOS tube NM4, the drain of the PMOS tube PM2 is connected with the drain of the NMOS tube NM2, the drain of the NMOS tube NM3, the gate of the NMOS tube NM3 and the gate of the NMOS tube NM4 and serves as the first input end of the bias current generating circuit, the drain of the PMOS tube PM4 is connected with one end of the resistor R2 and the gate of the NMOS tube NM2, the other end of the resistor R2 is connected with one end of the resistor R1 and one end of the switch S1 at a node X, the drain of the PMOS tube PM5, the drain of the NMOS tube NM1 and the gate of the NMOS tube NM1 are connected with the bias voltage VBN and serve as the second input end of the bias current generating circuit, the source of the NMOS tube NM1, the other end of the switch S1, the other end of the resistor R1, the source of the NMOS tube NM2, the source of the NMOS tube NM3 and the source of the NMOS tube NM4 are grounded.

2. A low power consumption fast starting oscillator circuit according to claim 1, characterized in that: The starting circuit comprises PMOS PM3, PMOS PM6, PMOS PM7, PMOS PM8, PMOS PM9 and switch S2, the source of PMOS PM3, the source of PMOS PM6, the source of PMOS PM7, the source of PMOS PM8, the source of PMOS PM9 and the first selection end of switch S2 are connected to power supply VDD, the gate of PMOS PM3 is connected to the gate of PMOS PM6, the gate of PMOS PM7, the drain of PMOS PM7, the drain of PMOS PM8 and the drain of PMOS PM9 and serves as the input end of the starting circuit, the drain of PMOS PM3 serves as the first output end of the starting circuit, the drain of PMOS PM6 serves as the second output end of the starting circuit, the gate of PMOS PM8 is connected to the second selection end of switch S2 and connected to bias voltage VBP, and the gate of PMOS PM9 is connected to the fixed end of switch S2.

3. A low power consumption fast starting oscillator circuit as claimed in claim 2, characterized in that: The PMOS PM3, PMOS PM6 and PMOS PM7 constitute a first PMOS current mirror.

4. The low power consumption fast start-up oscillator circuit according to claim 1, characterized in that: The oscillation circuit comprises PMOS PM10, PMOS PM11, PMOS PM12, NMOS NM7, NMOS NM9, NMOS NM6, NMOS NM8, switch S3, switch S4, capacitor C1, capacitor C2, RS flip-flop and inverter INV1, the source of PMOS PM10, the source of PMOS PM11 and the source of PMOS PM12 are connected to power supply VDD, the gate of PMOS PM10, the gate of PMOS PM11 and the gate of PMOS PM12 are connected to bias voltage VBP, the drain of PMOS PM10 is connected to one end of switch S3 and one end of switch S4, the other end of switch S3 is connected to one end of capacitor C1 and the gate of NMOS NM6, the other end of switch S4 is connected to one end of capacitor C2 and the gate of NMOS NM8, the drain of PMOS PM11 is connected to the drain of NMOS NM7 and the S end of RS flip-flop, the drain of PMOS PM12 is connected to the drain of NMOS NM9 and the R end of RS flip-flop, the gate of NMOS NM7 and the gate of NMOS NM9 are connected to bias voltage VBN, the source of NMOS NM7 is connected to the drain of NMOS NM6, the source of NMOS NM9 is connected to the drain of NMOS NM8, the Q end of RS flip-flop is connected to the input end of inverter INV1 and the control end of switch S4, the Q' end of RS flip-flop is connected to the control end of switch S3, and the output end of inverter INV1 generates oscillation signal CLK.

5. A low power consumption fast starting oscillator circuit as claimed in claim 4, characterized in that: The PMOS PM1, PMOS PM2, PMOS PM4, PMOS PM5, PMOS PM8, PMOS PM10, PMOS PM11 and PMOS PM12 constitute a second PMOS current mirror.

6. A control method of the low-power-consumption quick-start oscillator circuit according to any one of claims 1 to 5, characterized by The method comprises the following steps: When the circuit is not working, there is no current in the circuit, the bias voltage VBP of the gate of PMOS PM1 is high level, and the gate of NMOS NM3 is low level; at this time, the starting circuit works, the starting current I_Strat flows into PMOS PM7, the gate voltage of PMOS PM7 is pulled low, and the gate voltages of NMOS NM3 and NMOS NM1 are pulled high by the currents generated by PMOS PM3 and PMOS PM6 respectively, so that the gate voltages of NMOS NM3 and NMOS NM1 are pulled high, the gate voltages of NMOS NM4 and NMOS NM5 are pulled high to turn on, and the gate voltage of PMOS PM1 is pulled low, so that the circuit generates current; PMOS PM2, PM4, PM5 and PM8 generate current, and when the current of PMOS PM8 is greater than the starting current I_Strat, the gate voltage of PMOS PM7 is pulled high, PMOS PM3, PM6 and PM7 are turned off, the starting circuit is turned off, and the circuit works normally; When the switch S1 is open, the total resistance R=R1+R2 is large, the generated current is small, and since the starting current I_Strat itself is small, the size ratio relationship of PMOS PM8 and PMOS PM1 does not need to be large to turn off the starting circuit; When the switch S1 is closed, the total resistance R=R2 is small, the generated current is large, and if PMOS PM8 and PMOS PM1 control the starting circuit in the same ratio relationship, the circuit has not been completely started, and the starting circuit is turned off, at this time, the gate voltages of PMOS PM3 and NMOS NM1 need a long time to reach a stable state due to the absence of starting current, and the starting time of the circuit is long; if the ratio relationship of PMOS PM8 and PMOS PM1 is small, the circuit can start quickly and be turned off when the total resistance is small, but when the total resistance is large, the current generated by PMOS PM8 is small, which cannot completely turn off PMOS PM7, and the starting circuit is still working; When the total resistance is small, the switch S2 is switched to the power supply VDD, and PMOS PM9 is turned off, only PMOS PM8 is used to turn off the starting circuit; when the total resistance is large, the switch S2 is switched to the bias voltage VBP, PMOS PM9 works, and PMOS PM8 and PMOS PM9 work together to turn off the starting circuit, which improves the starting time of the circuit; The oscillation circuit controls the switches S3 and S4 through the two opposite outputs Q and Q' of the RS flip-flop, so that the capacitors C1 and C2 are alternately charged and discharged, and the voltages of the capacitors C1 and C2 are higher than the threshold voltages of NMOS NM6 and NM8, the input voltage of the RS flip-flop is pulled low, and the state change of the outputs Q and Q' generates an oscillation signal.

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