Semiconductor device and method of manufacturing the same

Abstract

The invention provides a semiconductor device. The semiconductor device includes a substrate, a word line structure, a first gate structure and a second gate structure. The substrate has an active region and a surrounding region surrounding the active region. The word line structure is disposed in the active region of the substrate. The first gate structure is disposed in the peripheral region of the substrate, where a bottom surface of the first gate structure is bent toward the substrate, and the bottom surface of the first gate structure is located below a top surface of the substrate. The second gate structure is disposed in the peripheral region of the substrate, the second gate structure is located between the word line structure and the first gate structure, and the bottom surface of the second gate structure is coplanar with the top surface of the substrate. The bottom surface of the first gate structure is arc-shaped, so that larger driving current can be supported. Therefore, the problem of leakage current can be improved.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In recent decades, as electronic products have continued to improve, the demand for memory capacity has also increased. To increase the storage capacity of memory devices (e.g., dynamic random access memory (DRAM) devices), more memory cells are integrated into the memory. As integration increases, semiconductor devices become smaller. However, smaller devices can introduce leakage current issues.

[0003] Accordingly, the present disclosure provides a semiconductor device and a method for manufacturing the same, wherein the semiconductor device in a peripheral region has a curved bottom surface. Summary of the Invention

[0004] According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a substrate, a word line structure, a first gate structure, and a second gate structure. The substrate has an active region and a peripheral region surrounding the active region. The word line structure is disposed in the active region of the substrate. A first gate structure is disposed in the peripheral region of the substrate, wherein a bottom surface of the first gate structure is curved toward the substrate and the bottom surface of the first gate structure is lower than the top surface of the substrate. A second gate structure is disposed in the peripheral region of the substrate and is located between the word line structure and the first gate structure, wherein the bottom surface of the second gate structure is coplanar with the top surface of the substrate.

[0005] According to some embodiments of the present disclosure, the first gate structure includes a first dielectric layer disposed below the top surface of the substrate, a first lower conductive layer disposed on the first dielectric layer, a first upper conductive layer disposed on the first lower conductive layer, and a first top cap layer disposed on the first upper conductive layer.

[0006] According to some embodiments of the present disclosure, the first dielectric layer has a U-shaped cross-sectional profile.

[0007] According to some embodiments of the present disclosure, the bottom surface of the first lower conductive layer is curved and located below the top surface of the substrate, and the top surface of the first lower conductive layer is located above the top surface of the substrate.

[0008] According to some embodiments of the present disclosure, the second gate structure includes a second dielectric layer disposed above the top surface of the substrate, a second lower conductive layer disposed on the second dielectric layer, a second upper conductive layer disposed on the second lower conductive layer, and a second top cover layer disposed on the second upper conductive layer.

[0009] According to some embodiments of the present disclosure, a first height from the top surface of the substrate to the top surface of the first lower conductive layer is equal to a second height from the top surface of the substrate to the top surface of the second lower conductive layer.

[0010] According to some embodiments of the present disclosure, a first thickness of the first lower conductive layer at a central axis is greater than a second thickness of the second lower conductive layer at a central axis.

[0011] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes the following steps: forming a word line structure in an active area of ​​a substrate; forming a hard mask layer on the word line structure in the active area and in a peripheral area of ​​the substrate; forming a photoresist on the hard mask layer, wherein the photoresist is located in the peripheral area of ​​the substrate; forming an oxide layer covering the photoresist and the hard mask layer; performing an etch-back process to remove a portion of the oxide layer and expose the top surface of the photoresist; stripping the photoresist to form an opening in the oxide layer; etching the hard mask layer and a portion of the substrate from the opening in the oxide layer to form a groove, wherein the bottom surface of the groove is arc-shaped; forming a first gate structure in the groove.

[0012] According to some embodiments of the present disclosure, before forming the first gate structure in the recess, the method further includes removing the oxide layer and the hard mask layer.

[0013] According to some embodiments of the present disclosure, forming the hard mask layer includes forming an underlayer on the substrate, and forming an anti-reflective coating on the underlayer.

[0014] According to some embodiments of the present disclosure, the method further includes forming a second gate structure in a peripheral region of the substrate, wherein the second gate structure is located between the word line structure and the first gate structure.

[0015] According to some embodiments of the present disclosure, forming a first gate structure in a groove and forming a second gate structure include forming a dielectric layer on a substrate, forming a lower conductive layer on the dielectric layer, wherein the lower conductive layer fills the groove and the top surface of the lower conductive layer is parallel to the top surface of the substrate, forming an upper conductive layer on the lower conductive layer, and forming a top cover layer on the upper conductive layer.

[0016] According to some embodiments of the present disclosure, the method further includes forming a first gate photoresist and a second gate photoresist on the cap layer, wherein the first gate photoresist is disposed on the groove, and the second gate photoresist is disposed between the word line structure and the first gate photoresist.

[0017] According to some embodiments of the present disclosure, the method further includes removing the cap layer, the upper conductive layer, the lower conductive layer, and the dielectric layer not covered by the first gate photoresist and the second gate photoresist to form the first gate structure and the second gate structure.

[0018] According to some embodiments of the present disclosure, the method further includes stripping the first gate photoresist and the second gate photoresist.

[0019] It is to be understood that both the foregoing general description and the following detailed description are by way of examples, and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present disclosure may be more fully understood by reading the following detailed description of the embodiments in conjunction with the accompanying drawings:

[0021] Figure 1 is a schematic cross-sectional view of a semiconductor device according to some embodiments.

[0022] Figure 2 FIG. 4 is a schematic cross-sectional view of a semiconductor device after exposing a top surface of a peripheral region of a substrate according to some embodiments.

[0023] Figure 3 FIG. 4 is a schematic cross-sectional view of a semiconductor device after forming a hard mask layer and a photoresist according to some embodiments.

[0024] Figure 4 FIG. 4 is a schematic cross-sectional view of a semiconductor device after forming an oxide layer covering a hard mask layer and a photoresist according to some embodiments.

[0025] Figure 5 FIG. 4 is a schematic cross-sectional view of a semiconductor device after a portion of an oxide layer is removed according to some embodiments.

[0026] Figure 6 is a schematic cross-sectional view of a semiconductor device after photoresist stripping according to some embodiments.

[0027] Figure 7 is a schematic cross-sectional view of a semiconductor device after etching a portion of a hard mask layer according to some embodiments.

[0028] Figure 8 FIG. 4 is a schematic cross-sectional view of a semiconductor device after etching a portion of a substrate according to some embodiments.

[0029] Figure 9 is a schematic cross-sectional view of a semiconductor device after the hard mask layer is removed according to some embodiments.

[0030] Figure 10 is a schematic cross-sectional view of a semiconductor device after a dielectric layer, a lower conductive layer, an upper conductive layer, and a cap layer are formed according to some embodiments.

[0031] Figure 11 FIG. 4 is a schematic cross-sectional view of a semiconductor device after forming a first gate structure and a second gate structure according to some embodiments.

[0032] Figure 12According to some embodiments Figure 11 An enlarged cross-sectional schematic diagram of a semiconductor device. DETAILED DESCRIPTION

[0033] Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0034] It should be understood that the following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific embodiments or examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or symbols in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself specify the relationship between the various embodiments and / or configurations discussed.

[0035] Furthermore, for ease of description, the present disclosure may use spatially relative terms, such as "below," "beneath," "lower," "above," "upper," etc., to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0036] It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers may be present.

[0037] Figure 1 is a schematic cross-sectional view of a semiconductor device 100 according to some embodiments. Figure 1The semiconductor device 100 includes a substrate 110, wherein the substrate 110 has an active region A1 and a peripheral region A2 surrounding the active region A1. In some embodiments, the peripheral region A2 is located at the periphery of the substrate 110 and surrounds the active region A1. In some embodiments, the substrate 110 may be, for example, a silicon (Si) substrate. Alternatively, the substrate 110 may be a silicon substrate doped with other IV-IV, III-V, or II-VI semiconductor materials. In some other embodiments, the substrate 110 may include a layered semiconductor, such as silicon / silicon germanium, silicon-on-insulator, or silicon germanium-on-insulator.

[0038] In some embodiments, active region A1 may be doped with an N-type dopant such as phosphorus (P), arsenic (As), or antimony (Sb). In other embodiments, active region A1 may be doped with a P-type dopant such as boron (B) or indium (In). In some embodiments, substrate 110 may be or include an undoped region. In some embodiments, active region A1 may have a higher doping concentration than substrate 110.

[0039] In some embodiments, the hard mask 120 and the insulating layer 130 may be formed on the active area A1 and the peripheral area A2 of the substrate 110. In some embodiments, the gate structure 140 and the word line structure W may be formed in the active area A1. The gate structure 140 may include a bottom conductive layer 142, an intermediate conductive layer 144, and a top conductive layer 146. The top conductive layer 146 is formed on the intermediate conductive layer 144 and covers the insulating layer 130. In some embodiments, the material of the bottom conductive layer 142 may be a metal nitride, such as TiN. In some embodiments, the material of the intermediate conductive layer 144 may be polysilicon. In some embodiments, the material of the top conductive layer 146 may be a metal nitride, such as TiN. The remaining portion of the material of the top conductive layer 146 located on the substrate 110 may be considered a word line structure W, wherein the word line structure W is a linear structure and is connected to the corresponding gate structure 140.

[0040] See also Figure 2 A mask (not shown) is formed to cover the active area A1 of the substrate 110. After forming the mask covering the active area A1 of the substrate 110, one or more etching processes are performed to remove portions of the hard mask 120, the insulating layer 130, and the top conductive layer 146 that are not protected by the mask. After performing the one or more etching processes, the top surface 112 of the substrate 110 at the peripheral area A2 is exposed. Then, after removing a portion of the hard mask 120, the insulating layer 130, and the top conductive layer 146, the mask is removed.

[0041] refer to Figure 3 The hard mask layer 150 is formed on the word line structure W of the active area A1 of the substrate 110 and on the peripheral area A2. In some embodiments, the hard mask layer 150 includes a bottom layer 152 and an anti-reflective coating 154. The bottom layer 152 is formed on the substrate 110, and the anti-reflective coating 154 is formed on the bottom layer 152. Figure 3 A photoresist 160 is formed on the hard mask layer 150 , wherein the photoresist 160 is located in the peripheral area A2 of the substrate 110 . In other words, the photoresist 160 is formed on the anti-reflective coating layer 154 .

[0042] refer to Figure 4 An oxide layer 170 is formed to cover the photoresist 160 and the hard mask layer 150. The oxide layer 170 is formed by a suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). The oxide layer 170 covers the photoresist 160 and the hard mask layer 150 in the peripheral area A2. The oxide layer 170 can also cover the hard mask layer 150 in the active area A1. The oxide layer 170 can also fill the gap between the two photoresists 160.

[0043] refer to Figure 5 , a portion of the oxide layer 170 is removed. In some embodiments, an etch-back process is performed to remove a portion of the oxide layer 170. After the etch-back process, the top surface of the photoresist 160 is exposed. For example, a chemical mechanical polishing process can be performed to make the top surface of the photoresist 160 coplanar with the top surface of the oxide layer 170. In other words, the oxide layer 170 still covers the hard mask layer 150 located in the active area A1.

[0044] Next, refer to Figure 6 , the photoresist 160 is stripped to form an opening 172 in the oxide layer 170 and expose the top surface of the anti-reflective coating 154. A portion of the oxide layer 170 may be removed so that the thickness of the oxide layer 170 becomes thinner. Figure 7 , a portion of hard mask layer 150 is removed through opening 172 to form opening 174 in oxide layer 170 and hard mask layer 150. After forming opening 174, a portion of top surface 112 of substrate 110 is exposed. Opening 174 is deeper than opening 172. The bottom surface of opening 174 is flat. In other words, top surface 112 of substrate 110 is not removed.

[0045] refer to Figure 8, a portion of the top surface 112 of the substrate 110 is removed through the opening 174 to form a groove 176 in the substrate 110. In some embodiments, the bottom surface of the groove 176 is curved toward the bottom surface 114 of the substrate 110. The groove 176 has a substantially semicircular cross-sectional shape. Figure 9 The oxide layer 170 and the hard mask layer 150 are removed to expose the top surface 112 of the peripheral area A2 of the substrate 110. In some embodiments, the word line structure W in the active area A1 may be exposed.

[0046] refer to Figure 10 , a dielectric layer 180, a lower conductive layer 182, an upper conductive layer 184, and a cap layer 186 are formed on the substrate 110. First, the dielectric layer 180 is formed on the substrate 110, wherein the dielectric layer 180 fills a portion of the groove 176. The lower conductive layer 182 is formed on the dielectric layer 180, wherein the lower conductive layer 182 fills the groove 176, and the top surface of the lower conductive layer 182 is parallel to the top surface 112 of the substrate 110. Then, the upper conductive layer 184 is formed on the lower conductive layer 182. Finally, the cap layer 186 is formed on the upper conductive layer 184.

[0047] Dielectric layer 180, lower conductive layer 182, upper conductive layer 184, and cap layer 186 are formed by a suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). In some embodiments, dielectric layer 180 may include an oxide. In some embodiments, lower conductive layer 182 may include polysilicon. In some embodiments, upper conductive layer 184 may include a metal, such as tungsten. In some embodiments, cap layer 186 may include a nitride.

[0048] Still refer to Figure 10 , a first gate photoresist 190 and a second gate photoresist 192 are formed on the cap layer 186 , wherein the first gate photoresist 190 is disposed on the groove 176 , and the second gate photoresist 192 is disposed between the word line structure W and the first gate photoresist 190 . Figure 11 , the cap layer 186, the upper conductive layer 184, the lower conductive layer 182 and the dielectric layer 180 not covered by the first gate photoresist 190 and the second gate photoresist 192 are removed to form the first gate structure 200 and the second gate structure 210. Then, the first gate photoresist 190 and the second gate photoresist 192 are stripped.

[0049] Figure 12 yes Figure 11 Schematic diagram of the enlarged cross section. Figure 11 and Figure 12The first gate structure 200 is disposed in the peripheral area A2 of the substrate 110. The bottom surface of the first gate structure 200 is curved toward the bottom surface 114 of the substrate 110, and the bottom surface 200B of the first gate structure 200 is located below the top surface 112 of the substrate 110. The second gate structure 210 is disposed in the peripheral area A2 of the substrate 110, and the second gate structure 210 is located between the word line structure W and the first gate structure 200, wherein the bottom surface 214B of the second gate structure 210 is coplanar with the top surface 112 of the substrate 110.

[0050] The first gate structure 200 includes a first dielectric layer 202, a first lower conductive layer 204, a first upper conductive layer 206, and a first capping layer 208. The first dielectric layer 202 is disposed below the top surface 112 of the substrate 110. The first lower conductive layer 204 is disposed on the first dielectric layer 202. The first upper conductive layer 206 is disposed on the first lower conductive layer 204. The first capping layer 208 is disposed on the first upper conductive layer 206.

[0051] In some embodiments, the first dielectric layer 202 has a U-shaped cross-sectional profile. The bottom surface 204B of the first lower conductive layer 204 is curved and located below the top surface 112 of the substrate 110 , while the top surface 204T of the first lower conductive layer 204 is located above the top surface 112 of the substrate 110 .

[0052] The second gate structure 210 includes a second dielectric layer 212, a second lower conductive layer 214, a second upper conductive layer 216, and a second cap layer 218. The second dielectric layer 212 is disposed on the top surface 112 of the substrate 110. The second lower conductive layer 214 is disposed on the second dielectric layer 212. The second upper conductive layer 216 is disposed on the second lower conductive layer 214. The second cap layer 218 is disposed on the second upper conductive layer 216.

[0053] In some embodiments, a first height H1 from the top surface 112 of the substrate 110 to the top surface 204T of the first lower conductive layer 204 is equal to a second height H2 from the top surface 112 of the substrate 110 to the top surface 214T of the first lower conductive layer 204. In some embodiments, a first thickness T1 (bottom surface 204B to top surface 204T) at the first central axis C1 of the first lower conductive layer 204 is greater than a second thickness T2 (bottom surface 214B to top surface 214T) at the second central axis C2 of the second lower conductive layer 214.

[0054] This disclosure provides a method for manufacturing a semiconductor device. The peripheral region of the semiconductor device includes a first gate structure and a second gate structure. The bottom surface of the first gate structure is curved, while the bottom surface of the second gate structure is flat. The first gate structure can support a higher drive current. The disclosed semiconductor device can also improve leakage current issues.

[0055] Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0056] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and variations of the present disclosure that fall within the scope of the appended claims.

[0057]

Explanation of symbols

[0058] 100:Semiconductor device

[0059] 110:Substrate

[0060] 112: Top surface

[0061] 114: bottom surface

[0062] 120:Hard Mask

[0063] 130: Insulation layer

[0064] 140: Gate structure

[0065] 142: bottom conductive layer

[0066] 144: Middle conductive layer

[0067] 146: top conductive layer

[0068] 150:Hard mask layer

[0069] 152: Bottom

[0070] 154: Anti-reflective coating

[0071] 160: Photoresist

[0072] 170: oxide layer

[0073] 172: Opening

[0074] 174: Open

[0075] 176: Groove

[0076] 180: Dielectric layer

[0077] 182: lower conductive layer

[0078] 184: Upper conductive layer

[0079] 186: Top cover

[0080] 190: first gate photoresist

[0081] 192: Second gate photoresist

[0082] 200: first gate structure

[0083] 200B: bottom surface

[0084] 202: first dielectric layer

[0085] 204: lower conductive layer

[0086] 204B: bottom surface

[0087] 204T: Top surface

[0088] 206: first upper conductive layer

[0089] 208: First top cover layer

[0090] 210: Second gate structure

[0091] 212: Second dielectric layer

[0092] 214: second lower conductive layer

[0093] 214B: bottom surface

[0094] 214T: Top surface

[0095] 216: second upper conductive layer

[0096] 218: Second top cover layer

[0097] A1: Active area

[0098] A2: Surrounding area

[0099] C1: First central axis

[0100] C2: Second central axis

[0101] H1: First Height

[0102] H2: Second height

[0103] T1: First thickness

[0104] T2: Second thickness

[0105] W: Character line structure.

Claims

1. A semiconductor device, characterized in that: include: A substrate having an active region and a peripheral region surrounding the active region; A word line structure is disposed in the active area of ​​the substrate; a first gate structure disposed in the peripheral region of the substrate, wherein a bottom surface of the first gate structure is bent toward the substrate and is lower than a top surface of the substrate; and The second gate structure is disposed in the peripheral area of ​​the substrate and is located between the word line structure and the first gate structure, wherein the bottom surface of the second gate structure is coplanar with the top surface of the substrate.

2. The semiconductor device according to claim 1, wherein The first gate structure includes: A first dielectric layer is disposed below the top surface of the substrate; a first lower conductive layer disposed on the first dielectric layer; A first upper conductive layer is disposed on the first lower conductive layer; and The first top cover layer is disposed on the first upper conductive layer.

3. The semiconductor device according to claim 2, wherein The first dielectric layer has a U-shaped cross-sectional profile.

4. The semiconductor device according to claim 2, wherein A bottom surface of the first lower conductive layer is curved and is located below the top surface of the substrate, and a top surface of the first lower conductive layer is located above the top surface of the substrate.

5. The semiconductor device according to claim 2, wherein The second gate structure includes: a second dielectric layer disposed over the top surface of the substrate; a second lower conductive layer disposed on the second dielectric layer; A second upper conductive layer is disposed on the second lower conductive layer; and The second top cover layer is disposed on the second upper conductive layer.

6. The semiconductor device according to claim 5, wherein A first height from the top surface of the substrate to the top surface of the first lower conductive layer is equal to a second height from the top surface of the substrate to the top surface of the second lower conductive layer.

7. The semiconductor device according to claim 5, wherein A first thickness of the first lower conductive layer at a central axis is greater than a second thickness of the second lower conductive layer at a central axis.

8. A method for manufacturing a semiconductor device, characterized in that: include: forming a word line structure in an active region of the substrate; forming a hard mask layer on the word line structure in the active region and in a peripheral region of the substrate; forming a photoresist on the hard mask layer, wherein the photoresist is located in the peripheral region of the substrate; forming an oxide layer to cover the photoresist and the hard mask layer; performing an etch-back process to remove a portion of the oxide layer and expose a top surface of the photoresist; stripping the photoresist to form an opening in the oxide layer; Etching the hard mask layer and a portion of the substrate through the opening in the oxide layer to form a groove, wherein a bottom surface of the groove is arc-shaped; and A first gate structure is formed in the groove.

9. The method according to claim 8, characterized in that Before forming the first gate structure in the groove, the method further includes: The oxide layer and the hard mask layer are removed.

10. The method according to claim 8, characterized in that Forming the hard mask layer includes: forming a bottom layer on the substrate; and An antireflective coating is formed on the base layer.

11. The method according to claim 8, characterized in that Further including: A second gate structure is formed in the peripheral area of ​​the substrate, and the second gate structure is located between the word line structure and the first gate structure.

12. The method according to claim 11, characterized in that The forming of the first gate structure and the forming of the second gate structure in the groove comprises: forming a dielectric layer on the substrate; forming a lower conductive layer on the dielectric layer, wherein the lower conductive layer fills the groove, and the top surface of the lower conductive layer is parallel to the top surface of the substrate; forming an upper conductive layer on the lower conductive layer; and A cap layer is formed on the upper conductive layer.

13. The method according to claim 12, characterized in that Further including: A first gate photoresist and a second gate photoresist are formed on the cap layer, wherein the first gate photoresist is disposed on the groove, and the second gate photoresist is disposed between the word line structure and the first gate photoresist.

14. The method according to claim 13, characterized in that Further including: The top cap layer, the upper conductive layer, the lower conductive layer, and the dielectric layer not covered by the first gate photoresist and the second gate photoresist are removed to form the first gate structure and the second gate structure.

15. The method according to claim 14, characterized in that Further including: The first gate photoresist and the second gate photoresist are stripped off.

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