Semiconductor structure and preparation method thereof, and memory system

Abstract

The embodiment of the invention provides a semiconductor structure and a preparation method thereof, and a memory system. The semiconductor structure comprises a lamination structure, a grid line isolation structure and a contact structure. The laminated structure comprises a first region where a plurality of steps are formed, and each step comprises a first dielectric layer and a first gate layer which are stacked in the first direction. The grid line isolation structure passes through the laminated structure along a first direction and extends along a second direction intersecting with the first direction. The contact structures penetrate through the corresponding steps in the first direction and are connected with the first gate layers of the corresponding steps, the portions, between the gate line isolation structures and the contact structures, of the first gate layers extend in the third direction, and the third direction intersects with the first direction and the second direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor design and manufacturing, and more specifically, to a semiconductor structure, a method for preparing a semiconductor structure, and a memory system. Background Art

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices, and cloud storage, the requirements for the storage density of semiconductor structures such as three-dimensional memory are becoming increasingly higher. However, due to factors such as process, equipment, and materials, it is difficult to further increase the storage density of semiconductor structures.

[0003] In addition, with the increase in the number of stacked layers and the improvement in storage density per unit area in semiconductor structures such as three-dimensional memories, the process steps in the preparation of semiconductor structures have become complicated and lengthy, and the preparation cost of semiconductor structures has also gradually increased.

[0004] Therefore, how to simplify the preparation process of the semiconductor structure and reduce the preparation cost of the semiconductor structure while taking into account the reliability and overall performance of the semiconductor structure is an urgent problem to be solved. Summary of the Invention

[0005] The embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, and a memory system that can at least partially solve the above-mentioned technical problems or other problems.

[0006] On one hand, the present application provides a semiconductor structure, which includes: a stacked structure, including a first region formed with a plurality of steps, the steps including a first dielectric layer and a first gate layer stacked along a first direction, a gate line isolation structure, which passes through the stacked structure along the first direction and extends along a second direction intersecting with the first direction; and a contact structure, which passes through the corresponding steps along the first direction and is connected to the first gate layer of the corresponding steps, wherein a portion of the first gate layer between the gate line isolation structure and the contact structure extends along a third direction, and the third direction intersects with the first direction and the second direction.

[0007] In one embodiment of the present application, the stacked structure also includes a second region distributed adjacent to the first region in the second direction; and the gate line isolation structure includes: a first gate line isolation structure, extending along the second direction and passing through the first region and the second region; a second gate line isolation structure, extending along the second direction in the second region; and a third gate line isolation structure, extending along the second direction in the first region, wherein the second gate line isolation structure and the third gate line isolation structure are both located between adjacent first gate line isolation structures along the third direction.

[0008] In one embodiment of the present application, the second gate line isolation structure and the third gate line isolation structure are staggered along the third direction.

[0009] In one embodiment of the present application, the first gate line isolation structure includes a first sub-portion, an isolation structure, and a second sub-portion extending along the second direction and spaced apart from each other, wherein the first sub-portion is located in the first region, the isolation structure is located on a side of the second region close to the first region, and the second sub-portion is located in the second region.

[0010] In one embodiment of the present application, the gate line isolation structure includes a sidewall in contact with the stacked structure, wherein a surface of the sidewall is a curved surface, and the curved surface includes at least one of a concave surface and a convex surface.

[0011] In one embodiment of the present application, both sides of the side wall along the second direction have a wavy shape.

[0012] In one embodiment of the present application, the stacked structure further includes a second dielectric layer distributed adjacent to the first gate layer in the second direction.

[0013] In one embodiment of the present application, the surface of the first gate layer in contact with the second dielectric layer is a curved surface, and the curved surface includes at least one of a concave surface and a convex surface.

[0014] In one embodiment of the present application, along the first direction, the thickness of the first gate layer of the step is greater than the thickness of the second gate layer located below the step.

[0015] In one embodiment of the present application, in a direction intersecting with the first direction, a size of the first gate layer is larger than a size of the second gate layer.

[0016] In one embodiment of the present application, the contact structure passes through the stacked structure along the first direction and is connected to the first gate layer and the second gate layer respectively.

[0017] In one embodiment of the present application, the contact structure includes a contact conductive layer and a dielectric filling layer wrapped by the contact conductive layer, wherein the contact conductive layer extends along the first direction and is connected to the first gate layer.

[0018] Another aspect of the present application provides a memory system, comprising: a controller; and the semiconductor structure provided in any one aspect of the present application, wherein the controller is coupled to the memory and is configured to control the semiconductor structure to store data.

[0019] On the other hand, the present application provides a method for preparing a semiconductor structure, the method comprising: forming a stacked structure, wherein a first region of the stacked structure comprises a plurality of steps, the steps comprising a stacked first dielectric layer and a gate sacrificial layer; forming a contact hole and a gate line gap, the contact hole passing through the step along a first direction, the gate line gap passing through the stacked structure along the first direction and extending along a second direction intersecting the first direction; removing a portion of the gate sacrificial layer via the gate line gap and the contact hole to form a sacrificial gap, and forming a first gate layer in the sacrificial gap, wherein a portion of the first gate layer between the gate line gap and the contact hole extends along a third direction, wherein the third direction intersects with the first direction and the second direction.

[0020] In one embodiment of the present application, forming contact holes and gate line gaps includes: forming contact holes; forming first holes passing through the stacking structure along a first direction, wherein a plurality of the first holes are arranged at intervals along the second direction; and removing at least a portion of the stacking structure located between adjacent first holes in the second direction to form the gate line gaps.

[0021] In one embodiment of the present application, forming the contact hole and the gate line gap further includes: forming the contact hole in the process of forming the first hole.

[0022] In one embodiment of the present application, the stacking structure also includes a second region distributed adjacent to the first region in the second direction, and the method also includes: forming a channel hole located in the second region in the process of forming the first hole; and / or forming a virtual channel hole located in the first region in the process of forming the first hole.

[0023] In one embodiment of the present application, the sacrificial gap includes a first gap located in the first area and a second gap located in the second area, and a portion of the gate sacrificial layer is removed through the gate line gap and the contact hole to form the sacrificial gap, including: removing a portion of the gate sacrificial layer located at the edge of the gate line gap through the portion of the gate line gap located in the first area, and continuing to remove a portion of the gate sacrificial layer through the portion of the gate line gap located in the first area and the contact hole to form the first gap; and removing a portion of the gate sacrificial layer located in the second area through the portion of the gate line gap located in the second area to form the second gap connected to the first gap.

[0024] In one embodiment of the present application, the gate sacrificial layer includes a first surface and a second surface opposite to each other in the first direction, and a third surface connecting the first surface and the second surface. Continuing to remove part of the gate sacrificial layer through the portion of the gate line gap located in the first region and the contact hole includes: removing a portion of the gate sacrificial layer of the step from the first surface and the third surface of the gate sacrificial layer of the step; and removing a portion of the gate sacrificial layer located below the step from the third surface of the gate sacrificial layer located below the step.

[0025] In one embodiment of the present application, the method further includes: filling the gate line gap and the contact hole with a first sacrificial layer; and forming a channel structure in the channel hole, and forming a dummy channel structure in the dummy channel hole.

[0026] In one embodiment of the present application, the step also includes a second sacrificial layer located on the gate sacrificial layer, and continuing to remove part of the gate sacrificial layer through the portion of the gate line gap located in the first area and the contact hole also includes: removing the first sacrificial layer and the second sacrificial layer to expose the first surface of the gate sacrificial layer of the step, and continuing to remove part of the gate sacrificial layer through the exposed gate line gap and the contact hole.

[0027] In one embodiment of the present application, the method further includes: before removing a portion of the gate sacrificial layer through the gate line gap and the contact hole, forming an isolation structure in a portion of the gate line gap located in the second region and close to the first region.

[0028] In one embodiment of the present application, the method further includes: forming a contact conductive layer on an inner wall of the contact hole in the process of forming the first gate layer; and forming a dielectric filling layer in a remaining space of the contact hole.

[0029] According to at least one embodiment of the present application, a semiconductor structure, a preparation method thereof, and a memory system are provided. The semiconductor structure includes a stacked structure, a gate line isolation structure, and a contact structure, wherein the stacked structure includes a plurality of steps, the contact structure passes through the corresponding steps along the stacking direction of the stacked structure (hereinafter referred to as the first direction) and is connected to the gate layer of the corresponding step, the gate line isolation structure extends along a second direction intersecting with the first direction, wherein the portion of the gate layer between the gate line isolation structure and the contact structure extends along a third direction intersecting with both the first direction and the second direction. In other words, in the semiconductor structure provided in the embodiment of the present application, the contact structure can pass through the corresponding steps along the stacking direction, thereby reducing the over-etching that occurs in the process of forming the contact hole to accommodate the contact structure, thereby reducing the possibility of short circuits between the gate layers due to breakdown of the gate layer and failure of the semiconductor structure. In addition, the portion of the gate layer connected to the contact structure is only located between the gate line isolation structure and the contact structure along the third direction, which can improve the reliability and storage density of the semiconductor structure while achieving a good connection between the gate layer and the contact structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Other features, objectives and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings. In the drawings:

[0031] Figure 1 is a schematic top view of a semiconductor structure according to one embodiment of the present application;

[0032] Figure 2A yes Figure 1 The semiconductor structure shown is a schematic cross-sectional view taken along line AA';

[0033] Figure 2B yes Figure 1 A schematic cross-sectional view of the semiconductor structure shown is taken along line BB';

[0034] Figure 2C yes Figure 1 A schematic cross-sectional view of the semiconductor structure shown is taken along line CC';

[0035] Figure 2D yes Figure 1 The semiconductor structure is shown as a schematic cross-sectional view taken along line DD';

[0036] Figure 3 is a schematic top view of a gate line isolation structure according to one embodiment of the present application;

[0037] Figure 4 is a schematic cross-sectional view of a channel structure and a dummy channel structure according to one embodiment of the present application;

[0038] Figure 5 is a flow chart of a method for preparing a semiconductor structure according to one embodiment of the present application;

[0039] Figure 6-Figure 59 are schematic process diagrams of a method for preparing a semiconductor structure according to one embodiment of the present application; and

[0040] Figure 60 It is a schematic diagram of the memory system structure according to one embodiment of the present application.

[0041] Specific methods

[0042] The present application will be described in detail below in conjunction with the accompanying drawings. The exemplary embodiments mentioned herein are only used to explain the present application and are not used to limit the scope of the present application. Throughout the specification, the same reference numerals refer to the same elements.

[0043] In the drawings, the thickness, size, and shape of components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used to indicate approximation, not degree, and are intended to account for the inherent variations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0044] It should also be understood that the expression "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "including", "including", "having", "having" and / or "having" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or parts, but do not exclude the presence or addition of one or more other features, elements, parts and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. When describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". Also, the term "exemplary" is intended to refer to an example or illustration.

[0045] In addition, when the expressions “connected”, “covered” and / or “formed on” are used in the present application, it may indicate that the corresponding components are in direct contact or indirect contact, unless otherwise clearly defined or inferred from the context.

[0046] Unless otherwise specified, all words used in this document (including technical terms and scientific terms) have the same meaning as commonly understood by those of ordinary skill in the art to which this application belongs. In addition, unless otherwise specified in this application, words defined in commonly used dictionaries should be interpreted as having the same meaning as they have in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0047] It should be noted that, unless there is a conflict, the embodiments and features of the embodiments in this application can be combined with each other. In addition, unless explicitly limited or inconsistent with the context, the specific steps in the methods described in this application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0048] Figure 1 is a schematic top view of a semiconductor structure 1000 according to one embodiment of the present application.

[0049] Figure 2A It will Figure 1 The semiconductor structure 1000 is shown as a schematic cross-sectional view taken along line AA′.

[0050] Figure 2B It will Figure 1 The semiconductor structure 1000 is shown as a schematic cross-sectional view taken along line BB′.

[0051] Figure 2C It will Figure 1 The semiconductor structure 1000 is shown as a schematic cross-sectional view taken along line CC′. Figure 2D It will Figure 1 The semiconductor structure 1000 is shown as a schematic cross-sectional view taken along line DD′.

[0052] like Figure 1-2D As shown, the semiconductor structure 1000 includes a stacked structure 200, a gate isolation structure 400, and a contact structure 600. The stacked structure 200 includes a first region 01 having a plurality of steps 21 formed therein. The steps 21 include a first dielectric layer 220 and a first gate layer 211 stacked along a first direction (z-direction). The gate isolation structure 400 passes through the stacked structure 200 along the z-direction and extends along a second direction (x-direction) intersecting the z-direction. The contact structure 600 passes through the corresponding step 21 along the z-direction and connects to the first gate layer 211 of the corresponding step 21. The portion 211-1 of the first gate layer 211 between the gate isolation structure 400 and the contact structure 600 extends along a third direction (y-direction), with the x-direction, y-direction, and z-direction intersecting each other.

[0053] Taking a three-dimensional memory as an example, the semiconductor structure may include a stacked structure formed by alternating gate layers and first dielectric layers, wherein a contact structure located in a step region of the stacked structure may enable electrical connection between the gate layer and an external circuit.

[0054] The contact structure can be accommodated in a contact hole formed by processes such as photolithography and etching and having a predetermined depth along the stacking direction, so as to form a connection with the gate layer at different stacking heights. However, with the improvement of the integration of the semiconductor structure and the increase in the number of stacking layers, the depth of the contact hole connected to the gate layer at a lower stacking height is increasingly deepened, so that over-etching is very likely to occur in the process of forming the contact hole, causing the gate layer to be broken down, and then causing a short circuit between different gate layers. In the semiconductor structure provided in the embodiment of the present application, the semiconductor structure includes a stacked structure, a gate line isolation structure and a contact structure, wherein the stacked structure includes a plurality of steps, the contact structure passes through the corresponding steps along the stacking direction of the stacked structure (hereinafter referred to as the first direction) and is connected to the gate layer of the corresponding step, the gate line isolation structure extends along a second direction intersecting with the first direction, wherein the portion of the gate layer between the gate line isolation structure and the contact structure extends along a third direction intersecting with both the first direction and the second direction.

[0055] In other words, in the semiconductor structure provided by the embodiments of the present application, the contact structure can pass through the corresponding step along the stacking direction, thereby reducing overetching during the formation of the contact hole to accommodate the contact structure, thereby reducing the possibility of shorting between gate layers due to gate layer breakdown and semiconductor structure failure. In addition, the portion of the gate layer connected to the contact structure is located only along the third direction between the gate line isolation structure and the contact structure, which can improve the reliability and storage density of the semiconductor structure while achieving a good connection between the gate layer and the contact structure.

[0056] Specifically, in some embodiments of the present application, the stacked structure 200 may include a first dielectric layer 220 and a composite layer 240 stacked along the z-direction, wherein the composite layer 240 may include a gate layer 210 and a second dielectric layer 230 disposed in the same layer. In other words, the gate layer 210 and the second dielectric layer 230 are adjacently distributed in the xy plane, for example, the gate layer 210 and the second dielectric layer 230 are adjacently distributed in the x-direction.

[0057] The stacked structure 200 may include a plurality of stacked layer pairs, wherein the stacked layer pairs may include a pair of first dielectric layers 220 and composite layers 240. For example, the stacked structure 200 may include 64 pairs, 128 pairs, or more than 128 pairs of stacked layer pairs.

[0058] Optionally, refer to Figure 1 and Figure 2B , the gate layer 210 may include a first gate layer 211 and a second gate layer 212. For example, Figure 2B The dotted box in FIG. 2 shows a plurality of steps 21 of the stacked structure 200, wherein the step 21 may include a stacked layer pair including a first dielectric layer 220 and a first gate layer 211. The portion of the stacked structure 200 below the step 21 may further include a plurality of stacked layer pairs including a first dielectric layer 220 and a second gate layer 212.

[0059] As an option, a thickness H1 of the first gate layer 211 along the z-direction is greater than a thickness H2 of the second gate layer 212 located below the step 21. Alternatively, in a direction intersecting the z-direction, such as the x-direction or the y-direction, a dimension D1 of the first gate layer 211 is greater than a dimension D2 of the second gate layer 212.

[0060] Optionally, the contact structure 600 passes through the stacked structure 200 along the z-direction and is respectively connected to the first gate layer 211 and the plurality of second gate layers 212. With this arrangement, the contact structure can pass through the corresponding steps along the stacking direction, thereby reducing over-etching during the formation of contact holes to accommodate the contact structure, thereby reducing the possibility of short circuits between gate layers due to gate layer breakdown, and thus reducing the possibility of semiconductor structure failure.

[0061] Furthermore, in one embodiment of the present application, the multiple contact structures 600 may have the same extension along the z-direction. For example, the multiple contact structures 600 all extend through the stacked structure 200 along the z-direction and have the same extension along the z-direction. Thus, the multiple contact structures 600 corresponding to different steps 21 can be formed in the same process. For example, multiple contact holes (not shown) extending through the stacked structure 200 along the z-direction may be formed in the same step, and the multiple contact holes may be filled in the same step to form the multiple contact structures 600. This simplifies the semiconductor structure fabrication process and reduces the fabrication cost of the semiconductor structure.

[0062] Furthermore, although the contact structure extends along the z-direction and connects to multiple gate layers (e.g., the first gate layer 211 and the multiple second gate layers 212) of the stacked structure, the first gate layer is larger than the second gate layer in a direction intersecting the z-direction, and the contact structure can only form substantial and effective electrical communication with the first gate layer. Furthermore, the second gate layer can be effectively isolated by a second dielectric layer disposed on the same layer as the second gate layer, thereby enabling different gate layers to achieve electrical communication with external circuits through the contact structure located in the step region of the stacked structure, while also improving the reliability and storage density of the semiconductor structure.

[0063] In other words, in at least one embodiment of the present application, the first gate layer 211 and the second gate layer 212 may both include a conductive material layer, and the first gate layer 211 and the second gate layer 212 are both connected to the contact structure 600, wherein the first gate layer 211 is connected to the contact structure 600, and an electrical connection is formed between the two; although the second gate layer 212 is also connected to the contact structure 600, since the size of the first gate layer 211 is larger than the size of the second gate layer 212 in the direction intersecting with the z direction, and the second gate layer is effectively isolated by the second dielectric layer arranged on the same layer as it, the second gate layer 212 is not electrically connected to the contact structure 600.

[0064] Alternatively, the first gate layer 211 and the second gate layer 212 may comprise the same conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide. The first dielectric layer 220 may serve as an isolation stack layer and may include, but is not limited to, an insulating dielectric material layer such as a silicon oxide layer.

[0065] refer to Figure 2A and Figure 2B The first region 01 of the stacked structure 200 may include a first dielectric layer 220 and a second dielectric layer 230 stacked along the z-direction. The first dielectric layer 220 and the second dielectric layer 230 are made of two different insulating dielectric materials. For example, the second dielectric layer 230 includes, but is not limited to, an insulating dielectric material layer such as a silicon nitride layer. Furthermore, the plurality of second dielectric layers 230 and the plurality of gate layers 210 may have the same stack height.

[0066] In addition, as the demand for storage capacity in semiconductor structures continues to increase, the number of storage stacks is gradually increasing. The stacked structure 200 may include multiple sub-stacked structures formed using, for example, a double stacking technique or a multi-stacked technique. The multiple sub-stacked structures may be stacked sequentially in a stacking direction to form the stacked structure 200, wherein each sub-stacked structure may include a first dielectric layer and a composite layer stacked along the z-direction. The number of layers in each sub-stacked structure may be the same or different. The content of a single stacked structure described below may be fully or partially applicable to a stacked structure formed by multiple sub-stacked structures, and therefore related or similar content will not be repeated.

[0067] refer to Figure 1-2D In one embodiment of the present application, the stacked structure 200 further includes a second region 02 adjacent to the first region 01 in the x-direction. The first region 01 may include a plurality of steps 21 and a plurality of contact structures 600, and the second region 02 may include a plurality of channel structures 300. The channel structures 300 will be described in detail below with reference to the accompanying drawings.

[0068] Optionally, the gate line isolation structure 400 may include a first gate line isolation structure 410, a second gate line isolation structure 420, and a third gate line isolation structure 430. The first gate line isolation structure 410 extends along the x-direction and passes through the first region 01 and the second region 02. The second gate line isolation structure 420 extends only along the x-direction in the second region 02. The third gate line isolation structure 430 extends only along the x-direction in the first region 01. Alternatively, the second gate line isolation structure 420 and the third gate line isolation structure 430 are located between two adjacent first gate line isolation structures 410 along the y-direction.

[0069] Alternatively, as Figure 1 As shown, the second gate line isolation structure 420 and the third gate line isolation structure 430 may be staggered along the y direction.

[0070] The gate layer 210 provided in some embodiments of the present application can be prepared using a gate-last process. Specifically, a stacked structure (not shown) can be formed by alternately stacking the first dielectric layer 220 and a gate sacrificial layer (not shown) along the z-direction. During the removal of the gate sacrificial layer using a process such as wet etching, the etchant and chemical precursor can be brought into contact with the gate sacrificial layer through the gate line gaps created when forming the gate line isolation structure, thereby removing a portion of the gate sacrificial layer.

[0071] Therefore, in at least one embodiment of the present application, the layout of the first gate line isolation structure 410, the second gate line isolation structure 420, and the third gate line isolation structure 430 in the xy plane can be selected according to different settings of the semiconductor structure architecture to reduce the size of the gate line isolation structure while optimizing the process window of the above-mentioned gate sacrificial layer removal step, thereby increasing the storage density of the semiconductor structure. For example, the second gate line isolation structure 420 and the third gate line isolation structure 430 can be arranged to be staggered along the y direction; the size of the second gate line isolation structure 420 extending in the x direction can be adjusted; the size of the third gate line isolation structure 430 extending in the x direction can be adjusted; the spacing between the second gate line isolation structure 420 and the third gate line isolation structure 430 can be adjusted; the spacing between multiple second gate line isolation structures 420 adjacent in the y direction can be adjusted; the spacing between multiple third gate line isolation structures 430 adjacent in the y direction can be adjusted; and the third gate line isolation structure 430 can be arranged to extend discontinuously in the x direction.

[0072] Furthermore, in at least one embodiment of the present application, the first gate line isolation structure 410 may include a first sub-portion 410-1, an isolation structure 410-2, and a second sub-portion 410-3 extending along the x-direction and spaced apart from each other, wherein the first sub-portion 410-1 is located in the first region 01, the isolation structure 410-2 is located in the second region 02 on a side close to the first region 01, and the second sub-portion 410-3 is located in the second region 02. The isolation structure can reduce the possibility of deformation and collapse of the stacked structure during the removal of a portion of the gate sacrificial layer, provide structural support for the stacked structure, and improve and release local stress in the semiconductor structure.

[0073] Optionally, the isolation structure 410 - 2 and the remaining portion of the first gate line isolation structure 410 (eg, the first sub-portion 410 - 1 or the second sub-portion 410 - 3 ) include different insulating dielectric materials.

[0074] Furthermore, the isolation structure 410-2 and the remaining portions of the first gate line isolation structure 410 can be formed in separate processes. For example, during the process of removing portions of the gate sacrificial layer by allowing the etchant and chemical precursor to contact the gate sacrificial layer through the gate line gap created during the formation of the gate line isolation structure, the portions of the gate sacrificial layer located in the first region 01 and the portions located in the second region 02 can be removed separately. During these separate removal processes, the isolation structure 410-2 can be pre-formed in the gate line gap, thereby blocking the flow of the etchant and chemical precursor through the isolation structure 410-2, thereby achieving separate removal of different portions of the gate sacrificial layer.

[0075] Optionally, the isolation structure 410-2 may include multiple isolation layers (not shown). The isolation layers may be alternately stacked with the first dielectric layer 220 along the z-direction and disposed in the same layer as the gate layer 210. Furthermore, the isolation structure 410-2 may further include isolation pillars (not shown) extending along the z-direction. Optionally, the isolation pillars and the isolation layers may comprise the same insulating dielectric material.

[0076] Optionally, the surface where the first gate layer 211 contacts the second dielectric layer 230 is a curved surface, the curved surface including at least one of a concave surface and a convex surface. As described above, by changing the layout of the first gate line isolation structure 410, the second gate line isolation structure 420, and the third gate line isolation structure 430 in the xy plane, the process window for the above-mentioned gate sacrificial layer removal step can be optimized while reducing the size of the gate line isolation structure and increasing the storage density of the semiconductor structure. In addition, the isolation structure 410-2 of the first gate line isolation structure 410 can block the flow of etchant and chemical precursors, thereby enabling the separate removal of different portions of the gate sacrificial layer. In these embodiments, the gate sacrificial layer in the stacked structure is selectively removed, and the first gate layer 211 and the second gate layer 212 are formed in the gap formed after the gate sacrificial layer is removed, wherein the remaining gate sacrificial layer forms the second dielectric layer 230. Therefore, as an option, the surface where the first gate layer 211 contacts the second dielectric layer 230 can be a curved surface. This can release the local stress of the semiconductor structure, increase the stability of the semiconductor structure, and effectively isolate the gate layer through the second dielectric layer arranged on the same layer, so that different gate layers can be connected to the external circuit through different contact structures located in the step area, thereby improving the reliability of the semiconductor structure while achieving connection with the external circuit.

[0077] Furthermore, the gate line isolation structure 400, the channel structure 300, the contact structure 600, and the like included in the semiconductor structure 1000 all have high aspect ratios. In other words, the dimensions of the gate line isolation structure 400, the channel structure 300, the contact structure 600, and the like in the z-direction are relatively large compared to their dimensions in directions intersecting the z-direction. Consequently, during the fabrication of these structures, processes such as etching require a relatively large etching depth, which increases the difficulty and cost of fabricating the semiconductor structure 1000.

[0078] Therefore, in at least one embodiment of the present application, a gate line gap (not shown) to accommodate the gate line isolation structure 400 can be formed in stages. For example, a channel hole (not shown), a contact hole (not shown), and a first hole (not shown) can be formed in the same process. The channel hole can accommodate the channel structure 300, and the contact hole can accommodate the contact structure 600. Multiple first holes are connected in the x-direction to form a gate line gap. By forming multiple holes for different structures of the semiconductor structure 1000 in the same process, such as the channel hole, the contact hole, and the first hole, the number of etching processes used to form high aspect ratio structures can be effectively reduced, thereby reducing the difficulty and cost of manufacturing the semiconductor structure 1000.

[0079] In addition, since the channel hole, contact hole and first hole are formed in the same process, they can also be prepared using the same photolithography mask, which can improve the overlay accuracy of the etching process, reduce the overlay error, and make the final semiconductor structure 1000 have relatively high overall performance.

[0080] Figure 3 4 is a schematic top view of a gate line isolation structure 400 according to one embodiment of the present application.

[0081] like Figure 1 and Figure 3 As shown, in this embodiment, the gate line isolation structure 400 includes a sidewall 401 in contact with the stacked structure 200, wherein the surface of the sidewall 401 is a curved surface, and the curved surface includes at least one of a concave surface and a convex surface. Optionally, the sidewall 401 has a wavy shape on both sides along the x-direction.

[0082] In other words, in this embodiment, the gate line gap that accommodates the gate line isolation structure 400 is formed by first forming a first hole and then removing at least the portion of the stacked structure located between adjacent first holes in the x-direction. As a result, the surface of the sidewall of the gate line gap that contacts the stacked structure 200 is a curved surface, and the surface of the sidewall 401 of the gate line isolation structure 400 formed in the gate line gap also includes a curved surface.

[0083] In addition, reference Figure 1 and Figure 2B The contact structure 600 includes a contact conductive layer 610 and a dielectric filling layer 620 wrapped by the contact conductive layer 610 , wherein the contact conductive layer 610 extends along the z direction and is connected to the first gate layer 211 .

[0084] As an option, the conductive material forming the contact conductive layer 610 may include any one or a combination of conductive metal materials and doped semiconductor materials, wherein the conductive metal material may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the doped semiconductor material may be, for example, doped crystalline silicon or silicide, etc., and this application does not limit this.

[0085] Furthermore, in one embodiment of the present application, the dielectric filling layer 620 may be a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. The contact structure includes a dielectric filling layer encased by a contact conductive layer, which can reduce the use of conductive material in the contact structure, thereby reducing the cost of semiconductor structure fabrication and reducing stress and deformation in the stacked structure.

[0086] In addition, refer again Figure 1 and Figure 2AIn one embodiment of the present application, the semiconductor structure further includes a dummy channel structure 500. Optionally, the dummy channel structure 500 may be located in the first region 01. The dummy channel structure 500 may provide support during the removal of the gate sacrificial layer from the stacked structure, thereby reducing the possibility of deformation and collapse of the stacked structure.

[0087] Figure 4 3 is a schematic cross-sectional view of a channel structure 300 and a dummy channel structure 500 according to one embodiment of the present application.

[0088] refer to Figure 1 、 Figure 2A 、 Figure 2C as well as Figure 4 , the channel structure 300 may be located in the second region 02. As an option, the dummy channel structure 500 may include the same layer structure as the channel structure 300.

[0089] For example, the channel structure 300 may include a functional layer 320 located on the inner wall of a channel hole (not shown) and a channel layer 330 located on the surface of the functional layer 320. The functional layer 320 may include a blocking layer, a charge trapping layer, and a tunneling layer sequentially disposed on the inner wall of the channel hole. The channel layer 330 may be located on the surface of the tunneling layer and may be used to transport the required charges (electrons or holes). The channel layer 330 may be made of a semiconductor material such as polycrystalline silicon or single crystal silicon and may contain conductive impurities. In addition, the channel structure 300 may further include a channel filling dielectric layer 340 that fills the remaining space of the channel hole after the functional layer 320 and the channel layer 330 are formed. The channel filling dielectric layer 340 includes an insulating dielectric material layer such as a silicon oxide layer. Similarly, a dummy channel structure 500 may be formed in the process of forming the channel structure 300 to simplify the manufacturing process of the semiconductor structure 1000. The dummy channel structure 500 may also include a first layer 520 located on the inner wall of the dummy channel hole (not shown) and a second layer 530 located on the surface of the first layer 520. The first layer 520 may be made of the same material as the functional layer 320, and the second layer 530 may be made of the same material as the channel layer 330. In addition, the dummy channel structure 500 may also include a third layer 540 that fills the remaining space of the dummy channel hole after the first layer 520 and the second layer 530 are formed. The third layer 540 may be made of the same material as the channel filling dielectric layer 340. Alternatively, the dummy channel structure 500 may include a different layer structure than the channel structure 300, which is not limited in this application.

[0090] Therefore, according to at least one embodiment of the present application, the semiconductor structure includes a stacked structure, a gate line isolation structure and a contact structure, wherein the stacked structure includes a plurality of steps, the contact structure passes through the corresponding steps along the stacking direction of the stacked structure (hereinafter referred to as the first direction) and is connected to the gate layer of the corresponding step, the gate line isolation structure extends along a second direction intersecting with the first direction, wherein the portion of the gate layer between the gate line isolation structure and the contact structure extends along a third direction intersecting with both the first direction and the second direction. In other words, in the semiconductor structure provided by the embodiment of the present application, the contact structure can pass through the corresponding steps along the stacking direction, thereby reducing the over-etching that occurs in the process of forming the contact hole to accommodate the contact structure, thereby reducing the possibility of short circuit between the gate layers due to the breakdown of the gate layer and the failure of the semiconductor structure. In addition, the portion of the gate layer connected to the contact structure is only located between the gate line isolation structure and the contact structure along the third direction, which can improve the reliability and storage density of the semiconductor structure while achieving a good connection between the gate layer and the contact structure.

[0091] Figure 5 2 is a flow chart of a method 2000 for preparing a semiconductor structure according to one embodiment of the present application. Figure 6-Figure 59 They are respectively process schematic diagrams of a method 2000 for preparing a semiconductor structure according to one embodiment of the present application.

[0092] like Figure 5 As shown, the method 2000 for preparing a semiconductor structure may include:

[0093] S1 , forming a stack structure, wherein a first region of the stack structure includes a plurality of steps, and the steps include a first dielectric layer and a gate sacrificial layer that are stacked.

[0094] S2, forming a contact hole and a gate line gap, wherein the contact hole passes through the step along a first direction, and the gate line gap passes through the stacked structure along the first direction and extends along a second direction intersecting the first direction.

[0095] S3, removing part of the gate sacrificial layer through the gate line gap and the contact hole to form a sacrificial gap, and forming a first gate layer in the sacrificial gap, wherein a portion of the first gate layer between the gate line gap and the contact hole extends along a third direction, wherein the third direction intersects with the first direction and the second direction.

[0096] The following will be combined Figure 6-Figure 59 The specific process of each step of the above-mentioned preparation method 2000 in one embodiment of the present application is described in detail.

[0097] Step S1

[0098] Figure 6It is a schematic cross-sectional view of a structure formed after forming an initial step 21 ′ according to a preparation method of one embodiment of the present application. Figure 7 It is a schematic cross-sectional view of a structure formed after forming the second sacrificial layer 260 according to a preparation method of one embodiment of the present application. Figure 8 It is a schematic cross-sectional view of a structure formed after forming the first step covering layer 101 according to a preparation method of one embodiment of the present application. Figure 9 It is a schematic cross-sectional view of a structure formed after forming the second step covering layer 102 according to a preparation method of one embodiment of the present application. Figure 10 2 is a schematic cross-sectional view of a structure formed after exposing the topmost first dielectric layer 220 - 1 according to a preparation method according to one embodiment of the present application. Figure 11 It is a schematic cross-sectional view of a structure formed after forming the third step covering layer 103 according to a preparation method of one embodiment of the present application.

[0099] like Figures 6-11 As shown, step S1 forms a stacked structure, wherein the first region of the stacked structure includes a plurality of steps, and the steps include a first dielectric layer and a gate sacrificial layer stacked, which may, for example, include: providing an initial substrate 100; forming a stacked structure 200' on the initial substrate 100; forming a plurality of initial steps 21' in the stacked structure 200'; forming a second sacrificial layer 260; and covering the plurality of initial steps 21' and the second sacrificial layer 260.

[0100] Specifically, if Figure 6 As shown, in one embodiment of the present application, the initial substrate 100 can be made of any suitable semiconductor material, such as single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or a III-V compound such as gallium arsenide. Furthermore, the initial substrate 100 can be made of single crystal silicon.

[0101] In one embodiment of the present application, the initial substrate 100 may be, for example, a composite substrate for supporting a device structure thereon. The initial substrate 100 may be formed by sequentially depositing multiple layers made of different materials using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0102] The initial substrate 100 may include a substrate sacrificial layer for subsequently forming a semiconductor connection layer for connecting the channel structure. The substrate sacrificial layer may include a single layer, a multilayer or a suitable composite layer. For example, the substrate sacrificial layer may include any one or more of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer. As an option, the substrate sacrificial layer may be a high dielectric constant dielectric layer. As another option, the substrate sacrificial layer may include a dielectric layer, a sacrificial layer and a dielectric layer arranged in sequence, wherein the dielectric layer may be a silicon nitride layer and the sacrificial layer may be a silicon oxide layer. As another option, the substrate sacrificial layer may include any one or more of a dielectric material, a semiconductor material and a conductive material. For example, the sacrificial layer may be single crystal silicon or polycrystalline silicon. Specifically, in one embodiment of the present application, the exemplary material for forming the sacrificial layer may be polycrystalline silicon.

[0103] Part of the initial substrate 100 may also form a well region doped with an N-type or P-type dopant via ion implantation or diffusion. The dopant may include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb). In some embodiments of the present application, the well region may be prepared using the same dopant or different dopants. Furthermore, the doping concentration of the well region may be the same or different, which is not limited in the present application.

[0104] After forming the initial substrate 100, a stacked structure 200' can be formed on the initial substrate 100 by one or more thin film deposition processes. The thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, and this application is not limited to this.

[0105] The stack structure 200' may include multiple pairs of first dielectric layers 220 and gate sacrificial layers 250 stacked alternately. For example, the stack structure 200' may include multiple dielectric layer pairs, such as 64, 128, or more pairs of first dielectric layers 220 and gate sacrificial layers 250.

[0106] In some embodiments, the first dielectric layer 220 and the gate sacrificial layer 250 may include a first dielectric material and a second dielectric material different from the first dielectric material, respectively. Exemplary materials for forming the first dielectric layer 220 and the gate sacrificial layer 250 may include silicon oxide and silicon nitride, respectively. The silicon oxide layer may serve as an isolation stack, while the silicon nitride layer may serve as a sacrificial stack. Subsequently, portions of the sacrificial stack may be etched away and replaced with a conductor layer comprising a conductive material to form the gate layer of the semiconductor structure.

[0107] The preparation method of a single stacking structure is described above. In fact, as the storage capacity demand of semiconductor structures continues to increase, the storage stack gradually increases. In order to break through the limitations of traditional process limits, a double stacking technology or a multi-stacking technology can also be used to form a stacking structure by stacking multiple sub-stack structures in sequence in the thickness direction of the stacking structure, wherein each sub-stack structure may include a plurality of first dielectric layers and gate sacrificial layers alternately stacked. The number of layers of each sub-stack structure may be the same or different. Since the content and structure involved in the preparation process of the single stacking structure described above can be fully or partially applied to the stacking structure formed by multiple sub-stack structures described here, the related or similar content will not be repeated. However, it can be understood by those skilled in the art that the subsequent preparation process can be carried out on the basis of a multi-stack structure or a single stacking structure.

[0108] refer to Figure 6 After the stack structure 200 ′ is formed, an initial step 21 ′ may be formed.

[0109] Optionally, by performing multiple trim-etch cycles on the edge portions of the stacked structure 200', the stacked structure 200' can have one or more inclined edges and a top dielectric layer pair (farther from the initial substrate 100) that is shorter than a bottom dielectric layer pair (closer to the initial substrate 100). Any suitable etching process can be used in the step structure formation process, such as any one or a combination of dry and wet etching processes. Furthermore, multiple chopping processes, for example, can be used to form the initial step 21'. Optionally, the initial step 21' can be formed in the first region 01 of the stacked structure 200'.

[0110] like Figure 6 and Figure 7 As shown, after forming the initial step 21', a second sacrificial layer 260 may be formed on the gate sacrificial layer 250 included in the initial step 21'. Optionally, the second sacrificial layer 260 may include a polysilicon material layer, which may be doped or undoped. Alternatively, the surface of the second sacrificial layer 260 may be subjected to a modification process, including an ion implantation process or a plasma implantation process.

[0111] like Figure 7 and Figure 8As shown, after the second sacrificial layer 260 is formed, the initial step 21' is formed into a step 21" of the stacked structure 200'. A first step covering layer 101 covering the step 21" may be formed by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. For example, the first step covering layer 101 may include but is not limited to an insulating dielectric material layer such as a silicon oxide layer.

[0112] like Figure 8 and Figure 9 As shown, after the first step covering layer 101 is formed, one or more thin film deposition processes may be continued to form a second step covering layer 102 covering the first step covering layer 101. The thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0113] Optionally, the second step covering layer 102 may be planarized to make the first surface 102-1 of the second step covering layer 102 away from the initial substrate 100 flush with the surface of the second sacrificial layer 260-1 farthest from the initial substrate 100 among the multiple second sacrificial layers 260, and the planarization process includes a chemical mechanical polishing process.

[0114] like Figure 9 and Figure 10 As shown, after forming the second step-covering layer 102, the second sacrificial layer 260-1 farthest from the initial substrate 100 and the gate sacrificial layer 250-1 farthest from the initial substrate 100 can be removed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can also be performed. Optionally, the second sacrificial layer 260-1 farthest from the initial substrate 100 has a relatively larger size along the z-direction than the remaining second sacrificial layers in the plurality of second sacrificial layers 260. Optionally, the gate sacrificial layer 250-1 farthest from the initial substrate 100 has a relatively larger size along the z-direction than the remaining gate sacrificial layers in the plurality of gate sacrificial layers 250.

[0115] like Figure 10 and Figure 11 As shown, a portion of the second step covering layer 102 can be removed to form a third step covering layer 103 by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, can also be performed.

[0116] Combine Figures 9-11After removing the second sacrificial layer 260-1 farthest from the initial substrate 100 and the gate sacrificial layer 250-1 farthest from the initial substrate 100, the first dielectric layer 220-1 farthest from the initial substrate 100 (hereinafter referred to as the uppermost first dielectric layer 220-1) among the plurality of first dielectric layers 220 can be exposed. Optionally, a planarization process can be performed on the third step cover layer 103 so that the surface of the third step cover layer 103 away from the initial substrate 100 is flush with the surface of the first dielectric layer 220-1. The planarization process includes a chemical mechanical polishing process.

[0117] Step S2

[0118] Figure 12 It is a schematic top view of a structure formed after forming a contact hole 601 according to a preparation method of one embodiment of the present application. Figure 13 It is a partial cross-sectional schematic diagram of a structure formed after forming a contact hole 601 according to a preparation method of one embodiment of the present application. Figure 14 It is a schematic top view of a structure formed after filling the contact hole 601 according to a preparation method of one embodiment of the present application. Figure 15 It is a partial cross-sectional schematic diagram of a structure formed after filling the contact hole 601 according to a preparation method of one embodiment of the present application. Figure 16 It is a schematic top view of a structure formed after forming a gate line gap 402 ′ according to a preparation method of one embodiment of the present application. Figure 16 It is a schematic top view of a structure formed after forming a gate line gap 402 ′ according to a preparation method of one embodiment of the present application. Figure 17 It is a schematic cross-sectional view of a structure formed after a portion of the first covering layer 106 is removed according to a preparation method in one embodiment of the present application. Figure 18 It is a schematic cross-sectional view of a structure formed after a portion of the first sacrificial layer 105 is removed according to a preparation method in one embodiment of the present application. Figure 19 It is a schematic cross-sectional view of a structure formed after forming the first expanded hole 402 - 1 according to a preparation method of one embodiment of the present application. Figure 20 It is a cross-sectional schematic diagram of a structure formed after forming the second expanded hole 402-2 according to a preparation method of one embodiment of the present application. Figure 21 It is a schematic cross-sectional view of a structure formed after forming a gate line gap 402 ′ according to a preparation method of one embodiment of the present application. Figure 22 4 is a schematic cross-sectional view of a structure formed after filling the gate line gap 402 ′ according to a preparation method of one embodiment of the present application. Figure 23 It is a schematic top view of a structure formed after forming the first protective layer 111 according to a preparation method of one embodiment of the present application. Figure 24 It will Figure 23 The semiconductor structure shown is a schematic cross-sectional view taken along line AA′. Figure 25 It will Figure 23 The semiconductor structure shown is a schematic cross-sectional view taken along line BB′. Figure 26 It will Figure 23 The semiconductor structure shown is a schematic cross-sectional view taken along line CC'.

[0119] like Figure 11-Figure 26 As shown, step S2 forms a contact hole and a gate line gap, wherein the contact hole passes through the step along the z direction, and the gate line gap passes through the stack structure along the first direction and extends along the x direction. This may, for example, include: forming a contact hole 601, wherein the contact hole 601 passes through the step 21" of the stack structure 200 along the z direction; forming first holes 402 passing through the stack structure 200' along the z direction, wherein a plurality of first holes 402 are arranged at intervals along the x direction; and removing at least a portion of the stack structure 200' located between adjacent first holes 402 in the x direction to form a gate line gap 402'.

[0120] Optionally, the first hole 402 and the contact hole 601 can be formed in the same process. The gate line gap and the contact hole both have a high aspect ratio. In other words, the dimensions of the gate line gap and the contact hole in the z direction are relatively large compared to their dimensions in a direction intersecting the z direction. Therefore, in the process of forming the gate line gap and the contact hole, a relatively large etching depth is required when using processes such as etching, which increases the difficulty and cost of manufacturing the semiconductor structure.

[0121] Therefore, in at least one embodiment of the present application, the gate line gap 402' can be formed in steps, for example, the first hole 402 and the contact hole 601 can be formed in the same process. By forming the contact hole and the first hole for the gate line gap in the same process, the number of etching processes used to form a high aspect ratio structure can be effectively reduced, thereby reducing the difficulty and cost of manufacturing the semiconductor structure.

[0122] In addition, since the contact hole and the first hole are formed in the same process, they can also be prepared using the same photolithography mask, which can improve the overlay accuracy of the etching process, reduce the overlay error, and make the final semiconductor structure have relatively high overall performance.

[0123] In addition, to enhance the above-mentioned effects, the channel hole 301, the first hole 402 and the contact hole 601 may be formed in the same process; or, the virtual channel hole 302, the first hole 402 and the contact hole 601 may be formed in the same process; or, the channel hole 301, the virtual channel hole 302, the first hole 402 and the contact hole 601 may be formed in the same process.

[0124] Alternatively, as Figure 12-13 As shown, multiple channel holes 301, multiple virtual channel holes 302, multiple first holes 402 and multiple contact holes 601 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning and chemical mechanical polishing, can also be performed.

[0125] As an option, the channel hole 301 may be located in the second region 02 of the stacked structure 200'. The channel hole 301 may pass through the stacked structure 200' along the z-direction and extend into the initial substrate 100. Optionally, the plurality of channel holes 301 may have the same depth in the z-direction to reduce the difficulty and cost of fabricating the semiconductor structure.

[0126] Alternatively, the dummy channel hole 302 may be located in the first region 01 of the stacked structure 200'. The dummy channel hole 302 may pass through the stacked structure 200' along the z-direction and extend into the initial substrate 100. Optionally, the plurality of dummy channel holes 302 may have the same depth in the z-direction to reduce the difficulty and cost of fabricating the semiconductor structure.

[0127] Optionally, the aperture size of the dummy channel hole 302 may be larger than the aperture size of the channel hole 301 .

[0128] Alternatively, the contact hole 601 may be located in the first region 01 of the stacked structure 200'. The contact hole 601 may pass through the step 21" of the stacked structure 200' along the z-direction and extend into the initial substrate 100. Optionally, the multiple contact holes 601 may have the same depth in the z-direction to reduce the difficulty and cost of fabricating the semiconductor structure.

[0129] As an option, Figure 12 As shown, multiple first holes 402 may be spaced apart along the x-direction to form a first hole group (shown in a dotted box). Alternatively, the first hole group may be located only in the first region 01. Alternatively, the first hole group may be located only in the second region 02. Alternatively, the first hole group may extend from the first region 01 into the second region 02 along the x-direction. The multiple first holes 402 may have the same depth in the z-direction. For example, the multiple first holes 402 may pass through the stacked structure 200' along the z-direction and extend into the initial substrate 100.

[0130] Furthermore, to reduce the difficulty and cost of manufacturing the semiconductor structure, the multiple channel holes 301 , the multiple dummy channel holes 302 , the multiple first holes 402 and the multiple contact holes 601 may have the same depth in the z direction.

[0131] Optionally, the aperture size of the first hole 402 may be equal to or larger than the aperture size of the dummy channel hole 302 .

[0132] like Figure 12-15 As shown, in order to facilitate processing of the plurality of first holes 402 in subsequent steps, a gate line gap 402' (eg Figure 16 As shown), the first sacrificial layer 105 can be filled in the various holes that have been formed. Optionally, a first sacrificial layer 105 is formed in the plurality of channel holes 301, the plurality of virtual channel holes 302, the plurality of first holes 402 and the plurality of contact holes 601 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The first sacrificial layer 105 may include a carbon-containing material layer. The first sacrificial layer 105 may be formed of a material with a high deposition rate to facilitate rapid filling of the various holes mentioned above, and the first sacrificial layer 105 should be relatively thin relative to the first dielectric layer 220 (such as Figure 6 As shown) and the gate sacrificial layer 250 (as Figure 6 Any material with high dry etching selectivity (as shown) to facilitate removal in subsequent steps.

[0133] Furthermore, a first capping layer 106 may be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The first capping layer 106 may cover a surface of the stacked structure 200′ away from the initial substrate 100. For example, the first capping layer 106 may include a polysilicon material layer.

[0134] like Figures 14-22 In some embodiments of the present application, the gate line gap 402' can be formed by processing the first holes 402. For example, at least the portion of the stacked structure 200' between the adjacent first holes 402 in the x-direction is removed to form the gate line gap 402'.

[0135] Specifically, if Figure 17 As shown, a portion of the first covering layer 106 can be removed to expose the portion of the first sacrificial layer 105 located in the first hole 402 by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, can also be performed.

[0136] like Figure 17-18 As shown, after exposing the portion of the first sacrificial layer 105 located in the first hole 402, the portion of the first sacrificial layer 105 located in the first hole 402 can be removed to expose the first hole 402, for example, by a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed.

[0137] like Figure 12 、 Figure 16 as well as Figure 17As shown, after the first holes 402 are exposed, a dry etching process or a combination of dry and wet etching processes can be used, for example; other manufacturing processes can also be performed to remove the portion of the stacked structure 200' located between the adjacent first holes 402 in the x-direction, so that the multiple first holes 402 in the first hole group that are spaced apart along the x-direction are connected.

[0138] Optionally, continue to use the above process to remove part of the stacked structure 200' along the radial direction of the first hole 402 to expand the aperture of the first hole 402. Figure 18-19 , the diameter of the portion of the first hole 402 in the stacked structure 200 ′ in the y direction can be expanded from d1 to d2, forming a first expanded hole 402 - 1 .

[0139] Alternatively, the first hole 402 may be expanded or extended in multiple directions step by step to form a gate line gap 402'. Figure 18-19 As shown, part of the stacked structure 200' can be removed along the radial direction of the first hole 402, so that the aperture of the part of the first hole 402 in the stacked structure 200' in the y direction is expanded from d1 to d2; then, as shown Figure 19-20 As shown, a portion of the initial substrate 100 may be further removed along the radial direction of the first hole 402 to form a second expanded hole 402-2, wherein the aperture of the second expanded hole 402-2 in the initial substrate 100 is also expanded from d1 to d2 in the y direction; thereafter, as shown in FIG. Figure 20-21 As shown, a portion of the first cover layer 106 may be removed to form a gate line gap 402'; then as shown in FIG. Figure 21-22 As shown, after the gate line gap 402 ′ is formed, the first sacrificial layer 105 may be used to fill the gate line gap 402 ′ to facilitate subsequent processing.

[0140] refer to Figure 12 、 Figure 16 as well as Figure 17 The gate line gap 402' may include a first gate line gap 403, a second gate line gap 404, and a third gate line gap 405. Optionally, the first gate line gap 403 extends along the x-direction and includes a first sub-region 403-1, a second sub-region 403-2, and a third sub-region 403-3, wherein the first sub-region 403-1, the second sub-region 403-2, and the third sub-region 403-3 all extend along the x-direction, and the first sub-region 403-1, the second sub-region 403-2, and the third sub-region 403-3 are spaced apart from each other in the x-direction. The second gate line gap 404 extends along the x-direction only in the first region 01. Optionally, the second gate line gap 404 includes a plurality of segments, each of which may extend along the x-direction, and the plurality of segments are spaced apart from each other in the x-direction. The third gate line gap 405 extends along the x-direction only in the second region 02.

[0141] In the subsequent process of removing the gate sacrificial layer by a process such as wet etching, the etchant and chemical precursor can be brought into contact with the gate sacrificial layer through the gate line gap, thereby removing a portion of the gate sacrificial layer.

[0142] Therefore, in at least one embodiment of the present application, the layout of the first gate line gap 403, the second gate line gap 404, and the third gate line gap 405 in the xy plane can be selected according to different settings of the semiconductor structure architecture that is ultimately formed, so as to optimize the process window of the above-mentioned gate sacrificial layer removal step while reducing the size of the gate line isolation structure formed based on the first gate line gap 403, the second gate line gap 404, and the third gate line gap 405, thereby increasing the storage density of the ultimately formed semiconductor structure. As some options, the second gate line gap 404 and the third gate line gap 405 can be arranged to be staggered along the y direction; the size of the second gate line gap 404 extending in the x direction can be adjusted; the size of the third gate line gap 405 extending in the x direction can be adjusted; the spacing between the second gate line gap 404 and the third gate line gap 405 can be adjusted; the spacing between multiple second gate line gaps 404 adjacent in the y direction can be adjusted; the spacing between multiple third gate line gaps 405 adjacent in the y direction can be adjusted; and the third gate line gap 405 can be arranged to extend discontinuously in the x direction, for example, the third gate line gap 405 includes multiple segments spaced apart in the x direction.

[0143] like Figure 16 、 Figure 17 、 Figure 22-26 As shown, after forming the gate line gap 402', the first sacrificial layer 105 and the first capping layer 106 can be removed, for example, by a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed to expose the channel hole 301, the dummy channel hole 302, the gate line gap 402', and the contact hole 601. Subsequently, a first protective layer 111 can be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, or a wet oxidation process. For example, the first protective layer 111 can include an insulating dielectric material layer such as silicon oxide. The first protective layer 111 can be located within the channel hole 301, the dummy channel hole 302, the gate line gap 402', and the contact hole 601. For example, the first protective layer 111 can be located at least at the bottom of the channel hole 301, the dummy channel hole 302, the gate line gap 402', and the contact hole 601 in the initial substrate 100. The first protection layer 111 can effectively isolate the various holes and gaps mentioned above from the initial substrate during the subsequent preparation process of the semiconductor structure.

[0144] Furthermore, when the second sacrificial layer 260 comprises a polysilicon material layer, a second protective layer 112 may be formed by, for example, a wet oxidation process. For example, the second protective layer 112 may comprise an insulating dielectric material layer such as silicon oxide. The second protective layer 112 may be located on the surface of the second sacrificial layer 260 exposed to the gate line gap 402' and the contact hole 601.

[0145] Step S3

[0146] Figure 27 It is a schematic top view of a structure formed after the first covering layer 106 is formed again according to a preparation method of one embodiment of the present application. Figure 28 It will Figure 27 The semiconductor structure shown is a schematic cross-sectional view taken along line AA′. Figure 29 It will Figure 27 The semiconductor structure shown is a schematic cross-sectional view taken along line BB′. Figure 30 It will Figure 27 The semiconductor structure shown is a schematic cross-sectional view taken along line CC'. Figure 31 It is a schematic top view of a structure formed after forming the fourth sub-region 403 - 4 according to a preparation method of one embodiment of the present application. Figure 32 It will Figure 31 The semiconductor structure shown is a schematic cross-sectional view taken along line AA′. Figure 33 It will Figure 31 The semiconductor structure shown is a schematic cross-sectional view taken along line BB′. Figure 34 It will Figure 31 The semiconductor structure shown is a schematic cross-sectional view taken along line EE'. Figure 35 It is a schematic top view of a structure formed after forming an isolation structure 410 - 2 according to a preparation method of one embodiment of the present application. Figure 36 It will Figure 35 The semiconductor structure shown is a schematic cross-sectional view taken along line AA′. Figure 37 It will Figure 35 The semiconductor structure shown is a schematic cross-sectional view taken along line BB′. Figure 38 It will Figure 35 The semiconductor structure shown is a schematic cross-sectional view taken along line EE'. Figure 39 It is a schematic cross-sectional view of a structure formed after forming a channel structure 300 according to a preparation method of one embodiment of the present application. Figure 40 It is a schematic top view of a structure formed after forming the first gap 201 according to a preparation method of one embodiment of the present application. Figure 41 It will Figure 40 The semiconductor structure shown is a schematic cross-sectional view taken along line AA′. Figure 42 It will Figure 40 The semiconductor structure shown is a schematic cross-sectional view taken along line BB′. Figure 43 It will Figure 40 The semiconductor structure shown is a schematic cross-sectional view taken along line CC'. Figure 44 1 is a schematic top view of a structure formed after exposing a portion of the gate line gap 402 ′ located in the second region 02 according to a preparation method in accordance with one embodiment of the present application. Figure 45 It will Figure 44 The semiconductor structure shown is a schematic cross-sectional view taken along line AA′. Figure 46 It will Figure 44 The semiconductor structure shown is a schematic cross-sectional view taken along line BB′. Figure 47 It will Figure 44 The semiconductor structure shown is a schematic cross-sectional view taken along line CC'. Figure 48 It is a schematic top view of a structure formed after filling the first gap 201 according to a preparation method of one embodiment of the present application. Figure 49 It will Figure 48 The semiconductor structure shown is a schematic cross-sectional view taken along line AA′. Figure 50 It will Figure 48 The semiconductor structure shown is a schematic cross-sectional view taken along line BB′. Figure 51 It will Figure 48 The semiconductor structure shown is a schematic cross-sectional view taken along line CC'. Figure 52 It is a schematic top view of a structure formed after forming the second gap 202 according to a preparation method of one embodiment of the present application. Figure 53 It will Figure 52 The semiconductor structure shown is a schematic cross-sectional view taken along line AA′. Figure 54 It will Figure 52 The semiconductor structure shown is a schematic cross-sectional view taken along line BB′. Figure 55 It will Figure 52 The semiconductor structure shown is a schematic cross-sectional view taken along line CC'. Figure 56 It is a schematic top view of a structure formed after forming a gate layer 210 according to a preparation method of one embodiment of the present application. Figure 57 It will Figure 56 The semiconductor structure shown is a schematic cross-sectional view taken along line AA′. Figure 58 It will Figure 56 The semiconductor structure shown is a schematic cross-sectional view taken along line BB′. Figure 59 It will Figure 56 The semiconductor structure shown is a schematic cross-sectional view taken along line CC'.

[0147] Combine Figure 1-2D 、 Figure 6 as well as Figure 23-Figure 59 Step S3 removes part of the gate sacrificial layer through the gate line gap and the contact hole to form a sacrificial gap, and forms a first gate layer in the sacrificial gap, wherein the portion of the first gate layer between the gate line gap and the contact hole extends along a third direction, wherein the third direction intersects with the first direction and the second direction. For example, the steps may include: removing part of the gate sacrificial layer 250 through the portion of the gate line gap 402' located in the first area 01 and the contact hole 601 to form a first gap 201; and removing the portion of the gate sacrificial layer 250 located in the second area 02 through the portion of the gate line gap 402' located in the second area 02 to form a second gap 202 connected to the first gap 201.

[0148] Optionally, forming the first gap 201 may include removing the portion of the gate sacrificial layer 250 located at the gate line gap edge 402' through the portion of the gate line gap 402' located in the first area 01, and continuing to remove part of the gate sacrificial layer 250 through the portion of the gate line gap 402' located in the first area 01 and the contact hole 601 to form the first gap 201.

[0149] Specifically, in some embodiments of the present application, before removing a portion of the gate sacrificial layer 250 through the gate line gap 402 ′ and the contact hole 601 , an isolation structure 410 - 2 may be formed in a portion of the gate line gap 402 ′ located in the second region 02 and close to the first region 01 .

[0150] like Figure 23-Figure 30 As shown, after forming the first protective layer 111, the first sacrificial layer 105 may be used again to fill the channel hole 301, the dummy channel hole 302, the gate line gap 402' and the contact hole 601 through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. After forming the first sacrificial layer 105, the first covering layer 106 may be used again to cover the surface of the stacked structure 200' away from the initial substrate 100. Optionally, other materials different from the first sacrificial layer 105 may be used to fill the channel hole 301, the dummy channel hole 302, the gate line gap 402' and the contact hole 601. Optionally, other materials different from the first covering layer 106 may be used to cover the surface of the stacked structure 200' away from the initial substrate 100. This application is not limited to this.

[0151] like Figures 27-39 As shown, after filling the channel hole 301, the dummy channel hole 302, the gate line gap 402' and the contact hole 601, forming the isolation structure 410-2 may include: removing a portion of the gate sacrificial layer 250 through the second sub-region 403-2 of the first gate line gap 403 to form a fourth sub-region 403-4; and filling the fourth sub-region 403-4 to form the isolation structure 410-2.

[0152] Alternatively, as Figures 27-34 As shown, the portion of the first covering layer 106 located above the second sub-region 403-2 and the portion of the first sacrificial layer 105 located in the second sub-region 403-2 can be removed to expose the second sub-region 403-2, for example, by a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, can also be performed. Afterwards, the portion of the gate sacrificial layer 250 adjacent to the second sub-region 403-2 can be removed, thereby expanding the size of the second sub-region 403-2 in a direction intersecting with the z-direction to form a fourth sub-region 403-4.

[0153] like Figures 31-39 As shown, during the formation of the fourth sub-region 403-4, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to fill the fourth sub-region 403-4 to form an isolation structure 410-2. For example, the filling material may include an insulating dielectric material such as silicon oxide. The isolation structure 410-2 is located in the second region 02 and adjacent to the first region 01.

[0154] The isolation structure 410-2 may include a plurality of isolation layers 411. The isolation layers 411 may be alternately stacked with the first dielectric layer 220 along the z-direction and provided on the same layer as the gate sacrificial layer 250 or a subsequently formed gate layer. In addition, the isolation structure 410-2 may further include an isolation column 412 extending along the z-direction. Optionally, the isolation column 412 and the isolation layer 411 may include the same insulating dielectric material. It should be noted that, when the isolation layer 411 and the first dielectric layer 220 are made of the same material, since the isolation layer 411 and the first dielectric layer 220 are formed in different process steps and are limited by the practical limitations of the filling process, the isolation layer 411 cannot completely fill the fourth sub-region 403-4. Therefore, in this case, the isolation layer 411 and the first dielectric layer 220 can still be distinguished.

[0155] After the isolation structure 410 - 2 is formed, a portion of the gate sacrificial layer 250 may be removed using the gate line gap 402 ′ and the contact hole 601 .

[0156] Optionally, in some embodiments of the present application, the method 2000 for preparing a semiconductor structure further includes forming a channel structure 300 in the channel hole 301 , and forming a dummy channel structure 500 in the dummy channel hole 501 .

[0157] Specifically, the portion of the first covering layer 106 located above the channel hole 301 and the virtual channel hole 501 can be removed, and the portion of the first sacrificial layer 105 located in the channel hole 301 and the virtual channel hole 501 can be removed, for example, by a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning and chemical mechanical polishing, can also be performed to expose the channel hole 301 and the virtual channel hole 501.

[0158] The channel structure 300 may include a channel hole 301 filled with a semiconductor layer and a composite dielectric layer. A functional layer 320 and a channel layer 330 may be formed on the inner wall of the channel hole 301 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0159] The functional layer 320 may include a blocking layer formed on the inner wall of the channel hole 301 to block the outflow of charges; a charge trapping layer formed on the surface of the blocking layer to store charges during operation of the semiconductor structure; and a tunneling layer formed on the surface of the charge trapping layer.

[0160] In some embodiments, the functional layer 320 may include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer 320 may have a structure other than the ONO configuration. The channel layer 330 may be formed on the surface of the tunneling layer and may be used to transport the desired charges (electrons or holes).

[0161] However, those skilled in the art should understand that, without departing from the teachings of this application, they may choose to form a functional layer on the sidewalls and bottom surface of the channel hole, or form a functional layer on the sidewalls of the channel hole according to different semiconductor structure architectures, and this application does not limit this.

[0162] In some embodiments, the channel layer 330 may be made of a semiconductor material such as polycrystalline silicon or single crystal silicon and may contain conductive impurities. For example, the channel layer may be an N-type doped or P-type doped polycrystalline silicon layer. Similar to the channel hole 301, the channel layer 330 may also have a cylindrical or pillar-like shape extending along the stacking direction within the stacked structure 200 ′. Alternatively, the channel layer 330 may also extend into the initial substrate 100.

[0163] In addition, the channel structure 300 also includes a channel plug (not shown) formed at one end of the channel hole 301 away from the initial substrate 100 (which can be understood as the top of the channel structure 300). Specifically, after forming the functional layer 320 and the channel layer 330, the channel hole 301 can be filled with a channel filling dielectric layer 340. The channel filling dielectric layer 340 may include an oxidizing dielectric layer, such as silicon oxide. Furthermore, during the filling process, a plurality of insulating gaps can be formed in the channel filling dielectric layer 340 by controlling the channel filling process to reduce structural stress. Then, a channel plug is formed in the portion of the channel filling dielectric layer 340 located at the top of the channel hole 301. The material of the channel plug can be made of the same material as the channel layer 330, such as N-type doped or P-type doped polysilicon. The channel plug is connected to the channel layer 330.

[0164] After forming the channel structure 300 , the dummy channel structure 500 may be formed using the same method as described above, and thus details related to or similar to the dummy channel structure 500 will not be described in detail.

[0165] Furthermore, as an option, since the dummy channel structure 500 does not have a storage function, the dummy channel hole 501 may be filled with only an insulating dielectric material layer, such as a silicon oxide layer, by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Similarly, by controlling the channel filling process, multiple insulating gaps may be formed in the insulating dielectric material layer to reduce the structural stress of the dummy channel structure 500.

[0166] like Figures 35-43 As shown, a portion of the first covering layer 106, which is located above the portion of the gate line gap 402' located in the first region 01 and the contact hole 601, can be removed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, can also be performed. The portion of the first covering layer 106 is removed, and the portion of the first sacrificial layer 105 is removed, which is located above the portion of the gate line gap 402' located in the first region 01 and the contact hole 601, so as to expose the portion of the gate line gap 402' located in the first region 01 and the contact hole 601.

[0167] Afterwards, the portion of the gate sacrificial layer 250 located at the edge of the gate line gap 402' can be removed through the portion of the gate line gap 402' located in the first region 01, such as the first sub-region 403-1 and the second gate line gap 404. Furthermore, portions of the gate sacrificial layer 250 can be further removed through the portion of the gate line gap 402' located in the first region 01 and the contact hole 601 to form the first gap 201.

[0168] Optionally, the portion of the gate line gap 402 ′ located in the first region 01 and the contact hole 601 may be used as a passage for providing an etchant, and a process such as wet etching may be used to remove a portion of the gate sacrificial layer 250 .

[0169] refer to Figure 37 and Figure 42 In some embodiments of the present application, the step 21″ includes a second sacrificial layer 260 located on the gate sacrificial layer 250. After removing a portion of the first sacrificial layer 105, which is located in the portion of the gate line gap 402′ located in the first area 01 and the contact hole 601, and exposing the portion of the gate line gap 402′ located in the first area 01 and the contact hole 601, continuing to remove a portion of the gate sacrificial layer 250 through the portion of the gate line gap 402′ located in the first area 01 and the contact hole 601 may also include: removing the second sacrificial layer 250, thereby exposing the first surface 251 of the gate sacrificial layer 250 in the step 21″, and continuing to remove a portion of the gate sacrificial layer 250 through the exposed portion of the gate line gap 402′ located in the first area 01 and the contact hole 601.

[0170] In other words, the gate sacrificial layer 250 may include a first surface 251 and a second surface 252 that are opposite to each other in the z-direction, and a third surface 253 connecting the first surface 251 and the second surface 252. After removing a portion of the first sacrificial layer 105, the third surfaces 253 of the plurality of gate sacrificial layers 250 may be exposed through the portion of the gate line gap 402' located in the first region 01 or the contact hole 601. After removing the second sacrificial layer 250, the first surface 251 of the gate sacrificial layer 250 located at the step 21" that was originally located below the second sacrificial layer 250 is exposed, while the first surface 251 of the gate sacrificial layer 250 located below the step 21" is not exposed. Therefore, the gate sacrificial layer 250 at the step 21" can be removed from its exposed first surface 251 and third surface 253; the gate sacrificial layer 250 located below the step 21" can be removed only from its exposed third surface 253. This can make the size of the first portion 2010 of the first gap 201 located in the step 21" larger than the size of the second portion 2020 of the first gap 201 located between two adjacent first dielectric layers 220 below the step 21". For example, the size of the first portion 2010 in the z-direction is larger than the size of the second portion 2020 in the z-direction. In addition, the size of the first portion 2010 in the direction intersecting the z-direction is larger than the size of the second portion 2020 in the direction intersecting the z-direction, where the direction intersecting the z-direction may include the x-direction and the y-direction.

[0171] like Figures 40-47As shown, after the first gap 201 is formed, a portion of the first covering layer 106 can be removed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, can also be performed. The portion of the first covering layer 106 is above the portion of the gate line gap 402' located in the first area 02, and the portion of the first sacrificial layer 105 is removed. The portion of the first sacrificial layer 105 is located in the portion of the gate line gap 402' located in the second area 02, so as to expose the portion of the gate line gap 402' located in the second area 02, such as 5, the third gate line gap 405.

[0172] like Figures 44-51 As shown, the first gap 201 can be filled with a third sacrificial layer 109 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, so as to reduce the impact of the subsequent process of removing the gate sacrificial layer 250 on the first region 01. For example, the third sacrificial layer 109 can include a polysilicon material layer.

[0173] like Figures 48-55 As shown, optionally, the portion of the gate line gap 402' located in the second region 02 can serve as a path for providing an etchant, and a process such as wet etching can be used to remove a portion of the gate sacrificial layer 250 to form a second gap 202. The second gap 202 is connected to the first gap 201 to form a sacrificial gap 203. The portion of the gate line gap 402' located in the second region 02 can include a third gate line gap 405 and a third sub-region 403-3.

[0174] like Figures 52-59 As shown, after the sacrificial gap 203 is formed, a gate layer 210 can be formed in the sacrificial gap 203 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In other words, the first gate layer 211 and the second gate layer 212 included in the gate layer 210 are formed in the same process. The gate layer 210 may include a conductive material, which may include any one or a combination of a conductive metal material and a doped semiconductor material, wherein the conductive metal material may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the doped semiconductor material may be, for example, doped crystalline silicon or silicide, etc., which is not limited in this application.

[0175] Furthermore, in some embodiments of the present application, after forming the gate layer 210, a gate line isolation structure 400 may be formed by filling the gate line gap 402'. Specifically, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof may be used to fill the gate line gap 402' where the isolation structure 410-2 has been formed with a dielectric filling material to form the gate line isolation structure 400. The dielectric filling material may be an insulating dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride, or a semiconductor material such as polysilicon, which is not limited in this application.

[0176] In addition, in the stacked structure 200' (eg Figure 55 After the gate line isolation structure 400 and the gate layer 210 are formed in FIG. 2 , the stacked structure 200 ′ is formed into a laminated structure 200 .

[0177] Optionally, the method 2000 for preparing a semiconductor structure further includes forming a contact structure 600 .

[0178] As an option, the contact structure 600 can be formed during the process of forming the gate layer 210. For example, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof is used to form a contact conductive layer 610 on the inner wall of the contact hole 601. The contact conductive layer 610 may include a conductive material, which may include any one or a combination of a conductive metal material and a doped semiconductor material. The conductive metal material may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc. The doped semiconductor material may be, for example, doped crystalline silicon or silicide, etc., which is not limited in this application.

[0179] Furthermore, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to form a dielectric filling layer 620 encapsulated by the contact conductive layer 610 in the remaining space of the contact hole 610. The dielectric filling layer 620 can be made of, for example, a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. The contact structure includes a dielectric filling layer encapsulated by the contact conductive layer, which can reduce the use of conductive material in the contact structure, thereby reducing the cost of semiconductor structure preparation and reducing stress and deformation in the stacked structure.

[0180] Therefore, according to the method for preparing a semiconductor structure provided by at least one embodiment of the present application, the semiconductor structure includes a stacked structure, a gate line isolation structure and a contact structure, wherein the stacked structure includes a plurality of steps, the contact structure passes through the corresponding steps along the stacking direction of the stacked structure (hereinafter referred to as the first direction) and is connected to the gate layer of the corresponding step, the gate line isolation structure extends along a second direction intersecting with the first direction, wherein the portion of the gate layer between the gate line isolation structure and the contact structure extends along a third direction intersecting with both the first direction and the second direction. In other words, in the semiconductor structure provided by the embodiment of the present application, the contact structure can pass through the corresponding steps along the stacking direction, thereby reducing the over-etching that occurs in the process of forming the contact hole to accommodate the contact structure, thereby reducing the possibility of short circuit between the gate layers due to the breakdown of the gate layer and the failure of the semiconductor structure. In addition, the portion of the gate layer connected to the contact structure is only located between the gate line isolation structure and the contact structure along the third direction, which can improve the reliability and storage density of the semiconductor structure while achieving a good connection between the gate layer and the contact structure.

[0181] Figure 60 It is a structural diagram of a memory system 30000 according to one embodiment of the present application.

[0182] like Figure 60 As shown, at least one embodiment of another aspect of the present application further provides a memory system 30000. Memory system 30000 may include a semiconductor structure 32100 and a controller 32200. Semiconductor structure 32100 may be the same as the semiconductor structure described in any of the embodiments above, and this application will not further describe this. Semiconductor structure 32100 may be a two-dimensional semiconductor device or a three-dimensional semiconductor device, or even a portion of a two-dimensional semiconductor device or a portion of a three-dimensional semiconductor device. The following description will take a three-dimensional semiconductor device as an example.

[0183] Alternatively, the three-dimensional semiconductor device may include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0184] The memory system 30000 may include a semiconductor structure 32100 and a controller 32200. The semiconductor structure 32100 may be the same as the semiconductor structure described in any of the embodiments above, and will not be described in detail herein. The controller 32200 may control the semiconductor structure 32100 via a channel CH, and the semiconductor structure 32100 may perform operations based on the control of the controller 32200 in response to a request from the host 31000. The semiconductor structure 32100 may receive a command CMD and an address ADDR from the controller 32200 via the channel CH and access a region selected from the memory cell array in response to the address. In other words, the semiconductor structure 32100 may perform an internal operation corresponding to the command on the region selected by the address.

[0185] In some embodiments, the three-dimensional storage system can be implemented as a storage device such as a universal flash storage (UFS) device, a solid-state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, and micro MMC, a secure digital card in the form of SD, mini SD, and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) type storage device, a PCI-Express (PCI-E) type storage device, a compact flash (CF) card, a smart media card, or a memory stick. The storage system provided in this application, because it is provided with the semiconductor device provided in this application, has the same beneficial effects as the semiconductor device, and is not further described here.

[0186] Although an exemplary fabrication method and structure of a semiconductor device are described herein, it is understood that one or more features may be omitted, replaced, or added to the structure of the semiconductor device. In addition, the materials of the various layers illustrated are merely exemplary.

[0187] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of protection encompassed by this application is not limited to the technical solutions formed by the selected combination of the aforementioned technical features, but also encompasses other technical solutions formed by any combination of the aforementioned technical features or their equivalents without departing from the technical concept. For example, a technical solution formed by replacing the aforementioned features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor structure, characterized in that include: The stacked structure includes a first region having a plurality of steps, wherein the steps include a first dielectric layer and a first gate layer stacked along a first direction. a gate line isolation structure, passing through the stacked structure along the first direction and extending along a second direction intersecting the first direction; as well as a contact structure passing through the corresponding step along the first direction and connected to the first gate layer of the corresponding step, The portion of the first gate layer between the gate line isolation structure and the contact structure extends along a third direction, and the third direction intersects with the first direction and the second direction.

2. The semiconductor structure according to claim 1, wherein The stacked structure further includes a second region adjacent to the first region in the second direction; as well as The gate line isolation structure includes: a first gate line isolation structure extending along the second direction and passing through the first region and the second region; a second gate line isolation structure extending in the second region along the second direction; A third gate line isolation structure extends in the first region along the second direction, The second gate line isolation structure and the third gate line isolation structure are both located between adjacent first gate line isolation structures along the third direction.

3. The semiconductor structure according to claim 2, wherein: The second gate line isolation structure and the third gate line isolation structure are staggered along the third direction.

4. The semiconductor structure according to claim 2, wherein: The first gate line isolation structure includes a first sub-portion, an isolation structure, and a second sub-portion extending along the second direction and spaced apart from each other. The first sub-section is located in the first region, the isolation structure is located on a side of the second region close to the first region, and the second sub-section is located in the second region.

5. The semiconductor structure according to any one of claims 2 to 4, wherein: The gate line isolation structure includes a sidewall in contact with the stacked structure, Wherein, the surface of the side wall is a curved surface, and the curved surface includes at least one of a concave surface and a convex surface. The semiconductor structure according to claim 5 , wherein: Both sides of the side wall along the second direction have a wave shape.

7. The semiconductor structure according to claim 1, wherein The stacked structure further includes a second dielectric layer adjacent to the first gate layer in the second direction.

8. The semiconductor structure according to claim 7, wherein: A surface of the first gate layer in contact with the second dielectric layer is a curved surface, and the curved surface includes at least one of a concave surface and a convex surface.

9. The semiconductor structure according to claim 1, wherein Along the first direction, a thickness of the first gate layer of the step is greater than a thickness of the second gate layer below the step.

10. The semiconductor structure according to claim 9, wherein In a direction intersecting the first direction, a size of the first gate layer is larger than a size of the second gate layer.

11. The semiconductor structure according to claim 9, wherein The contact structure passes through the stacked structure along the first direction and is connected to the first gate layer and the second gate layer respectively.

12. The semiconductor structure according to claim 1, wherein The contact structure includes a contact conductive layer and a dielectric filling layer wrapped by the contact conductive layer. The contact conductive layer extends along the first direction and is connected to the first gate layer.

13. A method for preparing a semiconductor structure, characterized in that: include: forming a stack structure, wherein the first region of the stack structure comprises a plurality of steps, and the steps comprise a first dielectric layer and a gate sacrificial layer stacked together; forming a contact hole and a gate line gap, wherein the contact hole passes through the step along a first direction, and the gate line gap passes through the stacked structure along the first direction and extends along a second direction intersecting the first direction; removing a portion of the gate sacrificial layer through the gate line gap and the contact hole to form a sacrificial gap, and forming a first gate layer in the sacrificial gap, The portion of the first gate layer between the gate line gap and the contact hole extends along a third direction, wherein the third direction intersects with the first direction and the second direction.

14. The method according to claim 13, wherein: Forming contact holes and gate line gaps includes: forming a contact hole; forming a first hole passing through the stacked structure along a first direction, wherein a plurality of the first holes are arranged at intervals along the second direction; and At least a portion of the stacked structure located between the first holes adjacent to each other in the second direction is removed to form the gate line gap.

15. The method according to claim 14, wherein Forming the contact hole and the gate line gap also includes: In the process of forming the first hole, the contact hole is formed.

16. The method according to claim 14, wherein The stacked structure further includes a second region adjacent to the first region in the second direction, and the method further includes: In the process of forming the first hole, a channel hole is formed in the second region; and / or In the process of forming the first hole, a dummy channel hole is formed in the first region.

17. The method according to claim 16, wherein The sacrificial gap includes a first gap located in the first area and a second gap located in the second area, and removing a portion of the gate sacrificial layer through the gate line gap and the contact hole to form the sacrificial gap includes: removing a portion of the gate sacrificial layer located at an edge of the gate line gap through a portion of the gate line gap located in the first region, and continuing to remove a portion of the gate sacrificial layer through a portion of the gate line gap located in the first region and the contact hole to form the first gap; and The portion of the gate sacrificial layer located in the second region is removed through the portion of the gate line gap located in the second region to form the second gap connected to the first gap.

18. The method according to claim 17, wherein The gate sacrificial layer includes a first surface and a second surface opposite to each other in the first direction, and a third surface connecting the first surface and the second surface. Continuing to remove a portion of the gate sacrificial layer through a portion of the gate line gap located in the first region and the contact hole comprises: removing a portion of the gate sacrificial layer of the step from the first surface and the third surface of the gate sacrificial layer of the step; as well as A portion of the gate sacrificial layer below the step is removed from the third surface of the gate sacrificial layer below the step.

19. The method according to claim 17, wherein The method further comprises: filling the gate line gap and the contact hole with a first sacrificial layer; and A channel structure is formed in the channel hole, and a dummy channel structure is formed in the dummy channel hole.

20. The method according to claim 19, wherein The step further includes a second sacrificial layer located on the gate sacrificial layer, and further removing a portion of the gate sacrificial layer via a portion of the gate line gap located in the first region and the contact hole further includes: The first sacrificial layer and the second sacrificial layer are removed to expose the first surface of the gate sacrificial layer at the step, and a portion of the gate sacrificial layer is further removed through the exposed gate line gap and the contact hole.

21. The method according to claim 17, wherein The method further comprises: Before removing a portion of the gate sacrificial layer through the gate line gap and the contact hole, an isolation structure is formed in a portion of the gate line gap located in the second region and close to the first region.

22. The method according to claim 13, wherein The method further comprises: In the process of forming the first gate layer, forming a contact conductive layer on the inner wall of the contact hole; and A dielectric filling layer is formed in the remaining space of the contact hole.

23. A memory system, characterized in that: include: At least one semiconductor structure according to any one of claims 1 to 12; as well as The controller is coupled to the semiconductor structure and is used to control the semiconductor structure to store data.

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