IGBT (Insulated Gate Bipolar Translator) chip and gate voltage-withstanding process manufacturing method thereof

Abstract

The invention provides an IGBT (Insulated Gate Bipolar Translator) chip and a gate voltage-withstanding process manufacturing method thereof. The method comprises the following steps: carrying out a p-type ion implantation process on a current batch of IGBT wafers; performing a p-type ion annealing process on the IGBT wafer after the p-type ion implantation process, wherein the condition of the p-type ion annealing process is 1150 DEG C / 70min / N2 + O2; and performing a subsequent tape-out process on the IGBT wafer after the p-type ion annealing process. An oxygen component is introduced into the PBODY IMP Drive in process, so that the surface defects of a film layer caused in the PBODY IMP process are repaired to a certain extent, and the voltage endurance capability of a grid electrode of an IGBT product is further improved. The IGBT chip grid voltage withstanding process manufacturing method is simple and efficient, the grid voltage withstanding capability of the IGBT chip is easily improved, and the grid voltage withstanding capability of an IGBT product is effectively improved by about 30%.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular to an IGBT chip and a method for manufacturing the same using a gate withstand voltage process. Background Art

[0002] Insulated Gate Bipolar Transistor (IGBT) products are widely used in the industrial, automotive, communications, and consumer electronics sectors, with their primary voltage application range being between 600V and 1700V. Due to rapid economic development, the demand for new energy sources has increased significantly, and the market for energy-saving products such as industrial control and variable-frequency white appliances has continued to expand in recent years. The current demand for a single IGBT chip in different usage scenarios ranges from a few amperes to several hundred amperes, and the corresponding IGBT chip area also ranges from a few square millimeters to several hundred square millimeters. As product application scenarios expand and the environmental conditions they face become increasingly demanding, improving gate voltage withstand capability becomes particularly important.

[0003] Among the processes that influence gate voltage resistance, traditional methods involve the trench etch morphology and gate oxide film growth. The trench etch morphology affects the contact tightness between the gate oxide and the trench, while the composition of the gate oxide film growth affects the density and other defects within the film. The most traditional method for improving gate voltage resistance is to increase the gate oxide film thickness, such as from 1000Å to 1200Å. However, this also needs to be coordinated with the design, otherwise it will lead to overall device reliability failure. This, in turn, requires multiple rounds of tape-out debugging, which consumes a long period of time and considerable financial resources before finally achieving an IGBT chip with improved gate voltage resistance.

[0004] Obviously, the traditional methods mentioned above are inefficient and costly for design companies, and they may not necessarily result in IGBT chips with improved gate withstand voltage. For foundries facing increasingly fierce competition, high efficiency and quality are paramount. Therefore, a simple, efficient, and easily implemented manufacturing process for improving the gate withstand voltage of IGBT chips is crucial. Summary of the Invention

[0005] The object of the present invention is to provide an IGBT chip and a gate withstand voltage process manufacturing method thereof to improve the above-mentioned problem.

[0006] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, an embodiment of the present invention provides a method for manufacturing an IGBT chip gate withstand voltage process, the method comprising: Perform p-type ion implantation on the current batch of IGBT wafers; Perform a p-type ion annealing process on the IGBT wafer after the p-type ion implantation process. The p-type ion annealing process conditions are 1150°C / 70min / N2+O2; The IGBT wafer after the p-type ion annealing process is subjected to subsequent tape-out process.

[0007] In a second aspect, an embodiment of the present invention provides an IGBT chip, which is manufactured by the above-mentioned IGBT chip gate withstand voltage manufacturing method.

[0008] Compared with the prior art, the embodiment of the present invention provides an IGBT chip and its gate voltage withstand process manufacturing method, including: performing a p-type ion implantation process on the current batch of IGBT wafers; performing a p-type ion annealing process on the IGBT wafers after the p-type ion implantation process, and the p-type ion annealing process conditions are 1150℃ / 70min / N2+O2; and performing a subsequent tape-out process on the IGBT wafers after the p-type ion annealing process. Introducing oxygen components into the PBODY IMP Drive in process ensures that the surface defects of the film layer caused by the PBODY IMP process are repaired to a certain extent, thereby improving the gate voltage withstand capability of the IGBT product. This IGBT chip gate voltage withstand process manufacturing method is simple, efficient, and easy to implement to improve the gate voltage withstand capability of the IGBT chip, effectively improving the gate voltage withstand capability of the IGBT product by about 30%.

[0009] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0011] Figure 1 A schematic diagram of the steps of a method for manufacturing an IGBT chip gate voltage withstand process provided by an embodiment of the present invention.

[0012] Figure 2 A schematic diagram showing a comparison of gate withstand voltages according to an embodiment of the present invention. DETAILED DESCRIPTION

[0013] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0014] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0015] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are used only to distinguish the description and should not be understood as indicating or implying relative importance.

[0016] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0017] In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limiting the present invention.

[0018] In the description of the present invention, it should also be noted that, unless otherwise expressly specified or limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, or electrical connections; direct connections, indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0019] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0020] The embodiment of the present invention provides a method for manufacturing an IGBT chip gate voltage withstand process, please refer to Figure 1 , Figure 1 The schematic diagram of the steps of the IGBT chip gate withstand voltage manufacturing method provided by the embodiment of the present invention includes: step 1, step 2 and step 3, which are described in detail as follows.

[0021] Step 1: Perform a p-type ion implantation process on the current batch of IGBT wafers.

[0022] Among them, p-type ion implantation is also called PBODY IMP.

[0023] Step 2: performing a p-type ion annealing process on the IGBT wafer after the p-type ion implantation process.

[0024] Among them, the p-type ion annealing process is also called the PBODY IMP Drive-in process. The p-type ion annealing process conditions are 1150°C / 70min / N2+O2, that is, the process conditions are annealing at 1150°C in an N2 and O2 atmosphere for 70min.

[0025] Step 3: Perform a subsequent tape-out process on the IGBT wafer after the p-type ion annealing process.

[0026] Compared to traditional manufacturing processes, the IGBT chip gate voltage withstand process manufacturing method provided by the embodiment of the present invention introduces oxygen components during the PBODY IMP Drive-in process to ensure that the surface defects of the film layer caused by the PBODY IMP process are repaired to a certain extent, thereby improving the gate voltage withstand capability of the IGBT product. The IGBT gate voltage withstand of the traditional manufacturing process method is 60V~70V, while the IGBT chip gate voltage withstand process manufacturing method provided by the embodiment of the present invention can increase the IGBT gate voltage withstand to 80V~90V, effectively improving the gate voltage withstand capability of the IGBT product by approximately 30%, greatly improving the yield rate of the IGBT product, and ensuring that the IGBT product can smoothly enter the mass production stage.

[0027] In an optional implementation, in order to ensure the improvement effect on the gate voltage withstand capability, the embodiment of the present invention also provides an optional implementation, please refer to the following.

[0028] During the p-type ion annealing process, the nitrogen ratio (the ratio of N2 to O2) is within a target range. Optionally, when the nitrogen ratio is within the target range, the oxygen ratio is approximately 2%.

[0029] Optionally, the process of acquiring the target range includes: step 21, step 22, step 23 and step 24, which are described in detail as follows.

[0030] Step 21 : Obtain N batches of IGBT sample wafers that have undergone the same p-type ion implantation process.

[0031] The same-channel p-type ion implantation process refers to a p-type ion implantation process using the same dose Q and the same energy KE.

[0032] Step 22 : performing a p-type ion annealing process on the nth batch of IGBT sample wafers according to the nth nitrogen annealing ratio, and performing a subsequent tape-out process to obtain N batches of IGBT sample wafers for nitrogen annealing ratio analysis.

[0033] Among them, 1≤n≤N, the nitrogen-nourishing ratio decreases from the 1st to the Nth nitrogen-nourishing ratio (that is, the oxygen content increases successively), and the proportion of oxygen can be increased in a gradient of 0.1%.

[0034] Step 23 : Testing N batches of IGBT sample wafers that have completed the tape-out process to obtain a gate withstand voltage value set and a gate leakage current value set corresponding to each batch of IGBT sample wafers.

[0035] In an embodiment of the present invention, the tests performed on the IGBT sample wafer include: Vramp forward test and Vramp reverse test. The Vramp test, also known as the voltage ramp test, is a common gate oxide reliability assessment item. Starting from the operating voltage Vuse, the voltage is linearly increased from 0V to 100V until the oxide breaks down. The voltage at which the chip gate oxide breaks down is determined as the gate withstand voltage.

[0036] Step 24 : Analyze the gate withstand voltage value set and gate leakage current value set corresponding to each batch of IGBT sample wafers, and determine the target range interval from the first nitrogen nutrient ratio to the Nth nitrogen nutrient ratio.

[0037] Based on the foregoing, regarding the content in step 24, an embodiment of the present invention further provides an optional implementation method, please refer to the following, step 24, according to which the gate withstand voltage value set and the gate leakage current value set corresponding to each batch of IGBT sample wafers are analyzed, and the target range interval is determined from the first nitrogen feeding ratio to the Nth nitrogen feeding ratio, including: step 241 and step 242, which are specifically described as follows.

[0038] Step 241 , screening out IGBT sample wafers of the first target batch that simultaneously meet the first condition, the second condition, the third condition, and the fourth condition.

[0039] Among them, the first condition refers to that the lower limit value of the gate voltage withstand value set is greater than the gate voltage withstand lower limit threshold, the second condition refers to that the upper limit value of the gate voltage withstand value set is greater than the gate voltage withstand upper limit threshold, the third condition refers to that the lower limit value of the gate leakage current value is less than the gate leakage current lower limit threshold, and the fourth condition refers to that the upper limit value of the gate leakage current value is greater than the gate leakage current upper limit threshold.

[0040] Step 242 : determining a target range according to the nitrogen nutrient ratio corresponding to the IGBT sample wafers of the first target batch.

[0041] On the basis of the foregoing, regarding the content in step 24, an embodiment of the present invention further provides an optional implementation method, please refer to the following, step 24, according to which the gate withstand voltage value set and the gate leakage current value set corresponding to each batch of IGBT sample wafers are analyzed, and the target range interval is determined from the 1st nitrogen feeding ratio to the Nth nitrogen feeding ratio, including: step 243, step 244, step 245, step 246 and step 247, which are specifically described as follows.

[0042] Step 243 , obtaining the average gate withstand voltage and the average gate leakage current corresponding to each batch of IGBT sample wafers based on the gate withstand voltage value set and the gate leakage current value set corresponding to each batch of IGBT sample wafers.

[0043] Step 244 : determining a gate withstand voltage score corresponding to the nth batch of IGBT sample wafers based on an average gate withstand voltage value corresponding to the nth batch of IGBT sample wafers and a preset gate withstand voltage reference value.

[0044] The more the average gate voltage withstand value exceeds the gate voltage withstand reference value, the higher the gate voltage withstand score.

[0045] Step 245 : determining a gate leakage current score corresponding to the nth batch of IGBT sample wafers according to an average gate leakage current value corresponding to the nth batch of IGBT sample wafers and a preset gate leakage current standard value.

[0046] The more the average gate leakage current is below the gate leakage current benchmark value, the higher the gate leakage current score.

[0047] Step 246 : Determine a corresponding comprehensive score based on the gate leakage current score and gate withstand voltage score corresponding to the nth batch of IGBT sample wafers.

[0048] Step 247 : determining a target range based on the nitrogen nutrient ratio corresponding to the IGBT sample wafers of the second target batch.

[0049] Among them, the second type of target batch of IGBT sample wafers is a batch of IGBT sample wafers whose comprehensive score is greater than a preset score threshold.

[0050] Regarding the contents of step 246, the present embodiment also provides an optional implementation, which is referred to below. Step 246, based on the gate leakage current score and gate withstand voltage score corresponding to the nth batch of IGBT sample wafers, determines the corresponding comprehensive score, including: step 246-1, as follows.

[0051] Step 246 - 1 , performing weight conversion on the gate leakage current score and gate voltage withstand score corresponding to the nth batch of IGBT sample wafers according to the pre-configured voltage withstand weight and leakage current weight, so as to obtain a comprehensive score corresponding to the nth batch of IGBT sample wafers.

[0052] On the basis of the foregoing, regarding how to obtain the gate withstand voltage reference value and the gate leakage current reference value, the embodiment of the present invention further provides an optional implementation method, please refer to the following.

[0053] The process of obtaining the gate withstand voltage reference value and the gate leakage current reference value includes: step 301, step 302, step 303 and step 304, which are described in detail as follows.

[0054] Step 301 , performing a conventional p-type ion annealing process on the N+1 batch of IGBT sample wafers, wherein the p-type ion annealing process conditions are 1150° C. / 70 min / N 2 (the process conditions are annealing at 1150° C. in an N 2 atmosphere for 70 min).

[0055] Among them, the IGBT sample wafers of the N+1th batch also undergo the same p-type ion implantation process as the IGBT sample wafers of the first N batches.

[0056] Step 302 : performing a subsequent tape-out process on the N+1th batch of IGBT wafers after the p-type ion annealing process.

[0057] Step 303 : Testing the N+1th batch of IGBT sample wafers that have completed the tape-out process to obtain a gate withstand voltage value set and a gate leakage current value set corresponding to the N+1th batch of IGBT sample wafers.

[0058] Step 304 : determining a gate withstand voltage reference value and a gate leakage current reference value according to the gate withstand voltage value set and the gate leakage current value set corresponding to the IGBT sample wafers of the N+1th batch.

[0059] Among them, the gate withstand voltage reference value is the average value of the gate withstand voltage value set corresponding to the N+1th batch of IGBT sample wafers, and the gate leakage current standard value is the average value of the gate leakage current value set corresponding to the N+1th batch of IGBT sample wafers.

[0060] Based on the foregoing, regarding how to obtain the gate voltage lower limit threshold, gate voltage upper limit threshold, gate leakage current lower limit threshold and gate leakage current upper limit threshold, the embodiment of the present invention also provides an optional implementation method, please refer to the following.

[0061] The process of obtaining the gate withstand voltage lower limit threshold, the gate withstand voltage upper limit threshold, the gate leakage current lower limit threshold and the gate leakage current upper limit threshold includes: step 301, step 302, step 303 and step 305, which are described in detail as follows.

[0062] Step 301 , performing a conventional p-type ion annealing process on the N+1 batch of IGBT sample wafers, wherein the p-type ion annealing process conditions are 1150° C. / 70 min / N 2 (the process conditions are annealing at 1150° C. in an N 2 atmosphere for 70 min); Among them, the N+1 batch of IGBT sample wafers also undergoes the same p-type ion implantation process as the first N batches of IGBT sample wafers; Step 302 , performing a subsequent tape-out process on the N+1th batch of IGBT wafers after the p-type ion annealing process; Step 303 : Testing the N+1th batch of IGBT sample wafers that have completed the tape-out process to obtain a gate withstand voltage value set and a gate leakage current value set corresponding to the N+1th batch of IGBT sample wafers.

[0063] Step 305 : Determine the gate withstand voltage lower threshold, gate withstand voltage upper threshold, gate leakage current lower threshold, and gate leakage current upper threshold based on the gate withstand voltage value set and gate leakage current value set corresponding to the IGBT sample wafers of the N+1th batch.

[0064] Among them, the gate voltage resistance lower limit threshold is the lower limit value of the gate voltage resistance value set corresponding to the N+1th batch of IGBT sample wafers, the gate voltage resistance upper limit threshold is the upper limit value of the gate voltage resistance value set corresponding to the N+1th batch of IGBT sample wafers, the gate leakage current lower limit threshold is the lower limit value of the gate leakage current value set corresponding to the N+1th batch of IGBT sample wafers, and the gate leakage current upper limit threshold is the upper limit value of the gate leakage current value set corresponding to the N+1th batch of IGBT sample wafers.

[0065] Optionally, obtaining a gate withstand voltage value set and a gate leakage current value set corresponding to the nth batch of IGBT sample wafers includes: selecting a first preset number (for example, 3) of wafers from the nth batch of IGBT sample wafers; selecting a second preset number (for example, 11) of IGBT chips from each wafer; performing a gate withstand voltage test and a gate leakage current test on the obtained IGBT chips, and generating a gate withstand voltage value set and a gate leakage current value set corresponding to the nth batch of IGBT sample wafers based on the test results.

[0066] Please refer to Figure 2 , Figure 2 A schematic diagram comparing gate withstand voltages according to embodiments of the present invention. Lot A represents an IGBT sample wafer subjected to conventional p-type ion annealing conditions (1150°C / 70 min / N2), while Lot B represents an IGBT sample wafer subjected to the p-type ion annealing conditions provided by embodiments of the present invention (1150°C / 70 min / N2+O2). The top layer in the diagram shows the IGBT gate withstand voltage. Sample wafers corresponding to A1 and B1 underwent forward Vramp testing, while sample wafers corresponding to A2 and B2 underwent reverse Vramp testing. The comparison of these withstand voltage values ​​reveals that the conventional IGBT gate withstand voltage is 60V-70V, while the manufacturing method provided by embodiments of the present invention can increase the IGBT gate withstand voltage to 80V-90V, effectively improving the gate withstand voltage capability of IGBT products by approximately 30%, significantly increasing the yield rate of IGBT products and ensuring the smooth entry of IGBT products into mass production.

[0067] An embodiment of the present invention further provides an IGBT chip, which is manufactured by the above-mentioned IGBT chip gate withstand voltage manufacturing method.

[0068] In summary, an embodiment of the present invention provides an IGBT chip and a gate voltage withstand process manufacturing method thereof, comprising: performing a p-type ion implantation process on the current batch of IGBT wafers; performing a p-type ion annealing process on the IGBT wafers after the p-type ion implantation process, wherein the p-type ion annealing process conditions are 1150°C / 70min / N2+O2; and performing a subsequent tape-out process on the IGBT wafers after the p-type ion annealing process. Introducing oxygen components into the PBODY IMP Drive in process ensures that the surface defects of the film layer caused by the PBODY IMP process are repaired to a certain extent, thereby improving the gate voltage withstand capability of the IGBT product. This IGBT chip gate voltage withstand process manufacturing method is simple, efficient, and easy to implement to improve the gate voltage withstand capability of the IGBT chip, effectively improving the gate voltage withstand capability of the IGBT product by approximately 30%.

[0069] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

[0070] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

Claims

1. A method for manufacturing an IGBT chip gate withstand voltage process, characterized in that: The method comprises: Perform p-type ion implantation on the current batch of IGBT wafers; Perform a p-type ion annealing process on the IGBT wafer after the p-type ion implantation process. The p-type ion annealing process conditions are 1150°C / 70min / N2+O2; The IGBT wafer after the p-type ion annealing process is subjected to subsequent tape-out process.

2. The IGBT chip gate withstand voltage manufacturing method according to claim 1, characterized in that: During the p-type ion annealing process, the nitrogen ratio is within the target range; The process of obtaining the target range includes: Obtain N batches of IGBT sample wafers that have undergone the same p-type ion implantation process; Performing a p-type ion annealing process on the nth batch of IGBT sample wafers according to the nth nitrogen annealing ratio, and performing a subsequent tape-out process to obtain N batches of IGBT sample wafers for nitrogen annealing ratio analysis; Among them, 1≤n≤N, and the nitrogen-feeding ratio decreases from the first to the Nth; Testing N batches of IGBT sample wafers that have completed the tape-out process to obtain a gate withstand voltage value set and a gate leakage current value set corresponding to each batch of IGBT sample wafers; The target range is determined based on the gate withstand voltage value set and the gate leakage current value set corresponding to each batch of IGBT sample wafers, from the first nitrogen nutrient ratio to the Nth nitrogen nutrient ratio.

3. The IGBT chip gate withstand voltage manufacturing method according to claim 2, characterized in that: The analysis of the gate withstand voltage value set and the gate leakage current value set corresponding to each batch of IGBT sample wafers, and determining the target range interval from the first nitrogen feeding ratio to the Nth nitrogen feeding ratio, includes: Screening out the first target batch of IGBT sample wafers that simultaneously meet the first condition, the second condition, the third condition, and the fourth condition; The first condition refers to that the lower limit value of the gate withstand voltage value set is greater than the gate withstand voltage lower limit threshold value, the second condition refers to that the upper limit value of the gate withstand voltage value set is greater than the gate withstand voltage upper limit threshold value, the third condition refers to that the lower limit value of the gate leakage current value is less than the gate leakage current lower limit threshold value, and the fourth condition refers to that the upper limit value of the gate leakage current value is greater than the gate leakage current upper limit threshold value; The target range is determined based on the nitrogen nutrient ratio corresponding to the IGBT sample wafers of the first target batch.

4. The IGBT chip gate withstand voltage manufacturing method according to claim 2, characterized in that: The analysis of the gate withstand voltage value set and the gate leakage current value set corresponding to each batch of IGBT sample wafers, and determining the target range interval from the first nitrogen feeding ratio to the Nth nitrogen feeding ratio, includes: According to the gate withstand voltage value set and gate leakage current value set corresponding to each batch of IGBT sample wafers, an average gate withstand voltage value and an average gate leakage current value corresponding to each batch of IGBT sample wafers are obtained; Determine a gate withstand voltage score corresponding to the nth batch of IGBT sample wafers based on an average gate withstand voltage value corresponding to the nth batch of IGBT sample wafers and a preset gate withstand voltage reference value; Determine a gate leakage current score corresponding to the nth batch of IGBT sample wafers based on an average gate leakage current value corresponding to the nth batch of IGBT sample wafers and a preset gate leakage current standard value; Determine the corresponding comprehensive score based on the gate leakage current score and gate withstand voltage score of the nth batch of IGBT sample wafers; The target range is determined based on the nitrogen nutrient ratio corresponding to the second target batch of IGBT sample wafers, wherein the second target batch of IGBT sample wafers is a batch of IGBT sample wafers with a comprehensive score greater than a preset score threshold.

5. The IGBT chip gate withstand voltage manufacturing method according to claim 4, characterized in that: Determining the corresponding comprehensive score based on the gate leakage current score and gate withstand voltage score corresponding to the nth batch of IGBT sample wafers includes: According to the pre-configured withstand voltage weight and leakage current weight, the gate leakage current score and gate withstand voltage score corresponding to the nth batch of IGBT sample wafers are weighted converted to obtain the comprehensive score corresponding to the nth batch of IGBT sample wafers.

6. The IGBT chip gate withstand voltage manufacturing method according to claim 4, characterized in that: The process of obtaining the gate withstand voltage reference value and gate leakage current reference value includes: The N+1 batch of IGBT sample wafers were subjected to a conventional p-type ion annealing process at 1150°C / 70 min / N2; Among them, the N+1 batch of IGBT sample wafers also undergoes the same p-type ion implantation process as the first N batches of IGBT sample wafers; Perform subsequent tape-out process on the N+1th batch of IGBT wafers after the p-type ion annealing process; Testing the N+1th batch of IGBT sample wafers that have completed the tape-out process to obtain a gate withstand voltage value set and a gate leakage current value set corresponding to the N+1th batch of IGBT sample wafers; The gate withstand voltage reference value and the gate leakage current standard value are determined based on the gate withstand voltage value set and the gate leakage current value set corresponding to the IGBT sample wafers of the N+1th batch.

7. The IGBT chip gate withstand voltage manufacturing method according to claim 3, characterized in that: The process of obtaining the gate voltage lower threshold, the gate voltage upper threshold, the gate leakage current lower threshold, and the gate leakage current upper threshold includes: The N+1 batch of IGBT sample wafers were subjected to a conventional p-type ion annealing process at 1150°C / 70 min / N2; Among them, the N+1 batch of IGBT sample wafers also undergoes the same p-type ion implantation process as the first N batches of IGBT sample wafers; Perform subsequent tape-out process on the N+1th batch of IGBT wafers after the p-type ion annealing process; Testing the N+1th batch of IGBT sample wafers that have completed the tape-out process to obtain a gate withstand voltage value set and a gate leakage current value set corresponding to the N+1th batch of IGBT sample wafers; According to the gate withstand voltage value set and the gate leakage current value set corresponding to the IGBT sample wafers of the N+1th batch, the gate withstand voltage lower limit threshold, the gate withstand voltage upper limit threshold, the gate leakage current lower limit threshold and the gate leakage current upper limit threshold are determined.

8. The IGBT chip gate withstand voltage manufacturing method according to claim 2, characterized in that: Obtain the gate withstand voltage value set and gate leakage current value set corresponding to the nth batch of IGBT sample wafers, including: Selecting a first preset number of wafers from the nth batch of IGBT sample wafers; Selecting a second preset number of IGBT chips from each wafer; The obtained IGBT chips are subjected to gate withstand voltage test and gate leakage current test, and a gate withstand voltage value set and a gate leakage current value set corresponding to the nth batch of IGBT sample wafers are generated according to the test results.

9. An IGBT chip, characterized in that: The IGBT chip is manufactured by the IGBT chip gate withstand voltage manufacturing method according to any one of claims 1 to 8.

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