MOS transistor structure and preparation method thereof
By introducing a reinforcement layer into the MOS transistor structure, the problem of SiC MOSFET's thin insulation layer being easily broken down is solved, and its electric field strength resistance and reliability are improved.
Patent Information
- Application Number
- CN202410393559.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-01
- Publication Date
- 2025-10-21
Smart Images
Figure CN120825969A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a MOS transistor structure and a preparation method thereof. Background Art
[0002] The MOS transistor structure, abbreviated as MOS (Metal-Oxide-Semiconductor), is a commonly used semiconductor device. The main operating principle of the MOS structure is to control the current flow through the channel between the two source and drain regions by controlling the gate voltage, hence it is also called a field-effect transistor (FET). Compared to Si MOSFETs of the same power level, SiC MOSFETs have significantly lower on-resistance and switching losses, making them suitable for higher operating frequencies. Because the insulating layer of the SiC MOSFET is insulating and provides electrical isolation, the gate layer can only generate an electric field and cannot pass direct current. Therefore, it is controlled by voltage. In direct current, the gate layer and the source and drain regions are disconnected. Therefore, the thinner the insulating layer, the better the electric field effect, the lower the threshold voltage, and the stronger the conduction capability at the same gate voltage. However, due to the high electric field strength of the SiC MOSFET, a thinner insulating layer is prone to breakdown. Therefore, existing SiC MOSFETs cannot achieve both improved performance and reliability. Summary of the Invention
[0003] Therefore, in order to overcome at least some of the defects and shortcomings in the prior art, an embodiment of the present invention provides a MOS transistor structure and a method for preparing the same. By setting a reinforcement layer, this setting does not increase the on-resistance while ensuring that the insulating layer is relatively thin, thereby enhancing the performance of the MOS transistor structure and thus increasing its reliability.
[0004] On the one hand, an embodiment of the present invention provides a method for preparing a MOS transistor structure, for example, comprising: providing a substrate; the substrate comprising an epitaxial region, a first well region, a second well region, and a source region, the epitaxial region having a first surface, the first well region and the second well region being located at one end of the epitaxial region away from the first surface, the first well region and the second well region being arranged opposite to each other and a distance between the first well region and the second well region; the source region being located at one end of the first well region and the second well region away from the first surface; forming an insulating layer on a side of the substrate away from the first surface; the insulating layer having a second surface on a side close to the first surface, the insulating layer being laterally spanning the first well region, the second well region and the source region and contacting the first well region, the second well region and the source region; forming a gate layer on the side of the insulating layer away from the first surface; before forming the gate layer, forming a reinforcement layer on the side of the second surface of the insulating layer away from the first surface; the orthographic projection of the reinforcement layer on the epitaxial region is located between the first well region and the second well region, and the electric field strength of the reinforcement layer is stronger than the electric field strength of the insulating layer; wherein the epitaxial region has the same doping type as the source region, and the first well region and the second well region have the same doping type and are different from the doping type of the epitaxial region and the source region.
[0005] In one embodiment of the present invention, the step of forming an insulating layer on the side of the substrate away from the first surface includes forming a first insulating layer on the side of the substrate away from the first surface; the step of forming a reinforcement layer on the side of the second surface of the insulating layer away from the first surface before forming the gate layer includes forming the reinforcement layer on the side of the first insulating layer away from the first surface; the step of forming an insulating layer on the side of the substrate away from the first surface also includes forming a second insulating layer on the side of the reinforcement layer away from the first surface, and the second insulating layer covers the first insulating layer and the reinforcement layer.
[0006] In one embodiment of the present invention, the first insulating layer and the second insulating layer have the same thickness.
[0007] In one embodiment of the present invention, the first insulating layer is deposited on a side of the substrate away from the first surface, the reinforcing layer is deposited on a side of the first insulating layer away from the first surface, the reinforcing layer is etched, and the second insulating layer is deposited on a side of the etched reinforcing layer away from the first surface.
[0008] In one embodiment of the present invention, the step of forming a reinforcement layer on the side of the second surface of the insulating layer away from the first surface before forming the gate layer includes forming the reinforcement layer on the side of the insulating layer away from the first surface; the step of forming a gate layer on the side of the insulating layer away from the first surface includes forming the gate layer on the side of the reinforcement layer away from the first surface.
[0009] In one embodiment of the present invention, the thickness of the insulating layer is 200 to 1000 angstroms.
[0010] In one embodiment of the present invention, the material forming the reinforcement layer is silicon nitride.
[0011] In one embodiment of the present invention, the thickness of the reinforcement layer is between 100 and 1000 angstroms.
[0012] On the other hand, an embodiment of the present invention provides a MOS transistor structure, which is manufactured by any of the above-mentioned methods for manufacturing a MOS transistor structure.
[0013] On the other hand, an embodiment of the present invention provides a MOS transistor structure, for example, comprising: a substrate, comprising: an epitaxial region having a first surface; a first well region and a second well region, the first well region and the second well region being located at one end of the epitaxial region away from the first surface, the first well region and the second well region being arranged opposite to each other and a distance between the first well region and the second well region; a source region located at one end of the first well region and the second well region away from the first surface; an insulating layer located on a side of the substrate away from the first surface, the insulating layer having a second surface on a side close to the first surface, the insulating layer spanning the first surface. a well region, the second well region and the source region and in contact with the first well region, the second well region and the source region; a gate layer, located on the side of the insulating layer away from the first surface; a reinforcement layer, located on the side of the second surface of the insulating layer away from the first surface, the positive projection of the reinforcement layer on the epitaxial region is located between the first well region and the second well region, and the electric field resistance strength of the reinforcement layer is stronger than the electric field resistance strength of the insulating layer; wherein the epitaxial region and the source region have the same doping type, the first well region and the second well region have the same doping type and are different from the doping type of the epitaxial region and the source region.
[0014] As can be seen from the above, the above technical solution has at least one or more of the following beneficial effects:
[0015] In an embodiment of the present invention, a reinforcement layer is provided. The reinforcement layer is located on the side of the second surface of the insulating layer away from the first surface, and the orthographic projection of the reinforcement layer on the epitaxial region is located between the first well region and the second well region. The electric field strength of the reinforcement layer is stronger than the electric field strength of the insulating layer. This arrangement does not increase the on-resistance while ensuring that the insulating layer is relatively thin, thereby enhancing the performance of the MOS transistor structure and thus increasing its reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0017] Figure 1 A schematic flow chart of a method for preparing a MOS transistor structure provided in an embodiment of the present invention.
[0018] Figure 2 A schematic structural diagram of a MOS transistor structure provided by an embodiment of the present invention.
[0019] Figure 3 A schematic structural diagram of another MOS transistor structure provided by an embodiment of the present invention.
[0020] Figure 4 for Figure 2 A schematic structural diagram of a portion of a MOS transistor structure is shown.
[0021] Figure 5 for Figure 2 A schematic structural diagram of another partial MOS transistor structure is shown.
[0022] Figure 6 for Figure 2 A schematic structural diagram of another partial MOS transistor structure is shown.
[0023] Figure 7 for Figure 2 A schematic structural diagram of another partial MOS transistor structure is shown.
[0024] Figure 8 for Figure 3 A schematic structural diagram of a portion of a MOS transistor structure is shown.
[0025] Figure 9 for Figure 3 A schematic structural diagram of another partial MOS transistor structure is shown.
[0026] Description of Reference Numerals
[0027] 10: MOS transistor structure; 100: substrate; 110: epitaxial region; 111: first surface; 120: first well region; 130: second well region; 140: source region; 200: insulating layer; 210: first insulating layer; 211: second surface; 220: second insulating layer; 300: gate layer; 400: reinforcement layer. DETAILED DESCRIPTION
[0028] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0029] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts should fall within the scope of protection of the present invention.
[0030] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way are interchangeable where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0031] It should also be noted that the division of multiple embodiments in the present invention is only for the convenience of description and should not constitute a special limitation. The features in various embodiments can be combined and referenced to each other without contradiction.
[0032] like Figure 1 As shown, an embodiment of the present invention provides a method for preparing a MOS transistor structure, for example, including the following steps:
[0033] S1: Provide a substrate 100; substrate 100 includes, for example, an epitaxial region 110, a first well region 120, a second well region 130, and a source region 140. Epitaxial region 110 has a first surface 111. First well region 120 and second well region 130 are located within epitaxial region 110 at an end away from first surface 111. First well region 120 and second well region 130 are disposed opposite each other with a distance between them. Source region 140 is located within first well region 120 and second well region 130 at an end away from first surface 111.
[0034] S2: An insulating layer 200 is formed on the side of the substrate 100 away from the first surface 111; the side of the insulating layer 200 close to the first surface 111 has a second surface 211, and the insulating layer 200 spans the first well region 120, the second well region 130 and the source region 140 and is in contact with the first well region 120, the second well region 130 and the source region 140.
[0035] S3 : forming a gate layer 300 on a side of the insulating layer 200 away from the first surface 111 .
[0036] S4: Before forming the gate layer 300, a reinforcement layer 400 is formed on a side of the second surface 211 of the insulating layer 200 away from the first surface 111; the orthographic projection of the reinforcement layer 400 on the epitaxial region 110 is located between the first well region 120 and the second well region 130, and the electric field strength of the reinforcement layer 400 is stronger than the electric field strength of the insulating layer 200. The epitaxial region 110 and the source region 140 have the same doping type, and the first well region 120 and the second well region 130 have the same doping type and are different from the doping type of the epitaxial region 110 and the source region 140.
[0037] In an embodiment of the present invention, a reinforcing layer 400 is provided. The reinforcing layer 400 is formed on the side of the second surface 211 of the insulating layer 200 away from the first surface 111, and the orthographic projection of the reinforcing layer 400 on the epitaxial region 110 is located between the first well region 120 and the second well region 130. The electric field strength of the reinforcing layer 400 is stronger than the electric field strength of the insulating layer 200. This arrangement does not increase the on-resistance while ensuring that the insulating layer 200 is relatively thin, thereby improving the overall electric field strength, thereby enhancing the performance of the MOS transistor structure 10, and increasing its reliability.
[0038] Alternatively, as Figure 2 and Figure 3As shown, the doping type of the epitaxial region 110 is different from that of the first well region 120 and the second well region 130. For example, when the doping type of the first well region 120 and the second well region 130 is P-type, that is, the first well region 120 and the second well region 130 are P-type well regions (also called PW), the doping type of the epitaxial region 110 is N-type, that is, the epitaxial region 110 is an N-type epitaxial region (also called NEPI). In this embodiment, the epitaxial region 110 is, for example, an N-type epitaxial region, wherein the source region 140 is an N-type heavily doped region, and the doping concentration of N atoms in the source region 140 is, for example, approximately 10 19 per cubic centimeter.
[0039] Furthermore, if Figure 4 As shown, substrate 100 is, for example, rectangular in shape. For example, epitaxial region 110 is formed into a convex structure. The convex structure of epitaxial region 110 near the convex surface has, for example, a first placement space and a second placement space on both sides. First well region 120 and second well region 130 are formed in the first placement space and the second placement space, respectively. First well region 120, second well region 130, and the side of epitaxial region 110 near the convex surface of epitaxial region 110 are flush, that is, first well region 120, second well region 130, and epitaxial region 110 are formed as a whole into a rectangular shape, for example. For example, two source regions 140 are formed, and the two source regions 140 are respectively formed inside the first well region 120 and the second well region 130, and the first well region 120 and the second well region 130 are respectively arranged around the two source regions 140, and the side of the source region 140 close to the convex surface of the epitaxial region 110 is flush with the first well region 120 and the second well region 130, that is, the epitaxial region 110, the first well region 120, the second well region 130 and the side of the source region 140 close to the convex surface of the epitaxial region 110 are all on the same horizontal line.
[0040] like Figure 2 As shown, in one implementation of this embodiment, step S2 specifically includes step S21: forming a first insulating layer 210 on a side of the substrate 100 away from the first surface 111; step S4 is step S41: forming a reinforcing layer 400 on a side of the first insulating layer 210 away from the first surface 111; and step S2 further includes step S22: forming a second insulating layer 220 on a side of the reinforcing layer 400 away from the first surface 111. Specifically, the first insulating layer 210 is deposited on the side of the substrate 100 away from the first surface 111, the reinforcing layer 400 is deposited on the side of the first insulating layer 210 away from the first surface 111, the reinforcing layer 400 is etched, and the second insulating layer 220 is deposited on the side of the etched reinforcing layer 400 away from the first surface 111, wherein the second insulating layer 220 covers the first insulating layer 210 and the reinforcing layer 400. In this embodiment, the specific steps of the method for fabricating a MOS transistor structure are as follows: step S1, step S21, step S41, step S22, and step S3. For example, if Figure 4 and Figure 5 As shown, a substrate 100 is first formed, and then a first insulating layer 210 is formed on a side of the substrate 100 away from the first surface 111. The first insulating layer 210, for example, spans the first well region 120, the second well region 130, and the source region 140 and contacts the first well region 120, the second well region 130, and the source region 140. Optionally, the first insulating layer 210, for example, completely covers the convex surface of the epitaxial region 110, one end of the first insulating layer 210 contacts a portion of the first well region 120 and a portion of the source region 140 within the first well region 120, and the other end of the first insulating layer 210 contacts a portion of the second well region 130 and a portion of the source region 140 within the second well region 130. The first insulating layer 210, for example, is in conductive contact with the epitaxial region 110, the first well region 120, the second well region 130, and the source region 140. The first insulating layer 210 is formed, for example, by deposition, and the thickness of the first insulating layer 210 is, for example, 100 to 500 angstroms (abbreviated as Å). ).in, The first insulating layer 210 is, for example, an oxide, such as silicon oxide.
[0041] Secondly, if Figure 6 As described above, a reinforcement layer 400 is formed on the side of the first insulating layer 210 away from the first surface 111. The length of the reinforcement layer 400, that is, the length along the direction extending from the first well region 120 to the second well region 130, is less than the length of the first insulating layer 210. The reinforcement layer 400 is, for example, arranged in the middle position of the first insulating layer 210 and located between the first well region 120 and the second well region 130, that is, the orthographic projection of the reinforcement layer 400 on the epitaxial region 110 is located between the first well region 120 and the second well region 130. The reinforcement layer 400 is formed, for example, by deposition and etching, that is, the reinforcement layer 400 is deposited on the side of the first insulating layer 210 away from the first surface 111, and the reinforcement layer 400 is etched. The thickness of the reinforcement layer 400 is, for example, between 100 and 150 nm. Between, for example The material forming the reinforcement layer 400 is, for example, silicon nitride.
[0042] Furthermore, if Figure 7As shown, a second insulating layer 220 is formed on a side of the reinforcing layer 400 away from the first surface 111. The length of the second insulating layer 220 is, for example, equal to the length of the first insulating layer 210. Because the length of the reinforcing layer 400 is less than the length of the first insulating layer 210, a portion of the second insulating layer 220 is covered on the reinforcing layer 400, and the other portion is covered on the first insulating layer 210. The thickness of the first insulating layer 210 and the second insulating layer 220 are the same, that is, the thickness of the portion of the second insulating layer 220 in contact with the reinforcing layer 400 and the portion in contact with the first insulating layer 210 are the same as the thickness of the first insulating layer 210. At this time, the second insulating layer 220 is, for example, a convex structure. The second insulating layer 220 is, for example, formed by deposition. The thickness of the second insulating layer 220 is, for example, also The thickness of the insulating layer 200 located on the side of the first well region 120, the second well region 130 and the source region 140 away from the first surface 111 is, for example, approximately The total thickness of the insulating layer 200 and the reinforcement layer 400 on the side of the epitaxial region 110 located between the first well region 120 and the second well region 130 away from the first surface 111 is, for example, approximately It can be seen from this that the total thickness of the insulating layer 200 on the side of the epitaxial region 110 away from the first surface 111 between the first well region 120 and the second well region 130 is thickened due to the provision of the reinforcement layer 400, while the thickness of the insulating layer 200 on the side of the first well region 120, the second well region 130 and the source region 140 away from the first surface 111 does not change. The second insulating layer 220 is, for example, an oxide, such as silicon oxide. Figure 2 As shown, a gate layer 300 is formed on the side of the second insulating layer 220 away from the first surface 111. The gate layer 300 is, for example, also a convex structure. The gate layer 300 is, for example, formed by deposition. The gate layer 300 is, for example, polysilicon. Because the electric field strength of the reinforcing layer 400 is stronger than the electric field strength of the insulating layer 200, by forming the reinforcing layer 400 on the insulating layer 200, the on-resistance is not increased while ensuring that the thickness of the insulating layer 200 is relatively thin, thereby enhancing the electric field effect of the MOS transistor structure 10 and the conduction capability under the same gate layer 300 voltage. That is, the provision of the reinforcing layer 400 can improve the performance of the MOS transistor structure 10, thereby increasing its reliability.
[0043] like Figure 8 and Figure 9As shown, in another implementation of the present embodiment, step S4 is step S42: forming the reinforcement layer 400 on the side of the insulating layer 200 away from the first surface 111; step S3 is specifically: forming the gate layer 300 on the side of the reinforcement layer 400 away from the first surface 111. In this implementation, the specific step sequence of the preparation method of the MOS transistor structure is: step S1, step S2, step S42 and step S3. For example, an insulating layer 200 is formed on the side of the substrate 100 away from the first surface 111, and the insulating layer 200 spans the first well region 120, the second well region 130 and the source region 140 and contacts the first well region 120, the second well region 130 and the source region 140. The insulating layer 200 is formed, for example, by deposition and the thickness of the insulating layer 200 is, for example, A reinforcement layer 400 is formed on the side of the insulating layer 200 away from the first surface 111. The length of the reinforcement layer 400, i.e., the length along the direction extending from the first well region 120 to the second well region 130, is less than the length of the first insulating layer 210. The reinforcement layer 400 is, for example, arranged in the middle of the insulating layer 200 and located between the first well region 120 and the second well region 130. That is, the orthographic projection of the reinforcement layer 400 on the epitaxial region 110 is located between the first well region 120 and the second well region 130. The reinforcement layer 400 is, for example, formed by deposition and etching and the thickness of the reinforcement layer 400 is, for example, about 1000 nm. Between, for example The material forming the reinforcement layer 400 is, for example, silicon nitride.
[0044] Secondly, if Figure 3 As shown, a gate layer 300 is formed on the side of the reinforcement layer 400 away from the first surface 111. The length of the gate layer 300 is, for example, the same as the length of the insulating layer 200. Therefore, the length of the reinforcement layer 400 is less than the length of the gate layer 300. A portion of the gate layer 300 is covered on the reinforcement layer 400, and another portion is covered on the insulating layer 200. At this time, the gate layer 300 is, for example, a convex structure, and the gate layer 300 is formed, for example, by deposition. There are many ways to set the reinforcement layer 400, which are not limited here. Because the electric field strength of the reinforcement layer 400 is stronger than the electric field strength of the insulating layer 200, by setting the reinforcement layer 400 on the insulating layer 200, the on-resistance can be increased without increasing the thickness of the insulating layer 200, thereby enhancing the electric field effect of the MOS transistor structure 10 and the conduction capability under the same gate layer 300 voltage. That is, the setting of the reinforcement layer 400 can improve the performance of the MOS transistor structure 10, thereby increasing its reliability.
[0045] like Figure 2 and Figure 3As shown, the embodiment of the present invention further provides a MOS transistor structure 10, which is manufactured by the above-mentioned MOS transistor structure manufacturing method. Specifically, the MOS transistor structure 10 includes: a substrate 100, an insulating layer 200, a gate layer 300 and a reinforcement layer 400.
[0046] Specifically, substrate 100 includes, for example, an epitaxial region 110, a first well region 120, a second well region 130, and a source region 140. Epitaxial region 110 has a first surface 111. First well region 120 and second well region 130 are located at one end of epitaxial region 110 away from first surface 111. First well region 120 and second well region 130 are disposed opposite each other, with a gap between them. Source region 140 is located at one end of first well region 120 and second well region 130 away from first surface 111. Insulating layer 200 is located on a side of substrate 100 away from first surface 111. A side of insulating layer 200 closer to first surface 111 has a second surface 211. Insulating layer 200 spans first well region 120, second well region 130, and source region 140 and contacts first well region 120, second well region 130, and source region 140. The gate layer 300 is located on a side of the insulating layer 200 away from the first surface 111. The reinforcement layer 400 is located on a side of the second surface 211 of the insulating layer 200 away from the first surface 111. The orthographic projection of the reinforcement layer 400 on the epitaxial region 110 is located between the first well region 120 and the second well region 130. The electric field strength of the reinforcement layer 400 is stronger than that of the insulating layer 200. The epitaxial region 110 and the source region 140 have the same doping type, while the first well region 120 and the second well region 130 have the same doping type and are different from the doping type of the epitaxial region 110 and the source region 140.
[0047] In an embodiment of the present invention, a reinforcing layer 400 is provided. The reinforcing layer 400 is located on the side of the second surface 211 of the insulating layer 200 away from the first surface 111, and the orthographic projection of the reinforcing layer 400 on the epitaxial region 110 is located between the first well region 120 and the second well region 130. The electric field strength of the reinforcing layer 400 is stronger than the electric field strength of the insulating layer 200. This arrangement does not increase the on-resistance while ensuring that the insulating layer 200 is relatively thin, thereby enhancing the performance of the MOS transistor structure 10 and thus increasing its reliability.
[0048] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.
Claims
1. A method for preparing a MOS transistor structure, characterized in that: include: providing a substrate; The substrate includes an epitaxial region, a first well region, a second well region, and a source region. The epitaxial region has a first surface. The first well region and the second well region are located at one end of the epitaxial region away from the first surface. The first well region and the second well region are arranged opposite to each other and there is a distance between the first well region and the second well region. The source region is located at one end of the first well region and the second well region away from the first surface. forming an insulating layer on a side of the substrate away from the first surface; The insulating layer has a second surface on a side close to the first surface, and the insulating layer spans the first well region, the second well region, and the source region and contacts the first well region, the second well region, and the source region; forming a gate layer on a side of the insulating layer away from the first surface; Before forming the gate layer, forming a reinforcement layer on a side of the second surface of the insulating layer away from the first surface; The orthographic projection of the reinforcement layer on the epitaxial region is located between the first well region and the second well region, and the electric field strength of the reinforcement layer is stronger than the electric field strength of the insulating layer; The epitaxial region and the source region have the same doping type, and the first well region and the second well region have the same doping type but are different from the epitaxial region and the source region.
2. The method for preparing a MOS transistor structure according to claim 1, wherein: The step of forming an insulating layer on the side of the substrate away from the first surface includes forming a first insulating layer on the side of the substrate away from the first surface; the step of forming a reinforcement layer on the side of the second surface of the insulating layer away from the first surface before forming the gate layer includes forming the reinforcement layer on the side of the first insulating layer away from the first surface; the step of forming an insulating layer on the side of the substrate away from the first surface also includes forming a second insulating layer on the side of the reinforcement layer away from the first surface, and the second insulating layer covers the first insulating layer and the reinforcement layer.
3. The method for preparing a MOS transistor structure according to claim 2, wherein: The first insulating layer and the second insulating layer have the same thickness.
4. The method for preparing a MOS transistor structure according to claim 2, wherein: The first insulating layer is deposited on a side of the substrate away from the first surface, the reinforcing layer is deposited on a side of the first insulating layer away from the first surface, the reinforcing layer is etched, and the second insulating layer is deposited on a side of the etched reinforcing layer away from the first surface.
5. The method for preparing a MOS transistor structure according to claim 1, wherein: The step of forming a reinforcement layer on the side of the second surface of the insulating layer away from the first surface before forming the gate layer includes forming the reinforcement layer on the side of the insulating layer away from the first surface; the step of forming a gate layer on the side of the insulating layer away from the first surface includes forming the gate layer on the side of the reinforcement layer away from the first surface.
6. The method for preparing a MOS transistor structure according to any one of claims 1 to 5, wherein: The thickness of the insulating layer is 200 to 1000 angstroms.
7. The method for preparing a MOS transistor structure according to claim 1, wherein: The reinforcing layer is made of silicon nitride.
8. The method for preparing a MOS transistor structure according to claim 1, wherein: The thickness of the reinforcement layer is between 100 and 1000 angstroms.
9. A MOS transistor structure, characterized in that: It is manufactured by the method for preparing a MOS transistor structure according to any one of claims 1 to 8.
10. A MOS transistor structure, characterized in that: include: Substrate, including: an epitaxial region having a first surface; a first well region and a second well region, wherein the first well region and the second well region are located at one end of the epitaxial region away from the first surface, the first well region and the second well region are arranged opposite to each other and there is a distance between the first well region and the second well region; a source region, located in the first well region and the second well region at one end away from the first surface; an insulating layer, located on a side of the substrate away from the first surface, the insulating layer having a second surface on a side close to the first surface, the insulating layer spanning the first well region, the second well region, and the source region and contacting the first well region, the second well region, and the source region; a gate layer, located on a side of the insulating layer away from the first surface; a reinforcing layer, located on a side of the second surface of the insulating layer away from the first surface, wherein an orthographic projection of the reinforcing layer on the epitaxial region is located between the first well region and the second well region, and wherein an electric field strength of the reinforcing layer is stronger than an electric field strength of the insulating layer; The epitaxial region and the source region have the same doping type, and the first well region and the second well region have the same doping type but are different from the epitaxial region and the source region.