Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the following steps: providing a substrate; forming a channel structure layer comprising one or more channel lamination layers on the substrate, wherein the channel lamination layers comprise oppositely arranged inner side walls, sacrificial layers located between the oppositely arranged inner side walls, and channel layers located on the inner side walls and the sacrificial layers; forming a pseudo gate structure crossing the channel structure layer on the substrate; forming a source-drain doping layer connected with two ends of the channel layer on the substrate at two sides of the pseudo gate structure; removing the pseudo gate structure to form a gate groove exposing the sacrificial layer; removing the exposed sacrificial layer to form a through groove communicated with the gate groove; and forming a gate structure in the gate groove and the through groove. According to the embodiment of the invention, the inner side wall is formed in the step of forming the channel lamination, so that the shape of the inner side wall is relatively good, and a gap is not easy to exist between the inner side wall and the channel layer, thereby improving the blocking effect of the inner side wall on the source-drain doping layer, reducing the damage probability of the source-drain doping layer, and further improving the performance of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the rapid development of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to advance towards smaller process nodes driven by Moore's Law, making integrated circuits develop in the direction of smaller size, higher circuit precision and higher circuit complexity.

[0003] To better accommodate the scaling requirements of device sizes, semiconductor processes are gradually transitioning from planar transistors to more efficient three-dimensional transistors, such as gate-all-around (GAA) transistors. In a gate-all-around transistor, the gate surrounds the channel area on all sides. Compared to planar transistors, the gate of a gate-all-around transistor has greater control over the channel and can better suppress short-channel effects.

[0004] However, the performance of current semiconductor structures still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a channel structure layer on the substrate, the channel structure layer comprising one or more channel stacks stacked in sequence along the longitudinal direction, each channel stack comprising oppositely arranged inner side walls, a sacrificial layer located between the oppositely arranged inner side walls, and a channel layer located on the inner side walls and the sacrificial layer; forming a dummy gate structure across the channel structure layer on the substrate, the dummy gate structure covering the top and side walls of the channel structure layer along its extension direction; forming source-drain doping layers connected to both ends of the channel layer on the substrate on both sides of the dummy gate structure; removing the dummy gate structure to form a gate groove exposing the sacrificial layer; removing the exposed sacrificial layer to form a through groove intersecting the gate groove; and forming a gate structure in the gate groove and the through groove.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a channel structure layer is formed on the substrate, and the channel structure layer includes one or more channel stacks stacked in sequence along the longitudinal direction, and each channel stack includes relatively arranged inner side walls, a sacrificial layer located between the relatively arranged inner side walls, and a channel layer located on the inner side walls and the sacrificial layer. Since the inner side walls are formed in the step of forming the channel stack, the inner side walls can obtain a better morphology, and it is also difficult for there to be a gap between the inner side walls and the channel layer. Therefore, in the process of removing the sacrificial layer, the blocking effect of the inner side walls on the source and drain doping layers is improved, the probability of the source and drain doping layers being damaged is reduced, and the quality of the source and drain doping layers is improved, and the performance of the semiconductor structure is correspondingly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 44 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0010] As can be seen from the background art, to better adapt to the demand for device scaling, semiconductor processes are gradually transitioning from planar transistors to more efficient three-dimensional transistors, such as gate-all-around transistors. During the manufacturing process of gate-all-around transistors, after forming source and drain grooves, a sacrificial layer is typically laterally etched to form the portion of the width exposed by the source and drain grooves to form inner trenches. Inner sidewalls are then formed within the inner trenches to isolate the source and drain doped layers from the inner gate structure.

[0011] In the prior art, due to the limitations of process conditions, the inner trench is prone to present a more serious footing morphology, and the inner sidewall is also prone to present a footing morphology. After the pseudo-gate structure is subsequently removed, the exposed sacrificial layer needs to be removed, and in order to completely remove the sacrificial layer at the sidewall of the inner sidewall, the sacrificial layer is usually etched. In this process, due to the problem of the footing morphology of the inner sidewall, a gap is easily formed at the interface between the inner sidewall and the adjacent channel layer or at the interface between the inner sidewall and the adjacent substrate, thereby making the inner sidewall less effective in isolating the source / drain doped layer from the inner gate structure, and easily causing damage to the source / drain doped layer. In addition, in subsequent process steps, a leakage path is easily formed between the inner gate structure and the source / drain doped layer, and accordingly, the source / drain doped layer is easily damaged, thereby affecting the performance of the semiconductor structure. The inner gate structure refers to: the portion of the gate structure located between adjacent channel layers, or the portion located between adjacent channel layers and the substrate.

[0012] In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a channel structure layer on the substrate, the channel structure layer comprising one or more channel stacks stacked in sequence along the longitudinal direction, each channel stack comprising relatively arranged inner side walls, a sacrificial layer located between the relatively arranged inner side walls, and a channel layer located on the inner side walls and the sacrificial layer; forming a dummy gate structure across the channel structure layer on the substrate, the dummy gate structure covering the top and side walls of the channel structure layer along its extension direction; forming source and drain doping layers connected to both ends of the channel layer on the substrate on both sides of the dummy gate structure; removing the dummy gate structure to form a gate groove exposing the sacrificial layer; removing the exposed sacrificial layer to form a through groove intersecting the gate groove; and forming a gate structure in the gate groove and the through groove.

[0013] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a channel structure layer is formed on the substrate, and the channel structure layer includes one or more channel stacks stacked in sequence along the longitudinal direction, and each channel stack includes relatively arranged inner side walls, a sacrificial layer located between the relatively arranged inner side walls, and a channel layer located on the inner side walls and the sacrificial layer. Since the inner side walls are formed in the step of forming the channel stack, the inner side walls can obtain a better morphology, and it is also difficult for there to be a gap between the inner side walls and the channel layer. Therefore, in the process of removing the sacrificial layer, the blocking effect of the inner side walls on the source and drain doping layers is improved, the probability of the source and drain doping layers being damaged is reduced, and the quality of the source and drain doping layers is improved, and the performance of the semiconductor structure is correspondingly improved.

[0014] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0015] Figures 1 to 44 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0016] refer to Figure 1 , providing a substrate 100.

[0017] The substrate 100 is used to provide a process platform for subsequent process steps. Specifically, the substrate 100 is used to form a field effect transistor.

[0018] In this embodiment, the semiconductor structure is described by taking a gate-all-around transistor as an example, but in other embodiments, the semiconductor structure may also be a forksheet transistor or a complementary field effect transistor (CFET).

[0019] In this embodiment, the base 100 includes a substrate 101, which is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0020] In this embodiment, the substrate 100 includes a channel region I, and the channel region I is used for subsequently forming a channel structure layer.

[0021] refer to Figures 2 to 22 , a channel structure layer 110 (such as Figure 22 As shown), the channel structure layer 110 includes one or more channel stacks 111 stacked in sequence along the longitudinal direction, each channel stack 111 includes relatively arranged inner side walls 112, a sacrificial layer 113 located between the relatively arranged inner side walls 112, and a channel layer 114 located on the inner side walls 112 and the sacrificial layer 113.

[0022] A channel structure layer 110 is formed on the substrate 100. The channel structure layer 110 includes one or more channel stacks 111 stacked in sequence along the longitudinal direction. Each channel stack 111 includes relatively arranged inner sidewalls 112, a sacrificial layer 113 located between the relatively arranged inner sidewalls 112, and a channel layer 114 located on the inner sidewalls 112 and the sacrificial layer 113. Since the inner sidewalls 112 are formed in the step of forming the channel stack 111, the inner sidewalls 112 can obtain a better morphology, and it is also difficult for there to be a gap between the inner sidewalls 112 and the channel layer 114. Therefore, in the process of removing the sacrificial layer 113, the blocking effect of the inner sidewalls 112 on the source and drain doping layers is improved, the probability of damage to the source and drain doping layers is reduced, and the quality of the source and drain doping layers is improved, and the performance of the semiconductor structure is correspondingly improved.

[0023] The channel stack 111 provides a process basis for subsequently forming a channel layer 114 with a suspended spacing.

[0024] Specifically, the channel layer 114 serves as a conductive channel of the field effect transistor, and the sacrificial layer 113 is used to support the channel layer 114, thereby providing a process basis for the subsequent realization of the spaced-apart suspended setting of the channel layer 114. The sacrificial layer 113 is also used to occupy a spatial position for the subsequently formed gate structure.

[0025] The material of the channel layer 114 may include one or more of silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

[0026] As an example, the material of the channel layer 114 is silicon, and the material of the sacrificial layer 113 is silicon germanium. During the subsequent removal of the sacrificial layer 113, the etching selectivity of silicon germanium and silicon is relatively high. Therefore, by setting the material of the sacrificial layer 113 to silicon germanium and the material of the channel layer 114 to silicon, the impact of the removal process of the sacrificial layer 113 on the channel layer 114 can be effectively reduced, thereby improving the quality of the channel layer 114, and further facilitating the improvement of the performance of the semiconductor device. In other embodiments, the material of the channel layer can also be silicon germanium, and the material of the sacrificial layer can be silicon.

[0027] In this embodiment, the step of forming the channel stack 111 includes: performing one or more stacking operations, the stacking operations including: forming an inner wall group 115, the inner wall group 115 including relatively arranged inner walls 112; forming a sacrificial layer 113 between adjacent inner walls 112 corresponding to the inner wall group 115; forming a channel layer 114 on the inner wall group 115 and the sacrificial layer 113; wherein, in the first stacking operation, the inner wall group 115 is formed on the substrate 100, and in the remaining stacking operations, the inner wall group 115 is formed on the topmost layer of the channel stack 111 that has been formed.

[0028] By performing one or more stacking operations, i.e., first forming the inner wall group 115, then forming the sacrificial layer 113 between the adjacent inner wall groups 112 corresponding to the inner wall group 115, and then forming the channel layer 114 on the inner wall group 115 and the sacrificial layer 113, it is helpful to reduce the difficulty of forming the channel stack 111 and improve the quality of the channel stack 111.

[0029] Among them, forming the inner wall group 115, that is, forming a plurality of inner wall 112, is convenient for directly forming the inner wall 112 that meets the width requirement; moreover, compared with the solution of forming the inner groove by laterally etching the sacrificial layer and forming the inner wall in the inner groove, it is easy to improve the morphology quality of the inner wall 112.

[0030] In addition, the inner wall group 115 is formed first, and then the sacrificial layer 113 is formed between the adjacent inner walls 112 corresponding to the inner wall group 115. That is, when the inner wall 112 is formed, the sacrificial layer has not yet been formed, which prevents the morphology of the inner wall 112 from being affected by the morphology of other film layers (such as the sacrificial layer 113), thereby facilitating the inner wall 112 to obtain a better morphology.

[0031] It should be noted that the steps of the first stacking operation include: forming an inner wall group 115 on the substrate 100, the inner wall group 115 including relatively arranged inner walls 112; forming a sacrificial layer 113 on the substrate 100 between adjacent inner walls 112 corresponding to the inner wall group 115; and forming a channel layer 114 on the inner wall group 115 and the sacrificial layer 113.

[0032] It should also be noted that the steps of the second stacking operation include: forming an inner wall group 115 on the formed topmost channel stack 111, the inner wall group 115 including relatively arranged inner walls 112; forming a sacrificial layer 113 on the channel stack 111 between adjacent inner walls 112 corresponding to the inner wall group 115, that is, the newly formed inner wall 112 and sacrificial layer 113 cover the top of the topmost channel stack 111, and accordingly, the newly formed inner wall 112 and sacrificial layer 113 serve as the new topmost inner wall group 115 and sacrificial layer 113; forming a channel layer 114 on the topmost inner wall group 115 and sacrificial layer 113, and accordingly, the newly formed channel layer 114 serves as the new topmost channel layer 114, and the new topmost inner wall group 115, sacrificial layer 113 and channel layer 114 serve as the new topmost channel stack 111.

[0033] In this embodiment, the steps of forming the inner wall group 115 include: forming a fully covered inner wall material layer 1120; forming a patterned third mask layer 1121 on the inner wall material layer 1120; using the third mask layer 1121 as a mask, patterning the inner wall material layer 1120 to form the inner wall 112, and the adjacent and oppositely arranged inner walls 112 serve as the inner wall group 115.

[0034] In the same inner sidewall group 115 , the oppositely disposed inner sidewalls 112 are all located at the boundary of the same channel region I on the substrate 100 .

[0035] After forming a fully covered inner wall material layer 1120, a patterned third mask layer 1121 is first formed on the inner wall material layer 1120, and then the third mask layer 1121 is used as a mask to pattern the inner wall material layer 1120 to form the inner wall 112, which helps to reduce the difficulty of forming the inner wall 112, thereby improving the morphological accuracy, dimensional accuracy and positional accuracy of the inner wall 112.

[0036] The following combination Figures 2 to 11 , describe the steps of the first stacking operation in detail.

[0037] like Figures 2 to 3 As shown, an inner sidewall group 115 is formed on the substrate 100 , and the inner sidewall group 115 includes inner sidewalls 112 arranged opposite to each other.

[0038] In this embodiment, the steps of forming the inner wall group 115 include: forming an inner wall material layer 1120 that completely covers the top of the substrate 100; forming a patterned third mask layer 1121 on the inner wall material layer 1120; using the third mask layer 1121 as a mask, patterning the inner wall material layer 1120, removing the inner wall material layer 1120 located on the substrate 100 and exposed by the third mask layer 1121, forming the inner wall 112, and the adjacent and oppositely arranged inner walls 112 serve as the inner wall group 115.

[0039] It should be noted that the inner sidewall group 115 formed in the first stacking operation is the inner sidewall group 115 of the first layer, and the inner sidewalls 112 included in the inner sidewall group 115 of the first layer are the inner sidewalls 112 of the first layer.

[0040] The formation position of the inner sidewall 112 is defined by the third mask layer 1121 , which is beneficial to improving the morphology quality and dimensional accuracy of the inner sidewall 112 .

[0041] Specifically, after forming the inner sidewall 112 , the process further includes: removing the third mask layer 1121 .

[0042] As an example, in the step of forming the inner side wall 112, each inner side wall group 115 includes two strip-shaped inner side walls 112 that are oppositely arranged, so that in the subsequent step of forming the sacrificial layer 113, the two inner side walls 112 in the same inner side wall group 115 respectively cover the two oppositely arranged side walls of the same sacrificial layer 113, and the remaining side walls of the sacrificial layer 113 are exposed.

[0043] As another example, in the step of forming the inner wall 112, each inner wall group 115 includes four strip-shaped inner walls 112, and the four inner walls 112 form a "U" shape, so that in the subsequent step of forming the sacrificial layer 113, the inner walls 112 in the same inner wall group 115 surround and cover the side walls of the same sacrificial layer 113, which is beneficial to improving the morphological accuracy of the sacrificial layer 113, facilitating reducing the difficulty of subsequent removal of the sacrificial layer 113, and is also beneficial to improving the morphological accuracy of the subsequent formed through-groove, and is also beneficial to improving the stability of the inner wall 112, so that the inner wall 112 is not prone to bending, tilting or collapse.

[0044] like Figures 4 to 8 As shown, a sacrificial layer 113 (eg, Figure 8 shown).

[0045] In this embodiment, the steps of forming the sacrificial layer 113 include: Figures 4 and 5 As shown, an initial sacrificial layer 1130 is filled on the substrate 100 at the side of the inner sidewall 112, and the initial sacrificial layer 1130 exposes the top of the inner sidewall 112; Figures 6 to 8 As shown, the initial sacrificial layer 1130 in the outer area of ​​the inner sidewall group 115 is removed, and the initial sacrificial layer 1130 between the adjacent inner sidewalls 112 corresponding to the inner sidewall group 115 is retained as the sacrificial layer 113 .

[0046] Since the oppositely disposed inner sidewalls 112 in the same inner sidewall group 115 are all located on the substrate 100 at the boundary of the same channel region I, that is, the area between the oppositely disposed inner sidewalls 112 in the same inner sidewall group 115 is the channel region I. Therefore, the outer area of ​​the inner sidewall group 115 herein refers to the remaining area except the channel region I.

[0047] First, an initial sacrificial layer 1130 exposing the top of the inner wall 112 is filled on the substrate 100 on the side of the inner wall 112, and then the initial sacrificial layer 1130 in the outer area of ​​the inner wall group 115 (i.e., the remaining area except the channel area I) is removed. This helps to reduce the difficulty of forming the sacrificial layer 113 and improve process compatibility.

[0048] It should be noted that, in the first stacking operation, the sacrificial layer 113 formed is the first sacrificial layer 113 .

[0049] In this embodiment, the steps of forming the initial sacrificial layer 1130 include: Figure 4 As shown, a sacrificial material layer 1131 is filled on the substrate 100 at the side of the inner sidewall 112, and the sacrificial material layer 1131 covers the inner sidewall 112; Figure 5 As shown, the sacrificial material layer 1131 is planarized, and the sacrificial material layer 1131 on the top of the inner sidewall 112 is removed to expose the top of the inner sidewall 112 . The remaining sacrificial material layer 1131 serves as the initial sacrificial layer 1130 .

[0050] First, a sacrificial material layer 1131 covering the inner wall 112 is filled on the substrate 100 on the side of the inner wall 112, and then the sacrificial material layer 1131 is flattened and the sacrificial material layer 1131 on the top of the inner wall 112 is removed. This is beneficial to improving the uniformity of the thickness of the initial sacrificial layer 1130, thereby improving the uniformity of the thickness of the sacrificial layer 113.

[0051] Specifically, if Figure 4 As shown, a sacrificial material layer 1131 is filled on the substrate 100 at the side of the inner sidewall 112. The sacrificial material layer 1131 covering the inner sidewall 112 means that the sacrificial material layer 1131 covers the sidewall and top of the inner sidewall 112 of the first layer; Figure 5As shown, the sacrificial material layer 1131 is flattened, the sacrificial material layer 1131 on the top of the inner wall 112 is removed, and the remaining sacrificial material layer 1131 serves as the initial sacrificial layer 1130. Specifically, it means: removing the sacrificial material layer 1131 on the top of the inner wall 112 of the first layer, exposing the top of the inner wall 112 of the first layer, and the remaining sacrificial material layer 1131 serves as the initial sacrificial layer 1130 of the first layer.

[0052] It should be noted that the process of planarizing the sacrificial material layer 1131 includes a chemical mechanical planarization (CMP) process.

[0053] In this embodiment, after forming the sacrificial material layer 1131 and before performing a planarization process on the sacrificial material layer 1131, the second sacrificial layer 1135 (eg, Figure 4 During the planarization process, the second sacrificial layer 1135 (as shown) is removed. Figure 5 shown).

[0054] After forming the sacrificial material layer 1131, before flattening the sacrificial material layer 1131, a second sacrificial layer 1135 is formed on the sacrificial material layer 1131, so that during the flattening process of the sacrificial material layer 1131, the flattening speed of the sacrificial material layer 1131 at each position is more uniform, thereby making the thickness of the initial sacrificial layer 1130 more uniform.

[0055] In this embodiment, after forming the initial sacrificial layer 1130 and before forming the sacrificial layer 113, the following steps are further included: Figure 6 As shown, a first mask layer 1132 is formed on the inner sidewall group 115 and on the initial sacrificial layer 1130 between adjacent inner sidewalls 112 corresponding to the inner sidewall group 115; Figure 7 As shown, the first mask layer 1132 is used as a mask to remove the initial sacrificial layer 1130 in the outer area of ​​the inner sidewall group 115; Figure 8 As shown, after forming the sacrificial layer 113 , the process further includes: removing the first mask layer 1132 .

[0056] The first mask layer 1132 is formed to protect the initial sacrificial layer 1130 that needs to be retained.

[0057] First, a first mask layer 1132 is formed on the inner wall group 115 and on the initial sacrificial layer 1130 between the adjacent inner walls 112 corresponding to the inner wall group 115, and then the first mask layer 1132 is used as a mask to remove the initial sacrificial layer 1130 in the outer area of ​​the inner wall group 115. This is beneficial to reducing the difficulty of forming the sacrificial layer 113 and also beneficial to reducing the probability of damage to the inner wall 112 during the process of forming the sacrificial layer 113.

[0058] It should be noted that removing the initial sacrificial layer 1130 in the outer area of ​​the inner sidewall spacer set 115 refers to removing the initial sacrificial layer 1130 in the remaining area except the channel area I.

[0059] like Figures 9 to 11 As shown, a channel layer 114 is formed on the inner wall spacer set 115 and the sacrificial layer 113 .

[0060] In this embodiment, the steps of forming the channel layer 114 include: Figure 9 As shown, an initial channel layer 1140 covering the inner sidewall group 115 and the sacrificial layer 113 is formed on the substrate 100; Figures 10 and 11 As shown, the initial channel layer 1140 in the outer area of ​​the inner wall spacer set 115 is removed, and the initial channel layer 1140 on the top of the inner wall spacer set 115 and the sacrificial layer 113 is retained as the channel layer 114 .

[0061] First, an initial channel layer 1140 covering the inner wall group 115 and the sacrificial layer 113 is formed on the substrate 100, and then the initial channel layer 1140 in the outer area of ​​the inner wall group 115 is removed, and the initial channel layer 1140 on the top of the inner wall group 115 and the sacrificial layer 113 is retained as the channel layer 114, which helps to reduce the difficulty of forming the channel layer 114.

[0062] In this embodiment, the channel layer 114 formed on the first-layer inner sidewall spacer 112 and the sacrificial layer 113 is the first-layer channel layer 114 .

[0063] Specifically, the steps of forming the first channel layer 114 include: Figure 9 As shown, an initial channel layer 1140 is formed on the substrate 100, and the initial channel layer 1140 covers the sidewalls and the top of the first layer of the inner sidewall 112 corresponding to the inner sidewall group 115, and the top of the first layer of the sacrificial layer 113; Figure 11 As shown, the initial channel layer 1140 in the outer area of ​​the first inner wall spacer group 115 is removed, and the first inner wall spacer 112 and the initial channel layer 1140 on the top of the first sacrificial layer 113 are retained as the first channel layer 114.

[0064] It should be noted that the first channel layer 114 , the first inner sidewall spacer set 115 , and the first sacrificial layer 113 constitute the first channel stack 111 .

[0065] In this embodiment, after the initial channel layer 1140 is formed, before the initial channel layer 1140 in the outer area of ​​the inner sidewall group 115 is removed, the following steps are further included: Figure 10 As shown, a patterned second mask layer 1141 is formed on the initial channel layer 1140, and the second mask layer 1141 is located above the top of the inner wall group 115 and above the top of the corresponding sacrificial layer 113 inside the inner wall group 115; using the second mask layer 1141 as a mask, the initial channel layer 1140 in the outer area of ​​the inner wall group 115 is removed; after the channel layer 114 is formed, it also includes: removing the second mask layer 1141.

[0066] First, a graphic second mask layer 1141 is formed on the initial channel layer 1140, and the second mask layer 1141 is located in each channel area I. Then, the second mask layer 1141 is used as a mask to remove the initial channel layer 1140 in the outer area of ​​the inner wall group 115. This is beneficial to reducing the difficulty of forming the channel layer 114, and is also beneficial to reducing the probability of other film layers (such as the inner wall 112) being damaged during the process of forming the channel layer 114, thereby improving the morphological accuracy, dimensional accuracy and positional accuracy of the channel layer 114.

[0067] In this embodiment, after forming the first layer of the channel stack 111, the second layer of the channel stack 111 is formed. Figures 12 to 21 , describe the steps of the second stacking operation in detail.

[0068] In this embodiment, Figures 12 to 13 As shown, the steps of forming the second-layer inner wall group 115 include: forming an inner wall material layer 1120 that fully covers the top of the substrate 100, the side walls of the formed channel stack 111, and the top of the formed topmost channel stack 111; forming a patterned third mask layer 1121 on the inner wall material layer 1120; using the third mask layer 1121 as a mask, patterning the inner wall material layer 1120, removing the inner wall material layer 1120 located on the substrate 100 and at the top of the formed topmost channel stack 111 and exposed by the third mask layer 1121, to form the second-layer inner wall 112, and the adjacent and oppositely arranged second-layer inner wall 112 serves as the second-layer inner wall group 115.

[0069] Specifically, after forming the inner sidewall 112 , the process further includes: removing the third mask layer 1121 .

[0070] It should be noted that the inner sidewalls 112 of the second layer are located above the inner sidewalls 112 of the first layer, and the formation position of the inner sidewalls 112 of the second layer corresponds to the formation position of the inner sidewalls 112 of the first layer. For example, when the inner sidewalls 112 of the first layer cover the two opposite sidewalls of the sacrificial layer 113, the inner sidewalls 112 of the second layer are also strip-shaped, thereby covering the two opposite sidewalls of the subsequently formed sacrificial layer 113; when the inner sidewalls 112 of the first layer form a "U" shape and surround and cover the sidewalls of the sacrificial layer 113, the inner sidewalls 112 of the second layer also form a "U" shape and surround and cover the sidewalls of the subsequently formed sacrificial layer 113.

[0071] Accordingly, the third mask layer 1121 is located above the formed inner sidewall 112 .

[0072] In this embodiment, the step of forming the second sacrificial layer 113 is similar to the step of forming the first sacrificial layer 113 in the first stacking operation, and therefore will not be described again herein.

[0073] It should be noted that in the second stacking operation, the sacrificial layer 113 formed is the second sacrificial layer 113 . Therefore, in the Nth stacking operation, the sacrificial layer 113 formed is the Nth sacrificial layer 113 , where N is a natural number.

[0074] Specifically, the steps of forming the second initial sacrificial layer 1130 include: Figure 14 As shown, a sacrificial material layer 1131 is filled on the substrate 100 at the side of the inner sidewall 112. The sacrificial material layer 1131 covers the inner sidewall 112, that is, the sacrificial material layer 1131 covers the sidewalls and top of the inner sidewall 112 on the formed topmost trench stack 111 (that is, the inner sidewall 112 of the second layer), and also covers the top of the formed topmost trench stack 111 (that is, the first layer of trench stack 111); Figure 15 As shown, the sacrificial material layer 1131 is flattened, and the sacrificial material layer 1131 on the top of the inner wall 112 is removed, that is, the sacrificial material layer 1131 on the top of the inner wall 112 of the second layer is removed to expose the top of the inner wall 112, and the remaining sacrificial material layer 1131 serves as the initial sacrificial layer 1130 of the second layer.

[0075] In this embodiment, in the second stacking operation, after forming the sacrificial material layer 1131 and before performing the planarization process on the sacrificial material layer 1131, the second sacrificial layer 1135 (such as Figure 14 During the planarization process, the second sacrificial layer 1135 (as shown) is removed. Figure 15The function of forming the second sacrificial layer 1135 in the second stacking operation is similar to that of forming the second sacrificial layer 1135 in the first stacking operation, and thus will not be described in detail here.

[0076] In this embodiment, after forming the initial sacrificial layer 1130 and before forming the sacrificial layer 113, the following steps are further included: Figure 16 As shown, a first mask layer 1132 is formed on the inner sidewall group 115 and on the initial sacrificial layer 1130 between adjacent inner sidewalls 112 corresponding to the inner sidewall group 115; accordingly, as shown Figure 17 As shown, the first mask layer 1132 is used as a mask to remove the initial sacrificial layer 1130 in the outer area of ​​the inner sidewall group 115; Figure 18 As shown, after forming the sacrificial layer 113, the process further includes removing the first mask layer 1132. The function of the first mask layer 1132 in the second stacking operation is similar to that in the first stacking operation, so it will not be described in detail here.

[0077] It should be noted that removing the initial sacrificial layer 1130 in the outer area of ​​the inner sidewall spacer set 115 here refers to removing the initial sacrificial layer 1130 on the side of the formed channel stack 111 .

[0078] In this embodiment, the steps of forming the second channel layer 114 include: Figure 19 As shown, an initial channel layer 1140 is formed on the substrate 100, and the initial channel layer 1140 covers the sidewalls of the formed channel stack 111, the sidewalls and top of the second layer of the inner sidewall 112 corresponding to the inner sidewall group 115, and the top of the second layer of the sacrificial layer 113; Figure 21 As shown, the initial channel layer 1140 in the outer area of ​​the inner spacer group 115 is removed, and the second inner spacer 112 and the initial channel layer 1140 on top of the second sacrificial layer 113 are retained as the second channel layer 114 .

[0079] It should be noted that the second-layer channel layer 114, the second-layer inner wall group 115, and the second-layer sacrificial layer 113 constitute the second-layer channel stack 111. It can be understood that the N-th layer channel layer 114, the N-th layer inner wall group 115, and the N-th layer sacrificial layer 113 constitute the N-th layer channel stack 111, where N is a natural number.

[0080] In this embodiment, after the initial channel layer 1140 is formed, before the initial channel layer 1140 in the outer area of ​​the inner sidewall group 115 is removed, the following steps are further included: Figure 20As shown, a patterned second mask layer 1141 is formed on the initial channel layer 1140; using the second mask layer 1141 as a mask, the initial channel layer 1140 in the area outside the inner sidewall assembly 115 is removed; after the channel layer 114 is formed, the second mask layer 1141 is further removed. The function of the second mask layer 1141 in this embodiment is similar to that of the second mask layer 1141 in the first stacking operation, and therefore will not be further described here.

[0081] refer to Figure 22 , another channel stack 111 (ie, a third channel stack 111 ) is formed on the second channel stack 111 (ie, the second channel stack 111 ) formed by the second stacking operation.

[0082] It should be noted that the steps of the subsequent stacking operation are the same as those of the second stacking operation and will not be repeated here.

[0083] It should also be noted that Figure 22 2 illustrates a case where the channel structure layer 110 includes three channel stacks 111 stacked in sequence along the longitudinal direction. It is understood that the number of channel stacks 111 is not limited to three. For example, the number of channel stacks 111 may also be two, or any number greater than three.

[0084] In other embodiments, the step of forming a channel stack includes: performing one or more stacking operations to form one or more initial channel stacks stacked in sequence along the longitudinal direction on a substrate, the stacking operation including: forming an inner wall group, the inner wall group including relatively arranged inner walls; filling a sacrificial layer on the side of the inner wall, the sacrificial layer exposing the top of the inner wall; forming a channel layer on the inner wall and the sacrificial layer; wherein, in the first stacking operation, the inner wall group is formed on the substrate, and in the remaining stacking operations, the inner wall group is formed on the topmost initial channel stack that has been formed; after completing the last stacking operation, the initial channel stack in the outer area of ​​the inner wall group is removed, and the remaining initial channel stack is used as the channel stack.

[0085] First, one or more stacking operations are performed to form one or more initial channel stacks stacked in sequence along the longitudinal direction, and then the initial channel stacks in the outer area of ​​the inner wall group are removed. The remaining initial channel stacks are used as the channel stacks. That is, the initial channel stacks in the outer area of ​​the inner wall group can be removed through a single removal process, which is beneficial to saving process steps and thus beneficial to improving process efficiency.

[0086] It should be noted that the steps of forming the inner wall group are similar to those in the aforementioned embodiment and will not be repeated here.

[0087] refer to Figures 23 to 28As shown, in this embodiment, after forming the channel structure layer 110 and before forming the dummy gate structure, the method further includes: forming a shallow trench isolation structure (STI) 121 in the substrate 100 on the side of the channel structure layer 110, the shallow trench isolation structure 121 exposing the channel structure layer 110 (such as Figure 27 and Figure 28 shown).

[0088] in, Figure 27 For top view, Figure 28 for Figure 27 Schematic diagram of the cross-section structure along AA1. In order to show the structure of the semiconductor more clearly, Figure 27 The adhesion layer and the channel layer are omitted.

[0089] The shallow trench isolation structure 121 is used to isolate each semiconductor device to prevent leakage current between the devices.

[0090] Specifically, the material of the shallow trench isolation structure 121 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. As an example, the material of the shallow trench isolation structure 121 includes silicon oxide.

[0091] It should be noted that the steps of forming the shallow trench isolation structure 121 include: Figure 24 As shown, the third portion of the thickness of the substrate 100 is removed along the channel structure layer 110 to form a bottom fin 102 protruding from the substrate 101; Figure 26 As shown, an initial shallow trench isolation structure 120 is formed on the substrate 101 at the side of the bottom fin 102, covering the sidewall of the bottom fin 102 and the sidewall of the channel structure layer 110; Figure 27 and Figure 28 As shown, the initial shallow trench isolation structure 120 covering the sidewall of the channel structure layer 110 is removed, and the remaining initial shallow trench isolation structure 120 serves as a shallow trench isolation structure 121 .

[0092] As an example, the step of forming an initial shallow trench isolation structure 120 covering the side walls of the channel structure layer 110 on the substrate 101 on the side of the bottom fin 102 includes: forming a shallow trench isolation material layer (not shown) covering the side walls of the bottom fin 102 and the side walls and top of the channel structure layer 110 on the substrate 101 on the side of the bottom fin 102; removing the shallow trench isolation material layer above the top of the channel structure layer 110, and the remaining shallow trench isolation material layer serves as the initial shallow trench isolation structure 120.

[0093] As an example, the process of forming the shallow trench isolation material layer includes a flowable chemical vapor deposition (FCVD) process, and the process of removing the shallow trench isolation material layer above the top of the channel structure layer 110 includes a chemical mechanical polishing process.

[0094] In this embodiment, after forming the channel structure layer 110 and before forming the bottom fin 102, the following steps are further included: Figure 23 As shown, an adjustment layer 103 is formed to cover the sidewalls and top of the channel structure layer 110. The adjustment layer 103 also covers the substrate 100 on the side of the channel structure layer 110. Accordingly, as shown in FIG. Figure 24 As shown, during the process of forming the bottom fin 102, the adjustment layer 103 on the sidewall of the channel structure layer 110 is removed, and the adjustment layer 103 covering the substrate 100 and the substrate 100 of the third part thickness (such as Figure 24 After forming the bottom fin 102, the method further includes: removing the adjustment layer 103.

[0095] The adjustment layer 103 is used to adjust the width of the bottom fin 102 . Furthermore, under the protection of the adjustment layer 103 , removing the third portion of the thickness of the substrate 100 is beneficial to improving the topographical accuracy and dimensional accuracy of the bottom fin 102 .

[0096] Here, the width of the bottom fin 102 refers to the dimension in a direction perpendicular to the sidewall of the channel structure layer 110 .

[0097] Specifically, the adjustment layer 103 is formed by atomic layer deposition. The material of the adjustment layer 103 may include silicon oxide.

[0098] like Figure 25 As shown, in this embodiment, after the bottom fin 102 is formed and before the initial shallow trench isolation structure 120 is formed, it also includes: forming an adhesion layer 122 on the top of the substrate 101 covering the side walls and top of the channel structure layer 110, the side walls of the bottom fin 102, and the side of the bottom fin 102.

[0099] The adhesion layer 122 is used to improve the adhesion between the substrate 100 and the initial shallow trench isolation structure 120 .

[0100] Accordingly, in the step of forming the initial shallow trench isolation structure 120, the initial shallow trench isolation structure 120 is formed on the adhesion layer 122 (eg, Figure 26 shown).

[0101] Specifically, in the step of removing the initial shallow trench isolation structure 120 covering the sidewall of the channel structure layer 110, the adhesion layer 122 (eg, Figure 27 shown).

[0102] refer to Figure 29 In this embodiment, after forming the channel structure layer 110 and before forming the dummy gate structure, the method further includes: forming a dummy gate dielectric layer 131 on the top and sidewalls of the channel structure layer 110 .

[0103] The dummy gate dielectric layer 131 is used to protect the channel structure layer 110 in the subsequent step of removing the dummy gate structure.

[0104] Specifically, the material of the dummy gate dielectric layer 131 includes one or both of silicon oxide and silicon oxynitride.

[0105] It should be noted that the process of forming the dummy gate dielectric layer 131 includes an in-situ steam generation (ISSG) oxidation process or an atomic layer deposition process.

[0106] It should also be noted that after the dummy gate dielectric layer 131 is formed, the dummy gate dielectric layer 131 may be subjected to nitrogen doping treatment.

[0107] refer to Figures 30 to 32 A dummy gate structure 130 is formed on the substrate 100 and spans the channel structure layer 110 . The dummy gate structure 130 covers the top and sidewalls of the channel structure layer 110 along its extension direction.

[0108] The dummy gate structure 130 covers the top and sidewalls of the channel structure layer 110 along its extension direction. That is, in a direction perpendicular to the extension direction of the dummy gate structure 130 , the dummy gate structure 130 exposes both ends of the channel structure layer 110 .

[0109] The dummy gate structure 130 is used to occupy a space for the subsequent formation of a device gate structure.

[0110] Specifically, the material of the dummy gate structure 130 includes one or more of polysilicon, amorphous silicon, and amorphous carbon. As an example, the material of the dummy gate structure 130 is polysilicon.

[0111] It should be noted that the steps of forming the dummy gate structure 130 include: Figure 30 As shown, a dummy gate material layer 135 is formed on the substrate 100, and the dummy gate material layer 135 covers the sidewalls and the top of the channel structure layer 110; Figure 31 As shown, a gate mask structure 136 is formed on the dummy gate material layer 135; Figure 32 As shown, the gate mask structure 136 is used as a mask to pattern the dummy gate material layer 135 , and the remaining dummy gate material layer 135 serves as the dummy gate structure 130 .

[0112] The gate mask structure 136 is used as an etching mask for forming the dummy gate structure 130 , and is also used to protect the top of the dummy gate structure 130 .

[0113] It should also be noted that the gate mask structure 136 includes a first gate mask layer 137 covering the top of the dummy gate structure 130 , a second gate mask layer 138 covering the first gate mask layer 137 , and a third gate mask layer 139 covering the second gate mask layer 138 .

[0114] As an example, the material of the first gate mask layer 137 is silicon oxide, the material of the second gate mask layer 138 is silicon nitride, and the material of the third gate mask layer 139 is silicon oxide, that is, the gate mask structure 136 is an (Oxide-Nitride-Oxide) structure.

[0115] refer to Figure 33 In this embodiment, after forming the dummy gate structure 130 and before forming the source / drain doping layer, the process further includes: removing the dummy gate dielectric layer 131 exposed by the dummy gate structure 130 .

[0116] After forming the dummy gate structure 130 and before forming the source / drain doped layers, the dummy gate dielectric layer 131 exposed by the dummy gate structure 130 is removed to expose the ends of the channel layer 114 , thereby facilitating the subsequent formation of source / drain doped layers connected to both ends of the channel layer 114 .

[0117] refer to Figure 34 , a source-drain doped layer 140 connected to both ends of the channel layer 114 is formed on the substrate 100 on both sides of the dummy gate structure 130 .

[0118] When the device is working, the source-drain doped layer 140 is used as a source or a drain to provide a carrier source.

[0119] refer to Figure 35 In this embodiment, after forming the source-drain doped layer 140 and before forming the gate groove, it also includes: forming a gate sidewall 150 on the sidewall of the dummy gate structure 130, and the gate sidewall 150 is also located on the top of the source-drain doped layer 140.

[0120] The gate sidewall 150 is used to protect the sidewalls of the dummy gate structure 130 and the sidewalls of the subsequently formed gate structure; and the gate sidewall 150 located on top of the source-drain doped layer 140 can also be used as an etching stop position in the subsequent process of forming the source-drain interconnection layer (i.e., M0).

[0121] Correspondingly, the gate spacer 150 also covers the top and sidewalls of the gate mask structure 136 .

[0122] Specifically, the gate sidewall 150 can be a single-layer structure or a stacked structure, and the material of the sidewall 125 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbon nitride oxide, silicon nitride oxide, boron nitride, boron carbon nitride and low-K dielectric material (low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9).

[0123] In this embodiment, the gate spacer 150 includes a first spacer 151 located on the sidewall of the dummy gate structure 130 , and a second spacer 152 located on the first spacer 151 .

[0124] As an example, the material of the first sidewall spacer 151 is a low-K dielectric material, and the material of the second sidewall spacer 152 is silicon nitride.

[0125] refer to Figure 36 In this embodiment, after the source-drain doped layer 140 is formed and before the gate groove is formed, it also includes: forming an interlayer dielectric layer 160 on the shallow trench isolation structure 121 on the side of the dummy gate structure 130, and the interlayer dielectric layer 160 covers the source-drain doped layer 140 and the sidewall of the dummy gate structure 130.

[0126] The interlayer dielectric layer 160 is used to achieve electrical isolation between adjacent semiconductor devices.

[0127] Correspondingly, the interlayer dielectric layer 160 is also located on the gate spacer 150 .

[0128] Specifically, the material of the interlayer dielectric layer 160 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other suitable dielectric materials.

[0129] Continue to refer Figure 36 In this embodiment, after forming the interlayer dielectric layer 160 , the process further includes: removing the gate mask structure 136 to expose the top of the dummy gate structure 130 .

[0130] The gate mask structure 136 is removed to expose the top of the dummy gate structure 130 , so as to facilitate the subsequent removal of the dummy gate structure 130 from the top of the dummy gate structure 130 .

[0131] Specifically, after the interlayer dielectric layer 160 is formed, the gate mask structure 136 is removed. In the process of removing the gate mask structure 136 , a portion of the thickness of the interlayer dielectric layer 160 is also removed.

[0132] refer to Figure 37 , the dummy gate structure 130 is removed to form a gate groove 175 exposing the sacrificial layer 113 .

[0133] The gate groove 175 is used to provide a space for the subsequent formation of a gate structure.

[0134] refer to Figures 38 to 42In this embodiment, after forming the gate groove 175 and before forming the through groove, the method further includes: removing the first portion of the thickness of the substrate 100 at the bottom of the channel structure layer 110 to form a bottom trench 185 (such as Figure 38 As shown); forming a bottom isolation structure 180 in the bottom trench 185 (as shown Figure 42 shown).

[0135] The bottom isolation structure 180 is used to isolate the channel structure layer 110 from the substrate 100 , thereby facilitating reduction of leakage current and further improving the performance of the semiconductor structure.

[0136] In this embodiment, a radical surface treatment process is used to remove a first portion of the thickness of the substrate 100 at the bottom of the channel stack 111 .

[0137] The free radical etching process can achieve a high etching selectivity, and there is no plasma during the free radical etching process, which is beneficial for reducing the probability of damage to other film layers (such as the dummy gate dielectric layer 131 and the gate spacer 150) during the formation of the bottom trench 185. In other embodiments, a vapor phase etching process can also be used to remove the first portion of the thickness of the substrate at the bottom of the channel structure layer to form the bottom trench.

[0138] Specifically, the process parameters of the free radical etching process include: the reaction gases include NF3 and H2, the flow rate range of NF3 is 3 standard ml / min to 100 standard ml / min, the flow rate range of H2 is less than or equal to 500 standard ml / min, the reaction temperature is 0 degrees Celsius to 100 degrees Celsius, and the pressure range of the reaction chamber is 50 mTorr to 3000 mTorr.

[0139] By setting the process parameters of the free radical etching process within the above range, it is beneficial to ensure the etching rate while further improving the etching selectivity between the substrate 100 and other film layers, thereby further reducing the probability of other film layers being damaged.

[0140] It should be noted that, during the step of forming the bottom trench 185, the depth H of the bottom trench 185 along the normal direction of the top surface of the substrate 100 should not be too small or too large. If the depth H of the bottom trench 185 is too small, the bottom isolation structure 180 may not be able to effectively isolate the channel structure layer 110 from the substrate 100. If the depth H of the bottom trench 185 is too large, it may increase the difficulty of forming the bottom trench 185. Therefore, in this embodiment, during the step of forming the bottom trench 185, the depth H of the bottom trench 185 along the normal direction of the top surface of the substrate 100 ranges from 2 nanometers to 20 nanometers.

[0141] In this embodiment, a shallow trench isolation structure 121 is formed on the substrate 100. Therefore, the step of forming the bottom trench 185 includes: removing the second portion of the thickness of the shallow trench isolation structure 121 at the bottom of the gate groove 175 to expose part of the side wall of the substrate 100; and removing the first portion of the thickness of the substrate 100 at the bottom of the channel structure layer 110 through the exposed side wall of the substrate 100.

[0142] In this embodiment, the steps of forming the bottom isolation structure 180 in the bottom trench 185 include: Figure 39 As shown, a bottom isolation material layer 181 is formed in the bottom trench 185. The bottom isolation material layer 181 is also formed on the inner wall of the gate groove 175 and above the source and drain doping layer 140 outside the gate groove 175. Figure 40 As shown, the bottom isolation material layer 181 on the inner wall of the gate groove 175 and above the source / drain doped layer 140 outside the gate groove 175 is removed, and the remaining bottom isolation material layer 181 serves as the bottom isolation structure 180 .

[0143] In this embodiment, the process of forming the bottom isolation material layer 181 includes an atomic layer deposition process.

[0144] The atomic layer deposition process includes multiple atomic layer deposition cycles, so that the atomic layer deposition process has good gap filling performance and step coverage, which is beneficial for the bottom isolation material layer 181 to be better filled into the bottom groove 185, and is beneficial for reducing the probability of defects such as voids forming in the bottom isolation material layer 181.

[0145] In this embodiment, the process of removing the bottom isolation material layer 181 on the inner wall of the gate groove 175 and above the source / drain doped layer 140 outside the gate groove 175 includes an isotropic etching process.

[0146] The isotropic etching process has the characteristic of isotropic etching, that is, the etching rate along the direction parallel to the top surface of the substrate 100 is slightly different from the etching rate in the normal direction of the top surface of the substrate 100, thereby facilitating the removal of the bottom isolation material layer 181 located on the inner wall of the gate groove 175 and above the source and drain doped layer 140 located outside the gate groove 175.

[0147] Correspondingly, such as Figure 41 As shown, in this embodiment, after the bottom isolation structure 180 is formed, the remaining dummy gate dielectric layer 131 is removed to expose the sacrificial layer 113 .

[0148] The sacrificial layer 113 is exposed to prepare for subsequent removal of the sacrificial layer 113 .

[0149] In this embodiment, in the step of forming the channel stack 111, the inner sidewall group 115 is in the shape of a "U" (that is, the inner sidewall 112 corresponding to the inner sidewall group 115 is in the shape of a "U"), and surrounds and covers the sidewalls of the sacrificial layer 113; accordingly, in the step of forming the gate groove 175, the gate groove 175 exposes the inner sidewall 112 on part of the sidewall of the sacrificial layer 113; after forming the gate groove 175 and before forming the through groove, it also includes: removing the exposed inner sidewall 112 to expose the sacrificial layer 113.

[0150] The exposed inner sidewall 112 is removed to expose the sacrificial layer 113 , which facilitates the subsequent removal of the sacrificial layer 113 to form a through groove.

[0151] Specifically, an isotropic etching process is used to remove the exposed inner sidewall 112. The isotropic etching process includes a free radical etching process. The process parameters of the free radical etching include: the reaction gases include NF3 and H2, the flow rate range of NF3 is 3 standard ml / min to 200 standard ml / min, the flow rate range of H2 is 300 standard ml / min to 1000 standard ml / min, the reaction temperature is 0 degrees Celsius to 100 degrees Celsius, the pressure range of the reaction chamber is 1000 mTorr to 5000 mTorr, and the process time is 10 seconds to 120 seconds.

[0152] The free radical etching process can achieve a high etching selectivity, and there is no plasma during the free radical etching process, which is beneficial for reducing the probability of damage to other film layers (e.g., sacrificial layer 113, channel layer 114) during the removal of the exposed inner sidewall 112. In other embodiments, other suitable isotropic etching processes may also be used.

[0153] By setting the process parameters of the free radical etching process within the above range, it is beneficial to ensure the etching rate while further improving the etching selectivity between the inner sidewall 112 and other film layers, thereby further reducing the probability of other film layers being damaged.

[0154] refer to Figure 42 , removing the exposed sacrificial layer 113 to form a through groove 176 that penetrates the gate groove 175 .

[0155] The through-slot 176 is used to provide a space for the subsequent formation of a gate structure.

[0156] refer to Figure 43 After forming the through-groove 176 and before forming the gate structure, the method further includes forming an interfacial layer (IL) 190 on the inner wall of the gate groove 175 and the inner wall of the through-groove 176 .

[0157] The interface layer 190 is used to ensure good interface performance between the substrate 100 and a subsequently formed gate dielectric layer, thereby improving the formation quality of the gate dielectric layer.

[0158] As an example, the material of the interface layer 190 is silicon oxide.

[0159] refer to Figure 44 , a gate structure 170 is formed in the gate groove 175 and the through-groove 176 .

[0160] In this embodiment, the gate structure 170 is a device gate structure, which is used to form a field effect transistor together with the channel structure layer 110 and the source-drain doped layer 140 .

[0161] The gate structure 170 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) covering the gate dielectric layer.

[0162] The gate dielectric layer is used to isolate the gate electrode layer from the channel structure layer 110 .

[0163] The material of the gate dielectric layer includes one or more dielectric materials such as hafnium dioxide (HfO2), zirconium dioxide (ZrO2), hafnium oxide silicate (HfSiO), hafnium silicate nitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), aluminum oxide (Al2O3), silicon oxide (SiO2) and lanthanum oxide (La2O3).

[0164] In this embodiment, the gate structure 170 is a metal gate structure. Therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. The gate electrode layer includes a work function layer and an electrode layer covering the work function layer, or may include only the work function layer.

[0165] Accordingly, the gate dielectric layer includes a high-k gate dielectric layer. The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3. As an example, the material of the high-k gate dielectric layer is HfO2.

[0166] In this embodiment, the gate structure 170 surrounds and covers the channel layer 114, and the gate structure 170 located between the channel layers 114 and between the channel layer 114 and the substrate 100 serves as an inner gate structure 172 (eg, Figure 44 shown)

[0167] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include providing a substrate; forming a channel structure layer on the substrate, the channel structure layer comprising one or more channel stacks stacked in sequence along the longitudinal direction, each channel stack comprising oppositely disposed inner sidewalls, a sacrificial layer located between the oppositely disposed inner sidewalls, and a channel layer located on the inner sidewalls and the sacrificial layer; forming a dummy gate structure on the substrate, the dummy gate structure spanning the channel structure layer, wherein the dummy gate structure covers the top and sidewalls of the channel structure layer along its extension direction; forming a source-drain doped layer connected to both ends of the channel layer on the substrate at both sides of the dummy gate structure; removing the dummy gate structure to form a gate groove exposing the sacrificial layer; removing the exposed sacrificial layer to form a through groove interpenetrating with the gate groove; A gate structure is formed in the gate groove and the through-groove.

2. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the channel stack includes: performing one or more stacking operations, wherein the stacking operations include: forming an inner wall group, wherein the inner wall group includes inner walls arranged opposite to each other; forming a sacrificial layer between adjacent inner side walls corresponding to the inner side wall group; forming a channel layer on the inner sidewall group and the sacrificial layer; In the first stacking operation, the inner sidewall group is formed on the substrate, and in the remaining stacking operations, the inner sidewall group is formed on the topmost trench stack.

3. The method for forming a semiconductor structure according to claim 2, wherein: The step of forming the sacrificial layer includes: Filling an initial sacrificial layer on the substrate at the side of the inner sidewall, wherein the initial sacrificial layer exposes the top of the inner sidewall; The initial sacrificial layer in the outer area of ​​the inner sidewall group is removed, and the initial sacrificial layer between adjacent inner sidewalls corresponding to the inner sidewall group is retained as the sacrificial layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: After forming the initial sacrificial layer and before forming the sacrificial layer, the method further comprises: forming a first mask layer on the inner sidewall group and on the initial sacrificial layer between adjacent inner sidewalls corresponding to the inner sidewall group; Using the first mask layer as a mask, removing the initial sacrificial layer in the outer area of ​​the inner sidewall group; After forming the sacrificial layer, the method further includes: removing the first mask layer.

5. The method for forming a semiconductor structure according to claim 3, wherein: The step of forming the initial sacrificial layer comprises: Filling a sacrificial material layer on the substrate at the side of the inner sidewall, wherein the sacrificial material layer covers the inner sidewall; The sacrificial material layer is planarized, and the sacrificial material layer on the top of the inner sidewall is removed to expose the top of the inner sidewall, and the remaining sacrificial material layer serves as an initial sacrificial layer.

6. The method for forming a semiconductor structure according to claim 5, wherein: After forming the sacrificial material layer and before performing a planarization process on the sacrificial material layer, the method further includes: forming a second sacrificial layer on the sacrificial layer material layer; During the planarization process, the second sacrificial layer is removed.

7. The method for forming a semiconductor structure according to claim 2, wherein: The step of forming the channel layer includes: forming an initial channel layer on the substrate, covering the inner wall spacer set and the sacrificial layer; The initial channel layer in the outer area of ​​the inner wall spacer group is removed, and the initial channel layer on the inner wall spacer group and the top of the sacrificial layer is retained as the channel layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: After forming the initial channel layer and before removing the initial channel layer in the outer area of ​​the inner sidewall group, the method further comprises: forming a patterned second mask layer on the initial channel layer; Using the second mask layer as a mask, removing the initial channel layer in the outer area of ​​the inner sidewall group; After forming the channel layer, the method further includes: removing the second mask layer.

9. The method for forming a semiconductor structure according to claim 1, wherein: The steps of forming the channel stack include: Performing one or more stacking operations to form one or more initial channel stacks stacked in sequence along the longitudinal direction on the substrate, the stacking operation comprising: forming an inner sidewall group, the inner sidewall group comprising oppositely disposed inner sidewalls; filling a sacrificial layer on the side of the inner sidewall, the sacrificial layer exposing the top of the inner sidewall; and forming a channel layer on the inner sidewall and the sacrificial layer; wherein, in the first stacking operation, the inner sidewall group is formed on the substrate, and in the remaining stacking operations, the inner sidewall group is formed on the topmost initial channel stack that has been formed; After the last stacking operation is completed, the initial trench stack in the area outside the inner sidewall spacer group is removed, and the remaining initial trench stack serves as the trench stack.

10. The method for forming a semiconductor structure according to claim 2 or 9, wherein: The steps of forming the inner wall group include: forming a fully covered inner wall material layer; forming a patterned third mask layer on the inner sidewall material layer; The inner sidewall material layer is patterned using the third mask layer as a mask to form the inner sidewalls, and the adjacent and opposite inner sidewalls are formed as an inner sidewall group.

11. The method for forming a semiconductor structure according to claim 1, wherein: After forming the gate groove and before forming the through groove, the method further includes: removing a first portion of the thickness of the substrate at the bottom of the channel structure layer to form a bottom trench; and forming a bottom isolation structure in the bottom trench.

12. The method for forming a semiconductor structure according to claim 11, wherein: After forming the channel structure layer and before forming the dummy gate structure, the method further comprises: forming a dummy gate dielectric layer on the top and sidewalls of the channel structure layer; After forming the dummy gate structure and before forming the source / drain doping layer, the method further includes: removing the dummy gate dielectric layer exposed by the dummy gate structure; After forming the bottom isolation structure, the remaining dummy gate dielectric layer is removed to expose the sacrificial layer.

13. The method for forming a semiconductor structure according to claim 11, wherein: In the step of forming the bottom trench, the depth of the bottom trench is in a range of 2 nanometers to 20 nanometers along a normal direction of the top surface of the substrate.

14. The method for forming a semiconductor structure according to claim 11, wherein: After forming the channel structure layer and before forming the dummy gate structure, the method further includes: forming a shallow trench isolation structure in the substrate at a side of the channel structure layer, wherein the shallow trench isolation structure exposes the channel structure layer; The step of forming the bottom trench includes: removing the second portion of the thickness of the trench isolation structure at the bottom of the gate groove to expose part of the sidewall of the substrate; and removing the first portion of the thickness of the substrate at the bottom of the channel structure layer through the sidewall exposed by the substrate.

15. The method for forming a semiconductor structure according to claim 11, wherein: A free radical etching process is used to remove a first portion of the thickness of the substrate at the bottom of the channel stack.

16. The method for forming a semiconductor structure according to claim 15, wherein: The process parameters of the free radical etching process include: the reaction gases include NF3 and H2, the flow rate range of NF3 is 3 standard ml / min to 100 standard ml / min, the flow rate range of H2 is less than or equal to 500 standard ml / min, the reaction temperature is 0 degrees Celsius to 100 degrees Celsius, and the pressure range of the reaction chamber is 50 mTorr to 3000 mTorr.

17. The method for forming a semiconductor structure according to claim 11, wherein: The step of forming a bottom isolation structure in the bottom trench comprises: forming a bottom isolation material layer in the bottom trench, wherein the bottom isolation material layer is also formed on the inner wall of the gate groove and above the source and drain doping layer outside the gate groove; The bottom isolation material layer on the inner wall of the gate groove and above the source / drain doped layer outside the gate groove is removed, and the remaining bottom isolation material layer serves as a bottom isolation structure.

18. The method for forming a semiconductor structure according to claim 17, wherein: The process of forming the bottom isolation material layer includes an atomic layer deposition process; The process of removing the bottom isolation material layer on the inner wall of the gate groove and above the source / drain doping layer outside the gate groove includes an isotropic etching process.

19. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming the trench stack, the inner sidewalls are arranged in a U-shape and surround and cover the sidewalls of the sacrificial layer; In the step of forming the gate groove, the gate groove exposes the inner sidewall of a portion of the sidewall of the sacrificial layer; After forming the gate groove and before forming the through groove, the method further includes: removing the exposed inner sidewall to expose the sacrificial layer.

20. The method for forming a semiconductor structure according to claim 19, wherein: An isotropic etching process is used to remove the exposed inner sidewall, and the isotropic etching process includes a free radical etching process. The process parameters of the free radical etching process include: the reaction gases include NF3 and H2, the flow rate range of NF3 is 3 standard ml / min to 200 standard ml / min, the flow rate range of H2 is 300 standard ml / min to 1000 standard ml / min, the reaction temperature is 0 degrees Celsius to 100 degrees Celsius, the pressure range of the reaction chamber is 1000 mTorr to 5000 mTorr, and the process time is 10 seconds to 120 seconds.

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