Semiconductor structure and forming method thereof
By trimming the fins in the gate region to form a metal gate structure in the semiconductor fin field-effect transistor process, the problem of low transistor yield in the fin field-effect transistor process is solved, and the performance and yield of the transistor are improved.
Patent Information
- Application Number
- CN202410438384.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-11
- Publication Date
- 2025-10-21
AI Technical Summary
In the current process of manufacturing semiconductor fin field-effect transistors, the yield of semiconductor transistors is relatively low, mainly because the narrow width of the fins makes them easy to be damaged during the process, resulting in a decrease in performance.
After the source/drain doped layers are formed, the dummy gate is removed, and the fins located in the gate region are trimmed to reduce the fin width. A metal gate structure is then formed on the fins with reduced width. The fins are not trimmed during the formation of the source/drain doped layers and the removal of the dummy gate, so they are kept with a larger width to avoid damage.
It improved the yield of semiconductor transistors, optimized performance, reduced process difficulty, and enhanced drive current.
Smart Images
Figure CN120825973A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] As semiconductor transistors develop towards higher component density and higher integration, semiconductor fin field-effect transistor (Fin FET) technology has also undergone corresponding iterations, mainly reflected in: reducing the metal pitch, polysilicon pitch and diffusion partition size, while narrowing the width of the semiconductor fin.
[0003] To ensure that the on-state current of semiconductor transistors meets requirements, product design often involves increasing the height of the semiconductor fins to compensate for the on-state current loss caused by the narrowing of the semiconductor fin width. However, this design can easily lead to a reduction in the yield of semiconductor transistors during actual manufacturing processes. Summary of the Invention
[0004] The technical problem solved by the present invention is to improve the yield of semiconductor transistors in the process of manufacturing by providing a semiconductor structure and a forming method thereof.
[0005] In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a plurality of fins on the substrate; forming a dummy gate spanning the plurality of fins, and the area of the substrate where the dummy gate is formed is a gate region; forming a source-drain doping layer on the fin exposed by the dummy gate; removing the dummy gate to expose the fin located in the gate region; performing a trimming process on the fin located in the gate region to reduce the width of the fin; and forming a metal gate structure on the fin after the trimming process.
[0006] Optionally, the trimming process is dry etching.
[0007] Optionally, the reaction gas used in the dry etching includes one or more of fluorine gas, hydrogen fluoride, hydrogen trifluoride, fluorine radicals and nitrogen trifluoride radicals.
[0008] Optionally, a ratio of the reduction in the width of the fin to the initial width of the fin is within a range of greater than or equal to 5% and less than 40%.
[0009] Optionally, in the step of forming a plurality of fins on the substrate, the width of the fins is within a range of greater than or equal to 8 nanometers and less than or equal to 20 nanometers.
[0010] Optionally, the width of the fin after the trimming process is greater than 5 nanometers and less than or equal to 12 nanometers.
[0011] Optionally, a source-drain doping layer is formed on the fin exposed by the dummy gate through an epitaxial process.
[0012] Optionally, the formation method further includes forming an isolation layer between the multiple fins after forming the multiple fins and before forming the dummy gate, wherein the surface of the isolation layer is lower than the top of the fin; the dummy gate and the source-drain doping layer are formed on the fins exposed by the isolation layer.
[0013] Optionally, the step of forming the isolation layer includes: forming an isolation material layer that fills between the fins and covers the fins; and removing a portion of the isolation material layer to expose the fins, thereby forming the isolation layer.
[0014] Optionally, the formation method further includes: forming an interlayer dielectric layer covering the source / drain doping layer and the dummy gate before removing the dummy gate after forming the source / drain doping layer; and before removing the dummy gate, further including removing the interlayer dielectric layer above the dummy gate to expose the dummy gate to be removed.
[0015] Optionally, the formation method further comprises forming a spacer layer located on a sidewall of the dummy gate after forming the dummy gate spanning the plurality of fins and before forming the source / drain doping layer.
[0016] Correspondingly, the present invention also provides a semiconductor structure, comprising: a substrate; a plurality of fins located on the substrate; a metal gate structure spanning the fins; a source-drain doping layer located on the fins on both sides of the metal gate structure; the width of the fin below the metal gate structure is smaller than the width of the fin below the source-drain doping layer.
[0017] Optionally, the source-drain doped layer is an epitaxial layer.
[0018] Optionally, the width of the fin below the metal gate structure is within a range greater than 5 nanometers and less than or equal to 12 nanometers.
[0019] Optionally, the width of the fin below the source / drain doping layer is within a range of greater than or equal to 8 nanometers and less than or equal to 20 nanometers.
[0020] Optionally, the method further includes: an isolation layer located on the substrate and filled between the fins, wherein the surface of the isolation layer is lower than the top of the fin, and the metal gate structure and the source-drain doping layer are formed above the isolation layer.
[0021] Optionally, it further includes: an interlayer dielectric layer covering the source / drain doped layer.
[0022] Optionally, a sidewall layer covering the sidewalls of the metal gate structure is also included.
[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0024] The method for forming a semiconductor structure provided by an embodiment of the present invention removes the dummy gate after forming the source-drain doping layer, performs a trimming process on the fin located in the gate area to reduce the width of the fin, and then forms a metal gate structure on the fin with a reduced width. In this way, a metal gate structure is formed on the fin with a reduced width, and the fin located below the metal gate structure has a smaller width, which can increase the driving current and thus optimize the performance of the semiconductor structure. In the process of forming the source-drain doping layer and removing the dummy gate, the fin has not yet been trimmed, and the fin is still in a relatively wide state, so it is not easily damaged during the process, thereby reducing the process difficulty and improving the yield of the semiconductor transistor. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.
[0026] Figures 1 to 5 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;
[0027] Figures 6 to 11 1 is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention;
[0028] Figure 12 FIG. 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION
[0029] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.
[0030] As described in the background art, the design of the existing semiconductor fin field effect transistor has the problem of low yield rate of semiconductor transistors during the manufacturing process. Figures 1 to 5 ( Figure 1 b is along Figure 1 a is a cross-sectional view taken along the dotted line a1-a2; Figure 2 b is along Figure 2 a sectional view taken along the dotted line b1-b2; Figure 3 b is along Figure 3 a sectional view taken along the dashed line c1-c2; Figure 4 b is along Figure 4 a is a cross-sectional view taken along the dotted line d1-d2; Figure 5 b and Figure 5 c are respectively along Figure 5 The semiconductor structure formation method shown in FIG. 1 (a) is used to analyze the reasons why the manufacturing process causes low yield of semiconductor transistors. The semiconductor structure formation method mainly includes the following steps:
[0031] like Figure 1 As shown, a substrate 100 is provided, and a plurality of semiconductor fins 101 with a width w0 are formed on the substrate 100 .
[0032] like Figure 2 As shown, an isolation material is formed covering the semiconductor fin 101, and a portion of the isolation material is removed, so that the semiconductor fin 101 protrudes from the remaining isolation material, forming an isolation material layer 102. The protruding semiconductor fin 103 is trimmed to reduce its width from w0 to w1.
[0033] like Figure 3 As shown, a sacrificial gate 104 is formed across the semiconductor fin 101 ; the area surrounded by the sacrificial gate 104 is the gate region.
[0034] like Figure 4 As shown, a sidewall 105 and a source-drain doped layer 106 are formed on the semiconductor fin 101 exposed by the sacrificial gate 104;
[0035] like Figure 5 As shown, an insulating dielectric layer 107 is formed to cover the source and drain doped layer 106 ; the sacrificial gate 104 is removed, and a gate layer 108 is formed in the gate region.
[0036] like Figure 5 b and Figure 5 As shown in c, the semiconductor fin located under the source and drain doped layer 106 and the semiconductor fin located under the sacrificial gate 104 are manufactured in the same process step. After the semiconductor fin under the sacrificial gate 104 is narrowed, the width of the semiconductor fin under the source and drain doped layer 106 is reduced to w1. The semiconductor fin with reduced width is easily damaged during the process, thereby reducing the yield of the semiconductor transistor.
[0037] To solve the technical problem, an embodiment of the present invention provides a semiconductor structure and a method for forming the same. The method comprises: providing a substrate, forming a plurality of fins on the substrate; forming a dummy gate across the plurality of fins, wherein the region of the substrate where the dummy gate is formed is a gate region; forming a source / drain doping layer on the fin exposed by the dummy gate; removing the dummy gate to expose the fin in the gate region; performing a trimming process on the fin in the gate region to reduce the width of the fin; the width of the fin under the source / drain doping layer is greater than the width of the fin under the metal gate structure; and forming a metal gate structure on the trimmed fin. In the present invention, after forming the source / drain doping layer, the dummy gate is removed, the fin in the gate region is trimmed to reduce the width of the fin, and then a metal gate structure is formed on the fin with the reduced width. In this way, the metal gate structure is formed on the fin with the reduced width, and the fin below the metal gate structure has a smaller width, which can improve the drive current and thus optimize the performance of the semiconductor structure. During the process of forming the source / drain doping layer and removing the dummy gate, the fin has not yet been trimmed, and thus the fin is still in a relatively wide state and is not easily damaged during the process, thereby reducing the process difficulty and improving the yield of the semiconductor transistor.
[0038] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0039] refer to Figures 6 to 11 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention.
[0040] It should be noted that Figure 6 b is along Figure 6 a is a cross-sectional view taken along the dotted line A1-A2; Figure 7 b is along Figure 7 a is a cross-sectional view taken along the dotted line B1-B2; Figure 8 b is along Figure 8 a is a cross-sectional view taken along the dashed line C1-C2; Figure 9 b and Figure 9 c are respectively along Figure 9 a is a cross-sectional view taken along the dotted line D1-D2 and the line E1-E2; Figure 10 b and Figure 10 c are respectively along Figure 10 a is a cross-sectional view taken along the dashed line F1-F2 and the line G1-G2; Figure 11 b and Figure 11 c are respectively along Figure 11 a is a cross-sectional view taken along the dotted line H1-H2 and the line I1-I2.
[0041] refer to Figure 6, providing a substrate 200, and forming a plurality of fins 201 on the substrate, wherein the plurality of fins 201 are mainly used to form a channel region of a semiconductor transistor.
[0042] In this embodiment, the substrate 200 is used to provide a process platform for forming a semiconductor structure. The substrate 200 is a silicon substrate, and the material of the substrate 200 is single crystal silicon. In other embodiments, the material of the substrate 200 can also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium. The substrate 200 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. In other embodiments, an epitaxial layer (not shown) having the same crystal structure as the substrate 200 is formed on the surface of the substrate 200 to improve the quality of pattern transfer.
[0043] In this embodiment, the fin 201 and the substrate 200 are integrated. The material of the fin 201 is the same as that of the substrate 200, that is, silicon. In other embodiments, the material of the fin 201 can be different from that of the substrate 200, for example, one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.
[0044] In this embodiment, the width of the fin 201 is denoted by k0. The specific process for forming the plurality of fins 201 on the substrate 200 includes: forming a hard mask (not shown) on the surface of the substrate 200 for patterning the substrate 200. The hard mask includes a first mask layer (not shown), a second mask layer (not shown), and a third mask layer (not shown) sequentially located on the substrate 200; coating a layer of photoresist (not shown) on the surface of the third mask layer; patterning the photoresist through exposure and development; transferring the photoresist pattern to the hard mask; then transferring the hard mask pattern to the substrate 200; and etching a portion of the substrate 200 through a dry or wet etching process to form the plurality of fins 201. In this embodiment, the hard mask layer is removed after forming the plurality of fins 201. In other embodiments, the hard mask layer is removed after subsequently forming an isolation layer. For ease of description, all embodiments of the present invention are described using two fins as an example.
[0045] It should be noted that hard masks are less affected by semiconductor processing and are more suitable for narrow linewidth and linespace processes. For example, after high-temperature processing, the hard mask pattern formed is less susceptible to deformation and has a high degree of refinement. Therefore, the use of a hard mask can ensure the quality of pattern transfer. In other embodiments, patterning without a hard mask is also possible.
[0046] It should also be noted that if the width of the fin 201 is too large, it is not conducive to the high-density and high-integration design of the semiconductor transistor. If the width of the fin 201 is too small, the fin is easily damaged during the process, and the manufacturing process is more difficult. In this embodiment, the width of the fin 201 is within the range of greater than or equal to 8 nanometers and less than or equal to 20 nanometers.
[0047] refer to Figure 7 , forming a dummy gate 202 across the plurality of fins 201. The area of the substrate 200 where the dummy gate 202 is formed is a gate region 203. The dummy gate 202 is used to pre-occupy a spatial position for the subsequent formation of a metal gate structure, while also protecting the channel region of the semiconductor transistor at the metal gate structure.
[0048] In this embodiment, the material of the dummy gate 202 may be polysilicon or amorphous silicon.
[0049] Chemical vapor deposition (CVD) has advantages such as high speed, uniform film thickness, and good crystallinity. In this embodiment, a dummy gate film layer spanning multiple fins 201 can be formed on the surface of the substrate 200 by CVD. The dummy gate 202 is then formed by exposure, development, and etching processes on the dummy gate film layer.
[0050] Continue to refer Figure 7 After forming the plurality of fins 201 and before forming the dummy gate 202, the isolation layer 204 is formed between the plurality of fins 201. The isolation layer 204 is used to electrically isolate adjacent semiconductor transistors and prevent external impurities from entering the semiconductor structure through the bottom of the substrate 200 and causing semiconductor transistor failure.
[0051] In this embodiment, the isolation layer 204 is formed of silicon oxide, which has good chemical stability and strong isolation capability. In other embodiments, the isolation layer 204 may be formed of other insulating materials, such as silicon nitride, silicon oxynitride, etc.
[0052] In this embodiment, an isolation material layer is formed by chemical vapor deposition to fill between the fins 201 and cover the fins 201, and a portion of the isolation material layer is removed by dry etching or wet etching to expose the fins, thereby forming an isolation layer 204. Figure 7 As shown in FIG. 2 b , the surface 205 of the isolation layer 204 is lower than the top 206 of the fin 201 , and the isolation layer 204 surrounds and covers the sidewall of the bottom portion of the fin 201 ; the dummy gate 202 is formed on the exposed fin 201 .
[0053] refer to Figure 8, forming a source-drain doping layer 207 on the fin exposed by the dummy gate 202, the source-drain doping layer 207 is used as the source or drain of the field effect transistor. The formed source-drain doping layer 207 is formed on the fin 208 on both sides of the dummy gate 202; Figure 8 As shown in FIG. 2 b , the width of the fins 208 on both sides of the dummy gate 202 is the initial width k0 , that is, the width is relatively large, which is conducive to the epitaxial growth of the source and drain doping layers 207 .
[0054] In this embodiment, forming the source / drain doped layer 207 includes forming an ion-doped stress well to provide stress to the semiconductor transistor channel, thereby improving carrier mobility. Specifically, when forming an N-type channel transistor, the source / drain doped layer 207 includes a stress well doped with N-type carriers to enhance electron carrier mobility, and the stress well material is Si or SiC. When forming a P-type channel transistor, the source / drain doped layer 207 includes a stress well doped with P-type carriers to enhance hole carrier mobility, and the stress well material is SiGe.
[0055] In this embodiment, a source-drain doped layer 207 can be formed on the fin 208 exposed by the dummy gate 202 and on the isolation layer 204 by an epitaxial process. The film layer grown by the epitaxial process has advantages such as uniform thickness, dense structure, and better adhesion to the substrate 200 and the fin 208.
[0056] Continue to refer Figure 8 After forming the dummy gate 202 spanning the plurality of fins 201 and before forming the source / drain doped layer 207, the formation method further includes forming a spacer layer 209 on the sidewalls of the dummy gate 202. The spacer layer 209 is used to support the dummy gate 202 and provide a process foundation for subsequent removal of the dummy gate 202 and formation of an opening for a metal gate structure, thereby facilitating the subsequent replacement of the dummy gate 202 with a metal gate structure. In addition, the spacer layer 209 can also reduce the probability of damaging the source / drain doped layer 207 during the removal of the dummy gate 202, thereby ensuring the performance of the semiconductor transistor.
[0057] In this embodiment, the material of the spacer layer 209 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbon nitride oxide, silicon oxynitride, boron nitride, and carbonitride. As an example, the material of the spacer layer 209 is silicon nitride.
[0058] In this embodiment, the step of forming the sidewall layer 209 includes: forming a sidewall layer material on the sidewall of the dummy gate 202, and forming the sidewall layer 209 by exposure, development and etching; in the actual process, the sidewall layer material is etched using a dry etching process or a wet etching process to form the sidewall layer 209.
[0059] refer to Figure 9, the dummy gate 202 is removed to expose the fin 210 located in the gate region 203 , and at the same time, the two sides P1 and P2 of the fin 210 are exposed.
[0060] Removing the dummy gate 202 provides space for forming a metal gate structure. In this embodiment, the dummy gate 202 is removed through an exposure, development, and etching process, exposing the fin 210 located in the gate region 203 while retaining the fin 201 in other areas. Specifically, the dummy gate 202 in the gate region 203 is etched away using a dry or wet etching process.
[0061] In this embodiment, after forming the source / drain doped layer 207 and before removing the dummy gate 202, the formation method further includes: forming an interlayer dielectric layer 211 covering the source / drain doped layer 207 and the dummy gate 202. The interlayer dielectric layer 211 is used to isolate adjacent semiconductor transistors and adjacent metal wiring layers, and can also be used to support the sidewalls 209 of the dummy gate 202 during the subsequent removal of the dummy gate 202.
[0062] In this embodiment, the material of the interlayer dielectric layer 211 is silicon oxide. The material of the interlayer dielectric layer 211 can also be other insulating materials, such as silicon nitride, polymer materials, boron- or phosphorus-doped silica glass, etc. It should be noted that a smaller dielectric constant of the interlayer dielectric layer 211 can reduce parasitic capacitance. For example, the dielectric constant is within the range of greater than 0 and less than or equal to 3.
[0063] Continue to refer Figure 9 The specific process of forming the interlayer dielectric layer 211 includes: depositing an interlayer dielectric layer film on the surface of the substrate 200, the interlayer dielectric layer film covering the source and drain doping layer 207 and the dummy gate 202, and forming the interlayer dielectric layer 211 through exposure, development and etching processes.
[0064] In actual processes, in order to improve the structural density of the interlayer dielectric layer and reduce manufacturing costs, the plasma process and the chemical vapor deposition process are usually combined in the deposition method of the interlayer dielectric layer, such as a plasma enhanced chemical vapor deposition process or a high-density plasma chemical vapor deposition process. The deposition method includes the following steps: placing the substrate 200 on an anti-static chuck in the deposition chamber; introducing the gas to be reacted into the deposition chamber, turning on the RF source, and heating the gas to be reacted with low RF power; ionizing the gas to be reacted with high RF power to form a plasma, and depositing the interlayer dielectric layer on the substrate 200. Then, using an exposure, development and etching process, before removing the dummy gate 202, the interlayer dielectric layer 211 above the dummy gate 202 is removed by a dry etching process or a wet etching process to expose the dummy gate 202 to be removed.
[0065] refer to Figure 10, a trimming process is performed on the fin 210 located in the gate region to reduce the width of the fin 210 and increase the on-state current of the semiconductor transistor.
[0066] Specifically, the trimming process is performed by dry etching, which can better control the direction and amount of trimming.
[0067] In this embodiment, the step of trimming the fin 210 located in the gate region to reduce the width of the fin 210 includes: forming a mask (not shown) on the surface of the substrate 200, the mask having a first gap (not shown), the first gap (not shown) exposing the two side portions P1 and P2 of the fin 210 located in the gate region on the substrate 200; dry etching the exposed P1 and P2 portions of the fin 210 in the gate region to reduce the width of the fin 210 to k1, and the trimmed fin 210 becomes as follows: Figure 10 Fin 212 in b.
[0068] It should be noted that in this embodiment, a hard mask is used as the mask because it is less affected by semiconductor processing and is more suitable for narrow-linewidth semiconductor transistor channel processes. For example, after high-temperature processing, the hard mask pattern formed is less susceptible to deformation and has a high degree of refinement, thereby ensuring the quality of pattern transfer. In actual processing, after the pattern transfer is completed, a dry etching process can be used to remove the exposed gate region P1 and P2 on both sides of the fin 210, and then the hard mask is removed.
[0069] In the actual process, the reaction gases used in the dry etching process of the fin 210 include: one or more of fluorine gas, hydrogen fluoride, hydrogen trifluoride, fluorine radicals and nitrogen trifluoride radicals; the reaction gases have the advantages of high etching efficiency, good lateral etching and stable pattern line width uniformity, which is beneficial to ensuring the performance of semiconductor transistors.
[0070] In this embodiment, the hard mask has a three-layer structure (not shown). Chemical vapor deposition or atomic layer deposition techniques can be used to form the fourth, fifth, and sixth mask layers. The fourth mask layer is made of silicon oxide, which has a dominant compressive stress. When in contact with the substrate, it causes the substrate to shrink. The fifth mask layer is made of silicon nitride, which has a dominant tensile stress and can balance the substrate shrinkage caused by the compressive stress of the fourth mask layer. The sixth mask layer is also made of silicon oxide, which has a dominant compressive stress. When in contact with the fifth mask layer, it can balance the substrate expansion caused by the tensile stress of the fifth mask layer.
[0071] It should be noted that in this embodiment, the semiconductor fin is thinned, and a high-precision dry etching process suitable for micro-machining is used to trim the fin 210 located in the gate area, because the dry etching process can better control the etching direction, form a pattern with good surface smoothness, and reduce the leakage current of the semiconductor transistor.
[0072] It should also be noted that, for the width k1 of the trimmed fin 212, if the width k1 of the trimmed fin 212 is too large, it is not conducive to improving the on-state current of the semiconductor transistor. If the width k1 of the trimmed fin 212 is too small, the fin 212 is easily damaged during the manufacturing process, which is not conducive to the epitaxial growth of the source and drain doping layers. In this embodiment, the ratio of the reduced width of the fin to the initial width k0 of the fin is within a range of greater than or equal to 5% and less than 40%, that is, the width of the fin after the trimming process is greater than 5 nanometers and less than or equal to 12 nanometers. Reference Figure 11 A metal gate structure 213 is formed on the fin 212 after the trimming process. The metal gate structure 213 is formed at the location of the removed dummy gate 202. The metal gate structure 213 is used to control the on and off of the semiconductor transistor.
[0073] In this embodiment, the step of forming the metal gate structure 213 includes forming a gate dielectric layer (not shown) covering the fins 212 and a gate electrode layer (not shown) covering the gate dielectric layer. The gate dielectric layer is used to electrically isolate the gate electrode layer from the fins 212. The gate electrode layer is used to electrically connect the metal gate structure 213 to an external circuit.
[0074] In this embodiment, the material of the gate electrode layer includes one or more of titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide.
[0075] In this embodiment, the formation of the metal gate structure 213 further includes forming a work function layer (not shown). The work function layer is used to adjust the threshold voltage of the semiconductor transistor. For example, when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of titanium aluminide and aluminum titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride, and titanium silicon nitride.
[0076] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from zirconium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, or aluminum oxide. In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may only include the gate oxide layer.
[0077] In summary, in the semiconductor structure formation method provided by the embodiment of the present invention, a plurality of fins are formed on a substrate; a dummy gate is formed across the plurality of fins, and the region of the substrate where the dummy gate is formed is the gate region; a source-drain doping layer is formed on the fin exposed by the dummy gate; the dummy gate is removed to expose the fin located in the gate region; the fin located in the gate region is trimmed to reduce the width of the fin; the width of the fin under the source-drain doping layer is greater than the width of the fin under the metal gate structure; and a metal gate structure is formed on the fin after the trimming process. In the present invention, the dummy gate is removed after forming the source-drain doping layer, and the trimming process is only performed on the fin located in the gate region. During the process of forming the source-drain doping layer and removing the dummy gate, the fin has not yet been trimmed, so the fin is still in a relatively wide state and is not easily damaged during the process, thereby reducing the process difficulty and improving the yield of the semiconductor transistor.
[0078] In order to solve the technical problem, the present invention also provides a semiconductor structure accordingly. Figure 12 It is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.
[0079] The semiconductor structure of this embodiment includes: a substrate 200; a plurality of fins located on the substrate 200 spanning a metal gate structure 213 on the fins 212; a source-drain doped layer 207 located on the fins on both sides of the metal gate structure 213; and a width k1 of the fin 212 below the metal gate structure 213 that is less than a width k0 of the fin 208 below the source-drain doped layer 207.
[0080] In this embodiment, the substrate 200 is used to provide a process platform for forming a semiconductor structure. The substrate 200 is a silicon substrate, and the material of the substrate 200 is single crystal silicon. In other embodiments, the material of the substrate 200 can also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium. The substrate 200 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. In other embodiments, an epitaxial layer (not shown) having the same crystal structure as the substrate 200 is formed on the surface of the substrate 200 to improve the quality of pattern transfer.
[0081] In this embodiment, Figure 12As shown, the semiconductor structure further includes: an isolation layer 204 located on the substrate 200 and filled between the fins, the surface of the isolation layer 204 exposing the top 206 of the fin, that is, the surface 205 of the isolation layer 204 is lower than the top 206 of the fin; the isolation layer 204 surrounds and covers the sidewall of the bottom portion of the fin 212.
[0082] In this embodiment, the metal gate structure 213 spans the fin 212 and is located above the isolation layer 204. The metal gate structure 213 includes a gate dielectric layer (not shown) covering the fin 212 and a gate electrode layer (not shown) covering the gate dielectric layer. The gate electrode layer electrically connects the metal gate structure 213 to an external circuit. The metal gate structure 213 is used to control the on and off of the conductive channel during operation of the semiconductor transistor.
[0083] It should be noted that if the width of the fin 212 below the metal gate structure 213 is too wide, the parasitic capacitance between the gate electrode layer and the gate dielectric layer will increase, affecting the on-current of the semiconductor transistor. If the width of the fin 212 below the metal gate structure 213 is too narrow, the channel area of the semiconductor transistor will be small, also affecting the on-current of the semiconductor transistor. Accordingly, the width of the fin 212 below the metal gate structure 213 is within a range greater than 5 nanometers and less than or equal to 12 nanometers.
[0084] In this embodiment, the source / drain doped layer 207 is an epitaxial layer formed on the fins 208 on both sides of the metal gate structure 213 through an epitaxial process, and the source / drain doped layer 207 is located above the isolation layer 204 .
[0085] It should be noted that in this embodiment, the fin 208 below the source / drain doped layer 207 is wider than the fin 212 below the metal gate structure 213. If the width k0 is too wide, it will be detrimental to the high-density and high-integration design of the semiconductor transistor. If the width k0 of the fin 208 is too small, it will be easily damaged during processing, increasing the difficulty of the process. Accordingly, the width of the fin 208 below the source / drain doped layer 207 is within a range of greater than or equal to 8 nanometers and less than or equal to 20 nanometers.
[0086] In this embodiment, the semiconductor structure further includes: a sidewall layer (not shown) covering the sidewalls on both sides of the metal gate structure 213; the sidewall layer is located between the source and drain doping layer 207 and the metal gate structure 213; the sidewall layer is used to prevent the doping material from being injected into the channel when the source and drain doping layers are doped, resulting in the problem of the source and drain electrodes penetrating through the channel.
[0087] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 211 covering the source / drain doped layer 207. The interlayer dielectric layer 211 is used to isolate adjacent semiconductor transistors and adjacent metal wiring layers, thereby reducing parasitic capacitance and better protecting the source / drain doped layer 207.
[0088] In summary, the semiconductor structure of this embodiment includes multiple fins located on a substrate; a metal gate structure spanning the fins; source and drain doped layers located on both sides of the fins of the metal gate structure; and the width of the fins below the metal gate structure is smaller than the width of the fins below the source and drain doped layers. In this embodiment of the present invention, the fins below the metal gate structure are narrower, which can increase the drive current of the semiconductor device, thereby optimizing the performance of the semiconductor structure. The fins below the source and drain doped layers are wider, which facilitates the epitaxial growth of the source and drain doped layers and improves the yield of the semiconductor transistor.
[0089] It should be noted that the semiconductor structure of this embodiment can be formed using the formation method of the aforementioned embodiment or other formation methods. For a detailed description of the semiconductor structure of this embodiment, reference can be made to the corresponding description in the aforementioned embodiment, and this embodiment will not be repeated here.
[0090] Although the present invention has been disclosed above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the scope of protection of the technical solutions of the present invention.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of fins on the substrate; forming a dummy gate across the plurality of fins, wherein the area of the substrate where the dummy gate is formed is a gate region; forming a source-drain doping layer on the fin exposed by the dummy gate; removing the dummy gate to expose the fin located in the gate region; performing a trimming process on the fin located in the gate region to reduce the width of the fin; A metal gate structure is formed on the fin after the trimming process is completed.
2. The forming method according to claim 1, wherein: The trimming process is dry etching.
3. The forming method according to claim 2, wherein: The reaction gas used in the dry etching includes one or more of fluorine gas, hydrogen fluoride, hydrogen trifluoride, fluorine free radicals and nitrogen trifluoride free radicals.
4. The forming method according to claim 1, wherein: The ratio of the reduced width of the fin to the initial width of the fin is within a range of greater than or equal to 5% and less than 40%.
5. The forming method according to claim 1, wherein: In the step of forming a plurality of fins on the substrate, the width of the fins is within a range of greater than or equal to 8 nanometers and less than or equal to 20 nanometers.
6. The forming method according to claim 1, wherein: The width of the fin after the trimming process is within a range of greater than 5 nanometers and less than or equal to 12 nanometers.
7. The forming method according to claim 1, wherein: A source-drain doping layer is formed on the fin exposed by the dummy gate through an epitaxial process.
8. The forming method according to claim 1, wherein: The forming method further comprises forming an isolation layer between the plurality of fins after forming the plurality of fins and before forming the dummy gate, wherein the surface of the isolation layer is lower than the top of the fins; The dummy gate and the source-drain doping layer are formed on the fin exposed by the isolation layer.
9. The forming method according to claim 8, wherein: The step of forming the isolation layer includes: forming an isolation material layer that fills between the fins and covers the fins; The fin is exposed after a portion of the isolation material layer is removed to form an isolation layer.
10. The forming method according to claim 1, wherein: The formation method further comprises, after forming the source-drain doped layer and before removing the dummy gate, forming an interlayer dielectric layer covering the source-drain doped layer and the dummy gate; Before the step of removing the dummy gate, the step further includes removing the interlayer dielectric layer above the dummy gate to expose the dummy gate to be removed.
11. The forming method according to claim 1, wherein: The forming method further comprises forming a spacer layer located on a sidewall of the dummy gate after forming the dummy gate spanning the plurality of fins and before forming the source / drain doping layer.
12. A semiconductor structure, characterized in that include: substrate; a plurality of fins positioned on a substrate; a metal gate structure spanning the fin; Source and drain doping layers located on the fins on both sides of the metal gate structure; The width of the fin below the metal gate structure is smaller than the width of the fin below the source and drain doping layer.
13. The semiconductor structure according to claim 12, wherein: The source-drain doped layer is an epitaxial layer.
14. The semiconductor structure according to claim 12, wherein: The width of the fin below the metal gate structure is within a range greater than 5 nanometers and less than or equal to 12 nanometers.
15. The semiconductor structure according to claim 12, wherein: The width of the fin below the source / drain doping layer is within a range of greater than or equal to 8 nanometers and less than or equal to 20 nanometers.
16. The semiconductor structure according to claim 12, wherein: Also includes: An isolation layer is located on the substrate and filled between the fins, wherein a surface of the isolation layer is lower than the top of the fin, and the metal gate structure and the source-drain doping layer are formed above the isolation layer.
17. The semiconductor structure according to claim 12, wherein: Also includes: An interlayer dielectric layer covers the source-drain doped layer.
18. The semiconductor structure according to claim 12, wherein: The invention also includes a sidewall layer covering the sidewall of the metal gate structure.