Semiconductor structure and preparation method thereof

Abstract

The invention relates to the technical field of integrated circuits, in particular to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the steps of providing a substrate; an epitaxial material layer is formed on one side of the substrate, a first groove is formed in the epitaxial material layer, and a barrier layer is formed on the surface of the side wall of the first groove; based on the barrier layer, etching the epitaxial material layer at the bottom of the first groove to form a second groove communicated with the first groove, forming an epitaxial layer by the residual epitaxial material layer, and enabling the size of the first groove to be smaller than that of the second groove in the direction parallel to the substrate; removing the barrier layer; and sequentially forming a shielding gate structure and a control gate structure in the second groove and the first groove, wherein at least part of the control gate structure is located in the first groove. The size of the first groove is set to be smaller than that of the second groove, so that the first groove has a smaller size, and a mesa structure with a larger size can be formed in the epitaxial layer surrounding the first groove.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Power metal-oxide-semiconductor field-effect transistors (MOSFETs), due to their simple structure and excellent characteristics, have become an indispensable electronic device in modern industrial society. To improve device performance and adapt to diverse applications, research on power MOSFETs has evolved through structures such as lateral (LDMOS), vertical (VDMOS), and trench (UMOS). Based on their voltage resistance, they are now classified into three categories: high voltage, medium voltage, and low voltage. In the low voltage sector, the shielded-gate trench power MOSFET (SGTMOSFET) is currently one of the most competitive power MOSFET devices.

[0003] SGTMOSFET has good figure of merit (FOM), low specific on-resistance (Ron,sp) and low gate charge (Qg) and other characteristics. It is widely used in medium and low voltage high-performance DC / DC converters, low voltage system motor control, motor drive and other fields, which can effectively improve system efficiency and power density.

[0004] However, as the SGTMOSFET structure gradually becomes smaller, the discrete problem of threshold voltage has also emerged, which affects the performance of SGTMOSFET. Summary of the Invention

[0005] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to address the discrete problem of the SGTMOSFET threshold voltage in the prior art.

[0006] In order to achieve the above objectives, the present invention provides, in one aspect, a method for preparing a semiconductor structure, comprising: providing a substrate; forming an epitaxial material layer on one side of the substrate, wherein a first trench is provided in the epitaxial material layer, and a barrier layer is formed on the sidewall surface of the first trench; Based on the barrier layer, the epitaxial material layer at the bottom of the first trench is etched to form a second trench that is arranged to penetrate the first trench, and the remaining epitaxial material layer forms an epitaxial layer, and in a direction parallel to the substrate, the size of the first trench is smaller than the size of the second trench; removing the barrier layer; A shielding gate structure and a control gate structure are sequentially formed in the second trench and the first trench, and at least a portion of the control gate structure is located in the first trench.

[0007] In one embodiment, etching the epitaxial material layer at the bottom of the first trench based on the barrier layer to form a second trench penetrating the first trench includes: Based on the barrier layer, etching the epitaxial material layer at the bottom of the first trench to form a second initial trench penetrating the first trench; The sidewall of the second initial trench is etched to form the second trench, so that in a direction parallel to the substrate, a size of the first trench is smaller than a size of the second trench.

[0008] In one embodiment, the sequentially forming a shield gate structure and a control gate structure in the second trench and the first trench includes: filling the first trench and the second trench to form an insulating material layer; Etching the insulating material layer to form a third trench in the insulating initial layer, with the remaining insulating material layer forming an insulating layer, wherein the third trench has a smaller size than the first trench in a direction parallel to the substrate, and has a smaller size than the sum of the first trench and the second trench in a direction perpendicular to the substrate; A shielding gate structure is formed at the bottom of the third trench.

[0009] In one embodiment, after forming the shielding gate structure at the bottom of the third trench, the method includes: A dielectric layer is formed on a side of the shielding gate structure away from the substrate, wherein the dielectric layer is at least partially located in the second trench, and / or the dielectric layer is at least partially located in the first trench.

[0010] In one embodiment, the material of the dielectric layer is consistent with the material of the insulating layer.

[0011] In one embodiment, after forming the dielectric layer on the side of the shielding gate structure away from the substrate, the method includes: A control gate structure is formed on a side of the dielectric layer away from the substrate.

[0012] In one embodiment, in a direction perpendicular to the substrate, a size of the shielding gate structure is larger than a size of the control gate structure.

[0013] In one embodiment, in a direction parallel to the substrate, the size of the control gate structure is consistent with the size of the shielding gate structure, or the size of the control gate structure is smaller than the size of the shielding gate structure.

[0014] In one embodiment, after sequentially forming the shielding gate structure and the control gate structure in the second trench and the first trench, the method includes: A mesa structure surrounding the first trench is formed, and a bottom of the mesa structure is at a predetermined distance from a top of the second trench.

[0015] In one aspect, a semiconductor structure is provided. The semiconductor structure is manufactured using the method for manufacturing a semiconductor structure as described in any of the aforementioned embodiments.

[0016] The semiconductor structure and preparation method of the present invention have the following beneficial effects: by setting the size of the first trench smaller than the size of the second trench in a direction parallel to the substrate, the first trench has a smaller volume, and the epitaxial layer surrounding the first trench has a larger volume. Subsequently, a relatively large mesa structure can be formed in the epitaxial layer surrounding the first trench. That is, in the present application, by reducing the width of the first trench, the mesa width is widened, providing a preparation margin for the structure in the mesa structure, thereby reducing the difficulty of controlling the threshold voltage and on-resistance of the semiconductor structure and improving the discrete problem of the threshold voltage. At the same time, the width of the first trench is small, so that the width of the control gate structure is also small, which can reduce the control gate resistance and thus improve the switching speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in one embodiment; Figure 2 A schematic diagram of a semiconductor structure provided in a first embodiment; Figure 3 A schematic diagram of a semiconductor structure provided in a second embodiment; Figure 4 A schematic diagram of a semiconductor structure provided in a third embodiment; Figure 5 is a schematic diagram of a semiconductor structure provided in a fourth embodiment; Figure 6 is a schematic diagram of a semiconductor structure provided in a fifth embodiment; Figure 7 is a schematic diagram of a semiconductor structure provided in a sixth embodiment; Figure 8 is a schematic diagram of a semiconductor structure provided in a seventh embodiment; Figure 9 is a schematic diagram of a semiconductor structure provided in an eighth embodiment; Figure 10 is a schematic diagram of a semiconductor structure provided in a ninth embodiment; Figure 11 is a schematic diagram of a semiconductor structure provided in a tenth embodiment; Figure 12 is a schematic diagram of a semiconductor structure provided in an eleventh embodiment; Figure 13 A schematic diagram of a semiconductor structure provided in a twelfth embodiment; Figure 14 is a schematic diagram of a semiconductor structure provided in a thirteenth embodiment; Figure 15 is a schematic diagram of a semiconductor structure provided in a fourteenth embodiment; Figure 16 is a schematic diagram of a semiconductor structure provided in a fifteenth embodiment; Figure 17 is a schematic diagram of a semiconductor structure provided in a sixteenth embodiment; Figure 18 is a schematic diagram of a semiconductor structure provided in a seventeenth embodiment; Figure 19 is a schematic diagram of a semiconductor structure provided in an eighteenth embodiment; Figure 20 A schematic diagram of a semiconductor structure provided in a nineteenth embodiment; Figure 21 A schematic diagram of a semiconductor structure provided in the twentieth embodiment; Figure 22 A schematic diagram of a semiconductor structure provided in the twenty-first embodiment.

[0019] Explanation of the accompanying drawings: semiconductor structure-100; substrate-110; epitaxial layer-120; epitaxial material layer-121; barrier layer-130; shielding gate structure-140; control gate structure-150; dielectric layer-160; insulating material layer-170; mesa structure-180; P-type region-181; heavily doped region-1810; N-type region-182; interlayer dielectric layer-183; interlayer dielectric material layer-1830; contact structure-184; conductive layer-190; first trench-200; second trench-210; second initial trench-211; third trench-220; contact hole-230. DETAILED DESCRIPTION

[0020] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0022] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0023] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0024] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0025] While embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of the regions illustrated herein but are to include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region illustrated as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from implanted to non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions illustrated in the figures are schematic in nature, their shapes do not represent the actual shapes of regions of a device, and are not intended to limit the scope of the invention.

[0026] See also Figure 1 In one embodiment, a method for preparing a semiconductor structure 100 is provided. It is understood that the semiconductor structure 100 may include but is not limited to devices such as MOSFET.

[0027] The method for preparing the semiconductor structure 100 may include the following steps: Step S100: providing a substrate 110 .

[0028] Step S200 : forming an epitaxial material layer 121 on one side of the substrate 110 , wherein a first trench 200 is defined in the epitaxial material layer 121 , and a barrier layer 130 is formed on a sidewall surface of the first trench 200 .

[0029] Step S300: Based on the barrier layer 130, the epitaxial material layer 121 at the bottom of the first trench 200 is etched to form a second trench 210 that is arranged through the first trench 200. The remaining epitaxial material layer 121 forms an epitaxial layer 120. In the direction parallel to the substrate 110, the size of the first trench 200 is smaller than the size of the second trench 210.

[0030] Step S400 : removing the barrier layer 130 .

[0031] Step S500 : forming a shielding gate structure 140 and a control gate structure 150 in the second trench 210 and the first trench 200 in sequence, with at least a portion of the control gate structure 150 being located in the first trench 200 .

[0032] In step S100, refer to Figure 2 The substrate 110 can be made of a semiconductor material, an insulating material, or any combination thereof. The substrate 110 can have a single-layer structure or a multi-layer structure. The material of the substrate 110 can include silicon, silicon germanium, silicon germanium carbon, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, etc. Alternatively, for example, the substrate 110 can be a layered substrate including Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type and material of the substrate 110 should not limit the scope of protection of the present disclosure.

[0033] In step S200, refer to Figure 1 The material of the epitaxial material layer 121 may include silicon, etc. This embodiment does not limit the specific method of preparing the epitaxial material layer 121 and the parameters such as the thickness of the epitaxial material layer 121.

[0034] See also Figures 3 and 4 The first trench 200 extends from the surface of the epitaxial material layer 121 away from the substrate 110 to the interior of the epitaxial growth layer. For example, the first trench 200 can be formed using dry etching, which can include at least one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high-density plasma etching (HDP). This embodiment does not limit the specific depth of the first trench 200. It is understood that multiple first trenches 200 may be provided in the epitaxial material layer 121.

[0035] See also Figure 5A barrier layer 130 may be formed on the sidewall surface of the first trench 200. As an example, the material of the barrier layer 130 may include but is not limited to silicon dioxide, silicon nitride, photoresist, etc. Of course, the barrier layer 130 may also cover the surface of the epitaxial material layer 121 away from the substrate 110.

[0036] In step S300, refer to Figure 6 and Figure 7 The epitaxial material layer 121 at the bottom of the first trench 200 can be etched to form a second trench 210 extending through the first trench 200. The remaining epitaxial material layer 121 serves as the epitaxial layer 120. As an example, the second trench 210 can be formed using dry etching or other methods. In this case, the etching of the first trench 200 and the second trench 210 can be completed in the same etching machine, thereby improving the production efficiency of the semiconductor structure 100.

[0037] In a direction parallel to the substrate 110 (ie, horizontally), the first trench 200 may be smaller than the second trench 210. For example, the second trench 210 may be wider than the first trench 200, thereby allowing the first trench 200 to occupy a smaller volume.

[0038] In step S400, refer to Figure 8 The barrier layer 130 can be removed by dry etching, wet etching or physical removal. At this time, the semiconductor structure 100 only includes the first trench 200 and the second trench 210 that are set through.

[0039] In step S500, refer to Figures 9 to 14 , a shielding gate structure 140 and a control gate structure 150 may be formed in the first trench 200 and the second trench 210 .

[0040] Furthermore, the shielded gate structure 140 can be used to deplete the drift region, making the electric field distribution in the drift region of the semiconductor structure 100 more uniform. This avoids premature breakdown caused by surface electric field concentration and improves the voltage withstand capability of the semiconductor structure 100. Moreover, the shielded gate structure 140 can also smooth the electric field distribution through the capacitive coupling effect, reducing the parasitic capacitance of the semiconductor structure 100, thereby reducing switching losses. The control gate structure 150 can achieve electron flow control within the semiconductor device through voltage regulation.

[0041] This embodiment does not limit the specific parameters of the shielding gate structure 140 and the control gate structure 150. As an example, see Figure 15In a direction parallel to the substrate 110 (i.e., in the horizontal direction), the size of the control gate structure 150 is consistent with the size of the shield gate structure 140. In this case, the width of the shield gate structure 140 can be consistent with the width of the control gate structure 150. In another example, in a direction parallel to the substrate 110 (i.e., in the horizontal direction), the size of the control gate structure 150 can also be smaller than the size of the shield gate structure 140. It will be understood that the specific sizes of the control gate structure 150 and the shield gate structure 140 can be adjusted according to actual needs.

[0042] Of course, the width of the control gate structure 150 may also be at least partially smaller than the width of the shielding gate structure 140, or the width of the control gate structure 150 may also be at least partially larger than the width of the shielding gate structure 140. In this case, the shape of the control gate structure 150 may include an irregular pattern. For example, see Figure 21 The control gate structure 150 may include a convex shape with a narrow top and a wide bottom. Alternatively, see Figure 22 As an example, in a direction perpendicular to the substrate 110 (ie, in a vertical direction), the shielding gate structure 140 may be larger than the control gate structure 150 . In this case, the length of the shielding gate structure 140 may be larger than the length of the control gate structure 150 .

[0043] Furthermore, the shield gate structure 140 may be at least partially located within the second trench 210 , and the control gate structure 150 may be at least partially located within the first trench 200 .

[0044] Furthermore, a dielectric layer 160 may be disposed between the shielding gate structure 140 and the control gate structure 150. The dielectric layer 160 may span the second trench 210 and the first trench 200, or the dielectric layer 160 may be located in either the second trench 210 or the first trench 200. Figure 22 The dielectric layer 160 may not be disposed between the shielding gate structure 140 and the control gate structure 150 , that is, the shielding gate structure 140 and the control gate structure 150 are continuously disposed between them.

[0045] In this embodiment, by setting the size of the first trench 200 smaller than that of the second trench 210 in a direction parallel to the substrate 110, the first trench 200 has a smaller volume, thereby making the epitaxial layer 120 surrounding the first trench 200 have a larger volume. Subsequently, a larger mesa structure can be formed within the epitaxial layer 120 surrounding the first trench 200. That is, in this embodiment, by reducing the width of the first trench 200, the mesa width is widened, providing a fabrication margin for the structure within the mesa structure 180, thereby reducing the difficulty of controlling the threshold voltage and on-resistance of the semiconductor structure 100 and improving the discreteness of the threshold voltage. At the same time, the smaller width of the first trench 200 also reduces the width of the control gate structure 150, thereby reducing the control gate resistance and improving the switching speed.

[0046] In one embodiment, step S300 includes: Step S310 : etching the epitaxial material layer 121 at the bottom of the first trench 200 based on the barrier layer 130 to form a second initial trench 211 penetrating the first trench 200 .

[0047] Step S311 : etching the sidewalls of the second initial trench 211 to form the second trench 210 , so that in a direction parallel to the substrate 110 , the size of the first trench 200 is smaller than that of the second trench 210 .

[0048] In step S310, refer to Figure 6 The epitaxial material layer 121 at the bottom of the first trench 200 can be etched to form a second initial trench 211 that passes through the first trench 200 and has the same width as the first trench 200. At this time, the depth of the second initial trench 211 can be greater than the depth of the first trench 200.

[0049] In step S311, refer to Figure 7 By changing the etching method, the sidewalls of the second preliminary trench 211 can be etched, thereby widening the width of the second preliminary trench 211 and forming the second trench 210. Of course, the above two steps can be completed in the same machine, with different etching methods (etching recipes) for the two steps. For example, the etching gases (or etching gas ratios) for the two steps can be different.

[0050] In this embodiment, a first trench 200 and a second initial trench 211 of uniform width are first formed, and then the sidewall of the second initial trench 211 is etched to widen the second initial trench 211 and form the second trench 210, thereby achieving precise etching and obtaining a semiconductor structure 100 with better performance.

[0051] In one embodiment, step S500 includes: Step S510 : filling the first trench 200 and the second trench 210 to form an insulating material layer 170 .

[0052] Step S511: Etch the insulating material layer 170 to form a third trench 220 in the insulating initial layer, and the remaining insulating material layer 170 forms an insulating layer. In the direction parallel to the substrate 110, the size of the third trench 220 is smaller than the first trench 200, and in the direction perpendicular to the substrate 110, the size of the third trench 220 is smaller than the sum of the first trench 200 and the second trench 210.

[0053] Step S512 : forming a shielding gate structure 140 at the bottom of the third trench 220 .

[0054] In steps S510 to S512, please refer to Figure 9 , the first trench 200 and the second trench 210 may be filled first to form an insulating material layer 170, and the insulating material layer 170 may be used to form the shielding gate structure 140 and the control gate structure 150. Thereafter, refer to Figure 10 The insulating material layer 170 may be etched to form a third trench 220 , and the third trench 220 may be used to form the shielding gate structure 140 and the control gate structure 150 .

[0055] In one possible example, the shape of the third trench 220 may include a rectangle, thereby forming a regular shielding gate structure 140 and a control gate structure 150. In another possible example, the shape of the third trench 220 may include at least a portion of a narrow upper portion and a wide lower portion, thereby forming a shielding gate structure 140 and a control gate structure 150 of other shapes.

[0056] It is understood that in a direction perpendicular to the substrate 110 (i.e., in the vertical direction), the third trench 220 has a smaller size than the sum of the first trench 200 and the second trench 210. In other words, the third trench 220 retains the insulating material layer 170 at the bottom, preventing the shielding gate structure 140 from contacting the substrate 110, etc.

[0057] See also Figure 11 When forming the shielding gate structure 140, the gate material may be filled first. Figure 12 , remove the gate material at the top and retain the gate material at the bottom, thereby forming a shielding gate structure 140. At this time, by forming the shielding gate structure 140 through the above method, the length of the shielding gate structure 140 can be accurately controlled.

[0058] In one embodiment, after step S512, the following steps are included: Step S520 : forming a dielectric layer 160 on a side of the shielding gate structure 140 away from the substrate 110 , wherein the dielectric layer 160 is at least partially located in the second trench 210 and / or at least partially located in the first trench 200 .

[0059] In step S520, refer to Figure 13 For example, the material of the dielectric layer 160 can be the same as that of the insulating layer. As an example, the material of the dielectric layer 160 and the insulating layer can both be silicon dioxide.

[0060] In another example, the material of the dielectric layer 160 may be different from the material of the insulating layer. As an example, one of the dielectric layer 160 and the insulating layer may include a multi-layer structure.

[0061] This embodiment does not limit the specific location of the dielectric layer 160. For example, the dielectric layer 160 is at least partially located within the second trench 210, and / or the dielectric layer 160 is at least partially located within the first trench 200. In this case, the position and length of the control gate structure 150 can be adjusted by controlling the position or thickness of the dielectric layer 160.

[0062] In one embodiment, after step S520, the following steps are included: Step S540 : forming a control gate structure 150 on a side of the dielectric layer 160 away from the substrate 110 .

[0063] In step S540, refer to Figure 14 The material of the control gate structure 150 and the material of the shielding gate structure 140 may both include polysilicon or the like.

[0064] Of course, after forming the control gate structure 150 , the control gate structure 150 and the epitaxial layer 120 may be planarized by chemical mechanical polishing or physical polishing, which will not be described in detail in this embodiment.

[0065] Furthermore, before step S540, the following steps may be included: Step S530 : forming an adjustment layer on the remaining sidewalls of the third trench 220 .

[0066] In step S530 , the adjustment layer may be formed by first filling the remaining third trenches 220 with an oxide material layer, then removing a portion of the oxide material layer by etching, and retaining the oxide material layer on the sidewalls.

[0067] At this time, the thickness of the adjustment layer can be controlled to control the width of the control gate structure 150 to be formed later, thereby achieving the purpose of accurately adjusting the threshold voltage and antistatic capability.

[0068] In one embodiment, after step S500, the following steps are included: In step S600 , a mesa structure 180 is formed surrounding the first trench 200 , and a predetermined distance exists between the bottom of the mesa structure 180 and the top of the second trench 210 .

[0069] As an example, see Figure 15 , a P-type region 181 surrounding the first trench 200 can be formed by doping B or BF2. Figure 16 , an N-type region 182 surrounding the first trench 200 can be formed by doping P or As on the side of the B ions away from the substrate 110. Figure 17 An interlayer dielectric material layer 1830 may also be formed on the entire surface of the resulting structure on a side away from the substrate 110. For example, the material of the interlayer dielectric material layer 1830 may include silicon dioxide. The interlayer dielectric material layer 1830 may be formed using one or more processes including, but not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), high-density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric (SOD).

[0070] See also Figure 18 After forming the interlayer dielectric material layer 1830, the interlayer dielectric material layer 1830 and the N-type region 182 can be etched to form a contact hole 230. The remaining interlayer dielectric material layer 1830 forms the interlayer dielectric layer 183. The contact hole 230 can extend to the top surface of the P-type region 181. Figure 19 , doping can be performed at the bottom of the contact hole 230 to form a heavily doped region 1810. At this time, the doped ions can be the same as the ion types doped when forming the P-type region 181. Finally, refer to Figure 20 The contact hole 230 may be filled to form the contact structure 184. For example, the contact hole 230 may be filled with a metal material such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), or aluminum (Al).

[0071] Of course, after forming the contact structure 184 , a conductive layer 190 or conductive traces may be formed on the entire surface, which will not be described in detail in this embodiment.

[0072] In this embodiment, the mesa structure 180 includes a contact structure 184 and the like, which is relatively small in size. In this embodiment, by reducing the size of the control gate structure 150 , a larger fabrication volume is provided for the mesa structure 180 , thereby reducing the fabrication difficulty of the mesa structure 180 .

[0073] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0074] In one embodiment, a semiconductor structure 100 is provided. The contact structure 184 is fabricated using the method for fabricating the semiconductor structure 100 provided in any embodiment of this specification.

[0075] The semiconductor structure 100 may include at least a substrate 110 , an epitaxial layer 120 , a first trench 200 , a second trench 210 , a shielding gate structure 140 , and a control gate structure 150 .

[0076] The substrate 110 can be made of a semiconductor material, an insulating material, or any combination thereof. The substrate 110 can have a single-layer structure or a multi-layer structure. The material of the substrate 110 can include silicon, silicon germanium, silicon germanium carbon, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, etc. Alternatively, for example, the substrate 110 can be a layered substrate 110 including Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type and material of the substrate 110 should not limit the scope of protection of the present disclosure.

[0077] The epitaxial layer 120 is located on one side of the substrate 110 . The material of the epitaxial layer 120 may include silicon or the like.

[0078] The first trench 200 extends from the surface of the epitaxial layer 120 away from the substrate 110 to the interior of the epitaxial growth layer. The first trench 200 and the second trench 210 are intersecting. In a direction parallel to the substrate 110 (i.e., horizontally), the first trench 200 can be smaller than the second trench 210. For example, the width of the second trench 210 can be greater than the width of the first trench 200, thereby reducing the volume occupied by the first trench 200.

[0079] The shielding gate structure 140 and the control gate structure 150 may be located within the first trench 200 and the second trench 210. For example, in a direction perpendicular to the substrate 110 (i.e., in the vertical direction), the shielding gate structure 140 may be larger than the control gate structure 150. In this case, the length of the shielding gate structure 140 may be greater than the length of the control gate structure 150. For example, in a direction parallel to the substrate 110 (i.e., in the horizontal direction), the size of the control gate structure 150 is the same as the size of the shielding gate structure 140. In this case, the width of the shielding gate structure 140 may be the same as the width of the control gate structure 150. Of course, the width of the control gate structure 150 may also be at least partially smaller than the width of the shielding gate structure 140, or at least partially greater than the width of the shielding gate structure 140. In this case, the shape of the control gate structure 150 may include an irregular pattern. For example, the control gate structure 150 may include a convex shape that is narrow at the top and wide at the bottom.

[0080] Furthermore, the shield gate structure 140 may be at least partially located within the second trench 210 , and the control gate structure 150 may be at least partially located within the first trench 200 .

[0081] Furthermore, a dielectric layer 160 may be disposed between the shielding gate structure 140 and the control gate structure 150. The dielectric layer 160 may span the second trench 210 and the first trench 200, or the dielectric layer 160 may be located in either the second trench 210 or the first trench 200. Of course, the dielectric layer 160 may not be disposed between the shielding gate structure 140 and the control gate structure 150, that is, the shielding gate structure 140 and the control gate structure 150 may be disposed continuously therebetween.

[0082] In this embodiment, by setting the size of the first trench 200 smaller than that of the second trench 210 in a direction parallel to the substrate 110, the first trench 200 has a smaller volume, thereby making the epitaxial layer 120 surrounding the first trench 200 have a larger volume. Subsequently, a larger mesa structure can be formed within the epitaxial layer 120 surrounding the first trench 200. That is, in this embodiment, by reducing the width of the first trench 200, the mesa width is widened, providing a fabrication margin for the structure within the mesa structure 180, thereby reducing the difficulty of controlling the threshold voltage and on-resistance of the semiconductor structure 100 and improving the discreteness of the threshold voltage. At the same time, the smaller width of the first trench 200 also reduces the width of the control gate structure 150, thereby reducing the control gate resistance and improving the switching speed.

[0083] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0084] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming an epitaxial material layer on one side of the substrate, wherein a first trench is provided in the epitaxial material layer, and a barrier layer is formed on the sidewall surface of the first trench; Based on the barrier layer, the epitaxial material layer at the bottom of the first trench is etched to form a second trench that is arranged to penetrate the first trench, and the remaining epitaxial material layer forms an epitaxial layer, and in a direction parallel to the substrate, the size of the first trench is smaller than the size of the second trench; removing the barrier layer; A shielding gate structure and a control gate structure are sequentially formed in the second trench and the first trench, and at least a portion of the control gate structure is located in the first trench.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The step of etching the epitaxial material layer at the bottom of the first trench based on the barrier layer to form a second trench penetrating the first trench comprises: Based on the barrier layer, etching the epitaxial material layer at the bottom of the first trench to form a second initial trench penetrating the first trench; The sidewall of the second initial trench is etched to form the second trench, so that in a direction parallel to the substrate, a size of the first trench is smaller than a size of the second trench.

3. The method for preparing a semiconductor structure according to claim 1, wherein: The step of sequentially forming a shielding gate structure and a control gate structure in the second trench and the first trench includes: filling the first trench and the second trench to form an insulating material layer; Etching the insulating material layer to form a third trench in the insulating initial layer, with the remaining insulating material layer forming an insulating layer, wherein the third trench has a smaller size than the first trench in a direction parallel to the substrate, and has a smaller size than the sum of the first trench and the second trench in a direction perpendicular to the substrate; A shielding gate structure is formed at the bottom of the third trench.

4. The method for preparing a semiconductor structure according to claim 3, wherein: After forming the shielding gate structure at the bottom of the third trench, the method includes: A dielectric layer is formed on a side of the shielding gate structure away from the substrate, wherein the dielectric layer is at least partially located in the second trench, and / or the dielectric layer is at least partially located in the first trench.

5. The method for preparing a semiconductor structure according to claim 4, wherein: The material of the dielectric layer is consistent with that of the insulating layer.

6. The method for preparing a semiconductor structure according to claim 4, wherein: After forming a dielectric layer on a side of the shielding gate structure away from the substrate, the method includes: A control gate structure is formed on a side of the dielectric layer away from the substrate.

7. The method for preparing a semiconductor structure according to claim 1, wherein: In a direction perpendicular to the substrate, a size of the shielding gate structure is larger than a size of the control gate structure.

8. The method for preparing a semiconductor structure according to claim 1, wherein: In a direction parallel to the substrate, a size of the control gate structure is consistent with a size of the shielding gate structure, or a size of the control gate structure is smaller than a size of the shielding gate structure.

9. The method for preparing a semiconductor structure according to claim 1, wherein: After sequentially forming a shielding gate structure and a control gate structure in the second trench and the first trench, the method includes: A mesa structure surrounding the first trench is formed, and a bottom of the mesa structure is at a predetermined distance from a top of the second trench.

10. A semiconductor structure, characterized in that The semiconductor structure is manufactured using the method for manufacturing a semiconductor structure according to any one of claims 1 to 9.

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