Semiconductor structure and forming method thereof
By designing stepped etch stop layers and field plates in the semiconductor structure, the problem of uneven electric field distribution in high-power applications of power semiconductor devices is solved, achieving high breakdown voltage and high electron mobility, thus improving the stability and performance of the devices.
Patent Information
- Application Number
- CN202410425201.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-10
- Publication Date
- 2025-10-21
AI Technical Summary
Existing power semiconductor devices struggle to simultaneously meet the requirements of high breakdown voltage, electron mobility, and thermal stability in high-power applications.
The semiconductor structure design includes a substrate, a semiconductor layer, a gate structure, a first dielectric layer, an etch stop layer, a second dielectric layer, and a field plate. A stepped structure is formed by etching to redistribute the electric field. The etch stop layer is used to control the etching depth and form a field plate to reduce the electric field peak and improve the breakdown voltage.
It achieves a semiconductor structure with high breakdown voltage, low leakage current, high electron mobility and good thermal stability, simplifies the process flow and avoids the formation of unintended etching residues.
Smart Images
Figure CN120826005A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor structure and a method for forming the same. Background Art
[0002] Power semiconductor devices continue to develop and are widely used in applications such as wireless communications, electronic products, and electric vehicles. However, devices that can withstand high power require high breakdown voltages. Furthermore, optimal devices must exhibit high electron mobility and excellent thermal stability. Therefore, new semiconductor structures and their formation methods are needed to further advance related fields. Summary of the Invention
[0003] The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a semiconductor layer, a gate structure, a first dielectric layer, an etch stop layer, a second dielectric layer, and a field plate. The semiconductor layer is on the substrate. The gate structure is on the semiconductor layer. A first dielectric layer extends continuously over the gate structure and the semiconductor layer, the first dielectric layer including a first portion, a second portion, and a third portion, the third portion being on the upper surface of the gate structure, and the second portion being closer to the third portion than the first portion. The etch stop layer is on at least a first portion of the first dielectric layer. The second dielectric layer is on the etch stop layer. The field plate includes a first field plate portion on the second dielectric layer, and a second field plate portion and a third field plate portion on the second and third portions of the first dielectric layer, respectively. The lower surface of the first field plate portion is a first distance from the semiconductor layer, and the lower surface of the second field plate portion is a second distance from the semiconductor layer, the first distance being greater than the second distance. The field plate has a first projection on the substrate in a direction perpendicular to the substrate, and the gate structure has a second projection on the substrate in a direction perpendicular to the substrate, with the first projection completely covering the second projection.
[0004] The present disclosure also provides a method for forming a semiconductor structure. The method includes the following operations. Forming a gate structure on a semiconductor layer located on a substrate. Forming a first dielectric layer on the gate structure and the semiconductor layer. Forming an etch stop layer on the first dielectric layer. Forming a second dielectric layer on the etch stop layer, wherein the etch stop layer separates the second dielectric layer from the first dielectric layer. Etching a portion of the second dielectric layer to a depth that reaches at least the upper surface of the etch stop layer to form an opening in the remaining portion of the second dielectric layer, wherein the gate structure is located in the opening. Forming a field plate on the second dielectric layer and the opening, wherein the field plate has a first projection on the substrate in a direction perpendicular to the substrate, the gate structure has a second projection on the substrate in a direction perpendicular to the substrate, and the first projection completely covers the second projection. BRIEF DESCRIPTION OF THE DRAWINGS
[0005] When reading the figures accompanying this disclosure, it is recommended that you refer to the following to understand various aspects of this disclosure. It should be noted that, in accordance with standard industry practice, various feature dimensions may not be drawn to scale. For clarity of discussion, various feature dimensions may be arbitrarily increased or decreased. Furthermore, to simplify the drawings, conventional structures and components are depicted in simplified schematic form.
[0006] Figures 1A to 1C is a schematic diagram of a semiconductor structure according to some embodiments of the present disclosure.
[0007] Figures 2 to 4 is a schematic structural diagram of an intermediate process of a method for forming a semiconductor structure according to some embodiments of the present disclosure. DETAILED DESCRIPTION
[0008] To make the present disclosure more detailed and complete, the following description is provided for illustrative purposes only. However, this does not limit the present disclosure to any particular form. The present disclosure may be combined or substituted with one another where beneficial, or additional embodiments may be added without further explanation.
[0009] Spatially relative terms, such as "above" and "below," may be used in this disclosure to describe the relationship of one element to another element in the figures. Spatially relative terms are intended to encompass different orientations of the device when in use or operation, in addition to the orientation depicted in the figures. For example, a device may be oriented in other ways (rotated 90 degrees or in other orientations, etc.), and thus the spatially relative terms of this disclosure should be interpreted accordingly. In this disclosure, unless otherwise indicated, the same element numbers in different figures refer to the same or similar elements formed from the same or similar materials by the same or similar methods.
[0010] The present disclosure provides a semiconductor structure such as Figures 1A to 1C As shown, the semiconductor structure includes a substrate 101, a semiconductor layer 102, a gate structure 103, a first dielectric layer 104, an etch stop layer 105, a second dielectric layer 106, and a field plate 107. The semiconductor layer 102 is on the substrate 101. The gate structure 103 is on the semiconductor layer 102. The first dielectric layer 104 extends continuously on the gate structure 103 and the semiconductor layer 102, wherein the first dielectric layer 104 includes a first portion 104A, a second portion 104B, and a third portion 104C, wherein the third portion 104C is on the upper surface of the gate structure 103, and the second portion 104B is closer to the third portion 104C than the first portion 104A. The etch stop layer 105 is on the first portion 104A of the first dielectric layer 104, and may also be on the remaining portion of the first dielectric layer 104 except the first portion 104A, for example, on the second portion 104B and the third portion 104C, as shown in FIG. Figure 1CAs shown, the second dielectric layer 106 is on the etch stop layer 105, wherein the projection of the second dielectric layer 106 on the substrate 101 substantially completely overlaps with the projection of the first portion 104A of the first dielectric layer 104 on the substrate 101, but does not overlap with the projection of the remaining portion of the first dielectric layer 104 (including the second portion 104B and the third portion 104C) other than the first portion 104A on the substrate 101. The field plate 107 includes a first field plate portion 107A on the second dielectric layer 106 on the first portion 104A of the first dielectric layer 104, and a second field plate portion 107B and a third field plate portion 107C on the second portion 104B and the third portion 104C of the first dielectric layer 104, respectively, wherein a first distance D1 is between the bottom surface of the first field plate portion 107A and the semiconductor layer 102, a second distance D2 is between the bottom surface of the second field plate portion 107B and the semiconductor layer 102, and a third distance D3 is between the bottom surface of the third field plate portion 107C and the semiconductor layer 102, and the first distance D1 and the third distance D3 are greater than the second distance D2. In some embodiments, the first distance D1 is preferably to For example or The second distance D2 is preferably For example or And the third distance D3 is preferably to For example or The field plate 107 has a first projection on the substrate 101 , the gate structure 103 has a second projection on the substrate 101 , and the first projection completely covers the second projection.
[0011] The substrate 101 may be any suitable semiconductor substrate and include any suitable semiconductor element, compound, and / or alloy, such as C, Si, Ge, SiC, BN, AlN, GaN, GaP, GaAs, InP, InAs, InSb, ZnO, SiGe, AlGaAs, InGaAs, InGaP, AlInAs, GaAsP, AlGaN, InGaN, AlGaInP, the like, or combinations thereof. In some embodiments, the substrate 101 may further include any suitable active device (e.g., a diode, etc.), passive device (e.g., a resistor, a capacitor, etc.), conductive wire, the like, or combinations thereof, but not shown in the figures.
[0012] The semiconductor layer 102 includes a channel layer 102C and a barrier layer 102B on the channel layer 102C. The channel layer 102C provides a channel for carrier flow between the source and drain (not shown for simplicity, but the semiconductor structure actually also includes a source and drain structure on the semiconductor layer 102, as well as a gate structure 103 and a field plate 107 located between the source and drain structures). The barrier layer 102B facilitates the formation of a carrier flow channel in the channel layer 102C for a two-dimensional electron gas (2DEG) with high concentration, high electron mobility, and low resistance. In some embodiments, the channel layer 102C comprises epitaxial gallium nitride. In some embodiments, the barrier layer 102B comprises AlGaN.
[0013] The gate structure 103 controls the flow of carriers in the channel layer 102C. In some embodiments, the gate structure 103 includes a doped layer 103D and a metal layer 103M on the doped layer 103D. The doped layer 103D can be doped with an N-type dopant (e.g., C, Si, Ge, Sn, or the like) or a P-type dopant (e.g., Be, Mg, Ga, Sr, or the like) as desired. For example, in some embodiments, the doped layer 103D includes GaN doped with an N-type dopant or a P-type dopant. The metal layer 103M can be any suitable electrode metal.
[0014] The first dielectric layer 104 extends continuously over the gate structure 103 and the semiconductor layer 102 to provide insulation. For clarity, the first dielectric layer 104 includes a first portion 104A, a second portion 104B, and a third portion 104C. The first portion 104A and the remaining portion (including the second portion 104B and the third portion 104C) of the first dielectric layer 104 substantially completely overlap and are substantially offset from the second dielectric layer 106 in a direction perpendicular to the surface of the substrate 101. In some embodiments, the first dielectric layer 104 is in direct contact with the semiconductor layer 102 and the gate structure 103. In some embodiments, the first dielectric layer 104 comprises SiO2, Si3N4, SiON, or a combination thereof.
[0015] The etch stop layer 105 is on the first dielectric layer 104 to serve as an etch stop layer in the process of forming the semiconductor structure, so that the etching depth can be more effectively controlled. For example, the etching can be stopped or paused until it contacts the etch stop layer 105 to ensure that the material to be etched can be removed completely and without residue, and to avoid over-etching of the material under the etch stop layer 105. In other words, the etch stop layer 105 helps to avoid unexpected residues and / or defects in the semiconductor structure that affect the operation of the semiconductor structure. In some embodiments, the etch stop layer 105 includes AlN, Al2O3, SiN, or a combination thereof. In some embodiments, the thickness of the etch stop layer 105 is preferably to For example or
[0016] Second dielectric layer 106 is disposed on first portion 104A of first dielectric layer 104 but does not cover the remaining portion of first dielectric layer 104 (including second portion 104B and third portion 104C). Second dielectric layer 106 is vertically separated from first dielectric layer 104 by etch stop layer 105. Because second dielectric layer 106 and the remaining portion of first dielectric layer 104 (including second portion 104B and third portion 104C) are substantially completely offset in a direction parallel to the surface of substrate 101, first dielectric layer 104 and second dielectric layer 106 can collectively have a step-like shape. Furthermore, because etch stop layer 105 is located between first dielectric layer 104 and second dielectric layer 106, etching of second dielectric layer 106 can be stopped or paused at etch stop layer 105 during the formation of the step-like shape between first dielectric layer 104 and second dielectric layer 106, ensuring that the height of the resulting step more accurately meets the desired requirements (see the method below for details). In some embodiments, the second dielectric layer 106 includes SiO 2 , Si 3 N 4 , SiON, or a combination thereof.
[0017] The field plate 107 is located in the shape of a step between the first dielectric layer 104 and the second dielectric layer 106. The field plate 107 can redistribute the electric field distribution of the 2DEG drift region at the edge of the gate structure 103 to effectively reduce the electric field peak, thereby avoiding the occurrence of a breakdown voltage caused by an excessively high electric field peak (i.e., the semiconductor structure of the present disclosure can have a high breakdown voltage). Since the field plate 107 located in the shape of a step has a stepped shape, the field plate 107 can gradually redistribute the electric field distribution at the edge of the gate structure 103 to more significantly improve the breakdown voltage of the semiconductor structure. Moreover, the present disclosure does not require increasing the distance between the gate structure 103 and the source structure and / or drain structure to increase the breakdown voltage of the semiconductor structure. In some embodiments, the field plate 107 includes TiN, Ti, AlCu, Al, AlSi, or a combination thereof.
[0018] Continuing with the description of the field plate 107. In some embodiments, the field plate 107 extends continuously on the first dielectric layer 104 and the second dielectric layer 106. In some embodiments, the field plate 107 has a substantially uniform thickness, so that the upper surface of the field plate 107 also has a shape similar to the steps of the first dielectric layer 104 and the second dielectric layer 106. In some embodiments, the field plate 107 is separated from the gate structure 103 and the semiconductor layer 102 by the first dielectric layer 104. In some embodiments, the field plate 107 is located on the upper surface and side surfaces of the gate structure 103. In some embodiments, the lower surface of the first field plate portion 107A is higher than the upper surface of the gate structure 103, and the lower surface of the second field plate portion 107B is lower than the upper surface of the gate structure 103. In some embodiments, the upper surface of the first field plate portion 107A and the upper surface of the third field plate portion 107C are higher than the upper surface of the second field plate portion 107B. In some embodiments, when the etch stop layer 105 is as Figure 1C When the remaining portion of the first dielectric layer 104 (including the second portion 104B and the third portion 104C) is not covered, the field plate 107 is in direct contact with the remaining portion of the first dielectric layer 104. In some embodiments, the first field plate portion 107A is further away from the gate structure 103 than the second field plate portion 107B and the third field plate portion 107C.
[0019] In some embodiments, as Figure 1AAs shown by the dotted line in FIG, the top surface S2 of the remaining portion of the first dielectric layer 104 (including the second portion 104B and the third portion 104C) other than the first portion 104A can be lower than the top surface S1 of the first portion 104A of the first dielectric layer 104. This allows for more precise adjustment of the height difference between the field plates 107 on the first dielectric layer 104 and the second dielectric layer 106, thereby more precisely adjusting the electric field distribution under the field plates 107. In these embodiments, the etch stop layer 105 covers the first portion 104A of the first dielectric layer 104, but does not cover or expose the remaining portion of the first dielectric layer 104 (including the second portion 104B and the third portion 104C).
[0020] In some embodiments, as Figure 1B As shown, the semiconductor structure may further include a third dielectric layer 108 conformally located on the first dielectric layer 104 and the second dielectric layer 106, and the field plate 107 is further located on the third dielectric layer 108. When the semiconductor structure further includes the third dielectric layer 108, the height of the field plate 107 can be more precisely adjusted to more precisely adjust the electric field distribution under the field plate 107. In some embodiments, the third dielectric layer 108 continuously covers the first dielectric layer 104 and the second dielectric layer 106 to provide a more continuous and flat surface for the field plate 107 located thereon. In some embodiments, the third dielectric layer 108 has a substantially uniform thickness. In some embodiments, the number of third dielectric layers 108 is not limited to that shown in the figure and may include a structure of one or more layers. In some embodiments, the third dielectric layer 108 includes a high dielectric constant material (such as HfO2), SiO2, Si3N4, SiON, or a combination thereof.
[0021] The present disclosure also provides a method for forming the aforementioned semiconductor structure. The method includes the following operations: forming a gate structure 103 on a semiconductor layer 102 located on a substrate 101; forming a first dielectric layer 104 on the gate structure 103 and the semiconductor layer 102; forming an etch stop layer 105 on the first dielectric layer 104; forming a second dielectric layer 106 on the etch stop layer 105, wherein the etch stop layer 105 separates the second dielectric layer 106 from the first dielectric layer 104; etching a portion of the second dielectric layer 106 to a depth at least reaching an upper surface of the etch stop layer 105 to form an opening 106O in the remaining portion of the second dielectric layer 106, wherein the gate structure 103 is located in the opening 106O; and forming a field plate 107 on the second dielectric layer 106 and the opening 106O, wherein the field plate 107 has a first projection on the substrate 101, the gate structure 103 has a second projection on the substrate 101, and the first projection completely covers the second projection.
[0022] First, refer to Figure 2, a gate structure 103 is formed on a semiconductor layer 102 located on a substrate 101, and a first dielectric layer 104, an etch stop layer 105, and a second dielectric layer 106 are sequentially formed on the gate structure 103 and the semiconductor layer 102. The method of forming the gate structure 103, the first dielectric layer 104, the etch stop layer 105, and the second dielectric layer 106 may include any feasible method, such as chemical vapor deposition. In some embodiments, forming the gate structure 103 includes forming a doped layer 103D and a metal layer 103M formed on the doped layer 103D, and forming the semiconductor layer 102 includes forming a channel layer 102C and a barrier layer 102B formed on the channel layer 102C. In some embodiments, the method further includes forming a source structure and a drain structure on the semiconductor layer 102 before forming the first dielectric layer 104, the etch stop layer 105, and the second dielectric layer 106.
[0023] Next, a photoresist layer 109 is formed on the second dielectric layer 106, and the photoresist layer 109 is used as a mask to etch a portion of the second dielectric layer 106 to form a Figure 3The second dielectric layer 106 is shown. The second dielectric layer 106 is patterned through a photoresist layer 109 so that the first dielectric layer 104 and the patterned second dielectric layer 106 form a stepped shape. As a result, the field plate 107 is formed on this stepped shape and has a corresponding stepped shape. Specifically, the photoresist layer 109 overlaps with the first portion 104A of the first dielectric layer 104, while the opening 109O of the photoresist layer 109 overlaps with the remaining portion of the first dielectric layer 104 other than the first portion 104A (including the second portion 104B and the third portion 104C). The portion of the second dielectric layer 106 exposed by the opening 109O of the photoresist layer 109 can be etched using any suitable etching method, resulting in the patterned second dielectric layer 106 having an opening 106O exposing the remaining portion of the first dielectric layer 104 other than the first portion 104A (including the second portion 104B and the third portion 104C). In some embodiments, possible etching methods include wet etching (e.g., using etchants such as HF, buffered oxide etchant (BOE), H3PO4, or combinations thereof) or dry etching (e.g., using etching plasma gases such as Cl2; a combination of HCl and Cl2; a combination of BCl3 and SF6; a combination of S2F2 and C2F6; C3F8; C4F8; C5F8; a combination of C4F6, NF3, CHF3, CH2F2, CH3F, SiF4, C3F8, and CCl2F2; or combinations thereof). In some embodiments, the etching depth reaches at least the upper surface of the etch stop layer 105 to ensure that the exposed portion of the second dielectric layer 106 is completely removed. The etch stop layer 105 can also prevent the first dielectric layer 104 from being unintentionally over-etched. In some embodiments, after the etching stops at the etch stop layer 105, the etching can continue to etch the etch stop layer 105 to remove the etch stop layer 105 in the opening 106O. In some embodiments, after etching the etch stop layer 105 in the opening 106O, the portion of the first dielectric layer 104 below the opening 106O, i.e., the upper portion of the remaining portion (e.g., the second portion 104B and the third portion 104C) other than the first portion 104A, may be further etched, so that the upper surface of the remaining lower portion of the second portion 104B of the first dielectric layer 104 in the opening 106O is lower than the upper surface of the first portion 104A of the first dielectric layer 104 below the second dielectric layer 106 outside the opening 106O. In some embodiments, the thickness of the upper portion of the second portion 104B before etching is preferably about 1000 nm. to For example or and the thickness of the remaining lower portion of the second portion 104B after etching is preferably to For example or In some embodiments, etching the etch stop layer 105 is performed by a wet etching process (e.g., using an etchant such as diluted HF, BOE, or a combination thereof), and etching the first dielectric layer 104 is performed by a dry etching process. In some embodiments, etching the etch stop layer 105 and the first dielectric layer 104 is performed by a continuous wet etching process (e.g., using an etchant such as diluted HF, BOE, or a combination thereof).
[0024] Next, a field plate 107 is formed on the second dielectric layer 106 and the opening 106O to form a Figure 1A or Figure 1C or in some embodiments, a third dielectric layer 108 is conformally formed on the second dielectric layer 106 and the opening 106O and then a field plate 107 is formed on the third dielectric layer 108 to form a Figure 1B In some embodiments, when the embodiment includes forming the third dielectric layer 108, the first dielectric layer 104 may not be etched, so that the upper surface of the second portion 104B of the first dielectric layer 104 is substantially flush with the upper surface of the first portion 104A of the first dielectric layer 104. In some embodiments, as Figure 4 As shown, forming the field plate 107 includes depositing a field plate material 107' continuously extending on the first dielectric layer 104 and the second dielectric layer 106, and etching the edge portion of the field plate material 107' to form the field plate 107. In some embodiments, the field plate material 107' can be patterned by using the photoresist layer 110 formed on the field plate material 107' as a mask to form the field plate material 107' as shown in FIG. Figures 1A to 1C In the field plate 107 shown, the opening 110O of the photoresist layer 110 exposes the edge portion of the field plate material 107 ′ to be etched.
[0025] The semiconductor structure disclosed herein and the semiconductor structure formed by the method disclosed herein have a high breakdown voltage to reduce leakage current. Furthermore, the semiconductor structure has high electron mobility and good thermal stability. The semiconductor structure disclosed herein can be used not only in high electron mobility transistors (HEMTs), but also in high-power semiconductor devices. The stepped shape of the first and second dielectric layers, formed by an etch stop layer located between the first and second dielectric layers, makes the height of the stepped shape more consistent with expectations and reduces unintended etching residues remaining on the stepped shape. The field plate disclosed herein can have a more consistent height difference along the stepped shape, significantly increasing the breakdown voltage and precisely adjusting the charge distribution. The height difference of the stepped shape can also be finely adjusted by adding a third dielectric layer or etching the upper portion of the first dielectric layer. The continuously extending field plate disclosed herein with a height difference can be formed through a single patterning process, thereby simplifying the process, improving process efficiency, and avoiding damage to the field plate caused by forming field plates of different heights in multiple steps.
[0026]
Explanation of symbols
[0027] 101:Substrate
[0028] 102: semiconductor layer
[0029] 102B: Barrier layer
[0030] 102C: Channel layer
[0031] 103: Gate structure
[0032] 103D: Doping layer
[0033] 103M:Metal layer
[0034] 104: first dielectric layer
[0035] 104A: Part 1
[0036] 104B: Part 2
[0037] 104C: Part 3
[0038] 105: Etching stop layer
[0039] 106: second dielectric layer
[0040] 106O, 109O, 110O: Open
[0041] 107: Field board
[0042] 107': Field plate material
[0043] 107A: First field plate part
[0044] 107B: Second field plate part
[0045] 107C: The third field plate part
[0046] 108: third dielectric layer
[0047] 109, 110: Photoresist layer
[0048] D1: First distance
[0049] D2: Second distance
[0050] D3: The third distance
[0051] S1~S2: upper surface.
Claims
1. A semiconductor structure, characterized in that include: substrate; A semiconductor layer is on the substrate; A gate structure is on the semiconductor layer; A first dielectric layer continuously extends over the gate structure and the semiconductor layer, the first dielectric layer comprising a first portion, a second portion, and a third portion, the third portion being on an upper surface of the gate structure, and the second portion being closer to the third portion than the first portion; an etch stop layer on at least the first portion of the first dielectric layer; a second dielectric layer on the etch stop layer; as well as A field plate includes a first field plate portion on the second dielectric layer and a second field plate portion and a third field plate portion on the second portion and the third portion of the first dielectric layer, respectively, wherein a lower surface of the first field plate portion is a first distance from the semiconductor layer, a lower surface of the second field plate portion is a second distance from the semiconductor layer, the first distance is greater than the second distance, the field plate has a first projection on the substrate in a vertical direction along the substrate, the gate structure has a second projection on the substrate in the vertical direction along the substrate, and the first projection completely covers the second projection. 2 . The semiconductor structure of claim 1 , wherein the field plate extends continuously on the first dielectric layer and the second dielectric layer.
3. The semiconductor structure according to claim 1 , wherein a projection of the second dielectric layer on the substrate in the vertical direction along the substrate overlaps with a projection of the first portion of the first dielectric layer on the substrate in the vertical direction along the substrate, and the projection of the second dielectric layer on the substrate in the vertical direction along the substrate does not overlap with projections of the second portion and the third portion of the first dielectric layer on the substrate in the vertical direction along the substrate. 4 . The semiconductor structure according to claim 1 , wherein a lower surface of the third field plate portion is at a third distance from the semiconductor layer, and the third distance is greater than the second distance.
5. The semiconductor structure according to claim 1, wherein The invention also includes a third dielectric layer on the first dielectric layer and the second dielectric layer, and the field plate on the third dielectric layer. The semiconductor structure according to claim 1 , wherein an upper surface of the second portion of the first dielectric layer is lower than an upper surface of the first portion of the first dielectric layer. 7 . The semiconductor structure according to claim 1 , wherein the gate structure comprises a doped layer and a metal layer on the doped layer, and the semiconductor layer comprises a channel layer and a barrier layer on the channel layer.
8. A method for forming a semiconductor structure, characterized in that: include: forming a gate structure on a semiconductor layer located on a substrate; forming a first dielectric layer on the gate structure and the semiconductor layer; forming an etch stop layer on the first dielectric layer; forming a second dielectric layer on the etch stop layer, wherein the etch stop layer separates the second dielectric layer from the first dielectric layer; Etching a portion of the second dielectric layer to a depth that reaches at least an upper surface of the etch stop layer to form an opening in a remaining portion of the second dielectric layer, wherein the gate structure is located in the opening; as well as A field plate is formed on the second dielectric layer and the opening, wherein the field plate has a first projection on the substrate in a vertical direction along the substrate, the gate structure has a second projection on the substrate in the vertical direction along the substrate, and the first projection completely covers the second projection.
9. The method according to claim 8, wherein The method further includes etching a portion of the first dielectric layer below the opening so that an upper surface of the portion of the first dielectric layer below the opening is lower than an upper surface of a portion of the first dielectric layer below the second dielectric layer.
10. The method according to claim 8, wherein The method further includes conformally forming a third dielectric layer to cover the second dielectric layer and the opening before forming the field plate.