Semiconductor structure and forming method thereof
By introducing an etch stop layer and a stepped dielectric layer design into the semiconductor structure, controlling the etching depth, and combining the field plate to redistribute the electric field, the high breakdown voltage and thermal stability problems of existing power semiconductor components are solved, and the effects of high electron mobility and low leakage current are achieved.
Patent Information
- Application Number
- CN202410425240.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-10
- Publication Date
- 2025-10-21
AI Technical Summary
Existing power semiconductor components find it difficult to simultaneously achieve high breakdown voltage, electron mobility, and thermal stability, and existing processes make it difficult to precisely control etching depth, resulting in unexpected residues and defects.
A semiconductor structure design is adopted, including a substrate, a semiconductor layer, a gate structure, a first dielectric layer, an etch stop layer, a second dielectric layer and a field plate. The etching depth is controlled by the etch stop layer to form a stepped first dielectric layer and a second dielectric layer. The field plate is located on the stepped shape to redistribute the electric field to avoid excessive electric field peaks.
It improves the breakdown voltage of the semiconductor structure, reduces leakage current, maintains high electron mobility and good thermal stability, simplifies the process flow, avoids etching residues, and improves process efficiency.
Smart Images
Figure CN120826006A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor structure and a method for forming the same. Background Art
[0002] Power semiconductor devices continue to develop and are widely used in applications such as wireless communications, electronic products, and electric vehicles. However, devices that can withstand high power require high breakdown voltages. Furthermore, optimal devices must exhibit high electron mobility and excellent thermal stability. Therefore, new semiconductor structures and their formation methods are needed to further advance related fields. Summary of the Invention
[0003] The present invention provides a semiconductor structure. The semiconductor structure includes a substrate, a semiconductor layer, a gate structure, a first dielectric layer, an etch stop layer, a second dielectric layer, and a field plate. The semiconductor layer is on the substrate. The gate structure is on the semiconductor layer. The first dielectric layer extends continuously over the gate structure and the semiconductor layer and includes a first portion, a second portion, a third portion, and a fourth portion, wherein the third portion and the fourth portion are on the upper surface of the gate structure. The etch stop layer is on at least the first portion and the fourth portion of the first dielectric layer. The second dielectric layer is on the etch stop layer. The field plate includes a first field plate portion on the second dielectric layer, a second field plate portion and a third field plate portion on the second portion and the third portion of the first dielectric layer, respectively, and a fourth field plate portion on the second dielectric layer, wherein a first distance between the lower surface of the first field plate portion and the semiconductor layer is greater than a second distance between the lower surface of the second field plate portion and the semiconductor layer, and a third distance between the lower surface of the third field plate portion and the semiconductor layer is less than a fourth distance between the lower surface of the fourth field plate portion and the semiconductor layer.
[0004] The present invention also provides a method for forming a semiconductor structure, comprising forming a gate structure on a semiconductor layer located on a substrate; forming a first dielectric layer on the gate structure and the semiconductor layer; forming an etch stop layer on the first dielectric layer; forming a second dielectric layer on the etch stop layer, wherein the etch stop layer separates the second dielectric layer from the first dielectric layer; etching a portion of the second dielectric layer and making the etching depth reach at least the upper surface of the etch stop layer to form an opening in the remaining portion of the second dielectric layer, wherein a portion of the upper surface of the gate structure and a side surface connected to the portion are located below the opening; and forming a field plate on the second dielectric layer and the opening. BRIEF DESCRIPTION OF THE DRAWINGS
[0005] When reading the accompanying drawings, it is recommended that you refer to the following for an understanding of various aspects of the present invention. Please note that, in accordance with standard industry practice, various feature dimensions may not be drawn to scale. For clarity of discussion, various feature dimensions may be arbitrarily increased or decreased. Furthermore, to simplify the drawings, conventional structures and components are depicted in simplified schematic form.
[0006] Figures 1A to 1D is a schematic diagram of a semiconductor structure according to some embodiments of the present invention.
[0007] Figures 2 to 4 1 is a structural schematic diagram of an intermediate process of a method for forming a semiconductor structure according to some embodiments of the present invention. DETAILED DESCRIPTION
[0008] The present invention provides a semiconductor structure, such as Figures 1A to 1D As shown, the semiconductor structure includes a substrate 101, a semiconductor layer 102, a gate structure 103, a first dielectric layer 104, an etch stop layer 105, a second dielectric layer 106' and a field plate 107. The semiconductor layer 102 is on the substrate 101. The gate structure 103 is on the semiconductor layer 102. The first dielectric layer 104 extends continuously on the gate structure 103 and the semiconductor layer 102 and includes a first portion 104A, a second portion 104B, a third portion 104C and a fourth portion 104D, wherein the first portion 104A and the second portion 104B are next to the same side of the gate structure 103, and the third portion 104C and the fourth portion 104D are on the upper surface of the gate structure 103. The etch stop layer 105 is on the first portion 104A and the fourth portion 104D of the first dielectric layer 104, and may also be on the second portion 104B and the third portion 104C of the first dielectric layer 104 (as shown in FIG. Figure 1B). A second dielectric layer 106′ is on the etch stop layer 105, wherein a projection of the second dielectric layer 106′ on the substrate 101 overlaps with projections of the first portion 104A and the fourth portion 104D of the first dielectric layer 104 on the substrate 101, but does not overlap with projections of the second portion 104B and the third portion 104C of the first dielectric layer 104 on the substrate 101. The field plate 107 includes a first field plate portion 107A on the second dielectric layer 106', a second field plate portion 107B and a third field plate portion 107C on the second portion 104B and the third portion 104C of the first dielectric layer 104, respectively, and a fourth field plate portion 107D on the second dielectric layer 106', wherein the lower surface of the first field plate portion 107A is a first distance D1 from the semiconductor layer 102, the lower surface of the second field plate portion 107B is a second distance D2 from the semiconductor layer 102, the lower surface of the third field plate portion 107C is a third distance D3 from the semiconductor layer 102, and the lower surface of the fourth field plate portion 107D is a fourth distance D4 from the semiconductor layer 102, the first distance D1 is greater than the second distance D2, and the third distance D3 is less than the fourth distance D4. In some embodiments, the first distance D1 is preferably to For example or The second distance D2 is preferably to For example or The third distance D3 is preferably to For example or And the fourth distance D4 is preferably to For example or
[0009] The substrate 101 may be any suitable semiconductor substrate and include any suitable semiconductor element, compound, and / or alloy, such as C, Si, Ge, SiC, BN, AlN, GaN, GaP, GaAs, InP, InAs, InSb, ZnO, SiGe, AlGaAs, InGaAs, InGaP, AlInAs, GaAsP, AlGaN, InGaN, AlGaInP, the like, or combinations thereof. In some embodiments, the substrate 101 may further include any suitable active device (e.g., a diode, etc.), passive device (e.g., a resistor, a capacitor, etc.), conductive wire, the like, or combinations thereof, but not shown in the figures.
[0010] The semiconductor layer 102 includes a channel layer 102C and a barrier layer 102B on the channel layer 102C. The channel layer 102C provides a channel for carrier flow between the source and drain (not shown for simplicity, but in practice, the semiconductor structure also includes a source structure and a drain structure on the semiconductor layer 102, with the gate structure 103 and the field plate 107 located between the source and drain structures). The barrier layer 102B facilitates the formation of a carrier flow channel in the channel layer 102C for a two-dimensional electron gas (2DEG) with high concentration, high electron mobility, and low resistance. In some embodiments, the channel layer 102C comprises epitaxially deposited gallium nitride. In some embodiments, the barrier layer 102B comprises AlGaN.
[0011] The gate structure 103 controls the flow of carriers in the channel layer 102C. In some embodiments, the gate structure 103 includes a doped layer 103D and a metal layer 103M on the doped layer 103D. The doped layer 103D can be doped with an N-type dopant (e.g., C, Si, Ge, Sn, or the like) or a P-type dopant (e.g., Be, Mg, Ga, Sr, or the like) as desired. For example, in some embodiments, the doped layer 103D includes GaN doped with an N-type dopant or a P-type dopant. The metal layer 103M can be any suitable electrode metal.
[0012] The first dielectric layer 104 extends continuously over the gate structure 103 and the semiconductor layer 102 to provide insulation. In some embodiments, the first dielectric layer 104 is in direct contact with the semiconductor layer 102 and the gate structure 103. For clarity, the first dielectric layer 104 includes a first portion 104A, a second portion 104B, a third portion 104C, and a fourth portion 104D. The combination of the first portion 104A and the fourth portion 104D, and the combination of the second portion 104B and the third portion 104C, respectively, overlap and are offset from the second dielectric layer 106' in a direction perpendicular to the surface of the substrate 101. In some embodiments, the second portion 104B of the first dielectric layer 104 is closer to the gate structure 103 than the first portion 104A, and the third portion 104C is closer to the first portion 104A and the second portion 104B than the fourth portion 104D. In some embodiments, the first dielectric layer 104, including the second portion 104B and the third portion 104C, not only covers the semiconductor layer 102 but also continuously covers a portion of the top surface and side surfaces of the gate structure 103, such that at least a portion of the gate structure 103 is not covered by the second dielectric layer 106'. In some embodiments, the first dielectric layer 104 comprises SiO2, Si3N4, SiON, or a combination thereof.
[0013] The etch stop layer 105 is on the first dielectric layer 104 and has a portion on the gate structure 103 to serve as an etch stop layer in the process of forming the semiconductor structure, so that the etching depth can be more effectively controlled. For example, the etching can be stopped or paused until it contacts the etch stop layer 105 to ensure that the material to be etched can be removed completely and without residue, and to avoid over-etching of the material under the etch stop layer 105. In other words, the etch stop layer 105 helps to avoid unexpected residues and / or defects in the semiconductor structure that affect the operation of the semiconductor structure. In some embodiments, the etch stop layer 105 includes AlN, Al2O3, SiN, or a combination thereof. In some embodiments, the thickness of the etch stop layer 105 is preferably to For example or
[0014] The second dielectric layer 106' is formed on the first portion 104A and the fourth portion 104D of the first dielectric layer 104 and has a portion formed on the gate structure 103. The second dielectric layer 106' does not cover the second portion 104B and the third portion 104C of the first dielectric layer 104. The second dielectric layer 106' is vertically separated from the first dielectric layer 104 by the etch stop layer 105. Because the second dielectric layer 106' is substantially completely offset from the second portion 104B and the third portion 104C of the first dielectric layer 104 in a direction parallel to the surface of the substrate 101, the first dielectric layer 104 and the second dielectric layer 106' may collectively have a staircase-like shape. Furthermore, because the etch stop layer 105 is located between the first dielectric layer 104 and the second dielectric layer 106', when forming the step between the first dielectric layer 104 and the second dielectric layer 106', the etching of the second dielectric layer 106' can be stopped or paused at the etch stop layer 105, thereby making the height of the formed step more consistent with the desired shape (see the method below for details). In some embodiments, the second dielectric layer 106' includes SiO2, Si3N4, SiON, or a combination thereof.
[0015] The field plate 107 is located in the shape of a step formed by the first dielectric layer 104 and the second dielectric layer 106'. The field plate 107 can redistribute the electric field distribution at the edge of the gate structure 103 to effectively reduce the electric field peak at the edge of the gate structure 103, thereby avoiding the occurrence of a breakdown voltage caused by an excessively high electric field peak (that is, the semiconductor structure of the present invention can have a high breakdown voltage). Since the field plate 107 located in the shape of a step also has a step shape, the field plate 107 can gradually redistribute the electric field distribution at the edge of the gate structure 103 to more significantly improve the breakdown voltage of the semiconductor structure. Moreover, the present invention does not need to increase the breakdown voltage of the semiconductor structure by increasing the distance between the gate structure 103 and the source structure and / or drain structure. In some embodiments, the field plate 107 includes TiN, Ti, AlCu, Al, AlSi, or a combination thereof.
[0016] In some embodiments, the field plate 107 extends continuously over the first dielectric layer 104 and the second dielectric layer 106'. In some embodiments, the field plate 107 has a substantially uniform thickness, such that the top surface of the field plate 107 has a stepped shape similar to the stepped shape of the first dielectric layer 104 and the second dielectric layer 106'. In some embodiments, the field plate 107 is separated from the gate structure 103 and the semiconductor layer 102 by the first dielectric layer 104. In some embodiments, the field plate 107 covers the top and side surfaces of the gate structure 103. In some embodiments, the field plate 107 completely covers the gate structure 103. In some embodiments, the bottom surface of the first field plate portion 107A of the field plate 107 is higher than the top surface of the gate structure 103, and the bottom surface of the second field plate portion 107B of the field plate 107 is lower than the top surface of the gate structure 103. In some embodiments, the upper surface of the first field plate portion 107A and the upper surface of the third field plate portion 107C of the field plate 107 are higher than the upper surface of the second field plate portion 107B. In some embodiments, the upper surface of the fourth field plate portion 107D of the field plate 107 is higher than the upper surface of the first field plate portion 107A and the upper surface of the third field plate portion 107C. In some embodiments, when the etch stop layer 105 is as Figure 1AWhen shown uncovered with respect to second portion 104B and third portion 104C of first dielectric layer 104, field plate 107 is in direct contact with second portion 104B and third portion 104C of first dielectric layer 104. In some embodiments, first field plate portion 107A and second field plate portion 107B are adjacent to the same side of gate structure 103, and third field plate portion 107C and fourth field plate portion 107D are on an upper surface of gate structure 103. In some embodiments, first field plate portion 107A is further away from gate structure 103 than second field plate portion 107B, and third field plate portion 107C is closer to first field plate portion 107A and second field plate portion 107B than fourth field plate portion 107D.
[0017] In some embodiments, as Figure 1C As shown, the semiconductor structure may further include a third dielectric layer 108 conformally located on the first dielectric layer 104 and the second dielectric layer 106', and the field plate 107 is further located on the third dielectric layer 108. When the semiconductor structure further includes the third dielectric layer 108, the height of the field plate 107 can be more precisely adjusted as needed to more precisely adjust the electric field distribution under the field plate 107. In some embodiments, the third dielectric layer 108 continuously covers the first dielectric layer 104 and the second dielectric layer 106' to provide a more continuous and flat surface for the field plate 107 located thereon. In some embodiments, the third dielectric layer 108 has a substantially uniform thickness. In some embodiments, the third dielectric layer 108 is not limited to the number shown in the figure and may include a structure of one or more layers. In some embodiments, the third dielectric layer 108 includes SiO2, Si3N4, SiON, a high dielectric constant material (such as HfO2), or a combination thereof.
[0018] In some embodiments, as Figure 1D As shown, in the semiconductor structure, the upper surface S2 of the second portion 104B of the first dielectric layer 104 can be lower than the upper surface S1 of the first portion 104A of the first dielectric layer 104, and the upper surface S3 of the third portion 104C of the first dielectric layer 104 can be lower than the upper surface S4 of the fourth portion 104D of the first dielectric layer 104. Therefore, the height difference between the field plates 107 on the first dielectric layer 104 and the second dielectric layer 106' can be more precisely adjusted as needed to more precisely adjust the electric field distribution under the field plates 107. In these embodiments, the etch stop layer 105 covers the first portion 104A and the fourth portion 104D of the first dielectric layer 104, but does not cover or expose the second portion 104B and the third portion 104C of the first dielectric layer 104.
[0019] The present invention also provides a method for forming the aforementioned semiconductor structure. The method includes the following operations: forming a semiconductor layer 102 on a substrate 101; forming a gate structure 103 on the semiconductor layer 102; forming a first dielectric layer 104 on the gate structure 103 and the semiconductor layer 102; forming an etch stop layer 105 on the first dielectric layer 104; forming a second dielectric layer 106 on the etch stop layer 105, wherein the etch stop layer 105 separates the second dielectric layer 106 from the first dielectric layer 104; etching a portion of the second dielectric layer 106 to a depth at least reaching the top surface of the etch stop layer 105 to form an opening 106O in the remaining portion of the second dielectric layer 106 (the second dielectric layer 106′ in the figure), wherein a portion of the top surface of the gate structure 103 and a side surface connected to the portion are located below the vertical projection of the opening 106O; and forming a field plate 107 on the second dielectric layer 106′ and the opening 106O.
[0020] First, refer to Figure 2 , a gate structure 103 is formed on a semiconductor layer 102 located on a substrate 101, and a first dielectric layer 104, an etch stop layer 105, and a second dielectric layer 106 are sequentially formed on the gate structure 103 and the semiconductor layer 102. The method of forming the gate structure 103, the first dielectric layer 104, the etch stop layer 105, and the second dielectric layer 106 may include any feasible method, such as chemical vapor deposition. In some embodiments, forming the gate structure 103 includes forming a doped layer 103D and a metal layer 103M formed on the doped layer 103D, and forming the semiconductor layer 102 includes forming a channel layer 102C and a barrier layer 102B formed on the channel layer 102C. In some embodiments, the method further includes forming a source structure and a drain structure on the semiconductor layer 102 before forming the first dielectric layer 104, the etch stop layer 105, and the second dielectric layer 106.
[0021] Next, a photoresist layer 109 is formed on the second dielectric layer 106 so that the photoresist layer 109 serves as a mask to etch a portion of the second dielectric layer 106 to form a Figure 3The patterned second dielectric layer 106' is shown. The second dielectric layer 106 is patterned through the photoresist layer 109, so that the first dielectric layer 104 and the patterned second dielectric layer 106' form a stepped shape, and thus the field plate 107 is formed on this stepped shape and has a corresponding stepped shape. In detail, the photoresist layer 109 overlaps with the first portion 104A and the fourth portion 104D of the first dielectric layer 104, and the opening 109O of the photoresist layer 109 overlaps with the second portion 104B and the third portion 104C of the first dielectric layer 104. The portion of the second dielectric layer 106 exposed by the opening 109O of the photoresist layer 109 can be etched using any feasible etching method, so that the patterned second dielectric layer 106' has an opening 106O exposing the second portion 104B and the third portion 104C of the first dielectric layer 104. In some embodiments, possible etching methods include wet etching (e.g., using etchants such as HF, buffered oxide etchant (BOE), H3PO4, or combinations thereof) or dry etching (e.g., using etching plasma gases such as Cl2; a combination of HCl and Cl2; a combination of BCl3 and SF6; a combination of S2F2 and C2F6; C3F8; C4F8; C5F8; a combination of C4F6, NF3, CHF3, CH2F2, CH3F, SiF4, C3F8, and CCl2F2; or combinations thereof). In some embodiments, the etching depth reaches at least the upper surface of the etch stop layer 105 to ensure that the exposed portion of the second dielectric layer 106 is completely removed. The etch stop layer 105 can also prevent the first dielectric layer 104 from being unintentionally over-etched. In some embodiments, after the etching stops at the etch stop layer 105, the etching can continue to etch the etch stop layer 105 to remove the etch stop layer 105 in the opening 106O. In some embodiments, after etching the etch stop layer 105 in the opening 106O, the upper portions of the second portion 104B and the third portion 104C of the first dielectric layer 104 exposed below the opening 106O may be further etched, such that the upper surface of the remaining lower portion of the second portion 104B and the upper surface of the remaining lower portion of the third portion 104C of the first dielectric layer 104 in the opening 106O are lower than the upper surface of the first portion 104A and the upper surface of the fourth portion 104D of the first dielectric layer 104 located below the second dielectric layer 106′ outside the opening 106O, respectively. In some embodiments, the thickness of the upper portions of the second portion 104B and the third portion 104C before etching is preferably independently 0.1mm thick. to For example or and the thickness of the remaining lower portion of the second portion 104B and the third portion 104C after etching is independently preferably to For example or In some embodiments, etching the etch stop layer 105 is performed by a wet etching process (e.g., using an etchant such as diluted HF, BOE, or a combination thereof), and etching the first dielectric layer 104 is performed by a dry etching process. In some embodiments, etching the etch stop layer 105 and the first dielectric layer 104 is performed by a continuous wet etching process (e.g., using an etchant such as diluted HF, BOE, or a combination thereof).
[0022] Next, a field plate 107 is formed on the second dielectric layer 106' and the opening 106O to form a Figure 1A 、 Figure 1B or Figure 1D or in some embodiments, a third dielectric layer 108 is conformally formed on the second dielectric layer 106 'and the opening 106O, and then a field plate 107 is formed on the third dielectric layer 108 to form a Figure 1C In some embodiments, when the embodiment includes forming the third dielectric layer 108, the first dielectric layer 104 may not be etched, so that the upper surface of the second portion 104B of the first dielectric layer 104 is substantially flush with the upper surface of the first portion 104A of the first dielectric layer 104, and the upper surface of the third portion 104C of the first dielectric layer 104 is substantially flush with the upper surface of the fourth portion 104D of the first dielectric layer 104. In some embodiments, as Figure 4 As shown, forming the field plate 107 includes depositing a field plate material 107' continuously extending on the first dielectric layer 104 and the second dielectric layer 106', and etching the edge portion of the field plate material 107' to form the field plate 107. In some embodiments, the field plate material 107' can be patterned by using the photoresist layer 110 formed on the field plate material 107' as a mask to form the field plate material 107'. Figures 1A to 1D In the field plate 107 shown, the opening 110O of the photoresist layer 110 exposes the edge portion of the field plate material 107 ′ to be etched.
[0023] The semiconductor structure of the present invention and the semiconductor structure formed by the method of the present invention have a high breakdown voltage to reduce leakage current. In addition, the semiconductor structure has high electron mobility and good thermal stability. The semiconductor structure of the present invention can be used not only in high electron mobility transistors (HEMTs), but also in high-power semiconductor devices. The stepped shape of the first and second dielectric layers formed by the etch stop layer located between the first and second dielectric layers makes the height of the stepped shape more consistent with the desired height and reduces the amount of unintended etching residue remaining on the stepped shape. The field plate of the present invention can have a more consistent height difference along the stepped shape, significantly increasing the breakdown voltage and precisely adjusting the charge distribution. The height difference of the stepped shape can also be adjusted in more detail by adding a third dielectric layer or etching the upper portion of the first dielectric layer. The continuously extending field plate of the present invention with a height difference can be formed through a single patterning process, thereby simplifying the process, improving process efficiency, and avoiding damage to the field plate caused by forming field plates of different heights in multiple steps.
[0024]
Explanation of symbols
[0025] 101:Substrate
[0026] 102: semiconductor layer
[0027] 102B: Barrier layer
[0028] 102C: Channel layer
[0029] 103: Gate structure
[0030] 103D: Doping layer
[0031] 103M:Metal layer
[0032] 104: first dielectric layer
[0033] 104A: Part 1
[0034] 104B: Part 2
[0035] 104C: Part 3
[0036] 104D: Part 4
[0037] 105: Etching stop layer
[0038] 106, 106': second dielectric layer
[0039] 106O, 109O, 110O: Open
[0040] 107: Field board
[0041] 107': Field plate material
[0042] 107A: First field plate part
[0043] 107B: Second field plate part
[0044] 107C: The third field plate part
[0045] 107D: The fourth board section
[0046] 108: third dielectric layer
[0047] 109, 110: Photoresist layer
[0048] D1: First distance
[0049] D2: Second distance
[0050] D3: The third distance
[0051] D4: The fourth distance
[0052] S1~S4: upper surface.
Claims
1. A semiconductor structure, characterized in that include: substrate; A semiconductor layer is on the substrate; A gate structure is on the semiconductor layer; A first dielectric layer continuously extends over the gate structure and the semiconductor layer, the first dielectric layer comprising a first portion, a second portion, a third portion, and a fourth portion, wherein the third portion and the fourth portion are on an upper surface of the gate structure; an etch stop layer on at least the first portion and the fourth portion of the first dielectric layer; a second dielectric layer on the etch stop layer; as well as A field plate includes a first field plate portion on the second dielectric layer, a second field plate portion and a third field plate portion on the second portion and the third portion of the first dielectric layer, respectively, and a fourth field plate portion on the second dielectric layer, wherein a first distance between a lower surface of the first field plate portion and the semiconductor layer is greater than a second distance between a lower surface of the second field plate portion and the semiconductor layer, and a third distance between a lower surface of the third field plate portion and the semiconductor layer is less than a fourth distance between a lower surface of the fourth field plate portion and the semiconductor layer. 2 . The semiconductor structure of claim 1 , wherein the field plate extends continuously on the first dielectric layer and the second dielectric layer.
3. The semiconductor structure according to claim 1 , wherein a projection of the second dielectric layer on the substrate in a vertical direction along the substrate overlaps with projections of the first portion and the fourth portion of the first dielectric layer on the substrate in the vertical direction along the substrate, and the projection of the second dielectric layer on the substrate in the vertical direction along the substrate does not overlap with projections of the second portion and the third portion of the first dielectric layer on the substrate in the vertical direction along the substrate. 4 . The semiconductor structure of claim 1 , wherein the first field plate portion and the second field plate portion are beside a same side of the gate structure, and the second field plate portion is closer to the gate structure than the first field plate portion. The semiconductor structure of claim 4 , wherein the third field plate portion is closer to the first field plate portion and the second field plate portion than the fourth field plate portion. The semiconductor structure according to claim 1 , wherein: The invention also includes a third dielectric layer on the first dielectric layer and the second dielectric layer, and the field plate on the third dielectric layer.
7. The semiconductor structure according to claim 1, wherein an upper surface of the second portion of the first dielectric layer is lower than an upper surface of the first portion of the first dielectric layer, and an upper surface of the third portion of the first dielectric layer is lower than an upper surface of the fourth portion of the first dielectric layer.
8. A method for forming a semiconductor structure, characterized in that: include: forming a gate structure on a semiconductor layer located on a substrate; forming a first dielectric layer on the gate structure and the semiconductor layer; forming an etch stop layer on the first dielectric layer; forming a second dielectric layer on the etch stop layer, wherein the etch stop layer separates the second dielectric layer from the first dielectric layer; Etching a portion of the second dielectric layer to a depth that reaches at least the upper surface of the etch stop layer to form an opening in the remaining portion of the second dielectric layer, wherein a portion of the upper surface of the gate structure and a side surface connected to the portion are located below the opening; as well as A field plate is formed on the second dielectric layer and the opening.
9. The method according to claim 8, wherein The method further includes etching a portion of the first dielectric layer below the opening so that an upper surface of the portion of the first dielectric layer below the opening is lower than an upper surface of a portion of the first dielectric layer below the second dielectric layer.
10. The method according to claim 8, wherein The method further includes conformally forming a third dielectric layer on the second dielectric layer and the opening before forming the field plate.