Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the structure comprises a substrate which comprises a core region, an input / output region, a source region located on the side walls of the core region and the input / output region, and a common drain region located between the core region and the input / output region; the plurality of stacked second sacrificial layers, first channel layers, third sacrificial layers, second channel layers, fourth sacrificial layers and third channel layers are located on the core region; the first sacrificial layer, the second sacrificial layer, the first channel layer, the third sacrificial layer, the fourth sacrificial layer and the third channel layer are located on the input and output region in a stacked mode. On the input / output region, the first sacrificial layer, the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer form a laminated composite sacrificial layer, and a plurality of laminated second sacrificial layers, first channel layers, third sacrificial layers, second channel layers, fourth sacrificial layers and third channel layers are formed on the core region. The first sacrificial layer and the second sacrificial layer are stacked, or the third sacrificial layer and the fourth sacrificial layer are stacked, so that compared with a plurality of discrete second sacrificial layers, third sacrificial layers or fourth sacrificial layers which are formed on the core region, the first sacrificial layer and the second sacrificial layer are stacked; therefore, the thickness of the composite sacrificial layer on the input / output region is larger than that of the sacrificial layer on the core region, namely, the thickness of a gate oxide in a subsequently formed device for controlling input / output is also larger than that of a gate oxide in a device on the core region, and the working performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Surround gate (gate-all-around, GAA) devices have become a new direction of research and development in the industry. The characteristic of this technology is that the gate wraps the channel on all four sides. The source and drain are no longer in contact with the substrate. Instead, multiple source and drain electrodes such as linear (which can be understood as stick-shaped) or flat or sheet-shaped are distributed transversely perpendicular to the gate to achieve the basic structure and function of MOSFET. This design largely solves the various problems caused by the reduction in gate spacing, including capacitance effects, etc. In addition, the channel is wrapped by the gate on all four sides, so the channel current is smoother than the three-sided wrapping of FinFET.

[0003] However, the performance of existing all-around gate devices needs to be further improved. Summary of the Invention

[0004] The technical problem solved by the present invention is a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0005] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a core region, an input / output region, a source region located on the sidewalls of the core region and the input / output region, and a common drain region located between the core region and the input / output region; forming a first sacrificial layer on the substrate; forming a first photoresist layer on the first sacrificial layer in the input / output region; etching and removing the first sacrificial layer in the core region using the first photoresist layer as a mask; forming a second sacrificial layer on the substrate and the first sacrificial layer in the input / output region; forming a first channel layer on the second sacrificial layer; forming a third sacrificial layer on the first channel layer; and A second channel layer is formed on the third sacrificial layer; a second photoresist layer is formed on the second channel layer in the core area; the second channel layer in the input-output area is etched away using the second photoresist layer as a mask; a fourth sacrificial layer is formed on the second channel layer and the third sacrificial layer; a third channel layer is formed on the fourth sacrificial layer; the above steps are repeated until a plurality of stacked second sacrificial layers, first channel layers, third sacrificial layers, second channel layers, fourth sacrificial layers and third channel layers are formed on the core area, and a plurality of stacked first sacrificial layers, second sacrificial layers, first channel layers, third sacrificial layers, fourth sacrificial layers and third channel layers are formed on the input-output area.

[0006] In one possible design, in another implementation of another aspect of the embodiment of the present application, after the channel layer is formed on the fourth sacrificial layer, it also includes: removing all sacrificial layers through a removal modification process, forming a number of first trenches in the core area, and forming a number of second trenches on the input and output area; forming a number of first gate structures in the first trenches, and forming a number of second gate structures in the second trenches.

[0007] In one possible design, in another implementation of another aspect of the embodiment of the present application, the steps of forming the first gate structure and the second gate structure include: forming a gate dielectric material layer and a work function material layer located on the gate dielectric material layer in the first trench and the second trench; etching the gate dielectric material layer and the work function material layer in the first trench to form a first gate dielectric layer and a first work function layer, and the first gate structure includes the first gate dielectric layer and the first work function layer; etching the gate dielectric material layer and the work function material layer in the second trench to form a second gate dielectric layer and a second work function layer, and the second gate structure includes the second gate dielectric layer and the second work function layer.

[0008] In one possible design, in another implementation of another aspect of the embodiment of the present application, before forming the first trench and the second trench, it also includes: forming a number of separate dummy gates on the top channel layer; forming inner sidewalls on the sidewall surface of each dummy gate; using the dummy gates and the inner sidewalls as masks, etching all sacrificial layers and channel layers on the source region and the common drain region until the substrate is exposed, forming source and drain openings located on both sides of the core region and the input and output regions; forming a source structure in the source and drain openings located on the source region, and forming a common drain structure in the source and drain openings located on the common drain region.

[0009] In one possible design, in another implementation of another aspect of the embodiment of the present application, after forming the common drain structure and the source structure, it also includes: forming an interlayer dielectric layer on the common drain structure and the source structure; removing the dummy gate structure to form the gate opening, and forming a gate material layer in the gate opening, wherein the top surface of the gate material layer is higher than the top surface of the interlayer dielectric layer; flattening the gate material layer until the top surface of the interlayer dielectric layer is exposed to form a gate structure.

[0010] In one possible design, in another implementation of another aspect of the embodiment of the present application, the method of forming a first sacrificial layer also includes: forming a third photoresist layer on the surface of the substrate on the core area; using the third photoresist layer as a mask, forming a first sacrificial layer on the surface of the substrate on the input and output area.

[0011] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, including: a substrate, the substrate including a core region, an input-output region, a source region located on the side walls of the core region and the input-output region, and a common drain region located between the core region and the input-output region; a plurality of stacked second sacrificial layers, a first channel layer, a third sacrificial layer, a second channel layer, a fourth sacrificial layer and a third channel layer located on the core region; a plurality of stacked first sacrificial layers, a second sacrificial layer, a first channel layer, a third sacrificial layer, a fourth sacrificial layer and a third channel layer located on the input-output region.

[0012] In one possible design, in another implementation of another aspect of the embodiment of the present application, the semiconductor structure also includes: a plurality of first trenches located between the channel layers on the core region, a first gate structure located within the first trenches, a second trench located between the channel layers on the input and output regions, and a second gate structure located within the second trenches.

[0013] In one possible design, in another implementation of another aspect of the embodiment of the present application, the first gate structure includes: a first work function layer located in the first trench and a first gate dielectric layer located on the sidewall surface of the first work function layer; the second gate structure includes: a second work function layer located in the second trench and a second gate dielectric layer located on the sidewall surface, top surface and bottom surface of the second work function layer.

[0014] In one possible design, in another implementation of another aspect of the embodiment of the present application, the semiconductor structure further includes: source-drain openings located on both sides of the core region and the input-output region, a source structure located within the source-drain openings on the source region, and a common drain structure located within the source-drain openings on the common drain region.

[0015] In one possible design, in another implementation of another aspect of the embodiment of the present application, the semiconductor structure also includes: several interlayer dielectric layers located on the top surface of the source structure and the top surface of the common drain structure, a gate structure located between adjacent interlayer dielectric layers, and an inner sidewall located on the sidewall surface of the gate structure.

[0016] In one possible design, in another implementation of another aspect of the embodiment of the present application, the material of the first sacrificial layer, the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer includes germanium silicon; the material of the first channel layer, the second channel layer and the third channel layer includes silicon.

[0017] In one possible design, in another implementation of another aspect of the embodiment of the present application, the thickness dimension of the first groove along the direction perpendicular to the substrate is smaller than the thickness dimension of the first groove along the direction perpendicular to the substrate.

[0018] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0019] The anti-breakdown effect of the transistor structure is achieved, and the working performance of the semiconductor structure is improved.

[0020] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the device located on the input-output area is a device for controlling the input and output, that is, the device for controlling the input and output needs to operate under a high control voltage. In the technical solution of the present invention, a plurality of stacked first sacrificial layers, second sacrificial layers, first channel layers, third sacrificial layers, fourth sacrificial layers and third channel layers are formed on the input-output area, wherein the first sacrificial layer and the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer form a stacked composite sacrificial layer, and a plurality of stacked second sacrificial layers, first channel layers, third sacrificial layers, second channel layers, fourth sacrificial layers and third channel layers are formed on the core area. The composite sacrificial layer includes a stacked first sacrificial layer and a second sacrificial layer or a stacked third sacrificial layer and a fourth sacrificial layer. Compared with forming several discrete second sacrificial layers or third sacrificial layers or fourth sacrificial layers on the core area, the thickness of the composite sacrificial layer on the input and output area is greater than the thickness of the sacrificial layer on the core area, that is, the thickness of the gate oxide in the device that controls the input and output formed subsequently is also greater than the thickness of the gate oxide in the device on the core area. The function of the gate oxide is to adjust the threshold voltage of the transistor structure so that the second transistor structure can withstand high voltage, thereby achieving an anti-breakdown effect of the semiconductor structure and improving the working performance of the semiconductor structure.

[0021] Furthermore, the first gate structure and the second gate structure are formed between several channel layers. In the technical solution of the present invention, the thickness of the second trench between the channel layers on the input and output regions is greater than the thickness of the first trench between the channel layers on the core region. Therefore, the thickness of the gate oxide in the second gate structure is greater than the thickness of the gate oxide in the first gate structure, thereby avoiding the risk of opening formed by the second gate structure, making the second gate structure resistant to high voltage, thereby achieving the anti-breakdown effect of the transistor structure and improving the working performance of the semiconductor structure.

[0022] In the semiconductor structure provided by the technical solution of the present invention, the device on the input-output region is a device for controlling input and output, that is, the device for controlling input and output needs to operate under a high control voltage. In the technical solution of the present invention, the input-output region includes a plurality of stacked first sacrificial layers, second sacrificial layers, first channel layers, third sacrificial layers, fourth sacrificial layers, and third channel layers, wherein the first sacrificial layers, the second sacrificial layers, the third sacrificial layers, and the fourth sacrificial layers form a stacked composite sacrificial layer, and the core region includes a stacked second sacrificial layer, a first channel layer, a third sacrificial layer, a second channel layer, a fourth sacrificial layer, and a third channel layer. Therefore, compared with the plurality of separate second sacrificial layers, third sacrificial layers, or fourth sacrificial layers on the core region, the thickness of the composite sacrificial layer on the input-output region is greater than the thickness of the sacrificial layer on the core region, that is, the thickness of the gate oxide in the device for controlling input and output formed subsequently is also greater than the thickness of the gate oxide in the device for controlling input and output. The function of the gate oxide is to adjust the threshold voltage of the transistor structure so that the device for controlling input and output can withstand high voltage, thereby achieving an anti-breakdown effect of the semiconductor structure and improving the working performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural diagram of a semiconductor structure;

[0024] Figures 2 to 15 1 is a structural diagram of the formation process of the semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0026] As described in the background art, the method for forming a wraparound gate device needs to be improved. This will now be analyzed and explained in conjunction with specific embodiments.

[0027] Figure 1 It is a structural diagram of a semiconductor structure.

[0028] Please refer to Figure 1 The semiconductor structure includes: a substrate 100, the substrate 100 includes a core region I, an input-output region III, and a source-drain region II located between the core region I and the input-output region; the transistor structure includes: a plurality of first gate structures 101 located on the surface of the substrate 100 and a plurality of channel layers 102 located on the surface of the first gate structure 101; and a source-drain structure 103 located on the source-drain region II.

[0029] The semiconductor structure further includes a second gate structure 104 located on the core region I and the input / output region III.

[0030] In the above scheme, the thicknesses of the several channel layers in the several transistor structures are the same, that is, the thicknesses of the first gate structures formed between the several channel layers are also the same, but the ring-gate device includes core devices and input-output devices, and the control voltage of the input-output devices is higher than the control voltage of the core devices. The function of the first gate structure is to adjust the threshold voltage of the device structure. The first gate structures in different devices are the same, resulting in the same control voltages for different devices, which in turn leads to a breakdown effect in the input-output devices. In order to ensure the high-voltage resistance of the input-output devices, the thickness between the channel layers needs to be increased. The formation of the first gate structure in the input-output device between the current channel layers is likely to lead to the risk of the first gate structure being open, affecting the performance of the semiconductor device.

[0031] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same. The device located on the input and output area is a device for controlling the input and output, that is, the device for controlling the input and output needs to work under a high control voltage. In the technical solution of the present invention, a plurality of stacked first sacrificial layers, second sacrificial layers, first channel layers, third sacrificial layers, fourth sacrificial layers and third channel layers are formed on the input and output area, wherein the first sacrificial layer and the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer form a stacked composite sacrificial layer, and a plurality of stacked second sacrificial layers, first channel layers, third sacrificial layers, second channel layers, fourth sacrificial layers and third channel layers are formed on the core area. The channel layer, therefore, the composite sacrificial layer includes a stacked first sacrificial layer and a second sacrificial layer or a stacked third sacrificial layer and a fourth sacrificial layer. Compared with forming several discrete second sacrificial layers or third sacrificial layers or fourth sacrificial layers on the core area, the thickness of the composite sacrificial layer on the input-output area is greater than the thickness of the sacrificial layer on the core area, that is, the thickness of the gate oxide layer in the device for controlling the input and output formed subsequently is also greater than the thickness of the gate oxide in the device on the core area. The function of the gate oxide is to adjust the threshold voltage of the transistor structure so that the second transistor structure can withstand high voltage, thereby achieving an anti-breakdown effect of the semiconductor structure and improving the working performance of the semiconductor structure.

[0032] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] Figures 2 to 15 1 is a structural diagram of the formation process of the semiconductor structure in an embodiment of the present invention.

[0034] Please refer to Figure 2 , providing a substrate 200, the substrate 200 includes a core region I, an input-output region II, a source region III located on the sidewalls of the core region I and the input-output region II, and a common drain region IV located between the core region I and the input-output region II.

[0035] In this embodiment, the material of the substrate 200 is single crystal silicon; in other embodiments, the substrate 200 may also be a semiconductor material such as polycrystalline silicon, germanium, silicon germanium, gallium arsenide, silicon on insulator, or germanium on insulator.

[0036] The difference between the core region I and the input / output region II is that the control voltage of the transistor structure formed on the input / output region II is greater than the control voltage of the body transistor structure formed on the core region I.

[0037] Please refer to Figure 3 , an initial first sacrificial layer 201 is formed on the substrate 200 .

[0038] Please refer to Figure 4 , forming a first photoresist layer 202 on the initial first sacrificial layer 201 of the input / output region II; using the first photoresist layer 202 as a mask, etching away the initial first sacrificial layer 201 of the core region I to form a first sacrificial layer 203.

[0039] In other embodiments not shown, the method of forming the first sacrificial layer 203 also includes: forming a third photoresist layer on the surface of the substrate 200 on the core area I; using the third photoresist layer as a mask, forming the first sacrificial layer 203 on the surface of the substrate 200 on the input and output area II.

[0040] Please refer to Figure 5 , forming a second sacrificial layer 204 on the substrate 200 and the first sacrificial layer 203 of the input / output region II.

[0041] Since the control voltages of the devices on the core region I and the devices on the input-output region II are different, that is, the thickness of the gate oxide layer in the gate structure of the devices on the core region I and the thickness of the gate oxide layer in the gate structure of the devices on the input-output region II are different, therefore, in the process of forming the epitaxial layer, the thickness of the sacrificial layer on the input-output region II is increased to achieve the subsequent increase in the thickness of the gate oxide layer in the gate structure of the devices in the input-output region II.

[0042] Please refer to Figure 6 , a first channel layer 205 is formed on the second sacrificial layer 204 .

[0043] In this embodiment, the material of the channel layer is silicon.

[0044] Please refer to Figure 7 , a third sacrificial layer 206 is formed on the first channel layer 205 .

[0045] Please refer to Figure 8 , forming a second channel layer 207 on the third sacrificial layer 206 .

[0046] Please refer to Figure 9 , forming a second photoresist layer 208 on the second channel layer 207 in the core area I; and using the second photoresist layer 208 as a mask, etching and removing the second channel layer 207 in the input / output area II.

[0047] Please refer to Figure 10 , a fourth sacrificial layer 209 is formed on the second channel layer 207 and the third sacrificial layer 206 ; and a third channel layer 210 is formed on the fourth sacrificial layer 209 .

[0048] The first sacrificial layer 203 to the fourth sacrificial layer 209 function to provide a spatial basis for the subsequently formed first gate structure and second gate structure.

[0049] The material of the first to fourth sacrificial layers 203 to 209 includes silicon germanium.

[0050] The thickness of the first sacrificial layer 203 to the fourth sacrificial layer 209 ranges from 1 nanometer to 30 nanometers.

[0051] Repeat the above steps until a plurality of stacked second sacrificial layers 204, first channel layers 205, third sacrificial layers 206, second channel layers 207, fourth sacrificial layers 209 and third channel layers 210 are formed on the core area I, and a plurality of stacked first sacrificial layers 203, second sacrificial layers 204, first channel layers 205, third sacrificial layers 206, fourth sacrificial layers 209 and third channel layers 210 are formed on the input-output area II.

[0052] In the above scheme, the device on the input-output area II is a device for controlling input and output, that is, the device for controlling input and output needs to work under a high control voltage. In the technical solution of the present invention, the input-output area II includes a plurality of stacked first sacrificial layers 203, second sacrificial layers 204, first channel layers 205, third sacrificial layers 206, fourth sacrificial layers 209 and third channel layers 210, wherein the first sacrificial layers 203 and the second sacrificial layers 204, the third sacrificial layers 206 and the fourth sacrificial layers 209 form a stacked composite sacrificial layer, and the core area I includes a stacked second sacrificial layer 204, a first channel layer 205, a third sacrificial layer 206, a fourth sacrificial layer 209 and a third channel layer 210. The second channel layer 207, the fourth sacrificial layer 209 and the third channel layer 210, therefore, compared with the several discrete second sacrificial layers 204 or the third sacrificial layers 206 or the fourth sacrificial layers 209 on the core area I, the thickness of the composite sacrificial layer on the input-output area II is greater than the thickness of the sacrificial layer on the core area I, that is, the thickness of the gate oxide in the device that controls the input and output formed subsequently is also greater than the thickness of the gate oxide in the device that controls the input and output. The function of the gate oxide is to adjust the threshold voltage of the transistor structure so that the device that controls the input and output can withstand high voltage, thereby achieving the anti-breakdown effect of the semiconductor structure and improving the working performance of the semiconductor structure.

[0053] Please refer to Figure 11 , a plurality of dummy gates 211 separated from each other are formed on the top channel layer.

[0054] In this embodiment, the method for forming the dummy gate 211 includes: forming a dummy gate material layer (not shown in the figure) on the sidewall surface and top surface of the sacrificial layer and the channel layer described above; and patterning the dummy gate material layer to form the dummy gate 211.

[0055] The method for patterning the dummy gate material layer includes: forming a hard mask layer (not shown in the figure) on the surface of the dummy gate material layer, wherein the hard mask layer exposes a portion of the dummy gate material layer; using the hard mask layer as a mask, etching the dummy gate material layer to form the dummy gate 211.

[0056] The hard mask layer may be a single layer or a multi-layer structure. In this embodiment, the hard mask layer is a three-layer structure consisting of a silicon oxide material layer (not shown in the figure), a silicon nitride material layer (not shown in the figure), and a silicon oxide material layer (not shown in the figure).

[0057] Please refer to Figure 12 , forming an inner sidewall 212 on the sidewall surface of each dummy gate 211; using the dummy gate 211 and the inner sidewall 212 as a mask, etching all sacrificial layers and channel layers on the source region III and the common drain region IV until the substrate 200 is exposed, forming source and drain openings 214 located on both sides of the core region I and the input and output region II.

[0058] The inner sidewall 212 is flush with the dummy gate 211 .

[0059] In this embodiment, portions of the sacrificial layer on both sides are removed to form a first opening (not shown in the figure) and a second opening (not shown in the figure); an isolation structure 213 is formed in the first opening and the second opening.

[0060] The function of the isolation structure 213 is that in subsequent steps, a first trench 217 and a second trench 218 need to be formed in the isolation structure 213, a first gate structure is formed in the first trench 217, and a second gate structure is formed in the second trench 218. If there is no isolation structure 213, the first gate structure and the second gate structure will contact the source-drain structure, thereby causing leakage. The existence of the isolation structure 213 can prevent the gate structure from contacting the source-drain structure.

[0061] Please refer to Figure 13 A source structure 215 is formed in the source-drain opening 214 located on the source region III, and a common drain structure 2151 is formed in the source-drain opening 214 located on the common drain region IV; and an interlayer dielectric layer is formed on the common drain structure 2151 and the source structure 215.

[0062] Before forming the common drain structure 2151 and the source structure 215 , the substrate 200 at the bottom of the source / drain opening 214 is etched to form a shallow isolation trench (not shown in the figure); a shallow trench isolation structure (not shown in the figure) is formed in the shallow isolation trench.

[0063] The shallow isolation trench is used to isolate the transistor structures on the adjacent core region I and the input / output region II.

[0064] Please refer to Figure 14 , remove the pseudo gate structure to form the gate opening; remove all sacrificial layers through a removal modification process, form a plurality of first trenches 217 in the core area I, and form a plurality of second trenches 218 on the input and output area II.

[0065] In this embodiment, the process of removing all sacrificial layers includes one of a wet etching process and a dry etching process, or a combination of the two.

[0066] In a specific embodiment, the wet etching process parameters include: the etching solution includes at least two solutions of ammonia, hydrogen peroxide, acetic acid, and ammonium fluoride, and the mass concentration range of each solution is 0wt% to 30wt%, and the reaction temperature range is 0 degrees Celsius to 80 degrees Celsius.

[0067] In a specific embodiment, the process parameters of the dry etching process include: the etching gas includes at least three gases among fluorine, hydrogen, nitrogen, argon and ammonia, and the flow rate range of each gas is 0 mL / min to 2000 mL / min, the reaction pressure range is 0 mT to 3000 mT, the reaction temperature range is 0 degrees Celsius to 250 degrees Celsius, and the etching power range is 0 W to 1000 W.

[0068] Please refer to Figure 15 , forming a plurality of first gate structures in the first trench 217, and forming a plurality of second gate structures in the second trench 218; forming a gate material layer in the gate opening, wherein the top surface of the gate material layer is higher than the top surface of the interlayer dielectric layer; flattening the gate material layer until the top surface of the interlayer dielectric layer is exposed to form a gate structure 221.

[0069] The steps of forming the first gate structure and the second gate structure include: forming a gate dielectric material layer and a work function material layer located on the gate dielectric material layer in the first trench 217 and the second trench 218; etching the gate dielectric material layer and the work function material layer in the first trench 217 to form a first gate dielectric layer 2191 and a first work function layer 2201, and the first gate structure includes the first gate dielectric layer 2191 and the first work function layer 2201; etching the gate dielectric material layer and the work function material layer in the second trench 218 to form a second gate dielectric layer 219 and a second work function layer 220, and the second gate structure includes the second gate dielectric layer 219 and the second work function layer 220.

[0070] The gate dielectric material layer is made of tungsten, and the work function material layer is made of titanium nitride.

[0071] In this embodiment, the first gate dielectric layer 2191 and the second gate dielectric layer 219 function to adjust the threshold voltage of the MOS transistor. The thickness of the first gate dielectric layer 2191 and the second gate dielectric layer 219 depends on the threshold voltage required by the all-around gate device.

[0072] The thickness of the second gate structure is twice the thickness of the first gate structure.

[0073] In this embodiment, the thickness of the first gate dielectric layer 2191 ranges from 1 nanometer to 30 nanometers, and the thickness of the second gate dielectric layer 219 ranges from 2 nanometers to 60 nanometers.

[0074] In this embodiment, the number of the first gate structures is three, and the number of the second gate structures is two.

[0075] The gate structure 221 is made of metal.

[0076] In this embodiment, the gate structure 221 is made of tungsten.

[0077] In the above scheme, the first gate structure and the second gate structure are formed between several channel layers. In the technical scheme of the present invention, the thickness of the second trench 218 between the channel layers on the input and output region II is greater than the thickness of the first trench 217 between the channel layers on the core region I. Therefore, the thickness of the gate oxide in the second gate structure is greater than the thickness of the gate oxide in the first gate structure, avoiding the risk of opening formed by the second gate structure, making the second gate structure resistant to high voltage, thereby achieving the anti-breakdown effect of the transistor structure and improving the working performance of the semiconductor structure.

[0078] Please refer to Figures 10 to 15 The technical solution of the present invention also provides a semiconductor structure, including: a substrate 200, wherein the substrate 200 includes a core region I, an input-output region II, a source region III located on the sidewalls of the core region I and the input-output region II, and a common drain region IV located between the core region I and the input-output region II; a plurality of stacked second sacrificial layers 204, a first channel layer 205, a third sacrificial layer 206, a second channel layer 207, a fourth sacrificial layer 209, and a third channel layer 210 located on the core region I; and a plurality of stacked first sacrificial layers 203, a second sacrificial layer 204, a first channel layer 205, a third sacrificial layer 206, a fourth sacrificial layer 209, and a third channel layer 210 located on the input-output region II.

[0079] In this embodiment, the semiconductor structure further includes: a plurality of first trenches 217 located between the channel layers on the core region I, a first gate structure located within the first trenches 217, a second trench 218 located between the channel layers on the input-output region II, and a second gate structure located within the second trenches 218.

[0080] In this embodiment, the first gate structure includes: a first work function layer 2201 located in the first trench 217 and a first gate dielectric layer 2191 located on the side wall surface of the first work function layer 2201; the second gate structure includes: a second work function layer 220 located in the second trench and a second gate dielectric layer 219 located on the side wall surface, top surface and bottom surface of the second work function layer 220.

[0081] In this embodiment, the semiconductor structure further includes: source-drain openings 214 located on both sides of the core region I and the input-output region II, a source structure 215 located within the source-drain openings 214 on the source region III, and a common drain structure 2151 located within the source-drain openings 214 on the common drain region IV.

[0082] In this embodiment, the semiconductor structure further includes: several interlayer dielectric layers located on the top surface of the source structure 215 and the top surface of the common drain structure 2151, a gate structure located between adjacent interlayer dielectric layers, and an inner sidewall 212 located on the sidewall surface of the gate structure.

[0083] In this embodiment, the material of the first sacrificial layer 203 , the second sacrificial layer 204 , the third sacrificial layer 206 and the fourth sacrificial layer 209 includes silicon germanium; the material of the first channel layer 205 , the second channel layer 207 and the third channel layer 210 includes silicon.

[0084] In this embodiment, the thickness of the first trench 217 along the direction perpendicular to the substrate 200 is smaller than the thickness of the first trench 217 along the direction perpendicular to the substrate 200 .

[0085] In this embodiment, the semiconductor structure further includes a shallow trench isolation structure located between the adjacent first gate structure and the second gate structure.

[0086] In the above scheme, the device located on the input-output area II is a device for controlling input and output, that is, the device for controlling input and output needs to work under a high control voltage. In the technical solution of the present invention, a plurality of stacked first sacrificial layers 203, second sacrificial layers 204, first channel layers 205, third sacrificial layers 206, fourth sacrificial layers 209 and third channel layers 210 are formed on the input-output area II, wherein the first sacrificial layer 203 and the second sacrificial layer 204, the third sacrificial layer 206 and the fourth sacrificial layer 209 form a stacked composite sacrificial layer, and a plurality of stacked second sacrificial layers 204, first channel layers 205, third sacrificial layers 206, second channel layers 207, fourth sacrificial layers 209 and third channel layers are formed on the core area I. 210, so the composite sacrificial layer includes a stacked first sacrificial layer 203 and a second sacrificial layer 204 or a stacked third sacrificial layer 206 and a fourth sacrificial layer 209. Compared with forming several discrete second sacrificial layers 204 or third sacrificial layers 206 or fourth sacrificial layers 209 on the core area I, the thickness of the composite sacrificial layer on the input-output area II is greater than the thickness of the sacrificial layer on the core area I, that is, the thickness of the gate oxide in the device for controlling input and output formed subsequently is also greater than the thickness of the gate oxide in the device on the core area I. The function of the gate oxide is to adjust the threshold voltage of the transistor structure so that the second transistor structure can withstand high voltage, thereby achieving an anti-breakdown effect of the semiconductor structure and improving the working performance of the semiconductor structure.

[0087] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a core region, an input / output region, a source region located on sidewalls of the core region and the input / output region, and a common drain region located between the core region and the input / output region; forming a first sacrificial layer on the substrate; forming a first photoresist layer on the first sacrificial layer in the input / output region; Using the first photoresist layer as a mask, etching and removing the first sacrificial layer in the core area; forming a second sacrificial layer on the substrate and the first sacrificial layer in the input / output region; forming a first channel layer on the second sacrificial layer; forming a third sacrificial layer on the first channel layer; forming a second channel layer on the third sacrificial layer; forming a second photoresist layer on the second channel layer in the core region; Using the second photoresist layer as a mask, etching and removing the second channel layer in the input / output region; forming a fourth sacrificial layer on the second channel layer and the third sacrificial layer; forming a third channel layer on the fourth sacrificial layer; Repeat the above steps until several stacked second sacrificial layers, first channel layers, third sacrificial layers, second channel layers, fourth sacrificial layers and third channel layers are formed on the core area, and several stacked first sacrificial layers, second sacrificial layers, first channel layers, third sacrificial layers, fourth sacrificial layers and third channel layers are formed on the input and output area.

2. The method for forming a semiconductor structure according to claim 1, wherein: After forming the channel layer on the fourth sacrificial layer, the method further includes: All sacrificial layers are removed through a removal modification process, a plurality of first trenches are formed in the core area, and a plurality of second trenches are formed on the input and output area; a plurality of first gate structures are formed in the first trenches, and a plurality of second gate structures are formed in the second trenches.

3. The method for forming a semiconductor structure according to claim 2, wherein: The steps of forming the first gate structure and the second gate structure include: A gate dielectric material layer and a work function material layer located on the gate dielectric material layer are formed in the first trench and the second trench; the gate dielectric material layer and the work function material layer in the first trench are etched to form a first gate dielectric layer and a first work function layer, and the first gate structure includes the first gate dielectric layer and the first work function layer; the gate dielectric material layer and the work function material layer in the second trench are etched to form a second gate dielectric layer and a second work function layer, and the second gate structure includes the second gate dielectric layer and the second work function layer.

4. The method for forming a semiconductor structure according to claim 2, wherein: Before forming the first trench and the second trench, the method further includes: A plurality of separate dummy gates are formed on the top channel layer; inner sidewalls are formed on the sidewall surfaces of each dummy gate; using the dummy gates and the inner sidewalls as masks, all sacrificial layers and channel layers on the source region and the common drain region are etched until the substrate is exposed, thereby forming source-drain openings on both sides of the core region and the input-output region; a source structure is formed in the source-drain openings on the source region, and a common drain structure is formed in the source-drain openings on the common drain region.

5. The method for forming a semiconductor structure according to claim 4, wherein: After forming the common drain structure and the source structure, the method further includes: An interlayer dielectric layer is formed on the common drain structure and the source structure; the dummy gate structure is removed to form the gate opening, and a gate material layer is formed in the gate opening, wherein the top surface of the gate material layer is higher than the top surface of the interlayer dielectric layer; the gate material layer is flattened until the top surface of the interlayer dielectric layer is exposed to form a gate structure.

6. The method for forming a semiconductor structure according to claim 1, wherein: The method of forming the first sacrificial layer further includes: A third photoresist layer is formed on the surface of the substrate in the core area; and a first sacrificial layer is formed on the surface of the substrate in the input / output area using the third photoresist layer as a mask.

7. A semiconductor structure, characterized in that include: A substrate comprising a core region, an input / output region, a source region located on sidewalls of the core region and the input / output region, and a common drain region located between the core region and the input / output region; A plurality of stacked second sacrificial layers, a first channel layer, a third sacrificial layer, a second channel layer, a fourth sacrificial layer, and a third channel layer located on the core region; A plurality of stacked first sacrificial layers, a second sacrificial layer, a first channel layer, a third sacrificial layer, a fourth sacrificial layer and a third channel layer are located on the input / output region.

8. The semiconductor structure according to claim 7, wherein: Also includes: A plurality of first trenches are located between the channel layers on the core region, a first gate structure is located in the first trenches, a second trench is located between the channel layers on the input / output region, and a second gate structure is located in the second trenches.

9. The semiconductor structure according to claim 8, wherein: The first gate structure includes: a first work function layer located in a first trench and a first gate dielectric layer located on the sidewall surface of the first work function layer; the second gate structure includes: a second work function layer located in a second trench and a second gate dielectric layer located on the sidewall surface, top surface and bottom surface of the second work function layer.

10. The semiconductor structure according to claim 7, wherein: Also includes: The source-drain openings are located on both sides of the core region and the input-output region, the source structure is located in the source-drain openings on the source region, and the common drain structure is located in the source-drain openings on the common drain region.

11. The semiconductor structure according to claim 9, wherein: Also includes: A plurality of interlayer dielectric layers are located on the top surface of the source structure and the top surface of the common drain structure, a gate structure is located between adjacent interlayer dielectric layers, and an inner sidewall is located on the sidewall surface of the gate structure.

12. The semiconductor structure according to claim 7, wherein: The materials of the first sacrificial layer, the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer include silicon germanium; the materials of the first channel layer, the second channel layer and the third channel layer include silicon.

13. The semiconductor structure according to claim 8, wherein The thickness dimension of the first trench along the direction perpendicular to the substrate is smaller than the thickness dimension of the second trench along the direction perpendicular to the substrate.

Images