Array substrate, manufacturing method thereof and flat panel detector

Abstract

The invention belongs to the field of display, and particularly relates to an array substrate and a manufacturing method thereof and a flat panel detector, the array substrate comprises a substrate, and a first metal layer, a first semiconductor layer, a second metal layer, a gate insulation layer and a third metal layer which are sequentially formed on the substrate, the first metal layer comprises a drain electrode and a lower electrode of a photodiode, and the third metal layer comprises a drain electrode and a lower electrode of the photodiode. The lower electrode is in conductive connection with the drain electrode, the first semiconductor layer comprises a first semiconductor part, the first semiconductor part is located on the side, away from the substrate, of the drain electrode, the second metal layer comprises a source electrode, the source electrode is located on the side, away from the substrate, of the first semiconductor part, and the third metal layer comprises a grid electrode. The grid electrode is overlapped with the first semiconductor part. The drain electrode, the first semiconductor part and the source electrode are sequentially stacked on the substrate, so that the occupied area of the thin film transistor is reduced, the photosensitive area of the photodiode is increased, and the detection sensitivity of the flat panel detector is further improved.

Description

Technical Field

[0001] The present application belongs to the field of display, and specifically relates to an array substrate and a manufacturing method thereof, and a flat panel detector. Background Art

[0002] Flat X-ray Panel Detector (FPXD) based on Thin Film Transistor (TFT) technology is a crucial component in digital imaging technology. Due to its advantages such as fast imaging speed, good spatial and density resolution, high signal-to-noise ratio, and direct digital output, it has been widely used in industry, medicine, aviation and other fields.

[0003] The flat-panel detector includes the smallest detection unit composed of a thin-film transistor and a photodiode. The photodiode can convert visible light into an electrical signal. When the thin-film transistor is turned on, the electrical signal converted from visible light is output to the processor, which processes it to obtain image information.

[0004] The larger the photodiode's photosensitive area, the more sensitive it is. By increasing the photodiode's photosensitive area, the flat-panel detector's detection sensitivity and signal-to-noise ratio can be improved. However, the flat-panel detector's resolution limits the area occupied by the minimum detection unit, making it difficult to increase the photodiode's photosensitive area. Summary of the Invention

[0005] The purpose of the present application is to provide an array substrate and a manufacturing method thereof, and a flat panel detector, so as to increase the photosensitivity area of ​​the photodiode and thereby improve the detection sensitivity of the flat panel detector.

[0006] In order to achieve the above-mentioned object, the present application provides an array substrate, including a base substrate, and the array substrate further includes:

[0007] A first metal layer is formed on one side of the substrate, the first metal layer includes a drain electrode and a lower electrode of the photodiode, and the lower electrode is conductively connected to the drain electrode;

[0008] A first semiconductor layer is formed on a side of the first metal layer away from the substrate, the first semiconductor layer includes a first semiconductor portion, and the first semiconductor portion is located on a side of the drain away from the substrate;

[0009] a second metal layer formed on a side of the first semiconductor layer away from the substrate, the second metal layer comprising a source electrode, the source electrode being located on a side of the first semiconductor portion away from the substrate;

[0010] A gate insulating layer is formed on a side of the source electrode away from the substrate;

[0011] A third metal layer is formed on the side of the gate insulating layer away from the substrate, the third metal layer includes a gate, the gate at least partially surrounds the first semiconductor portion, and the distance from the side of the gate close to the substrate to the substrate is smaller than the distance from the side of the first semiconductor portion away from the substrate to the substrate.

[0012] Optionally, the first semiconductor layer is made of an intrinsic semiconductor, and the first semiconductor layer further includes a second semiconductor portion, and the second semiconductor portion is located on a side of the lower electrode away from the substrate;

[0013] The array substrate further includes an upper electrode formed on a side of the second semiconductor portion away from the base substrate. The upper electrode is made of a transparent conductive material. The photodiode includes the lower electrode, the second semiconductor portion and the upper electrode.

[0014] Optionally, the array substrate also includes a second semiconductor layer, which is formed between the first semiconductor layer and the first metal layer. The manufacturing material of the second semiconductor layer includes an N-type doped semiconductor. The second semiconductor layer includes a third semiconductor portion and a fourth semiconductor portion. The third semiconductor portion is located between the first semiconductor portion and the drain, and the fourth semiconductor portion is located between the second semiconductor portion and the lower electrode.

[0015] Optionally, the array substrate also includes a third semiconductor layer, which is formed on the side of the first semiconductor layer away from the base substrate. The third semiconductor layer includes a fifth semiconductor portion and a sixth semiconductor portion. The fifth semiconductor portion is located between the source and the first semiconductor portion, and the sixth semiconductor portion is located between the upper electrode and the second semiconductor portion. The material of the fifth semiconductor portion includes an N-type doped semiconductor, and the material of the sixth semiconductor portion includes a P-type doped semiconductor.

[0016] Optionally, the gate further includes a hollow area, and the orthographic projection of the source electrode on the substrate is at least partially located in the hollow area.

[0017] Optionally, the array substrate further includes a first passivation layer, a first flat layer, a bias electrode, a second passivation layer and a second flat layer, the first passivation layer is formed on the side of the third metal layer and the photodiode away from the base substrate, the first flat layer is formed on the side of the first passivation layer away from the base substrate, the bias electrode is formed on the side of the first flat layer away from the base substrate, and is connected to the upper electrode of the photodiode through a via hole passing through the first flat layer and the first passivation layer, the bias electrode is made of a transparent conductive material, and the second passivation layer and the second flat layer are sequentially formed on the side of the bias electrode and the first flat layer away from the base substrate.

[0018] The present application further provides a method for manufacturing an array substrate, wherein the method is used to manufacture the array substrate, and the method comprises:

[0019] Forming a first metal layer on one side of the base substrate, wherein the first metal layer includes a drain electrode and a lower electrode of the photodiode, and the lower electrode is conductively connected to the drain electrode;

[0020] forming a first semiconductor layer on a side of the first metal layer away from the base substrate, wherein the first semiconductor layer includes a first semiconductor portion, and the first semiconductor portion is located on a side of the drain away from the base substrate;

[0021] forming a second metal layer on a side of the first semiconductor layer away from the base substrate, wherein the second metal layer includes a source electrode, and the source electrode is located on a side of the first semiconductor portion away from the base substrate;

[0022] forming a gate insulating layer on a side of the source electrode away from the substrate;

[0023] A third metal layer is formed on the side of the gate insulation layer away from the base substrate, the third metal layer includes a gate, the gate at least partially surrounds the first semiconductor portion, and the distance from the side of the gate close to the base substrate to the base substrate is smaller than the distance from the side of the first semiconductor portion away from the base substrate to the base substrate.

[0024] Optionally, a second semiconductor portion is formed simultaneously with the formation of the first semiconductor portion, and the second semiconductor portion is located on a side of the lower electrode away from the base substrate.

[0025] Optionally, the method for manufacturing the array substrate further includes:

[0026] Before forming the first semiconductor layer, a second semiconductor layer is formed on a side of the first metal layer away from the base substrate, wherein the second semiconductor layer is made of an N-type doped semiconductor, and the second semiconductor layer includes a third semiconductor portion and a fourth semiconductor portion, wherein the third semiconductor portion is located between the first semiconductor portion and the drain electrode, and the fourth semiconductor portion is located between the second semiconductor portion and the lower electrode; and / or

[0027] The photodiode includes the lower electrode, the second semiconductor portion, and an upper electrode provided on a side of the second semiconductor portion away from the base substrate. The method for manufacturing the array substrate further includes:

[0028] An intrinsic semiconductor material layer is formed on the side of the first metal layer away from the substrate, and the intrinsic semiconductor material layer is patterned to form a first semiconductor structure and a second semiconductor structure, the first semiconductor structure is located on the side of the drain away from the substrate, and the second semiconductor structure is located on the side of the lower electrode away from the substrate; the first semiconductor structure is subjected to N-type doping treatment so that part of the first semiconductor structure forms the fifth semiconductor portion and the remaining part of the first semiconductor structure forms the first semiconductor portion; the second semiconductor structure is subjected to P-type doping treatment so that part of the second semiconductor structure forms the sixth semiconductor portion and the remaining part of the second semiconductor structure forms the second semiconductor portion.

[0029] The present application also provides a flat panel detector, comprising:

[0030] the array substrate;

[0031] A scintillator is formed on one side of the array substrate.

[0032] The array substrate, its manufacturing method, and flat panel detector disclosed in this application have the following beneficial effects:

[0033] In the present application, an array substrate includes a base substrate, and a first metal layer, a first semiconductor layer, a second metal layer, a gate insulating layer, and a third metal layer sequentially formed on the base substrate. The first metal layer includes a drain electrode and a lower electrode of a photodiode, the lower electrode being conductively connected to the drain electrode. The first semiconductor layer includes a first semiconductor portion, the first semiconductor portion being located on a side of the drain electrode away from the base substrate. The second metal layer includes a source electrode, the source electrode being located on a side of the first semiconductor portion away from the base substrate. The third metal layer includes a gate electrode, the gate electrode at least partially surrounding the first semiconductor portion, and the gate electrode and the first semiconductor portion overlapping in the thickness direction of the array substrate. The gate electrode, the first semiconductor portion, the drain electrode, and the source electrode constitute a thin film transistor. Since the drain electrode, the first semiconductor portion, and the source electrode are sequentially stacked on the base substrate, the occupied area of ​​the thin film transistor is reduced, the photosensitive area of ​​the photodiode is increased, and the detection sensitivity of the flat panel detector is thereby improved.

[0034] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by practice of the present application.

[0035] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0037] Figure 1 Schematic diagram of the structure of the array substrate in the embodiment of the present application.

[0038] Figure 2 Schematic diagram of the structure of the array substrate in the embodiment of the present application.

[0039] Figure 3 It is a flow chart of the method for manufacturing the array substrate in three examples of the present application.

[0040] Figure 4 It is a schematic diagram of the structure of the flat panel detector in the fifth example of the present application.

[0041] Description of reference numerals:

[0042] 10. array substrate; 20. scintillator;

[0043] 100. Base substrate;

[0044] 210, first metal layer; 211, drain; 212, lower electrode; 220, second metal layer; 221, source; 230, third metal layer; 231, gate; 2311, hollow area; 232, light shielding portion;

[0045] 310, first semiconductor layer; 311, first semiconductor portion; 312, second semiconductor portion; 320, second semiconductor layer; 321, third semiconductor portion; 322, fourth semiconductor portion; 330, third semiconductor layer; 331, fifth semiconductor portion; 332, sixth semiconductor portion;

[0046] 410, gate insulating layer; 420, first passivation layer; 430, first planarization layer; 440, second passivation layer; 450, second planarization layer;

[0047] 510, upper electrode; 520, bias electrode. DETAILED DESCRIPTION

[0048] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0049] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0050] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0051] Example 1

[0052] See also Figure 1As shown, in this embodiment, the array substrate 10 includes a base substrate 100, a first metal layer 210, a first semiconductor layer 310, a second metal layer 220, a gate insulating layer 410, and a third metal layer 230. The base substrate 100 includes a transparent substrate such as a glass substrate or a polyimide substrate. The first metal layer 210 is formed on one side of the base substrate 100 and includes a drain electrode 211 and a lower electrode 212 of the photodiode. The lower electrode 212 is conductively connected to the drain electrode 211.

[0053] The first semiconductor layer 310 is formed on the side of the first metal layer 210 away from the substrate 100. The first semiconductor layer 310 includes a first semiconductor portion 311, which is located on the side of the drain 211 away from the substrate 100. The second metal layer 220 is formed on the side of the first semiconductor layer 310 away from the substrate 100. The second metal layer 220 includes a source electrode 221, which is located on the side of the first semiconductor portion 311 away from the substrate 100. In other words, the drain 211, the first semiconductor portion 311, and the source electrode 221 are stacked in sequence on the substrate 100.

[0054] A gate insulating layer 410 is formed on the side of the source electrode 221 away from the substrate 100. The gate insulating layer 410 covers the source electrode 221 and at least a portion of the first metal layer 210. A third metal layer 230 is formed on the side of the gate insulating layer 410 away from the substrate 100. The third metal layer 230 includes a gate electrode 231. The gate electrode 231 at least partially surrounds the first semiconductor portion 311. The distance between the gate electrode 231 and the substrate 100 is shorter than the distance between the gate electrode 231 and the first semiconductor portion 311 and the first semiconductor portion 311. In other words, the gate electrode 231 and the first semiconductor portion 311 overlap in the thickness direction of the array substrate 10. The gate electrode 231, the first semiconductor portion 311, the drain electrode 211, and the source electrode 221 constitute a thin film transistor.

[0055] The larger the photodiode's photosensitive area, the more sensitive it is. By increasing the photodiode's photosensitive area, the flat-panel detector's detection sensitivity and signal-to-noise ratio can be improved. However, the flat-panel detector's resolution limits the area occupied by the minimum detection unit, making it difficult to increase the photodiode's photosensitive area.

[0056] In this embodiment, the array substrate 10 includes a base substrate 100, and a first metal layer 210, a first semiconductor layer 310, a second metal layer 220, a gate insulating layer 410 and a third metal layer 230 formed in sequence on the base substrate 100. The first metal layer 210 includes a drain 211 and a lower electrode 212 of the photodiode, and the lower electrode 212 is conductively connected to the drain 211. The first semiconductor layer 310 includes a first semiconductor portion 311, and the first semiconductor portion 311 is located on the side of the drain 211 away from the base substrate 100. The second metal layer 220 includes a source 221, and the source 221 is located on the side of the first semiconductor portion 311 away from the base substrate 100. The third metal layer 230 includes a gate 231, and the gate 231 at least partially surrounds the first semiconductor portion 311. In the thickness direction of the array substrate 10, the gate 231 overlaps with the first semiconductor portion 311. The gate 231, the first semiconductor portion 311, the drain 211 and the source 221 constitute a thin film transistor. Since the drain 211, the first semiconductor portion 311 and the source 221 are stacked in sequence on the base substrate 100, the occupied area of ​​the thin film transistor is reduced, the photosensitivity area of ​​the photodiode is increased, and the detection sensitivity of the flat panel detector is improved.

[0057] Furthermore, the drain electrode 211, the first semiconductor portion 311, and the source electrode 221 are sequentially stacked on the base substrate 100, increasing the relative area of ​​the drain electrode 211, the source electrode 221, and the first semiconductor portion 311. This increases electron tunneling capability and improves the electrical characteristics of the thin-film transistor. The photodiode's lower electrode 212 and the thin-film transistor's drain electrode 211 are co-located, reducing the manufacturing cost of the array substrate 10.

[0058] In some embodiments, the first semiconductor layer 310 is made of an intrinsic semiconductor, such as amorphous silicon, polycrystalline silicon, or oxide. The first semiconductor layer 310 also includes a second semiconductor portion 312, which is located on the side of the lower electrode 212 away from the base substrate 100. The array substrate 10 also includes an upper electrode 510, which is formed on the side of the second semiconductor portion 312 away from the base substrate 100. The upper electrode 510 is made of a transparent conductive material, such as indium tin oxide (ITO). The photodiode includes the lower electrode 212, the second semiconductor portion 312, and the upper electrode 510.

[0059] The second semiconductor portion 312 of the photodiode and the first semiconductor portion 311 of the thin film transistor are disposed in the same layer, which can reduce the manufacturing cost of the array substrate 10 .

[0060] It should be understood that in this application, "same-layer setting" refers to using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process, that is, one patterning process corresponds to one mask.

[0061] In some embodiments, the array substrate 10 further includes a second semiconductor layer 320, which is formed between the first semiconductor layer 310 and the first metal layer 210. The second semiconductor layer 320 is made of an N-type doped semiconductor and includes a third semiconductor portion 321 and a fourth semiconductor portion 322. The third semiconductor portion 321 is located between the first semiconductor portion 311 and the drain electrode 211, and the fourth semiconductor portion 322 is located between the second semiconductor portion 312 and the lower electrode 212. The third semiconductor portion 321 enables ohmic contact to be formed between the drain electrode 211 and the first semiconductor portion 311, thereby reducing contact resistance.

[0062] The third semiconductor portion 321 of the photodiode is provided in the same layer as an ohmic contact layer of the thin film transistor, which can reduce the manufacturing cost of the array substrate 10 .

[0063] In some embodiments, the array substrate 10 further includes a third semiconductor layer 330, which is formed on a side of the first semiconductor layer 310 away from the base substrate 100. The third semiconductor layer 330 includes a fifth semiconductor portion 331 and a sixth semiconductor portion 332. The fifth semiconductor portion 331 is located between the source electrode 221 and the first semiconductor portion 311, and the sixth semiconductor portion 332 is located between the upper electrode 510 and the second semiconductor portion 312. The fifth semiconductor portion 331 is made of an N-type doped semiconductor, and the sixth semiconductor portion 332 is made of a P-type doped semiconductor.

[0064] The fourth semiconductor portion 322 of the photodiode is made of N-type doped semiconductor material, the second semiconductor portion 312 of the photodiode is made of intrinsic semiconductor material, and the sixth semiconductor portion 332 of the photodiode is made of P-type doped semiconductor. That is, the photoelectric conversion layer of the photodiode can adopt a PIN structure.

[0065] The fifth semiconductor portion 331 can form an ohmic contact between the source electrode 221 and the first semiconductor portion 311, thereby reducing contact resistance. The sixth semiconductor portion 332 of the photodiode is provided in the same layer as another ohmic contact layer of the thin film transistor, which can reduce the manufacturing cost of the array substrate 10.

[0066] It should be noted that the photoelectric conversion layer of the photodiode may adopt a PIN structure, but is not limited thereto. The photoelectric conversion layer of the photodiode may also adopt a PN structure. The photoelectric conversion layer of the PN structure does not include the second semiconductor portion 312, and the specific structure may depend on the circumstances.

[0067] In some embodiments, the gate 231 further includes a hollow region 2311 , and an orthographic projection of the source 221 on the base substrate 100 is at least partially located within the hollow region 2311 .

[0068] When the gate 231 further includes a hollow area 2311 , the orthographic projection of the source 221 on the third metal layer 230 partially overlaps or does not overlap with the gate 231 . This design can reduce or eliminate the capacitance formed between the gate 231 and the source 221 , thereby improving the electrical characteristics of the thin film transistor.

[0069] In some embodiments, the array substrate 10 further includes a first passivation layer 420, a first planarization layer 430, a bias electrode 520, a second passivation layer 440, and a second planarization layer 450. The first passivation layer 420 is formed on the side of the third metal layer 230 and the photodiode away from the base substrate 100, and the first planarization layer 430 is formed on the side of the first passivation layer 420 away from the base substrate 100. The bias electrode 520 is formed on the side of the first planarization layer 430 away from the base substrate 100 and is connected to the top electrode 510 of the photodiode via a via extending through the first planarization layer 430 and the first passivation layer 420. The bias electrode 520 is made of a transparent conductive material, such as indium tin oxide. The second passivation layer 440 and the second planarization layer 450 are sequentially formed on the side of the bias electrode 520 and the first planarization layer 430 away from the base substrate 100.

[0070] The drain 211 , the first semiconductor portion 311 and the source 221 are sequentially stacked on the base substrate 100 . The source 221 can block the channel of the thin film transistor. Therefore, the bias electrode 520 can be made of a transparent conductive material to further increase the photosensitivity area of ​​the photodiode.

[0071] It should be noted that the bias electrode 520 can be made of a transparent conductive material, but is not limited thereto. The bias electrode 520 can also be made of a metal material, depending on the specific situation.

[0072] Example 2

[0073] The difference between the second embodiment and the first embodiment lies in the different structures of the thin film transistors.

[0074] See also Figure 2 As shown, in this embodiment, the array substrate 10 includes a base substrate 100, a first metal layer 210, a second metal layer 220, a third metal layer 230, a first semiconductor layer 310, a second semiconductor layer 320, a third semiconductor layer 330, a gate insulating layer 410, a first passivation layer 420, a first flat layer 430, a second passivation layer 440, a second flat layer 450 and an upper electrode 510.

[0075] A first metal layer 210 is formed on the side of the substrate 100 and includes a gate electrode 231 and a lower electrode 212. A gate insulating layer 410 is formed on the side of the first metal layer 210 away from the substrate 100, covering the edges of the gate electrode 231 and the lower electrode 212. A first semiconductor layer 310 is formed on the side of the gate insulating layer 410 away from the substrate 100 and includes a first semiconductor portion 311 and a second semiconductor portion 312. The first semiconductor portion 311 is located above the gate electrode 231, and the second semiconductor portion 312 is located above the lower electrode 212. A second metal layer 220 is formed on the side of the first semiconductor layer 310 away from the substrate 100 and includes a drain electrode 211 and a source electrode 221. The drain electrode 211 and the source electrode 221 are spaced apart on the side of the first semiconductor portion 311 away from the substrate 100. The drain electrode 211 is conductively connected to the lower electrode 212 through the gate insulating layer 410. The gate electrode 231 , the first semiconductor portion 311 , the drain electrode 211 , and the source electrode 221 constitute a thin film transistor.

[0076] The second semiconductor layer 320 is formed between the lower electrode 212 and the second semiconductor portion 312 and includes a fourth semiconductor portion 322. The third semiconductor layer 330 is formed on the side of the first semiconductor layer 310 away from the substrate 100 and includes a third semiconductor portion 321, a fifth semiconductor portion 331, and a sixth semiconductor portion 332. The third semiconductor portion 321 is located between the drain 211 and the first semiconductor portion 311, the fifth semiconductor portion 331 is located between the source 221 and the first semiconductor portion 311, and the sixth semiconductor portion 332 is located on the side of the second semiconductor portion 312 away from the substrate 100. The third and fifth semiconductor portions 321 and 331 can be made of an N-type doped semiconductor material, while the sixth semiconductor portion 332 can be made of a P-type doped semiconductor material. The photoelectric conversion layer of the photodiode includes the fourth semiconductor portion 322, the second semiconductor portion 312, and the sixth semiconductor portion 332 stacked in sequence, i.e., the photoelectric conversion layer adopts a PIN structure.

[0077] It should be noted that the third semiconductor portion 321 and the fifth semiconductor portion 331 can be arranged in the same layer as the sixth semiconductor portion 332, but is not limited to this. The third semiconductor portion 321, the fifth semiconductor portion 331 and the sixth semiconductor portion 332 can also be made separately. The third semiconductor portion 321 and the fifth semiconductor portion 331 are made of N-type doped semiconductor material, and the sixth semiconductor portion 332 is made of P-type doped semiconductor material. The specific details may depend on the circumstances.

[0078] The upper electrode 510 is formed on the side of the sixth semiconductor portion 332 away from the base substrate 100. The orthographic projection of the upper electrode 510 on the base substrate 100 is located within the orthographic projection of the photoelectric conversion layer on the base substrate 100, and the orthographic projection of the photoelectric conversion layer on the base substrate 100 is located within the orthographic projection of the lower electrode 212 on the base substrate 100. The first passivation layer 420 is formed on the side of the thin film transistor and photodiode away from the base substrate 100, and the first planarization layer 430 is formed on the side of the first passivation layer 420 away from the base substrate 100.

[0079] The third metal layer 230 is formed on the side of the first planar layer 430 away from the substrate 100. The third metal layer 230 includes a bias electrode 520 and a light shielding portion 232. The bias electrode 520 passes through the first planar layer 430 and the first passivation layer 420 and is conductively connected to the top electrode 510. The light shielding portion 232 is located above the first semiconductor portion 311 and is used to shield the first semiconductor portion 311 between the drain electrode 211 and the source electrode 221. The second passivation layer 440 and the second planar layer 450 are sequentially formed on the side of the third metal layer 230 and the first planar layer 430 away from the substrate 100.

[0080] Part of the film layers of the thin film transistor and the photodiode are arranged on the same layer, which can reduce the manufacturing cost of the array substrate 10.

[0081] Example 3

[0082] This application also provides a method for manufacturing an array substrate 10, which is used to manufacture the array substrate 10 disclosed in the first embodiment. Figure 1 and Figure 3 As shown, the manufacturing method of the array substrate 10 includes:

[0083] S100: forming a first metal layer 210 on one side of the base substrate 100, wherein the first metal layer 210 includes a drain electrode 211 and a lower electrode 212 of a photodiode, wherein the lower electrode 212 is conductively connected to the drain electrode 211;

[0084] S200: forming a first semiconductor layer 310 on a side of the first metal layer 210 away from the base substrate 100, wherein the first semiconductor layer 310 includes a first semiconductor portion 311, and the first semiconductor portion 311 is located on a side of the drain 211 away from the base substrate 100;

[0085] S300: forming a second metal layer 220 on a side of the first semiconductor layer 310 away from the substrate 100, wherein the second metal layer 220 includes a source electrode 221, and the source electrode 221 is located on a side of the first semiconductor portion 311 away from the substrate 100;

[0086] S400: forming a gate insulating layer 410 on a side of the source electrode 221 away from the substrate 100;

[0087] S500: A third metal layer 230 is formed on the side of the gate insulating layer 410 away from the base substrate 100. The third metal layer 230 includes a gate 231. The gate 231 at least partially surrounds the first semiconductor portion 311. The distance from the side of the gate 231 close to the base substrate 100 to the base substrate 100 is less than the distance from the side of the first semiconductor portion 311 away from the base substrate 100 to the base substrate 100.

[0088] The lower electrode 212 of the photodiode and the drain electrode 211 of the thin film transistor are disposed on the same layer, which can reduce the manufacturing cost of the array substrate 10. At the same time, because the lower electrode 212 and the drain electrode 211 are located on the same metal structure layer, they do not need to be electrically connected through vias, which can reduce the distance between the photodiode and the thin film transistor, thereby further increasing the photosensitive area of ​​the photodiode.

[0089] In some embodiments, the method for manufacturing the array substrate 10 further includes:

[0090] The second semiconductor portion 312 is formed simultaneously with the formation of the first semiconductor portion 311 . The second semiconductor portion 312 is located on a side of the lower electrode 212 away from the base substrate 100 .

[0091] The second semiconductor portion 312 of the photodiode and the first semiconductor portion 311 of the thin film transistor are arranged in the same layer, which can reduce the manufacturing cost of the array substrate 10 and reduce damage to the semiconductor portion of the thin film transistor during the etching process of the photodiode.

[0092] In some embodiments, the method for manufacturing the array substrate 10 further includes:

[0093] After the third metal layer 230 is formed, an upper electrode 510 is formed on the side of the second semiconductor portion 312 away from the base substrate 100, and then a first passivation layer 420 and a first flat layer 430 are formed in sequence. Then, a bias electrode 520 is formed on the side of the first flat layer 430 away from the base substrate 100. The bias electrode 520 passes through the first flat layer 430 and the first passivation layer 420 to be conductively connected to the upper electrode 510. Finally, a second passivation layer 440 and a second flat layer 450 are formed in sequence to cover the bias electrode 520 and the first flat layer 430.

[0094] The third metal layer 230 and the upper electrode 510 may be manufactured separately, but are not limited thereto. The third metal layer 230 and the upper electrode 510 may also be formed in one patterning process using a grayscale mask, depending on the specific circumstances.

[0095] The third metal layer 230 and the upper electrode 510 are manufactured using a single patterning process, which can reduce the manufacturing cost of the array substrate 10 .

[0096] In some embodiments, the method for manufacturing the array substrate 10 further includes:

[0097] Before forming the first semiconductor layer 310, a second semiconductor layer 320 is formed on the side of the first metal layer 210 away from the base substrate 100. The manufacturing material of the second semiconductor layer 320 includes an N-type doped semiconductor. The second semiconductor layer 320 includes a third semiconductor portion 321 and a fourth semiconductor portion 322. The third semiconductor portion 321 is located between the first semiconductor portion 311 and the drain 211, and the fourth semiconductor portion 322 is located between the second semiconductor portion 312 and the lower electrode 212.

[0098] The fourth semiconductor portion 322 of the photodiode is disposed in the same layer as an ohmic contact layer of the thin film transistor, which can reduce the manufacturing cost of the array substrate 10 .

[0099] In some embodiments, before forming the second metal layer 220 and the upper electrode 510 , the method for manufacturing the array substrate 10 further includes:

[0100] An intrinsic semiconductor material layer is formed on a side of the first metal layer 210 away from the base substrate 100, and the intrinsic semiconductor material layer is patterned to form a first semiconductor structure and a second semiconductor structure, wherein the first semiconductor structure is located on a side of the drain 211 away from the base substrate 100, and the second semiconductor structure is located on a side of the lower electrode 212 away from the base substrate 100;

[0101] The first semiconductor structure is subjected to N-type doping treatment and the doping depth is controlled so that a portion of the first semiconductor structure forms the fifth semiconductor portion 331 and the remaining portion of the first semiconductor structure forms the first semiconductor portion 311; the second semiconductor structure is subjected to P-type doping treatment and the doping depth is controlled so that a portion of the second semiconductor structure forms the sixth semiconductor portion 332 and the remaining portion of the second semiconductor structure forms the second semiconductor portion 312.

[0102] Two intrinsic semiconductor structures are first formed, and then one intrinsic semiconductor structure is formed into the fifth semiconductor portion 331 and the first semiconductor portion 311 by doping, and the other intrinsic semiconductor structure is formed into the sixth semiconductor portion 332 and the second semiconductor portion 312 , which can reduce the production cost of the array substrate 10 .

[0103] In some embodiments, one or more of the second semiconductor portion 312 , the fourth semiconductor portion 322 , and the sixth semiconductor portion 332 are formed after the second metal layer 220 .

[0104] When etching the photoelectric conversion layer of the photodiode, the second metal layer 220 can block the channel of the thin film transistor, thereby preventing the leakage of the thin film transistor from increasing, thereby improving the signal-to-noise ratio and image display quality of the detector backplane.

[0105] Example 4

[0106] This application also provides a method for manufacturing an array substrate 10, which is used to manufacture the array substrate 10 disclosed in the second embodiment. Figure 2 As shown, the manufacturing method of the array substrate 10 includes:

[0107] A first metal layer 210 is formed on one side of the array substrate 10 . The first metal layer 210 includes a gate electrode 231 and a lower electrode 212 that are spaced apart.

[0108] A gate insulating layer 410 is formed on the side of the first metal layer 210 away from the base substrate 100. The center area of ​​the lower electrode 212 is exposed on the gate insulating layer 410. The fourth semiconductor portion 322 is formed on the side of the lower electrode 212 away from the base substrate 100. Alternatively, the fourth semiconductor portion 322 may be first formed on the side of the lower electrode 212 away from the base substrate 100, and then the gate insulating layer 410 is formed to expose the fourth semiconductor portion 322. In other embodiments, the gate 231, the lower electrode 212, and the fourth semiconductor portion 322 may be formed in a single patterning process using a grayscale mask to reduce the manufacturing cost of the array substrate 10.

[0109] A first semiconductor layer 310 is formed on the side of the gate insulating layer 410 away from the base substrate 100. The first semiconductor layer 310 includes a first semiconductor portion 311 and a second semiconductor portion 312. The first semiconductor portion 311 is located above the gate 231, and the second semiconductor portion 312 is located above the fourth semiconductor portion 322. The first semiconductor portion 311 and the second semiconductor portion 312 are fabricated using the same photomask process, and grayscale masking can be used to achieve different thicknesses of the first semiconductor portion 311 and the second semiconductor portion 312.

[0110] A third semiconductor layer 330 is formed on the side of the first semiconductor portion 311 away from the substrate 100. The third semiconductor layer 330 includes a third semiconductor portion 321, a fifth semiconductor portion 331, and a sixth semiconductor portion 332. The third semiconductor portion 321 is located between the drain 211 and the first semiconductor portion 311, the fifth semiconductor portion 331 is located between the source 221 and the first semiconductor portion 311, and the sixth semiconductor portion 332 is located on the side of the second semiconductor portion 312 away from the substrate 100. The third semiconductor portion 321 and the fifth semiconductor portion 331 can be made of an N-type doped semiconductor material, and the sixth semiconductor portion 332 can be made of a P-type doped semiconductor material.

[0111] A drain electrode 211, a source electrode 221, and a top electrode 510 are formed on the side of the third semiconductor layer 330 away from the substrate 100. The drain electrode 211, the source electrode 221, and the top electrode 510 can be formed in a single patterning process using a grayscale mask. Finally, a first passivation layer 420, a first planarization layer 430, a third metal layer 230, a second passivation layer 440, and a second planarization layer 450 are sequentially formed.

[0112] Among them, when forming the first semiconductor layer 310 and the third semiconductor layer 330, an intrinsic semiconductor material layer can also be formed first, and then the intrinsic semiconductor material layer can be patterned to form two semiconductor structures. The semiconductor structure above the gate 231 is subjected to N-type doping treatment to control the doping depth to form the third semiconductor part 321, the fifth semiconductor part 331 and the first semiconductor part 311; the semiconductor structure above the fourth semiconductor part 322 is subjected to P-type doping treatment to control the doping depth to form the sixth semiconductor part 332 and the second semiconductor part 312.

[0113] Example 5

[0114] This application also provides a flat panel detector, see Figure 4 As shown, the flat panel detector includes the array substrate 10 disclosed in the first or second embodiment and a scintillator 20 , and the scintillator 20 is formed on one side of the array substrate 10 .

[0115] The flat panel detector includes an array substrate 10, which includes a base substrate 100, and a first metal layer 210, a first semiconductor layer 310, a second metal layer 220, a gate insulating layer 410 and a third metal layer 230 formed in sequence on the base substrate 100. The first metal layer 210 includes a drain 211 and a lower electrode 212 of a photodiode, and the lower electrode 212 is conductively connected to the drain 211. The first semiconductor layer 310 includes a first semiconductor portion 311, which is located on a side of the drain 211 away from the base substrate 100. The second metal layer 220 includes a source 221, which is located on a side of the first semiconductor portion 311 away from the base substrate 100. The third metal layer 230 includes a gate 231, which at least partially surrounds the first semiconductor portion 311. In the thickness direction of the array substrate 10, the gate 231 overlaps with the first semiconductor portion 311. The gate 231, the first semiconductor portion 311, the drain 211 and the source 221 constitute a thin film transistor. Since the drain 211, the first semiconductor portion 311 and the source 221 are stacked in sequence on the base substrate 100, the occupied area of ​​the thin film transistor is reduced, the photosensitivity area of ​​the photodiode is increased, and the detection sensitivity of the flat panel detector is improved.

[0116] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified with "first," "second," etc., may explicitly or implicitly include one or more of such features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0117] In this application, unless otherwise specified or limited, terms such as "assembly" and "connection" should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0118] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0119] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. An array substrate, comprising a base substrate, characterized in that: The array substrate further includes: A first metal layer is formed on one side of the substrate, the first metal layer includes a drain electrode and a lower electrode of the photodiode, and the lower electrode is conductively connected to the drain electrode; A first semiconductor layer is formed on a side of the first metal layer away from the substrate, the first semiconductor layer includes a first semiconductor portion, and the first semiconductor portion is located on a side of the drain away from the substrate; a second metal layer formed on a side of the first semiconductor layer away from the substrate, the second metal layer comprising a source electrode, the source electrode being located on a side of the first semiconductor portion away from the substrate; A gate insulating layer is formed on a side of the source electrode away from the substrate; A third metal layer is formed on the side of the gate insulating layer away from the substrate, the third metal layer includes a gate, the gate at least partially surrounds the first semiconductor portion, and the distance from the side of the gate close to the substrate to the substrate is smaller than the distance from the side of the first semiconductor portion away from the substrate to the substrate.

2. The array substrate according to claim 1, wherein: The first semiconductor layer is made of an intrinsic semiconductor, and the first semiconductor layer further includes a second semiconductor portion, and the second semiconductor portion is located on a side of the lower electrode away from the substrate; The array substrate further includes an upper electrode formed on a side of the second semiconductor portion away from the base substrate. The upper electrode is made of a transparent conductive material. The photodiode includes the lower electrode, the second semiconductor portion and the upper electrode.

3. The array substrate according to claim 2, wherein: The array substrate also includes a second semiconductor layer, which is formed between the first semiconductor layer and the first metal layer. The material of the second semiconductor layer includes an N-type doped semiconductor. The second semiconductor layer includes a third semiconductor portion and a fourth semiconductor portion. The third semiconductor portion is located between the first semiconductor portion and the drain, and the fourth semiconductor portion is located between the second semiconductor portion and the lower electrode.

4. The array substrate according to claim 2, wherein: The array substrate also includes a third semiconductor layer, which is formed on a side of the first semiconductor layer away from the base substrate. The third semiconductor layer includes a fifth semiconductor portion and a sixth semiconductor portion. The fifth semiconductor portion is located between the source and the first semiconductor portion, and the sixth semiconductor portion is located between the upper electrode and the second semiconductor portion. The material of the fifth semiconductor portion includes an N-type doped semiconductor, and the material of the sixth semiconductor portion includes a P-type doped semiconductor.

5. The array substrate according to claim 1, wherein: The gate further includes a hollow region, and the orthographic projection of the source electrode on the substrate is at least partially located in the hollow region.

6. The array substrate according to claim 1, wherein: The array substrate also includes a first passivation layer, a first flat layer, a bias electrode, a second passivation layer and a second flat layer. The first passivation layer is formed on the side of the third metal layer and the photodiode away from the base substrate. The first flat layer is formed on the side of the first passivation layer away from the base substrate. The bias electrode is formed on the side of the first flat layer away from the base substrate and is connected to the upper electrode of the photodiode through a via hole penetrating the first flat layer and the first passivation layer. The bias electrode is made of a transparent conductive material. The second passivation layer and the second flat layer are sequentially formed on the side of the bias electrode and the first flat layer away from the base substrate.

7. A method for manufacturing an array substrate, characterized in that: The method for manufacturing the array substrate is used to manufacture the array substrate according to any one of claims 1 to 6, and the method for manufacturing the array substrate includes: Forming a first metal layer on one side of the base substrate, wherein the first metal layer includes a drain electrode and a lower electrode of the photodiode, and the lower electrode is conductively connected to the drain electrode; forming a first semiconductor layer on a side of the first metal layer away from the base substrate, wherein the first semiconductor layer includes a first semiconductor portion, and the first semiconductor portion is located on a side of the drain away from the base substrate; forming a second metal layer on a side of the first semiconductor layer away from the base substrate, wherein the second metal layer includes a source electrode, and the source electrode is located on a side of the first semiconductor portion away from the base substrate; forming a gate insulating layer on a side of the source electrode away from the substrate; A third metal layer is formed on the side of the gate insulation layer away from the base substrate, the third metal layer includes a gate, the gate at least partially surrounds the first semiconductor portion, and the distance from the side of the gate close to the base substrate to the base substrate is smaller than the distance from the side of the first semiconductor portion away from the base substrate to the base substrate.

8. The method for manufacturing an array substrate according to claim 7, wherein: A second semiconductor portion is formed simultaneously with the formation of the first semiconductor portion, wherein the second semiconductor portion is located on a side of the lower electrode away from the base substrate.

9. The method for manufacturing an array substrate according to claim 8, wherein: The method for manufacturing the array substrate further includes: Before forming the first semiconductor layer, a second semiconductor layer is formed on a side of the first metal layer away from the base substrate, wherein the second semiconductor layer is made of an N-type doped semiconductor, and the second semiconductor layer includes a third semiconductor portion and a fourth semiconductor portion, wherein the third semiconductor portion is located between the first semiconductor portion and the drain electrode, and the fourth semiconductor portion is located between the second semiconductor portion and the lower electrode; and / or The photodiode includes the lower electrode, the second semiconductor portion, and an upper electrode provided on a side of the second semiconductor portion away from the base substrate. The method for manufacturing the array substrate further includes: An intrinsic semiconductor material layer is formed on the side of the first metal layer away from the substrate, and the intrinsic semiconductor material layer is patterned to form a first semiconductor structure and a second semiconductor structure, the first semiconductor structure is located on the side of the drain away from the substrate, and the second semiconductor structure is located on the side of the lower electrode away from the substrate; the first semiconductor structure is subjected to N-type doping treatment so that part of the first semiconductor structure forms the fifth semiconductor portion and the remaining part of the first semiconductor structure forms the first semiconductor portion; the second semiconductor structure is subjected to P-type doping treatment so that part of the second semiconductor structure forms the sixth semiconductor portion and the remaining part of the second semiconductor structure forms the second semiconductor portion.

10. A flat panel detector, characterized in that: include: The array substrate according to any one of claims 1 to 6; A scintillator is formed on one side of the array substrate.

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